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TARGET DATA
March 2004
STE50NM50
N-CHANNEL 550V @ Tjmax - 0.065Ω - 50A ISOTOP
MDmesh™ MOSFET
TYPICAL RDS(on) = 0.065Ω
HIGH dv/dt AND AVALANCHE CAPABILITIES
100% AVALANCHE TESTED
LOW INPUT CAPACITANCE AND GATE
CHARGE
LOW GATE INPUT RESISTANCE
TIGHT PROCESS CONTROL AND HIGH
MANUFACTURING YIELDS
DESCRIPTION
The MDmesh™ is a new revolutionary MOSFET
technology that associates the Multiple Drain pro-
cess with the Company’s PowerMESH™ horizontal
layout. The resulting product has an outstanding low
on-resistance, impressively high dv/dt and excellent
avalanche characteristics. The adoption of the
Company’s proprietary strip technique yields overall
dynamic performancethat is significantly betterthan
that of similar competition’s products.
APPLICATIONS
The MDmesh™ family is very suitable for increasing
power density of high voltage converters allowing
system miniaturization and higher efficiencies.
ABSOLUTE MAXIMUM RATINGS
(•)Pulse width limited by safe operating area
(1) ISD ≤50A, di/dt ≤400A/µs, VDD ≤V(BR)DSS,T
j≤TJMAX.
TYPE VDSS
(@Tjmax) RDS(on) ID
STE50NM50 550V < 0.085Ω50 A
Symbol Parameter Value Unit
VGS Gate- source Voltage ±30 V
IDDrain Current (continuous) at TC= 25°C 50 A
IDDrain Current (continuous) at TC= 100°C 32 A
IDM (
)Drain Current (pulsed) 200 A
PTOT Total Dissipation at TC= 25°C 450 W
Derating Factor 3.6 W/°C
dv/dt (1) Peak Diode Recovery voltage slope 15 V/ns
Tstg Storage Temperature –65 to 150 °C
TjMax. Operating Junction Temperature 150 °C
ISOTOP
INTERNAL SCHEMATIC DIAGRAM
STE50NM50
2/6
THERMAL DATA
(*) with conductive GREASE Applies
AVALANCHE CHARACTERISTICS
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)
OFF
ON (2)
DYNAMIC
(2) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
Rthj-case Thermal Resistance Junction-case Max 0.28 °C/W
Rthc-sink (*) Thermal Resistance Case-sink Typ 0.05 °C/W
Symbol Parameter Max Value Unit
IAR Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by Tjmax) 15 A
EAS Single Pulse Avalanche Energy
(starting Tj=25°C,I
D=I
AR,V
DD =50V) 810 mJ
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V(BR)DSS Drain-source
Breakdown Voltage ID= 250 µA, VGS = 0 500 V
IDSS Zero Gate Voltage
Drain Current (VGS =0) VDS =MaxRating 10 µA
VDS = Max Rating, TC=125°C 100 µA
IGSS Gate-body Leakage
Current (VDS =0) VGS =±30V ±100 nA
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VGS(th) Gate Threshold Voltage VDS =V
GS,I
D=250µA 345V
RDS(on) Static Drain-source On
Resistance VGS =10V,I
D=25A 0.065 0.085 Ω
Symbol Parameter Test Conditions Min. Typ. Max. Unit
gfs (2) Forward Transconductance VDS >I
D(on) xR
DS(on)max,
ID=25A 20 S
Ciss Input Capacitance VDS =25V,f=1MHz,V
GS =0 3700 pF
Coss Output Capacitance 610 pF
Crss Reverse Transfer
Capacitance 50 pF
RGGate Input Resistance f=1 MHz Gate DC Bias = 0
Test Signal Level = 20mV
Open Drain
1.7 Ω
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STE50NM50
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
SWITCHING OFF
SOURCE DRAIN DIODE
(2) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(3) Pulse width limited by safe operating area.
Symbol Parameter Test Conditions Min. Typ. Max. Unit
td(on) Turn-on Delay Time VDD =250V,I
D=25A
RG=4.7ΩVGS =10V
(see test circuit, Figure 3)
40 ns
trRise Time 35 ns
QgTotal Gate Charge VDD =400V,I
D=50A,
VGS =10V 87 117 nC
Qgs Gate-Source Charge 23 nC
Qgd Gate-Drain Charge 42 nC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
tr(Voff) Off-voltage Rise Time VDD =400V,I
D=50A,
RG=4.7Ω, VGS =10V
(see test circuit, Figure 5)
18 ns
tfFall Time 23 ns
tcCross-over Time 44 ns
Symbol Parameter Test Conditions Min. Typ. Max. Unit
ISD Source-drain Current 50 A
ISDM (3) Source-drain Current (pulsed) 200 A
VSD (2) ForwardOnVoltage ISD =50A,V
GS =0 1.5 V
trr
Qrr
Irrm
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD =40A,di/dt=100A/µs,
VDD =100V,T
j=25°C
(see test circuit, Figure 5)
520
7.8
30
ns
µC
A
trr
Qrr
Irrm
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD =40A,di/dt=100A/µs,
VDD =100V,T
j=150°C
(see test circuit, Figure 5)
680
11.2
33
ns
µC
A
STE50NM50
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Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Fig. 4: Gate Charge test Circuit
Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit
Fig. 3: Switching Times Test Circuit For
Resistive Load
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STE50NM50
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 11.8 12.2 0.466 0.480
B 8.9 9.1 0.350 0.358
C 1.95 2.05 0.076 0.080
D 0.75 0.85 0.029 0.033
E 12.6 12.8 0.496 0.503
F 25.15 25.5 0.990 1.003
G 31.5 31.7 1.240 1.248
H4 0.157
J 4.1 4.3 0.161 0.169
K 14.9 15.1 0.586 0.594
L 30.1 30.3 1.185 1.193
M 37.8 38.2 1.488 1.503
N4 0.157
O 7.8 8.2 0.307 0.322
B
E
H
O
N
JK
L
M
F
A
C
G
D
ISOTOP MECHANICAL DATA
STE50NM50
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consequen ces of use o f suc h info rmation nor for any infr ingeme nt of paten ts or other righ ts of third parties whic h may resul t from
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mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
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