STE50NM50 N-CHANNEL 550V @ Tjmax - 0.065 - 50A ISOTOP MDmeshTM MOSFET TARGET DATA TYPE STE50NM50 VDSS (@Tjmax) RDS(on) ID 550V < 0.085 50 A TYPICAL RDS(on) = 0.065 HIGH dv/dt AND AVALANCHE CAPABILITIES 100% AVALANCHE TESTED LOW INPUT CAPACITANCE AND GATE CHARGE LOW GATE INPUT RESISTANCE TIGHT PROCESS CONTROL AND HIGH MANUFACTURING YIELDS DESCRIPTION The MDmeshTM is a new revolutionary MOSFET technology that associates the Multiple Drain process with the Company's PowerMESHTM horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Company's proprietary strip technique yields overall dynamic performance that is significantly better than that of similar competition's products. ISOTOP INTERNAL SCHEMATIC DIAGRAM APPLICATIONS The MDmeshTM family is very suitable for increasing power density of high voltage converters allowing system miniaturization and higher efficiencies. ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Gate- source Voltage 30 V ID Drain Current (continuous) at TC = 25C 50 A ID Drain Current (continuous) at TC = 100C 32 A VGS IDM () PTOT dv/dt (1) Tstg Tj Parameter Drain Current (pulsed) 200 A Total Dissipation at TC = 25C 450 W Derating Factor 3.6 W/C Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature 15 V/ns -65 to 150 C 150 C (*)Pulse width limited by safe operating area (1) ISD 50A, di/dt 400A/s, VDD V(BR)DSS, Tj T JMAX. March 2004 1/6 STE50NM50 THERMAL DATA Rthj-case Thermal Resistance Junction-case Max Rthc-sink (*) Thermal Resistance Case-sink Typ 0.28 C/W 0.05 C/W (*) with conductive GREASE Applies AVALANCHE CHARACTERISTICS Symbol Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Parameter 15 A EAS Single Pulse Avalanche Energy (starting Tj = 25 C, ID = IAR, VDD = 50 V) 810 mJ ELECTRICAL CHARACTERISTICS (TCASE = 25 C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS Parameter Drain-source Breakdown Voltage Test Conditions ID = 250 A, VGS = 0 IDSS VDS = Max Rating Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating, TC = 125 C IGSS Gate-body Leakage Current (VDS = 0) Min. Typ. Max. 500 Unit V 10 VGS = 30 V A 100 A 100 nA ON (2) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 A RDS(on) Static Drain-source On Resistance Min. Typ. Max. Unit 3 4 5 V 0.065 0.085 Typ. Max. Unit VGS = 10 V, ID = 25 A DYNAMIC Symbol gfs (2) Parameter Test Conditions Forward Transconductance VDS > ID(on) x RDS(on)max, ID = 25 A VDS = 25 V, f = 1 MHz, VGS = 0 20 S 3700 pF Ciss Input Capacitance Coss Output Capacitance 610 pF Crss Reverse Transfer Capacitance 50 pF RG Gate Input Resistance 1.7 f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain (2) Pulsed: Pulse duration = 300 s, duty cycle 1.5 % 2/6 Min. STE50NM50 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Parameter Turn-on Delay Time Rise Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge Test Conditions Min. Typ. Max. Unit VDD = 250 V, ID = 25 A RG = 4.7 VGS = 10 V (see test circuit, Figure 3) 40 ns 35 ns VDD = 400 V, ID = 50 A, VGS = 10 V 23 nC 42 nC 87 117 nC SWITCHING OFF Symbol tr(Voff) Parameter Off-voltage Rise Time tf Fall Time tc Cross-over Time Test Conditions Min. VDD = 400 V, ID = 50 A, RG = 4.7, VGS = 10 V (see test circuit, Figure 5) Typ. Max. Unit 18 ns 23 ns 44 ns SOURCE DRAIN DIODE Symbol Max. Unit Source-drain Current 50 A ISDM (3) Source-drain Current (pulsed) 200 A VSD (2) Forward On Voltage ISD = 50 A, VGS = 0 1.5 V trr Qrr Irrm Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 40 A, di/dt = 100 A/s, VDD = 100 V, Tj = 25C (see test circuit, Figure 5) 520 7.8 30 ns C A trr Qrr Irrm Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 40 A, di/dt = 100 A/s, VDD = 100 V, Tj = 150C (see test circuit, Figure 5) 680 11.2 33 ns C A ISD Parameter Test Conditions Min. Typ. (2) Pulsed: Pulse duration = 300 s, duty cycle 1.5 % (3) Pulse width limited by safe operating area. 3/6 STE50NM50 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 4/6 STE50NM50 ISOTOP MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. A 11.8 12.2 0.466 TYP. MAX. 0.480 B 8.9 9.1 0.350 0.358 C 1.95 2.05 0.076 0.080 D 0.75 0.85 0.029 0.033 E 12.6 12.8 0.496 0.503 F 25.15 25.5 0.990 1.003 G 31.5 31.7 1.240 1.248 H 4 J 4.1 4.3 0.161 0.169 K 14.9 15.1 0.586 0.594 L 30.1 30.3 1.185 1.193 M 37.8 38.2 1.488 1.503 8.2 0.307 0.157 N 4 O 7.8 0.157 0.322 A G B O F E H D N J K C L M 5/6 STE50NM50 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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