AM29F800T-120EC - Advanced Micro Devices

PRELIMINARY

8/18/97 Publication# 20375 Rev: CAmendment/+1

Issue Date: August 19 97

Am29F800T/Am29F800B

8 Megabit (1,048,576 x 8-Bit/524,288 x 16-Bit) CMOS

5.0 Volt-only, Sector Erase Flash Memory

DISTINCTIVE CHARACTERISTICS

■5.0 V ± 10% for read and write operations

— Min imize s sy st em lev el p owe r req u ire me nts

■Compatible with JEDEC standards

— Pinout and software compatible with

single-power-supply flash

— Superior inadvertent write protection

■Package options

— 44-pin SO

— 48-pin TSOP

■Minimum 100, 000 write/erase cy cles guaranteed

■High performance

— 70 ns maximum access time

■Sector erase architecture

— One 16 Kby te, t wo 8 Kbyt es , one 3 2 Kby te, and

fifteen 64 Kbytes

— Any combi nation of sect ors can be erased. Als o

supports full chip erase.

■Sector pr ote ctio n

— Hardware method that disables any combination

of sectors fr om write or erase operat ions.

Implemented using standard PROM

programming equipment.

■Embe dd ed Er as e Algo rith m

— Automatically pre-programs and erases the chip

or any sector

■Embedded Program Algorithm

— Automatically programs and verifies data at

specified address

■Data Polling and T oggle Bit feature for detection

of program or erase cycle completion

■Ready/Busy output (RY/BY)

— Hardware method for detection of program or

erase cycle completion

■Erase Suspend/Resume

— Supports reading data from or programming

data to a sector not being erased

■Low power consumption

— 20 mA typical active rea d current for Byte Mode

— 28 mA typical active read current for Word Mode

— 30 mA typica l prog ram/er ase cur rent

■Enhanced power management for standby

mode

—1 µA typical standby current

■Boot Code Sector Ar chite c tur e

— T = Top sector

— B = Bottom sector

■Hardware RESET pin

— Resets internal state machine to the read mode

GENERAL DESCRIPTION

The A m2 9 F 8 00 is an 8 Mb it , 5. 0 Volt-on ly F la sh mem-

ory organized as 1 Mbyte of 8 bits each or 512K words

of 16 bits each. For flexible erase capability , the 8 Mbits

of data are divided into 19 sectors as follows: one 16

Kbyte, two 8 Kby te, one 32 Kby te, and fi fteen 64 Kbyte.

Eight bit s of data appear on DQ0–DQ7 in byte mode; in

word mode 16 bits appear on DQ0–DQ15. The

Am29F800 is offered in 44-pin SO and 48-pin TSOP

packages. This device is designed to be programmed

in-system with the standard system 5.0 Volt VCC sup-

ply. A VPP of 12.0 volts is not required for program or

erase operations. The d evice can al so be progr ammed

in standard EPROM programmers.

The standard Am29F800 offers access times of 70 ns, 90

ns, 120 ns, and 150 ns, allowing high-speed micropro-

cessors to operate without wait states. To eliminate bus

conten tion, the de vice has sep arate chip enable ( CE),

write enable (WE), and output enable (OE) controls.

The Am29F800 is entirely command set compatible

with the JEDEC single-power-supply Flash standard.

Commands are written to the command register using

standard microprocessor write timings. Register con-

tents s erve as input to an int ernal s tat e-machi ne which

controls the erase and program circuitry. Write cycles

also inter nally latch addresses and data needed for the

programming and erase operations. Reading data out

2 Am29F800T/Am29F800B 8/18/97

PRELIMINARY

of the device is similar to read ing from 1 2.0 Volt Flash

or EPROM devices.

The Am29F800 is programmed by executing the pro-

gram command sequence. This will invoke the Embed-

ded Program Algorithm which is an internal algorithm

that aut omatic ally time s the prog ra m p ulse wid ths and

verifies proper cell margin. Erase is accomplished by

executing the erase command sequence. This

will invoke the Embedded Erase Algorithm w hich is an

internal algorithm that automatically preprograms the

array if it is not already programmed before executing

the erase operation. During erase, the device automat-

ically times t he eras e pulse widths and verifies prope r

cell margin.

This device also features a sector erase architecture.

This allows for sectors of memory to be erased and re-

programmed without affecting the data contents of

other sec tors. A sector is typ ically era sed and verifie d

within 1.5 seconds. The Am29F800 is erased when

shi ppe d from the factory.

The Am29F800 device also features hardware sector

protection. This feature will disable both program and

erase operations in any combination of nineteen sec-

tors of memory.

AMD has implemented an Erase Suspend feature that

enables the user to put erase on hold for any period of

time to read data from or program data to a sector that

was not being erased. Thus, true background erase

can be achieved.

The device features single 5.0 Volt power supply oper-

ation for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operati ons. A low VCC det ector au-

tomat ically inh ibits write opera tio ns during powe r tran-

sitions. The end of program or erase is detected by the

RY/BY pin. Data Polling of DQ7, or by the Toggle Bit

(DQ6). Onc e the end of a program or e rase cycle has

been completed, the device automatically resets to the

read mode.

The Am29F800 also has a hardware RESET pin.

When this pin is driven low, execution of any Embed-

ded Program Algorithm or Emb edded Eras e Algorithm

will be terminated. The internal state machine will then

be reset into the read mode. The RESET pin may be

tied to the system reset circuitry. Therefore, if a system

reset occurs during the Embedded Program Algorithm

or Embedded Erase Algorithm, the device will be auto-

matically re set t o the read m ode and will have erro ne-

ous data stored in the address locations being

operat ed on . These locatio ns will nee d re-w riting af ter

the Reset. Resetting the device will enable the sys-

tem’s microprocessor to read the boot-up firmware

from the Fla sh memo r y.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The Am29F800 memory electrically erases all

bits within a sector simultaneously via Fowler-Nor-

dhiem tunneling. The bytes/words are programmed

one byte/word at a time using the EPROM program-

ming mechanism of hot electron injection.

8/18/97 Am29F800T/Am29F800B 3

PRELIMINARY

PRODUCT SELECTOR GUIDE

BLOCK DIAGRAM

Family Part No: Am29F800

Ordering Part No: VCC = 5.0 V ± 10% -70 -90 -120 -150

Max Access Time (ns) 70 90 120 150

CE (E) Access (ns) 70 90 120 150

OE (G) Access (ns) 30 35 50 55

Erase Voltage

Generator Input/Output

Buffers

Data

Latch

Y-Gating

Cell MatrixX-Decoder

Y-Decoder

Address Latch

Chip Enable

Output Enable

Logic

PGM Voltag e

Generator

Timer

VCC Detector

State

Control

Command

A0–A18

STB

DQ0–DQ15

RY/BY

Buffer RY/BY

BYTE

RESET

A–1

VCC

VSS

20375C-1

4 Am29F800T/Am29F800B 8/18/97

PRELIMINARY

CONNECTION DIAGRAMS

20375C-2

RY/BY

A18

A17

VSS

DQ0

DQ8

DQ1

DQ9

DQ2

DQ10

DQ3

DQ11

RESET

A10

A11

A12

A13

A14

A15

A16

BYTE

VSS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VCC

8/18/97 Am29F800T/Am29F800B 5

PRELIMINARY

CONNECTION DIAGRAMS

A16

DQ2

BYTE

VSS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ9

DQ1

DQ8

DQ0

VSS

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

A15

A18

A14

A13

A12

A11

A10

RESET

RY/BY

A17

Standard TSOP

20375C-3

A15

A18

A14

A13

A12

A11

A10

RESET

RY/BY

A17

A16

DQ2

BYTE

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ9

DQ1

DQ8

DQ0

DQ5

DQ12

DQ4

DQ11

DQ3

DQ10

Reverse TSOP

20375C-4

6 Am29F800T/Am29F800B 8/18/97

PRELIMINARY

PIN CONFIGURATION

A0–A18 = 19 Addresses

BYTE = Selects 8-b it or 16 -b it mo de

CE = Chi p En ab le

DQ0–DQ14 = 15 Data Inputs/Outputs

DQ15/A-1 = DQ15 Data Input/Output,

A-1 Address Mux

NC = Pin Not Connected Internally

OE = Output Enable

RESET = Hard wa re Re se t Pin , Activ e Low

RY/BY = Ready/Busy Output

VCC = +5.0 Volt Si ngle-Pow er Supply

(±10% for -70, -90 , -120, -150)

VSS = Device Ground

WE = Write Enable

LOGIC SYMBOL

16 or 8

DQ0–DQ15

A0–A18

CE (E)

OE (G)

WE (W)

A-1

RY/BY

RESET

BYTE

20375C-5

8/18/97 Am29F800T/Am29F800B 7

PRELIMINARY

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (V alid Combination) is formed

by a combination of:

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

E = Extended (–55°C to +125°C)

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 048)

F = 48-Pin Thin Small Outline Package (TSOP)

Reverse Pin out (TSR0 48)

S = 44-Pin Small Outline Package (SO 044)

DEVICE NUMBER/DESCRIPTION

Am29F800

8 Megabit (1M x 8-Bit/512K x 16-Bit) CMOS Flash Memory

5.0 Volt-only Program and Erase

AM29F800 -70 E C

OPTION AL PR OC ESS IN G

Blank = Standard Processing

B = Burn-In

SPEED OPTION

See Product Selector Guide and

Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top sector

B = Bottom sector

Valid Combinations

AM29F800T-70,

AM29F800B-70 EC, EI, FC, FI, SC, SI

AM29F800T-90,

AM29F800B-90 EC, EI, EE, EEB,

FC, FI, FE, FEB,

SC, SI, SE, SEB

AM29F800T-120,

AM29F800B-120

AM29F800T-150,

AM29F800B-150

8 Am29F800T/Am29F800B 8/18/97

PRELIMINARY

Table 1. Am29F800 User Bus Operations (BYTE = VIH)

Table 2. Am29F800 User Bus Operations (BYTE = VIL)

Legend:

L = logic 0, H = logic 1, X = Don’t Care. See Characteristics for voltage levels.

Notes:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 7.

2. Refer to the section on Sector Protection.

Read Mode

The Am29F800 has two control functions which must

be satisfied in order to obtain data at the outputs. CE is

the power control and should be used f or devic e selec-

tion. OE is the output control and should be used to

gate data to the output pins if a device is sel ect ed.

Addres s access time (tACC) is equal to the delay from

stable addresses to valid output data. The chip enable

access time (tCE) is the delay from stable addresses

and stable CE to valid data at the output pins.

The output enable access time is the delay from the

falling edge of OE to valid data at the output

pins (assuming the addresses have been stable for at

leas t tACC–tOE time).

Standby Mode

There are two w ays to implement t he standby mode on

the Am29F800 device, both using the CE pin.

A CMOS standby mode is achieved with the CE input

held at VCC ± 0.3 V. Und er this cond ition the cu rrent is

typically reduced to less than 5 µA. A TTL standby

mode is achieved with the CE pin held at VIH. Under

this cond itio n the current is typica lly re d uce d to 1 mA.

Operation CE OE WE A0 A1 A6 A9 DQ0–DQ15 RESET

Autoselect, AMD Manuf. Code (Note 1) L L H L L L VID Code H

Autoselect Device Code (Note 1) L L H H L L VID Code H

Read L L X A0A1A6A9 D

OUT H

Standby HXXXXXXHIGH Z H

Output Disable L H H X X X X HIGH Z H

Write L H L A0 A1 A6 A9 DIN H

Verify Sector Protect (Note 2) L L H L H L VID Code H

Temporary Sector Unprotect X XXXXXX X V

Hardware Reset XXXXXXXHIGH Z L

Operation CE OE WE A0 A1 A6 A9 DQ0–DQ7 DQ8–DQ15 RESET

Autoselect, AMD Manuf. Code

(Note 1) LLHLLLV

ID Code HIGH Z H

Autoselect Device Code (Note 1) L L H H L L VID Code HIGH Z H

Read L L X A0A1A6A9 D

OUT HIGH Z H

Standby HXXXXXXHIGH ZHIGH ZH

Output Disable L H H XXXXHIGH ZHIGH ZH

Write L H L A0 A1 A6 A9 DIN HIGH Z H

Verify

Sector Protect (Note 2) LLHLHLV

ID Code HIGH Z H

Temporary

Sector Unprotect XXXXXXX X HIGH ZV

Hardware Reset XXXXXXXHIGH ZHIGH Z L

8/18/97 Am29F800T/Am29F800B 9

PRELIMINARY

In the standby mode the outputs ar e in the high imped-

ance state, independent of the OE input.

Output Disable

With the OE input at a logic high level ( VIH), output from

the device is disabled. This will cause the output pins

to be in a high impeda nce st ate.

Autoselect

The autoselect mode allows the reading of a binary

code from the device and will identify its manufacturer

and type. This mode is intended for use by program-

ming equipment for the purpose of automatically

matching the device to be programmed with its corre-

sponding programming algorithm. This mode is func-

tional over the entire temperature range of the device.

To activate this mode, the programming equipment

must force VID (11.5 V to 12.5 V) on address pin A9.

Two identifier bytes may then be sequenced from the

device outputs by toggling address A0 from VIL to VIH.

All addresses are don’t cares except A0, A1, and A6

(see Table 3).

The manuf a cturer a nd d e vice co d es may a lso be re a d

via the command register, for instances when the

Am29F800 is erased or programmed i n a system wi th-

out access to high voltage on the A9 pin. The command

sequence is illustrated in Table 4 (see Autoselect Com-

mand Sequence).

Byte 0 (A0 = VIL) represents the manufacturer’s code

(AMD=01H) and byte 1 (A0 = VIH) the de vic e ide nt ifie r

code (Am29F800T = D6H and Am29F800B = 58H for

x8 mode; Am29F800T = 22D6H and Am29F800B =

2258H for x16 mode). These two bytes/words are

given in the table below. All identifiers for manufacturer

and devic e will exhibit o dd parity with DQ 7 defined as

the pa rity b it. In ord er to re ad th e pro pe r device co des

when executing the Autoselect, A1 must be VIL (see

Tables 3 and 4).

The autoselect mode also facilitates the determination

of sector protection in the system. By performing a read

operation at the address location XX02H with the

higher order address bits A12–A18 set to the desired

sector address, the device will return 01H for a pro-

tected sector and 00H for a non-protected sector.

Table 3. Am29F800 Sector Protection Verify Autoselect Codes

*Outputs 01H at protected sector addresses

Table 4. Expanded Autoselect Code Table

(B) – Byte mode

(W) – Word mode

Type A12–A18 A6 A1 A0 Code (HEX)

Manufacturer Code—AMD X VIL VIL VIL 01H

Am29F800 Device

Am29F800T Byte XV

IL VIL VIH D6H

Word 22D6H

Am29F800B Byte XV

IL VIL VIH 58H

Word 2258H

Sector Protection Sector

Address VIL VIH VIL 01H*

Type Code DQ

15 DQ

14 DQ

13 DQ

12 DQ

11 DQ

10 DQ

9DQ

8DQ

7DQ

6DQ

5DQ

4DQ

3DQ

2DQ

1DQ

Manufacturer Code—AMD 01H 0000000000000001

Am29F800

Device

Am29F800T(B)

(W) D6H

22D6H A-1

0HI-Z

1HI-Z

0HI-Z

1HI-Z

Am29F800B(B)

(W) 58H

2258H A-1

0HI-Z

1HI-Z

0HI-Z

1HI-Z

Sector Protection 01H 0000000000000001

10 Am29F800T/Am29F800B 8/18/97

PRELIMINARY

Table 5 . Se c tor Ad dre s s Tabl e s (Am2 9F8 0 0 T)

Note: The address range is A18:A–1 if in byte mode (BYTE = VIL). The address range is A18:A0 if in word mode (BYTE = VIH).

A18 A17 A16 A15 A14 A13 A12 Sector

Size (x16)

Address Range (x8)

Address Ran ge

SA00000XXX

64 Kbytes

32 Kwords 00000h–07FFFh 00000h–0FFFFh

SA10001XXX

64 Kbytes

32 Kwords 08000h–0FFFFh 10000h–1FFFFh

SA20010XXX

64 Kbytes

32 Kwords 10000h–17FFFh 20000h–2FFFFh

SA30011XXX

64 Kbytes

32 Kwords 18000h–1FFFFh 30000h–3FFFFh

SA40100XXX

64 Kbytes

32 Kwords 20000h–27FFFh 40000h–4FFFFh

SA50101XXX

64 Kbytes

32 Kwords 28000h–2FFFFh 50000h–5FFFFh

SA60110XXX

64 Kbytes

32 Kwords 30000h–37FFFh 60000h–6FFFFh

SA70111XXX

64 Kbytes

32 Kwords 38000h–3FFFFh 70000h–7FFFFh

SA81000XXX

64 Kbytes

32 Kwords 40000h–47FFFh 80000h–8FFFFh

SA91001XXX

64 Kbytes

32 Kwords 48000h–4FFFFh 90000h–9FFFFh

SA101010XXX

64 Kbytes

32 Kwords 50000h–57FFFh A0000h–AFFFFh

SA111011XXX

64 Kbytes

32 Kwords 58000h–5FFFFh B0000h–BFFFFh

SA121100XXX

64 Kbytes

32 Kwords 60000h–67FFFh C0000h–CFFFFh

SA131101XXX

64 Kbytes

32 Kwords 68000h–6FFFFh D0000h–DFFFFh

SA141110XXX

64 Kbytes

32 Kwords 70000h–77FFFh E0000h–EFFFFh

SA1511110XX

32 Kbytes

16 Kwords 78000h–7BFFFh F0000h–F7FFFh

SA161111100

8 Kbytes

4 Kwords 7C000h–7CFFFh F8000h–F9FFFh

SA171111101

8 Kbytes

4 Kwords 7D000h–7DFFFh FA000h–FBFFFh

SA18111111X

16 Kbytes

8 Kwords 7E000h–7FFFFh FC000h–FFFFFh

8/18/97 Am29F800T/Am29F800B 11

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Table 6. Sector Address Tables (Am29F800B)

Note: The address range is A18:A–1 if in byte mode (BYTE = VIL). The address range is A18:A0 if in word mode (BYTE = VIH).

A18 A17 A16 A15 A14 A13 A12 Sector

Size (x16)

Address Range (x8)

Address Range

SA0000000X

16 Kbytes

8 Kwords 00000h–01FFFh 00000h–03FFFh

SA10000010

8 Kbytes

4 Kwords 02000h–02FFFh 04000h–05FFFh

SA20000011

8 Kbytes

4 Kwords 03000h–03FFFh 06000h–07FFFh

SA300001XX

32 Kbytes

16 Kwords 04000h–07FFFh 08000h–0FFFFh

SA40001XXX

64 Kbytes

32 Kwords 08000h–0FFFFh 10000h–1FFFFh

SA50010XXX

64 Kbytes

32 Kwords 10000h–17FFFh 20000h–2FFFFh

SA60011XXX

64 Kbytes

32 Kwords 18000h–1FFFFh 30000h–3FFFFh

SA70100XXX

64 Kbytes

32 Kwords 20000h–27FFFh 40000h–4FFFFh

SA80101XXX

64 Kbytes

32 Kwords 28000h–2FFFFh 50000h–5FFFFh

SA90110XXX

64 Kbytes

32 Kwords 30000h–37FFFh 60000h–6FFFFh

SA100111XXX

64 Kbytes

32 Kwords 38000h–3FFFFh 70000h–7FFFFh

SA111000XXX

64 Kbytes

32 Kwords 40000h–47FFFh 80000h–8FFFFh

SA121001XXX

64 Kbytes

32 Kwords 48000h–4FFFFh 90000h–9FFFFh

SA131010XXX

64 Kbytes

32 Kwords 50000h–57FFFh A0000h–AFFFFh

SA141011XXX

64 Kbytes

32 Kwords 58000h–5FFFFh B0000h–BFFFFh

SA151100XXX

64 Kbytes

32 Kwords 60000h–67FFFh C0000h–CFFFFh

SA161101XXX

64 Kbytes

32 Kwords 68000h–6FFFFh D0000h–DFFFFh

SA171110XXX

64 Kbytes

32 Kwords 70000h–77FFFh E0000h–EFFFFh

SA181111XXX

64 Kbytes

32 Kwords 78000h–7FFFFh F0000h–FFFFFh

12 Am29F800T/Am29F800B 8/18/97

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Write

Device erasure and programming are accomplished

via the command register. The contents of the register

serv e as inputs to the i nternal stat e machine. T he state

machine outputs dictate the function of the device.

The command register itself does not occupy any ad-

dressable memory location. The register is a latch used

to store the commands, along with the address and

data inf ormation needed to exec ute the command. T he

command register is written to by bringing WE to VIL,

while CE is at VIL and OE is at VIH. Addresses are

latched on the falling edge of WE or CE, whichever

happens later; while data is latched on the rising edge

of WE or CE, whichever happens first. Standard micro-

processor write timings are used.

Refer to AC Write Characteristics and the Erase/Pro-

gramming Waveforms for specific t iming parameters.

Sector Protection

The Am29F800 features hardware sector protection.

This feature will disable both program and erase oper-

ation s in any combin a tio n o f n in e te e n se c to rs o f m e m -

ory. The sector protect feature is enabled using

programming

equipment at the user ’s site

. The device

is shipped with all sectors unprotected. Alternatively,

AMD may program and protect sectors in the factory

prior to shipping the device (AMD’s ExpressFlash™

Service).

It is possible to determine if a sector is protected in the

system by writing an Autoselect command. Performing

a read operat ion at the addres s location X X02H, where

the higher order address bits A12–A18 is the desired

sector address, will produce a logical “1” at DQ0 for a

protected sector. See Table 3 for Autoselect codes.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ-

ously protected sectors of the Am29F800 device in

order to change data in-system. The Sector Unprotect

mode is activated by setting the RESET pin to high volt-

age (12 V). During this mode, formerly protected sec-

tors can be programmed or erased by selecting the

sector addresses. Once the 12 V is taken away from

the RESET pin, all the previously protected sectors will

be protected again. Refer to Figures 17 and 18.

Command Definitions

Device oper ation s are selected by writing specific ad-

dress and data seque nces into the comman d regis ter.

Writ ing incorrect address and data values or writ-

ing them in the improper sequence will reset the

device to the read mode. Table 7 defines the valid

Suspend (B0H) and Erase Resume (30H) commands

are valid only while the Sector Erase operation is in

progress. Moreover, both Reset/Read commands are

functionally equivalent, resetting the device to the

read mode.

8/18/97 Am29F800T/Am29F800B 13

PRELIMINARY

Table 7. Am29F800 Command Definitions

Legend:

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE or CE pulse.

PD = Data to be programmed at location PA. Data is latched on the rising edge of WE or CE pulse.

SA = Address of the sector to be erased. Address bits A18–A12 uniquely select any sector.

Notes:

1. All values are in hexadecimal.

2. See Tables 1 and 2 for description of bus operations.

3. The data is 00H for an unprotected sector group and 01H for a protected sector group. The complete bus address is

composed of the sector address (A18–A12), A1 = 1, and A0 = 0.

4. Read and program functions in non-erasing sectors are allowed in the Erase Suspend mode.

5. Address bits A18–A11 are don’t care for unlock and command cycles.

Command

Sequence

Read/Reset

(Note 2)

Bus

Write

Cycles

Req’d

First Bus

Write Cycle

Second Bus

Read/Write

Cycle Third Bus Write

Cycle

Fourth Bus

Read/Write

Cycle Fifth Bus

Write Cycle Sixth Bus

Write Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Reset/Read Word 1XXX

XXF0 RA RD

Byte F0

Autoselect

Manufacturer ID Word 3555 XXAA 2AA XX55 555 XX90 XX00 XX01

Byte AAA AA 555 55 AAA 90 00 01

Autoselect

Device ID

(Top Boot Block)

Word 3555 XXAA 2AA XX55 555 XX90 XX01 22D6

Byte AAA AA 555 55 AAA 90 02 D6

Autoselect

Device ID

(Bottom Boot

Block)

Word

555 XXAA 2AA XX55 555 XX90 XX01 2258

Byte AAA AA 555 55 AAA 90 02 58

Autoselect

Sector Protect

Verify (Note 3)

Word

555 XXAA 2AA XX55 555 XX90 (SA)

X02 XX00

XX01

Byte AAA AA 555 55 AAA 90 (SA)

X04 00

Byte Program Word 4555 XXAA 2AA XX55 555 XXA0 PA PD

Byte AAA AA 555 55 AAA A0

Chip Erase Word 6555 XXAA 2AA XX55 555 XX80 555 XXAA 2AA XX55 555 XX10

Byte AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10

Sector Erase Word 6555 XXAA 2AA XX55 555 XX80 555 XXAA 2AA XX55 SA XX30

Byte AAA AA 555 55 AAA 80 AAA AA 555 55 30

Erase Suspend

(Note 4) Word 1XXX

XXB0

Byte B0

Erase Resume Word 1XXX

XX30

Byte 30

14 Am29F800T/Am29F800B 8/18/97

PRELIMINARY

Read/Reset Command

The read or reset operation is initiated by writing the

read/r eset command sequence i nto the command reg-

ister. Microprocessor read cycles retrieve array data

from the memory. The device remains enabled for

reads until th e co mma n d re gis te r con te nt s are a lte re d .

The device will automatically power-up in the read/

reset state. In this case, a command sequence is not

required to read data. Standard microprocessor read

cycles will retrieve array data. This default value en-

sures t hat no s purious al teration of the memory cont ent

occurs during the power transition. Refer to the AC

Read Characteristics and Waveforms for the specific

timing para meters.

Autoselect Command

Flash memories are intended for use in applications

where the local CPU can alter memory contents. As

such, manufac ture and device codes must be accessi-

ble while the device resides in the target system.

PROM programmers typically access the signature

codes by ra ising A9 to a high vo ltage . Ho w ever, multi-

plexing high voltage onto the address lines is not gen-

erally a desirable system design practice.

The device contains an aut oselec t command operati on

to suppl ement traditional PROM pr ogramming method-

ology. The operation is initiated by writing the autose-

lect command sequence into the command register.

Following the command write, a read cycle from ad-

dress XX00H retriev es the manufac ture code of 01H. A

read cycle from address XX01H returns the device

code (Am29F800T = D6H and Am29F800B = 58H for

x8 mode; Am29F800T = 22D6H and Am29F800B =

2258H fo r x16 mode) (see Ta bles 3 and 4).

All manufacturer and device codes will ex hibit odd par-

ity with DQ7 def in ed as the parit y bit .

Furthermore, the write protect status of sectors can be

read in this mode. Scanning the sector addresses

(A18, A17, A16, A15, A14, A13, and A12) while (A6,

A1, A0) = (0, 1, 0) will produce a logical “1” at device

output DQ0 for a protec ted sector.

To terminat e the operatio n, it is neces sary to write the

read/reset command sequence into the register.

Byte/Word Programming

The device is programmed on a byte-by-byte (or

word-b y-word ) basis. Progra mming is a four bus cy cle

operation. There are two “unlock” write cycles. These

are foll owed by the program set-up command and data

write cycles. Addresses are latched on the falling edge

of CE or WE, whichever happens later and the data is

latc hed on t he rising edge of CE or WE, whichever hap-

pens first. The rising edge of CE or WE (whichever

happens first) begins programming using the Embed-

ded Program Algorithm. Upon executing the algorithm,

the system is

not

required to provi de further contro ls or

timings. The device will automatically provide adequate

internally generated program pulses and verify the pro-

grammed cell margin.

The automatic programming operation is completed

when the data on DQ7 (also used as Data Polling) is

equivalent to the data written to this bit at which time

the device ret urns to the read mode and addresses ar e

no longer latched (see Table 8, Hardware Sequence

Flags). Therefore, the device re quires that a valid ad-

dress to the device be supplied by the system at this

particular instance of time for Data Polling opera tions.

Data Polling must be performed at the memory location

which is being programmed.

Any commands written to the chip during the Embed-

ded Program Algorithm will be ignored. If a hardware

reset occurs during the programming operation, the

data at that particular location will be corrupted.

Programming is allowed in any sequence and across

sector boundaries. Beware that a data “0” cannot be

programmed back to a “1”. Attempting to do so may

cause the device to exceed programming time limits

(DQ5 = 1) or result in an apparent success, according

to the data polling algorithm, but a read from reset/read

mode will show that the data is s till “0”. Only erase o p-

eratio ns can conv ert “0”s to “1”s.

Figure 1 illustrates the Embedded Programming Algo-

rithm using typical command strings and

bus operations.

Chip Erase

Chip erase is a six bus cyc le o perat ion . There are two

“unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are

then followed by the chip erase command.

Chip erase does

not

require the user to program the

device prior to erase. Upon executing the Embedded

Erase Algorithm command sequence the device will

automatically program and verify the entire memory for

an all zero data pattern prior to electrical erase. The

erase is performed sequentially on all sectors at the

same time (see Table “Erase and Programming Perfor-

mance”). The system is not required to provide any

controls or timings during these operations.

The automatic erase begins on the rising edge of the

last WE pulse in the command sequence and termi-

nates when the data on DQ7 is “1” (see Write Opera-

tion S ta tus section) at wh ich time th e de vice retu rns to

read the mode.

Figure 2 illustrates the Embedded Erase Algorithm

using typical command strings and bus operations.

8/18/97 Am29F800T/Am29F800B 15

PRELIMINARY

Sector Erase

Sector erase is a six bus cycle operation. There are two

“unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are

then followed by the sector erase command. The sec-

tor address (any address location within the desired

sect or) is latche d on the falling ed ge of WE , while the

command (30H) is latched on the rising edge of WE.

After a time-out of 80 µs from the rising edge of the

la st sect or er ase comman d, t he s ect or er as e oper ati on

will begin.

Multip le s e ctors m a y be e ra se d s e qu e nt ia lly by writing

the six bus cycle opera tions as de scribed above . This

sequence is followed with writes of the Sector Erase

command to addresses in other sectors desired to be

seque ntia lly era sed. The time betw ee n writes mu st be

less tha n 80 µs otherwise that c ommand will not be ac-

cepted and erasure will start. It is recommended that

processor interrupts be disabled during this time to

guarantee this condition . The int errupts can be re-en-

abled after the last Sector Erase command is written. A

time-out of 80 µs from the rising edge of the last WE will

initiate the execution of the Sector Erase command(s).

If another falling edge of the WE occu rs within t he 80

µs time-out win do w t he time r is res e t. (Mo nito r DQ3 to

determine if the sector erase timer window is still open.

See DQ3, Sector Erase Timer.) Any command other

than Sec tor Er ase or Erase Sus pend during t his period

will reset the device to the read mode, ignoring the pre-

vious command string. In that case, restart the erase

on those sectors and allow them to complete.

Loading the sector erase buffer may be done in

any sequence and with any number of s ectors (0 to18).

Refer t o D Q3 , S ect o r Era se Timer, in t he Write Op era-

tion St a tu s se c tio n .

Sector erase does

not

require the user to program the

device prior to erase. The device automatically pro-

grams all memory locations in the sector(s) to be

erased prior to electrical erase. When erasing a sector

or sect ors the remai ning unsel ected sec tors are no t af-

fected. The system is

not

required to provide any con-

trols or timings during these operations.

The automati c sector erase begins after the 80 µs time

out from the rising edge of the WE pulse for the last

sector erase command pulse and terminates when the

data on DQ7, Data Polling, is “1” (see Write Operation

Status s ect ion) a t w hic h t ime the d evice re turn s to t he

read mode. Data Polling must be performed at an ad-

dres s with in any of th e se c to rs b e ing e ra sed.

Figure 2 illustrates the Embedded Erase Algorithm

using typical command strings and bus operations.

Erase Suspend

The Erase Suspend command allows the us er to inter-

rupt a Sector Erase operation and then perform data

reads or programs to a sector not being erased. This

comma nd is applica ble O NLY durin g the Sec tor Erase

operation which includes the time-out period for sector

erase. The Erase Suspend command will be igno red if

written during the Chip Erase operation or Embedded

Program Algorithm. Writing the Erase Suspend com-

mand during the Sector Erase time-out results in imme-

diate termination of t he time-out period and suspension

of the erase operation.

Any other command written during the Erase Suspend

mode will be ignored except the Erase

Resume command. Writing the Erase Resume com-

mand r esumes t he erase operation. The addresses are

“don’ t-cares” when wr iting the Eras e Suspend or Erase

Resu me comman d .

When the Erase Suspend command is written during a

Sector Erase operation, the chip will take a maximum

of 20 µs to suspend the operation and go into erase

suspended mode, at which time the user can read or

program from a sector that is not being erased. Read-

ing data in this mode is the same as reading from the

sta ndard read mode, e xcept that t he data must be read

from sectors that have not been erase suspended.

Successively reading from the erase-suspended sec-

tor while the device is in the erase-suspend-read mode

will cause DQ2 to toggle . Aft er ente rin g the erase -s u s-

pend mode, the user can program the device by writing

the appr opriat e command seque nce for Byt e Pr ogram.

This program mode is known as the erase sus-

pend-program mode. Again, programming in this mode

is the same as programming in regular Byte Program

mode, except that the data must be programmed to

sectors that are not erase suspended. Successively

reading from t he erase suspended sector while the de-

vice is in the erase s uspend-program mode will cause

DQ2 to toggle. The end of the erase s uspend-prog ram

operation is detected by the RY/BY output pin, DATA

Polli ng of DQ7, or by the Toggle Bit (DQ 6), whic h is the

same as the regul ar Byte Program oper ation. Note that

DQ7 must be read from the Byte Program address

while DQ6 can be read from any address.

When the erase operation has been suspended, the de-

vice defaults to the erase-suspend- read mode. Reading

data in this mode is the same as reading from the stan-

dard read mode except that the data must be read from

sectors that have not been erase-suspended.

To resume the operation of Sector Erase, the Resume

command (30H) should be written. Any further writes of

the Resume command at this point will be ignored. An-

other Erase Suspend command can be written after the

chip has resumed erasing.

16 Am29F800T/Am29F800B 8/18/97

PRELIMINARY

Write Operation Status Table 8. Hardware Sequence Flags

Notes:

1. DQ2 can be toggled when sector address applied is that of an erasing sector. Conversely, DQ2 cannot be toggled when the

sector address applied is that of a non-erasing sector. DQ2 is therefore used to determine which sectors are erasing and

which are not.

2. These status flags apply when outputs are read from the address of a non-erase-suspended sector.

3. If DQ5 is high (exceeded timing limits), successive reads from a problem sector will cause DQ2 to toggle.

DQ7: Data Polling

The Am29F800 device features Data Polling as a

method to indic ate to the host that the embedded algo-

rithms are in progress or completed. During the Em-

bedded Program Algorithm, an attempt to read the

device will produce the complement of the data last

written to DQ7. Upon completion of the Embedded Pro-

gram Algorithm, an attempt to read the device will pro-

duce the true data last written to DQ7. During the

Embedded Erase Algorithm, an attempt to read the de-

vice will produce a “0” at the DQ7 output.

Upon compl eti on of t he Em bedded Er ase Al gori thm an

attempt to read the device will produce a “1” at the DQ7

output. The flowchart for Data Polling (DQ7) is shown

in Figure 3.

For chip erase, the Data Polling is va lid after th e rising

edge of the sixth WE pulse in the six write pulse se-

quence. For s ector e rase, t he Data Polling is valid after

the last r isi ng edge of the s ector e r ase WE pulse. Data

Polling must be performed at sector addresses within

any of the sectors being erased and not a protected

sector. Otherwise, the status may not be valid.

Just prior to the completion of Embedded Algorithm op-

erations DQ7 may change asynchronously while the

output enable (OE) is asserted low . This means that the

device is driving status information on DQ7 at

one insta nt of time and then that by te’s valid dat a at the

next instant of time. Depending on when the

syst em sampl es the DQ7 out put, it may read th e st atus

or valid data. Even if the device has completed

the Embedded Algorithm operations and DQ7 has a

valid data, the data outputs on DQ0–DQ6 may be still

invalid. The valid data on DQ0–DQ7 will be read on the

successive read attempts.

The Data P olling feature is on ly activ e during the Em -

bedded Programming Algorithm, Em bedded Erase Al-

gorithm, or sector erase time-out (see Table 7).

See Figure 11 for the Data Polling timing specifications

and diagrams.

DQ6: Toggle Bit

The Am29F800 also features the “Toggle Bit” as a

method to indicate to the host system that the embed-

ded algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cy-

cle, successive attempts to read (OE toggling) data

from the device at any address will result in DQ6 tog-

gling betwe en one and zero. Once the Embedded Pro-

gram or Erase Algorithm cycle is completed, DQ6 will

stop toggling and valid data will be read on

the next

successive attempt. During programming, the Toggle

Bit is valid af ter the rising edge of the fourth WE pulse

in the four write pulse sequence. For chip erase, the

Toggle B it is valid after the risin g edge of the six th WE

pulse in the six write pulse sequence. For Sector erase,

the Toggle Bit is valid after the last rising edge of the

sector erase WE pulse . T h e To gg le B it is a c tive durin g

the sector erase time-out .

Either CE or OE toggling will cause DQ6 to toggle. In

addition, an Erase Suspend/Resume command will

Status DQ7 DQ6 DQ5 DQ3 DQ2 RDY/BSY

In Progress

Byte Programming DQ7 Toggle 0 0 No Tog 0

Program/Erase in Auto-Erase 0 Toggle 0 1 (Note 1) 0

Erase

suspend

mode

Erase sector address 1 No Tog 0 1 Toggle 1

Non-era se sec tor

address Data Data Data Data Data 1

Program in erase suspend DQ7

(Note 2) Toggle 0 1 1

(Note 1) 0

Exceeded

Time

Limits

Byte Programming DQ7 Toggle 1 0 No Tog 0

Program/Erase in Auto-Erase 0 Toggle 1 1 (Note 3) 0

Program in erase suspend DQ7 Toggle 1 1 (Note 3) 0

8/18/97 Am29F800T/Am29F800B 17

PRELIMINARY

cause DQ6 to toggle. See Figure 12 for the Toggle Bit

timing specifications and diagrams.

DQ5: Exceeded Timing Limits

DQ5 will indic ate if the program or era se time has ex-

ceeded the specified limits (internal pulse count).

Under these conditions DQ 5 w ill produce a “1”. This is

a failu re cond ition which indica tes tha t the pro gram o r

erase cycle was not successfully completed. Data Poll-

ing is the only operating function of the device under

this co ndition . The CE circuit will partia lly powe r down

the de vice unde r these conditio ns (to ap proxima tely 2

mA). The OE and WE pins will control the output dis-

able functions as described in Table 1.

The DQ5 failure condition will also appear if a user tries

to program a 1 to a location that is previously pro-

grammed to 0. In this case the device locks out and

never completes the Embedded Program Algorithm.

Hence, the system nev er reads a valid dat a on DQ7 bit

and DQ6 never stops t oggling. Once t he device has e x-

ceeded timing limits, the DQ5 bit will indicate a “1”.

Please note that this is not a device failure condition

since the device was incorrectly used. If this occurs,

reset the dev ice .

DQ3: Sector Erase T imer

After the completion of the initial sector erase com-

mand sequence the sector erase time-out will begin.

DQ3 will remain low until the time-out is complete. Data

Polling and Toggle Bit are valid after the initial sector

erase co mmand sequence.

If Data Polling or the Toggle Bit indicates the device has

been written with a valid eras e command, DQ3 may be

used to determine if the sector erase timer window is

still open. If DQ3 is high (“1”) the internally controlled

erase cycle has begun; attempts to write subsequent

commands (other than Erase Suspend) to the device

will be ignored until the erase operation is completed

as indicat ed by Data Polling or Toggle Bit. If DQ3 is low

(“0”), the device will accept additional sector erase

commands. To insure the command has been ac-

cepted, the system software should check the status of

DQ3 prior to and following each subsequent sector

erase command. If DQ3 were high on the second sta-

tus chec k, the command m ay not have been accept ed.

Refer to Table 8, Hardware Sequence Flags.

DQ2: Toggle Bit 2

This toggle bit, along with DQ6, can be used to deter-

mine whether the device is in the Embedded

Erase Algorith m o r in Erase sus p end.

Successive reads from the erasing sector will cause

DQ2 to toggle during the Embedded Erase Algorithm.

If the device is in the erase suspend-read mode, suc-

cessive reads from the erase-suspend sector will

cause DQ2 to toggle. When the device is in the erase

suspend-program mode, successive reads from the

byte address of t he non- erase s uspend sect or will i ndi-

cate a logic “1” at the DQ2 bit. Not e that a sector whi ch

is selected for erase is not available for read in Erase

Suspend mode. Other sectors which are not selected

for Erase can be read in Erase Suspend.

DQ6 is different from DQ2 in that DQ6 toggles only

when the standard program or erase, or erase sus-

pend-program operation is in progress.

If the DQ5 failure condition is observed while in Sector

Erase mode (i.e., exc eeded timing limits), the DQ2 tog-

gle bit can gi ve extra info rmation. I n thi s case, the nor-

mal fun ction of DQ2 is modified. If DQ5 is at logic “1 ”,

then DQ2 will toggle with consecutive reads only at the

sector address that caused the failure condition. DQ2

will toggle at the sector address where the failure oc-

curred and will not toggle at other sector addresses.

RY/BY: Ready/Busy

The Am29F800 provides a RY/BY open-drain output

pin as a way to indicate to the host system that the Em-

bedded Algorithms are either in progress or have been

comp leted. If the outp ut is low, the devic e is busy with

either a program or erase operation. If the output is

high, the device is ready to accept any read/write or

erase operati on. When the RY/B Y pin is low , th e device

will not accept any additional program or erase com-

mand s with the exc eption of t he Era se Susp end c om-

mand. If the Am 29F800 is plac ed i n an Er ase Sus pend

mode, the RY/BY output will be high.

During programming, the RY/BY pin is driven low afte r

the rising edge of the fourth WE puls e. During an erase

operation, the RY/BY pin is driven low after the rising

edge of the sixth WE pulse . Th e RY/BY pin should be

ignored while RESET is at VIL. Refer to Figure 13 for a

detailed timi ng diagr am.

Since this is an open-drain output, several RY/BY

pins can be tied t ogether in parallel with a pull- up resis-

tor to VCC.

RESET: Hardware Reset

The Am29F800 device may be reset by driving the

RESET pin to VIL. The RESET pin must be kept low

(VIL) for at least 500 ns. Any operation in progress will

be terminated and the internal state machine will be

reset to the read mode 20 µs after the RESET pin is

driven low. Furthermore, once the RESET pin goes

high, the device requires an additional 50 ns before it

will allow read access. When the RESET pin is low, the

device will be in the standby mode for the duration of

the pulse and all the data output pins will be tri-stated.

If a hardware reset occurs during a program or erase

operation, the data at that particular location will

be indeterminate.

The RESET pin may be tied to the system reset input.

Therefore, if a system reset occurs during

the Embedded Program or Erase Algorithm, t he device

18 Am29F800T/Am29F800B 8/18/97

PRELIMINARY

will be automatically reset to read mode and this will

enable the system’s microprocessor to read the

boot-up firmware from the Flash memory.

Byte/Word Configuration

The BYTE pin selects the byte (8-bit) mode or word

(16 bit) mode for the Am29F800 device. When this pin is

driven high, the device operates in the word (16 bit)

mode. The data is read and programmed at DQ0–

DQ15. When this pin is driven low, the device operates

in byte (8 bit) mo de. Under this mode, t he DQ15/A-1 pin

becomes the lowest address bit and DQ8–DQ14 bits are

tri-stated. However, the command bus cycle is always

an 8-bit operation and hence commands are written at

DQ0–DQ7 and the DQ8–DQ15 bits are ignored. Refer

to Figures 15 and 16 for the timing diagram.

Data Protection

The Am29F800 is designed to offer protection against

accidental erasure or programming caused by spurious

system level sign als that ma y exist d uring pow er tran-

sitions. During power up the device automatically re-

sets t he internal st ate machine i n the Read mode. Als o,

with its control register architecture, alteration of the

memory contents onl y occurs after successful comple-

tion of specific multi-bus cycle command sequences.

The device also incorporates several features to pre-

vent inadvertent write cycles resulting from VCC

power-up and power-down transitions or system noise.

Low VCC Write Inhibit

To avoid initiation of a write cycle during VCC power-up

and power-down, the Am29F800 locks out write cycles

for VCC < VLKO (see DC Characteristics section for volt-

ages). When VCC < VLKO, the command register

is disabled, all internal program/erase circuits are dis-

abled, and the device resets to the read mode. The

Am29F800 ignores all writes until VCC > VLKO. The

user must ensure that the control pins are in the cor rect

logic state when VCC > VLKO to prevent unintentional

writes.

Write Pulse “Glitch” Protection

Noise pulses of less t han 5 ns (typ ical) on OE, CE, o r

WE will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE = VIL,

CE = VIH, or WE = VIH. To initiate a write cycle CE and

WE must be a logical zero while OE is a logical one.

Power-Up Write Inhibit

Power-up of the device with WE = CE = VIL and

OE = VIH will not accept commands on the rising edge

of WE. The internal state machine is automatically

rese t to th e rea d mo d e on po w er-up.

8/18/97 Am29F800T/Am29F800B 19

PRELIMINARY

EMBEDDED ALGORITHMS

Figure 1. Embedded Programming Algorithm

Start

Program mi ng Com ple ted

Last Address

Write Program Command Sequence

(see below)

Data Poll Device

Increment Address

Yes

555H/AAH

2AAH/55H

555H/A0H

Program Address/Program Data

Program Command Sequence (Address/Command):

20375C-6

20 Am29F800T/Am29F800B 8/18/97

PRELIMINARY

EMBEDDED ALGORITHMS

Note:

1. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each

subsequent sector erase command. If DQ3 were high on the second status check, the command may not have been ac-

cepted.

Figu re 2. E mb e dde d Erase Al gor ithm

Start

Erasure Completed

Write Erase Command Sequence

(see below)

Data Polling or Toggle Bit

Successfully Completed

555H/AAH

2AAH/55H

555H/80H

Chip Erase Command Sequence

(Address/Command):

555H/AAH

2AAH/55H

555H/10H

555H/AAH

2AAH/55H

555H/80H

Individual Sector/Multiple Sector

Erase Command Sequence

(Address/Command):

555H/AAH

Sector Address/30H

2AAH/55H

Additional sector

erase commands

are optional

20375C-7

8/18/97 Am29F800T/Am29F800B 21

PRELIMINARY

Figur e 3. Data Polling Algorithm

Start

Fail

DQ7=Data

No Pass

Yes

Note:

1. DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

DQ7=Data

DQ5=1

Yes

Read Byte

(DQ0–DQ7)

Addr=VA

Read Byte

(DQ0–DQ7)

Addr=VA

VA =Byte address for programming

=any of the sector addresses within the

sector being era sed during secto r erase

operation

=Valid address equals any non-protected

sector group address during chip erase

20375C-8

22 Am29F800T/Am29F800B 8/18/97

PRELIMINARY

Figure 4. Toggle Bit Algorithm

Figur e 5. Ma xim u m Ne gative Ove rs h oot Waveform

Figure 6. Maxim um Po sitive Overs hoo t Waveform

Start

Fail

DQ6=Toggle

Pass

Yes

Note:

1. DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as DQ5 changing to “1”.

DQ6=Toggle

DQ5=1

Yes

Read Byte

(DQ0–DQ7)

Addr=Don’t Care

Read Byte

(DQ0–DQ7)

Addr=Do n’t Car e

20375C-9

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

20375C-10

20 ns

VCC + 0.5 V

2.0 V

20 ns 20 ns

VCC + 2.0 V

20375C-11

8/18/97 Am29F800T/Am29F800B 23

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Pla stic Pac ka ges . . . . . . . . . . . . . . . –65°C to +125°C

Ambi ent Temperature

with Power Applied . . . . . . . . . . . . . –55°C to +12 5°C

Voltage with Respect to Ground

All pins except A9 (Note 1) . . . . . . . .–2.0 V to +7.0 V

VCC (Note 1). . . . . . . . . . . . . . . . . . . .–2.0 V to +7.0 V

A9 (Note 2) . . . . . . . . . . . . . . . . . . . .–2.0 V to +13.0 V

Out p u t S ho rt Circ u it Cu r rent (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V . During

voltage transitions, inputs may overshoot VSS to –2.0 V

for periods of up to 20 ns. Maximum DC voltage on input

and I/O pins is VCC + 0.5 V. During voltage transitions,

input and I/O pins may overshoot to VCC + 2.0 V for

periods up to 20ns.

2. Minimum DC input voltage on A9 pin is –0.5 V. During

voltage transitions, A9 may overshoot VSS to –2.0 V for

periods of up to 20 ns. Maximum DC input voltage on A9

is +12.5 V which may overshoot to 14.0 V for periods up

to 20 ns.

3. No more than one output shorted to ground at a time. Du-

ration of the short circuit should not be greater than one

second.

Stresses ab ove those listed un der “Absolute M aximum Rat-

ings” may ca use per manen t damag e to the d evice. Th is is a

stress rating only ; func tion al op era tion of the devi ce at th ese

or any o ther conditions above those indicated in th e opera-

tional sections of this specification is not implied. Exposure of

the device to absolute maximum rating conditions for ex-

tended periods may affect device reliability.

OPERATING RANGES

Commerci al (C) Devices

Ambient Temperature (TA) . . . . . . . . . . .0°C to +7 0°C

Indus tr ial (I) De v ice s

Ambient Temperature (TA) . . . . . . . . .–40°C to +8 5°C

Extended (E) Devices

Ambient Temperature (TA) . . . . . . . .–55°C to +12 5 °C

VCC S upp ly Volta ges

VCC for Am29F800T/B-70, 90,

120, 150 . . . . . . . . . . . . . . . . . . . . +4.50 V to +5.50 V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

24 Am29F800T/Am29F800B 8/18/97

PRELIMINARY

DC CHARACTERISTICS

TTL/NMOS Compatible

Notes:

1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz).

The frequency component typically is less than 2 mA/MHz, with OE at VIH.

2. ICC active while Embedded Program or Erase Algorithm is in progress.

3. Not 100% tested.

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA

ILIT A9 Input Load Current VCC = VCC Max, A9 = 13.0 V 35 µA

ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA

ICC1 VCC Active Curren t (Note 1) CE = VIL, OE = VIH Byte 40 mA

Word 50

ICC2 VCC Active Current (Notes 2, 3) CE = VIL, OE = VIH 60 mA

ICC3 VCC Standby Current VCC = VCC Max, CE = VIH, OE = VIL 1.0 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 2.0 VCC + 0.5 V

VID Voltage for Autoselect and

Temporary Sector Unprotect VCC = 5.25 Volt 10.5 13.0 V

VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V

VOH Output High Voltage IOH = –2.5 mA, VCC = VCC Min 2.4 V

VLKO Low VCC Lock-Out Voltage 3.2 4.2 V

8/18/97 Am29F800T/Am29F800B 25

PRELIMINARY

DC CHARACTERISTICS (Continued)

CMOS Compatible

Notes:

1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz).

The frequency component typically is less than 2 mA/MHz, with OE at VIH.

2. ICC active while Embedded Program or Erase Algorithm is in progress.

3. Not 100% tested.

4. ICC3 = 20

A max at extended temperatures (>+85

Parameter

Symbo l Para met er Des cri ptio n Test Condition s Min Typ Max Unit

ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA

ILIT A9 Input Load Current VCC = VCC Max, A9 = 13.0 V 35 µA

ILO Output Leakage Current VOUT = VSS to VCC,

VCC = VCC Max ±1.0 µA

ICC1 VCC Active Curren t (Note 1) CE = VIL, OE = VIH Byte 20 40 mA

Word 28 50

ICC2 VCC Active Current (Notes 2, 3) CE = VIL, OE = VIH 30 50 mA

ICC3 VCC Standby Current (Note 4) VCC = VCC Max,

CE = VCC ± 0.3 V,

OE = VIL, RESET = VCC ± 0.3 V 15µA

IL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 0.7 x VCC VCC + 0.3 V

VID Voltage for Autoselect and

Temporary Sector Unprotect VCC = 5.25 Volt 10.5 13.0 V

VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V

VOH1 Output Low Voltage IOH = –2.5 mA, VCC = VCC Min 0.85 VCC V

VOH2 IOH = –100 µA, VCC = VCC Min VCC –0.4 V

VLKO Low VCC Lock-Out Voltage 3.2 4.2 V

26 Am29F800T/Am29F800B 8/18/97

PRELIMINARY

AC CHARACTERISTICS

Read-only Operations Characteristics

Figure 7. Test Conditions

Parameter

Symbols

Description Test Setup

Speed Op tion s (Not es 1

and 2)

UnitJEDEC Standard -70 -90 -120 -150

tAVAV tRC Read Cycle Time (Note 4) Min 70 90 120 150 ns

tAVQV tACC Address to Output Delay CE = VIL Max 70 90 120 150 ns

OE = VIL

tELQV tCE Chip Enable to Output Delay OE = VIL Max 70 90 120 150 ns

tGLQV tOE Output Enable to Output Delay Max 30 35 50 55 ns

tEHQZ tDF Chip Enable to Output High Z (Notes 3, 4) Max 20 20 30 35 ns

tGHQZ tDF Output Enable to Output High Z (Notes 3, 4) Max 20 20 30 35 ns

tAXQX tOH Output Hold Time From Addresses, CE,

or OE, Whichever Occurs First Min0000ns

Ready RESET Pin Low to Read Mode (Note 4) Max 20 20 20 20 µs

tELFL CE to BYTE Switching Low or High Max 5 5 5 5 ns

tELFH

tFLQZ

BYTE Switching Low to Output High Z

(Note 3) Max 20 30 30 30 ns

Notes:

1. Test Conditions (for -70 only):

Output Load: 1 TTL gate and 30 pF

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to 3.0 V

Timing measurement reference level

input and output voltage: 1.5 V

2. Test Conditions (for all others):

Output Load: 1 TTL gate and 100 pF

Input rise and fall times: 20 ns

Input pulse levels: 0.45 V to 2.4 V

Timing measurement reference

level, input and output voltages:

0.8 V and 2.0 V

3. Output driver disable time.

4. Not 100% test ed.

2.7 kΩ

Diodes = IN3064

or Equivalent

CL6.2 kΩ

5.0 V

IN3064

or Equivalent

Notes:

For -70: CL

= 30 pF including jig capacitance

For all others: CL = 100 pF including jig capacitance

Device

Under

Test

20375C-12

8/18/97 Am29F800T/Am29F800B 27

PRELIMINARY

AC CHARACTERISTICS

Write/Erase/Pr ogram Operations

Notes:

1. This does not include the preprogramming time.

2. Not 100% tested.

3. These timings are for Temporary Sector Unprotect operation.

4. Output Driver Disable Time.

Parameter

Symbols

Description -70 -90 -120 -150 UnitJEDEC Standard

tAVAV tWC Write Cycle Time (Note 2) Min 70 90 120 150 ns

tAVWL tAS Address Setup Time Min 0 0 0 0 ns

tWLAX tAH Address Hold Time Min 45 45 50 50 ns

tDVWH tDS Data Setup Time Min 30 45 50 50 ns

tWHDX tDH Data Hold Time Min 0 0 0 0 ns

tOEH

Output

Enable

Hold Time

Read (Note 2) Min 0 0 0 0 ns

Toggle and Data Polling (Note 2) Min 10 10 1 0 10 ns

tGHWL tGHWL Read Recover Time Before Write

(OE High to WE Low) Min 0 0 0 0 ns

tELWL tCS CE Setup Time Min 0 0 0 0 ns

tWHEH tCH CE Hold Time Min 0 0 0 0 ns

tWLWH tWP Write Pulse Width Min 35 45 50 50 ns

tWHWL tWPH Write Pulse Width High Min 20 20 20 20 ns

tWHWH1 tWHWH1 Byte Programming Operation Typ 7 7 7 7 µs

tWHWH2 tWHWH2 Sector Erase Operation (Note 1) Typ1111sec

Max 8 8 8 8 sec

tVCS VCC Set Up Time (Note 2) Min 50 50 50 50 µs

tVIDR Rise Time to VID Min 500 500 500 500 ns

tRP RESET Pulse Width Min 500 500 5 00 500 ns

tBUSY Program/Erase Valid to RY/BY Delay (Note 2) Min 30 35 50 55 ns

tRSP RESET Setup Time for Temporary Sector Unprotect

(Notes 2, 3) Min 4 4 4 4 µs

28 Am29F800T/Am29F800B 8/18/97

PRELIMINARY

KEY TO SWITCHING WAVEFORMS

SWITCHING WAVEFORMS

Figure 8. AC Waveforms for Read Operations

Must Be

Steady

May

Change

from H to L

May

Change

from L to H

Does Not

Apply

Don’t Care,

Any Chang e

Permitted

Will Be

Steady

Will Be

Changing

from H to L

Will Be

Changing

from L to H

Changing,

State

Unknown

Center

Line is High-

Impedance

“Off” State

WAVEFORM INPUTS OUTPUTS

KS000010

Addresses

Outputs

Addresses Stable

High Z High Z

(tDF)

(tOH)

Output Valid

20375C-13

tACC

tOEH

tOE

(tCE)

tRC

8/18/97 Am29F800T/Am29F800B 29

PRELIMINARY

SWITCHING WAVEFORMS

Notes:

1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. DQ7 is the output of the complement of the data written to the device.

4. D

OUT

is the output of the data written to the device.

5. Figure indicates last two bus cycles of four bus cycle sequence.

6. These waveforms are for the x16 mode.

Figur e 9. Pro gr a m O pe rat i on Timin gs

Notes:

1. SA is the sector address for Sector Erase.

2. These waveforms are for the x16 mode.

Figure 10. AC Waveforms Chip/Sector Erase Operations

DOUT

tAH

Data Polling

tDF

tOH

tOE

tDS

tCS tWPH

tDH

tWP

tGHWL

Addresses

Data

5.0 V

DQ7

555H PA

A0H

3rd Bus Cycle

20375C-14

tWC tRC

tAS

tWHWH1

tCE

tAS

tWP

tCS tDH

555H 2AAH SA

Data

VCC

AAH 55H

Addresses 2AAH

tVCS

tDS

555H 555H

tWPH

tGHWL

tAH

AAH 55H80H 10H/30H

20375C-15

555 for chip erase

30 Am29F800T/Am29F800B 8/18/97

PRELIMINARY

SWITCHING WAVEFORMS

Note:

*DQ7=Valid Data (The device has completed the Embedded operation).

Figure 11. AC Waveforms for Data Polling During Em be d de d Al gor ith m O pe ra ti ons

Note:

*DQ6 stops toggling (The device has completed the Embedded operation).

Figure 12. A C Wavefor m s for Toggle Bit Dur in g Embedded Algo rith m Oper ati on s

DQ0–DQ6

Valid Data

tOE

DQ7=

Valid Data

High Z

DQ7 DQ7

DQ0–DQ6 DQ0–DQ6=Invalid

20375C-16

tOEH

tCE

tCH

tDF

tOH

tWHWH 1 or 2

tOEH

DQ6=

Stop Toggling DQ0–DQ7

Valid

DQ6=ToggleDQ6=Toggle

Data

(DQ0–DQ7)

tOE 20375C-17

8/18/97 Am29F800T/Am29F800B 31

PRELIMINARY

SWITCHING WAVEFORMS

Figure 13. RY/BY Timing Diagram During Program/Erase Operations

Figu re 14. RESE T Timing Diagram

RY/BY tBUSY

Entire programming

or erase operations

The rising edge of the last WE signal

20375C-18

RESET

20375C-19

tReady

tRP

32 Am29F800T/Am29F800B 8/18/97

PRELIMINARY

SWITCHING WAVEFORMS

Figure 15. BYTE Timing Diagram for Read Operation

Figure 16. BYTE Timing Diagram for Write Operations

BYTE

tELFL

tELFH

DQ0–DQ14 Data Output

(DQ0–DQ14) Data Ou tpu t

(DQ0–DQ7)

DQ15/A–1 DQ15

Output Address

Input

20375C-20

tFLQZ

BYTE

The falling edge of the last WE signal

tHOLD (tAH)

tSET

(tAS)

20375C-21

8/18/97 Am29F800T/Am29F800B 33

PRELIMINARY

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once again.

Figure 17 . Tempo rary S ec tor Unp ro tect Alg or ithm

Figure 18. Temporary Sector Unprotect Timing Diagram

Start

Perform Era se or

Program Operations

RESET = VIH

Tem por ary Se ctor Group

Unprote ct Com ple ted

(Note 2)

RESET = VID

(Note 1)

20375C-22

0 V or 5 V

12 V

Program or Erase Command Sequence

RESET

0 V or 5 V

tVIDR

tRSP

20375C-23

34 Am29F800T/Am29F800B 8/18/97

PRELIMINARY

AC CHARACTERISTICS

Write/Erase/Pr ogram Operations

Alternate CE Contro lled Writes

Notes:

1. This does not include the preprogramming time.

2. Not 100% tested.

Parameter

Symbols

Description -70 -90 -120 -150 UnitJEDEC Standard

tAVAV tWC Write Cycle Time (Note 2) Min 70 90 120 150 ns

tAVEL tAS Address Setup Time Min 0 0 0 0 ns

tELAX tAH Address Hold Time Min 45 45 50 50 ns

tDVEH tDS Data Setup Time Min 30 45 50 50 ns

tEHDX tDH Data Hold Time Min 0 0 0 0 ns

tOES Output Enable Setup Time Min 0 0 0 0 ns

tOEH Outp ut Ena ble

Hold Time

Read (Note 2) Min 0 0 0 0 ns

Toggle and Data Polling (Note 2) Min 10 10 10 10 ns

tGHEL tGHEL Read Recover Time Before Write Min 0 0 0 0 ns

tWLEL tWS WE Setup Time Min 0 0 0 0 ns

tEHWH tWH WE Hold Time Min 0 0 0 0 ns

tELEH tCP CE Pulse Width Min 35 45 50 50 ns

tEHEL tCPH CE Pulse Width High Min 20 20 20 20 ns

tWHWH1 tWHWH1 Byte Programming Operation Typ 7 7 7 7 µs

Word Programming Operation Typ 14 14 14 14 µs

tWHWH2 tWHWH2 Sector Erase Operation (Note 1) Typ1111sec

Max 8 8 8 8 sec

tFLQZ BYTE Switching Low to Output High Z (Note 2) Max 20 30 30 30 ns

8/18/97 Am29F800T/Am29F800B 35

PRELIMINARY

SWITCHING WAVEFORM

Notes:

1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. DQ7 is the output of the complement of the data written to the device.

4. DOUT is the output of the data written to the device.

5. Figure indicates last two bus cycles of four bus cycle sequence.

6. These waveforms are for the x16 mode.

Figu re 1 9. A l ternate CE Controlled Program Operation Timings

DOUT

tAH

Data Polling

tDS

tWS tCPH

tDH

tCP

tGHEL

Addresses

Data

5.0 Volt

DQ7

555H PA

A0H

20375C-24

tWC tAS

tWHWH1

36 Am29F800T/Am29F800B 8/18/97

PRELIMINARY

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. The typical erase and programming times assume the following conditions: 25

C, 5.0 volt VCC, 100,000 cycle s. The se

conditions do not apply to erase/program endurance. Programming typicals assume checkerboard pattern.

2. The maximum erase and programming times assume the following conditions: 90

C, 4.5 volt VCC, 100,00 0 cycle s.

3. Although Embedded Algorithms allow for longer chip program and erase time, the actual time will be considerably less since

bytes program or erase significantly faster than the worst case byte.

4. System-level overhead is defined as the time required to execute the four bus cycle command necessary to program each

byte. In the preprogramming step of the Embedded Erase algorithm, all bytes are programmed to 00H before erasure.

5. The Embedded Algorithms allow for 2.5 ms byte program time. DQ5 = “1” only after a byte takes the theoretical maximum

time to program. A minimal number of bytes may require significantly more programming pulses than the typical byte. The

majority of the bytes will program within one or two pulses. This is demonstrated by the Typical and Maximum Programming

Times listed above.

LATCHUP CHARACTERISTICS

Includes all pins except VCC. Te st cond itio ns: VCC = 5.0 V, one pin at a time.

Parameter

Limits

Unit CommentsTyp (Note 1) Max (Note 2)

Sector Erase Time 1.0 8 sec Excludes 00H programming prior to

erasure

Chip Erase Time (Note 3) 19 152 sec

Byte Programming Time (Note 5) 7 300 µs Excludes system-level overhead (Note 4)

Word Programming Time (Note 5) 14 600 µs

Chip Programming Time (Notes 3, 5) 7.2 21.6 sec

Erase/Program Endurance 1,000,000 cycles Minimum 100,000 cycles guaranteed

Min Max

Input Voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V

VCC Current –100 mA +100 mA

8/18/97 Am29F800T/Am29F800B 37

PRELIMINARY

TSOP PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25

C, f = 1.0 MHz.

SO PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25

C, f = 1.0 MHz.

DATA RETENTION

Parameter

Symbol Parameter Description Test Setup Typ Max Unit

CIN Input Capacitance VIN = 0 6 7.5 pF

COUT Output Capacitance VOUT = 0 8.5 12 pF

CIN2 Control Pin Capacitance VIN = 0 8 10 pF

Parameter

Symbol Parameter Description Test Setup Typ Max Unit

CIN Input Capacitance VIN = 0 6 7.5 pF

COUT Output Cap ac itan ce VOUT = 0 8.5 12 pF

CIN2 Control Pin Capacitance VPP = 0 8 10 pF

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time 150°C10Years

125°C20Years

38 Am29F800T/Am29F800B 8/18/97

PRELIMINARY

PHYSICAL DIMENSIONS

TS 048

48-Pin Standard Thin Small Outline Package (measured in millimeters)

18.30

18.50

19.80

20.20

11.90

12.10

0.05

0.15

0.50 BSC

0.95

1.05

16-038-TS48-2

TS 048

DA101

8-8-94 ae



Pin 1 I.D.

1.20

MAX

0.50

0.70

0.10

0.21

0.25MM (0.0098") BSC 0°

5°

0.08

0.20

8/18/97 Am29F800T/Am29F800B 39

PRELIMINARY

PHYSICAL DIMENSIONS (continued)

TSR048

48-Pin Reversed Thin Small Outline Package (measured in millimeters)

18.30

18.50

19.80

20.20

11.90

12.10

SEATING PLANE

0.05

0.15

0.50 BSC

0.95

1.05

16-038-TS48

TSR048

DA104

8-8-94 ae



Pin 1 I.D.

1.20

MAX

0.50

0.70

0.10

0.21

0.25MM (0.0098") BSC 0°

5°

0.08

0.20

40 Am29F800T/Am29F800B 8/18/97

PRELIMINARY

PHYISICAL DIMENSIONS (continued)

SO 044

44-Pin Small Outline Package (measured in millimeters)

44 23

122

13.10

13.50 15.70

16.30

1.27 NOM.

28.00

28.40

2.17

2.45

0.35

0.50 0.10

0.35

2.80

MAX. SEATING

PLANE

16-038-SO44-2

SO 044

DA82

11-9-95 lv

0.10

0.21

0.60

1.00

0°

8°

END VIEW

SIDE VIEW

TOP VIEW

8/18/97 Am29F800T/Am29F800B 41

PRELIMINARY

REVISION SUMMARY FOR Am29F800

Distinctive Characteristics:

High P erforman ce:

The fastest speed option available

is now 70 ns.

Enhanced power management for standby mode:

Changed typical standby current to 1µA.

General Description:

Added 70 ns speed option.

Produc t Se l ecto r Guide:

Adde d -70 colu mn.

Pin Config ura ti on:

Added -70 speed option.

Ordering Information, Standard Products:

The -70 speed option is now listed in the example.

Valid Combinations:

Added combinations for the -70

speed option.

Table 7, Command Definitions:

Corrected byte addresses for unlock and command cy-

cles from “2AA” to “AAA”.

In the previous data sheet re vision, the addresses for

command definitions were shortened from four hexa-

decimal digits to three. The more accurately represents

the actual address bits required, A10–A0. The remain-

ing up p er ad d res s b its a re don ’t ca re s.

The new address is compatible with the previous four-

digit definition of “AAAA”; the only dif ference is t hat the

highest-order hexadecimal digit “A” is now “don’t care”.

In fact, software programs written using the previous

four-digit definitions do not require any changes; they

rema in comp let ely com patib le with the ne w thre e-digit

defin itions.

The addresses for the byte-mode read cycles (fourth

cycle) in the autoselect mode are corrected from 01h to

02h for device ID, and from SAX02h to SAX04h for

sector protect verification.

Note 5 is clarified.

Operating Ranges:

Supply Voltages:

Added -70 speed option to the

list.

DC Characteristic s:

CMOS Compatible:

Added column f or typical ICC spec -

ifications. Revised max ICC specifications.

AC Characteristic s:

Read Only Operations Characteristics:

Added the -70

colu mn and te s t co n d itions.

Test Conditions, Figure 7:

Changed speed option i n firs t CL statement to -70.

AC Characte ristics:

Write/Erase/Program Operations, Alternate CE Con-

trolled Writes:

Added the -70 column; revised word/

byte programming and sector erase specifications.

Erase and Programm in g Pe rfor ma nce:

Revised specifications.

Trademarks

AMD, the AMD logo, and combinations thereof, and ExpressFlash are trademarks of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purpos es only and may be trademarks of their respective companies.