1. General description
The 74AVC1T45 is a single bit, dual supply transceiver with 3-state output that enables
bidirectional leve l tran sla tion. It featur es two 1-bi t in put-o utpu t p orts (A and B), a dire ction
control input (DI R) an d du a l supp ly pin s (V CC(A) and VCC(B)). Both VCC(A) and VCC(B) can
be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for
translating betwe e n an y of th e low vo ltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and
3.3 V). Pins A and DIR are referenced to VCC(A) and pin B is referenced to VCC(B). A HIGH
on DIR allows transmission from A to B and a LOW on DIR allows transmission from B to
A.
The device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at
GND level, both A and B are in the high-impedance OFF-state.
2. Features and benefits
Wide supply voltage range:
VCC(A): 0.8 V to 3.6 V
VCC(B): 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V t o 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114E Class 3B exceeds 8000 V
MM JESD22-A115 -A ex ce eds 20 0 V
CDM JESD22-C101C exceeds 1000 V
Maximum data rates:
500 Mbit/s (1.8 V to 3.3 V translation)
320 Mbit/s (< 1.8 V to 3.3 V translation)
320 Mbit/s (translate to 2.5 V or 1.8 V)
280 Mbit/s (translate to 1.5 V)
240 Mbit/s (translate to 1.2 V)
Suspend mode
Latch-up pe rform a nc e exceeds 100 mA per JESD 78 Clas s II
74AVC1T45
Dual-supply voltage level translator/transceiver; 3-state
Rev. 4 — 22 June 2012 Product data sheet
74AVC1T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 22 June 2012 2 of 23
NXP Semiconductors 74AVC1T45
Dual-supply voltage level translator/transceiver; 3-state
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from −40 °Cto+85°C and −40 °Cto+125°C
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Table 1. Ordering information
Type number Package
Temp erature range Name Description Version
74AVC1T45GW −40 °Cto+125°C SC-88 plastic surface-mounted package; 6 leads SOT363
74AVC1T45GM −40 °Cto+125°C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 1 ×1.45 ×0.5 mm SOT886
74AVC1T45GN −40 °C to +125 °C XSON6 extremely thin small outline package; no leads;
6 terminals; body 0.9 ×1.0 ×0.35 mm SOT1115
74AVC1T45GS −40 °C to +125 °C XSON6 extremely thin sma ll outline package; no leads;
6 terminals; body 1.0 ×1.0 ×0.35 mm SOT1202
Table 2. Marking
Type number Marking code[1]
74AVC1T45GW B5
74AVC1T45GM B5
74AVC1T45GN B5
74AVC1T45GS B5
Fig 1. Logic symbol Fig 2. Logic diagra m
001aag885
VCC(B)
VCC(A)
5
DIR
3
A
B
4
001aag886
VCC(B)
VCC(A)
DIR
A
B
74AVC1T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 22 June 2012 3 of 23
NXP Semiconductors 74AVC1T45
Dual-supply voltage level translator/transceiver; 3-state
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
[2] The input circuit of the data I/O is always active.
[3] The DIR input circuit is referenced to VCC(A).
[4] When either VCC(A) or VCC(B) is at GND level, the device goes into suspend mode.
Fig 3. Pin configuration SOT363 Fig 4. Pin configuration SOT886 Fig 5. Pin configuration SOT1115
and SOT1202
74AVC1T45
V
CC(A)
V
CC(B)
GND
AB
001aag971
1
2
3
6
DIR
5
4
74AVC1T45
GND
001aag972
VCC(A)
A
DIR
VCC(B)
B
Transparent top view
2
3
1
5
4
6
aaa-000876
74AVC1T45
Transparent top view
16V
CC(A) VCC(B)
25GND DIR
34AB
Table 3. Pin description
Symbol Pin Description
VCC(A) 1 supply voltage port A and DIR
GND 2 ground (0 V)
A 3 data input or output
B 4 data input or output
DIR 5 direction control
VCC(B) 6 supply voltage port B
Table 4. Function table[1]
Supply voltage Input Input/output[2]
VCC(A), VCC(B) DIR[3] A B
0.8 V to 3.6 V L A = B input
0.8 V to 3.6 V H input B = A
GND[4] XZZ
74AVC1T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 22 June 2012 4 of 23
NXP Semiconductors 74AVC1T45
Dual-supply voltage level translator/transceiver; 3-state
8. Limiting values
[1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are obs erved.
[2] VCCO is the supply voltage associated with the output port.
[3] VCCO + 0.5 V should not exceed 4.6 V.
[4] For SC-88 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the input port.
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC(A) supply voltage A −0.5 +4.6 V
VCC(B) supply voltage B −0.5 +4.6 V
IIK input clamping current VI<0V −50 - mA
VIinput voltage [1] −0.5 +4.6 V
IOK output clamping current VO<0V −50 - mA
VOoutput voltage Active mode [1][2][3] −0.5 VCCO +0.5 V
Suspend or 3-state mode [1] −0.5 +4.6 V
IOoutput current VO=0VtoV
CCO -±50 mA
ICC supply current ICC(A) or ICC(B) -100mA
IGND ground current −100 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb =−40 °C to +125 °C[4] -250mW
Table 6. Recommended operating con ditions
Symbol Parameter Conditions Min Max Unit
VCC(A) supply voltage A 0.8 3.6 V
VCC(B) supply voltage B 0.8 3.6 V
VIinput voltage 0 3.6 V
VOoutput voltage Active mode [1] 0V
CCO V
Suspend or 3-state mode 0 3.6 V
Tamb ambient temperature −40 +125 °C
Δt/ΔV input transition rise and fall rate VCCI = 0.8 V to 3.6 V [2] -5ns/V
74AVC1T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 22 June 2012 5 of 23
NXP Semiconductors 74AVC1T45
Dual-supply voltage level translator/transceiver; 3-state
10. Static characteristics
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the data input port.
[3] For I/O ports, the parameter IOZ includes the input leakage current.
Table 7. Typical static characteristics at Tamb = 25 °C[1][2]
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
VOH HIGH-level output voltage VI = VIH or VIL
IO=−1.5 mA; VCC(A) =V
CC(B) = 0.8 V - 0.69 - V
VOL LOW-level output voltage VI = VIH or VIL
IO = 1.5 mA; VCC(A) =V
CC(B) = 0.8 V - 0.07 - V
IIinput leakage current DIR input; VI = 0 V or 3.6 V;
VCC(A) =V
CC(B) = 0.8 V to 3.6 V -±0.025 ±0.25 μA
IOZ OFF-state output current A or B port; VO=0 Vor V
CCO;
VCC(A) =V
CC(B) = 0.8 V to 3.6 V [3] -±0.5 ±2.5 μA
IOFF power-off leakage current A port; VI or VO = 0 V to 3.6 V;
VCC(A) =0V;V
CC(B) = 0.8 V to 3.6 V -±0.1 ±1μA
B port; VI or VO = 0 V to 3.6 V;
VCC(B) =0V;V
CC(A) = 0.8 V to 3.6 V -±0.1 ±1μA
CIinput capacitance DIR input; VI= 0 V or 3.3 V;
VCC(A) =V
CC(B) =3.3V -1.0-pF
CI/O input/output capacitance A and B port; Suspend mode;
VO=V
CCO or GND; VCC(A) =V
CC(B) =3.3V -4.0-pF
Table 8. Static characteristics [1][2]
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °CUnit
Min Max Min Max
VIH HIGH-level
input voltage data input
VCCI = 0.8 V 0.70VCCI - 0.70VCCI -V
VCCI = 1.1 V to 1.95 V 0.65VCCI - 0.65VCCI -V
VCCI = 2.3 V to 2.7 V 1.6 - 1.6 - V
VCCI = 3.0 V to 3.6 V 2 - 2 - V
DIR input
VCC(A) = 0.8 V 0.70VCC(A) -0.70V
CC(A) -V
VCC(A) = 1.1 V to 1.95 V 0.65VCC(A) -0.65V
CC(A) -V
VCC(A) = 2.3 V to 2.7 V 1.6 - 1.6 - V
VCC(A) = 3.0 V to 3.6 V 2 - 2 - V
74AVC1T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 22 June 2012 6 of 23
NXP Semiconductors 74AVC1T45
Dual-supply voltage level translator/transceiver; 3-state
VIL LOW-level
input voltage data input
VCCI = 0.8 V - 0.30VCCI - 0.30VCCI V
VCCI = 1.1 V to 1.95 V - 0.35VCCI - 0.35VCCI V
VCCI = 2.3 V to 2.7 V - 0.7 - 0.7 V
VCCI = 3.0 V to 3.6 V - 0.9 - 0.9 V
DIR input
VCC(A) = 0.8 V - 0.30VCC(A) - 0.30VCC(A) V
VCC(A) = 1.1 V to 1.95 V - 0.35VCC(A) - 0.35VCC(A) V
VCC(A) = 2.3 V to 2.7 V - 0.7 - 0.7 V
VCC(A) = 3.0 V to 3.6 V - 0.9 - 0.9 V
VOH HIGH-level
output voltage VI = VIH or VIL
IO=−100 μA;
VCC(A) =V
CC(B) = 0.8 V to 3.6 V VCCO − 0.1 - VCCO − 0.1 - V
IO = −3mA;
VCC(A) =V
CC(B) =1.1V 0.85 - 0.85 - V
IO = −6mA;
VCC(A) =V
CC(B) =1.4V 1.05 - 1.05 - V
IO = −8mA;
VCC(A) =V
CC(B) =1.65V 1.2 - 1.2 - V
IO = −9mA;
VCC(A) =V
CC(B) =2.3V 1.75 - 1.75 - V
IO = −12 mA;
VCC(A) =V
CC(B) =3.0V 2.3 - 2.3 - V
VOL LOW-level
output voltage VI = VIH or VIL
IO = 100 μA;
VCC(A) =V
CC(B) = 0.8 V to 3.6 V -0.1-0.1V
IO = 3 mA; VCC(A) =V
CC(B) = 1.1 V - 0.25 - 0.25 V
IO = 6 mA; VCC(A) =V
CC(B) = 1.4 V - 0.35 - 0.35 V
IO = 8 mA;
VCC(A) =V
CC(B) =1.65V - 0.45 - 0.45 V
IO = 9 mA; VCC(A) =V
CC(B) = 2.3 V - 0.55 - 0.55 V
IO = 12 mA;
VCC(A) =V
CC(B) =3.0V -0.7-0.7V
IIinput leakage
current DIR input; VI = 0 V or 3.6 V;
VCC(A) =V
CC(B) = 0.8 V to 3.6 V -±1-±1.5 μA
IOZ OFF-state
output current A or B port; VO=0 Vor V
CCO;
VCC(A) =V
CC(B) =3.6V [3] -±5-±7.5 μA
IOFF power-off
leakage
current
A port; VI or VO = 0 V to 3.6 V;
VCC(A) =0V; V
CC(B) = 0.8 V to 3.6 V -±5-±35 μA
B port; VI or VO = 0 V to 3.6 V;
VCC(B) =0V; V
CC(A) = 0.8 V to 3.6 V -±5-±35 μA
Table 8. Static characteristics …continued[1][2]
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °CUnit
Min Max Min Max
74AVC1T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 22 June 2012 7 of 23
NXP Semiconductors 74AVC1T45
Dual-supply voltage level translator/transceiver; 3-state
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the data input port.
[3] For I/O ports, the parameter IOZ includes the input leakage current.
ICC supply current A port; VI = 0 V or VCCI; IO = 0 A
VCC(A) = 0.8 V to 3.6 V;
VCC(B) = 0.8 V to 3.6 V -8-12μA
VCC(A) = 3.6 V; VCC(B) = 0 V - 8 - 12 μA
VCC(A) = 0 V; VCC(B) = 3.6 V −2-−8-μA
B port; VI = 0 V or VCCI; IO = 0 A
VCC(A) = 0.8 V to 3.6 V;
VCC(B) = 0.8 V to 3.6 V -8-12μA
VCC(A) = 3.6 V; VCC(B) = 0 V −2-−8-μA
VCC(A) = 0 V; VCC(B) = 3.6 V - 8 - 12 μA
A plus B port (ICC(A) + ICC(B));
IO=0A; V
I=0 Vor V
CCI;
VCC(A) = 0.8 V to 3.6 V;
VCC(B) = 0.8 V to 3.6 V
-16-24μA
Table 8. Static characteristics …continued[1][2]
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °CUnit
Min Max Min Max
74AVC1T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 22 June 2012 8 of 23
NXP Semiconductors 74AVC1T45
Dual-supply voltage level translator/transceiver; 3-state
11. Dynamic characteristics
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.
ten is a calculated value using the formula shown in Section 13.4 “Enable times”
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.
ten is a calculated value using the formula shown in Section 13.4 “Enable times”
[1] CPD is used to determine the dynamic power dissipation (PD in μW).
PD=C
PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL×VCC2×fo) = sum of the outputs.
[2] fi = 10 MHz; VI=GNDtoV
CC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω.
Table 9. Typical dynamic characteristics at VCC(A) = 0.8 V and Tamb = 25 °C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 an d Figure 7
Symbol Parameter Conditions VCC(B) Unit
0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V
tpd propagation delay A to B 15.5 8.1 7.6 7.7 8.4 9.2 ns
B to A 15.5 12.7 12.3 12.2 12.0 11.8 ns
tdis disable time DIR to A 12.2 12.2 12.2 12.2 12.2 12.2 ns
DIR to B 11.7 7.9 7.6 8.2 8.7 10.2 ns
ten enable time DIR to A 27.2 20.6 19.9 20.4 20.7 22.0 ns
DIR to B 27.7 20.3 19.8 19.9 20.6 21.4 ns
Table 10. Typical dynamic characteristics at VCC(B) = 0.8 V and Tamb = 25 °C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 an d Figure 7
Symbol Parameter Conditions VCC(A) Unit
0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V
tpd propagation delay A to B 15.5 12.7 12.3 1 2.2 12.0 11.8 ns
B to A 15.5 8.1 7.6 7.7 8.4 9.2 ns
tdis disabl e ti me DIR to A 12.2 4.9 3.8 3.7 2.8 3.4 ns
DIR to B 11.7 9.2 9.0 8.8 8.7 8.6 ns
ten enable time DIR to A 27.2 17.3 16.6 16.5 17.1 17.8 ns
DIR to B 27.7 17.6 16.1 15.9 14.8 15.2 ns
Table 11. Typica l power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 °C [1][2]
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions VCC(A) and VCC(B) Unit
0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V
CPD power dissipation
capacitance A port: (direction A to B);
B port: (direct ion B to A) 122222pF
A port: (direction B to A);
B port: (direct ion A to B) 91111121417pF
74AVC1T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 22 June 2012 9 of 23
NXP Semiconductors 74AVC1T45
Dual-supply voltage level translator/transceiver; 3-state
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.
ten is a calculated value using the formula shown in Section 13.4 “Enable times”
Table 12 . Dynam ic characteristics for temperature range −40 °C to +85 °C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 an d Figure 7.
Symbol Parameter Conditions VCC(B) Unit
1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.1 5 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V
Min Max Min Max Min Max Min Max Min Max
VCC(A) = 1.1 V to 1.3 V
tpd propagation
delay A to B 1.0 9.0 0.7 6.8 0.6 6.1 0.5 5.7 0.5 6.1 ns
B to A 1.0 9.0 0.8 8.0 0.7 7.7 0.6 7.2 0.5 7.1 ns
tdis disable time DIR to A 2.2 8.8 2.2 8.8 2.2 8.8 2.2 8.8 2.2 8.8 ns
DIR to B 2.2 8.4 1.8 6.7 2.0 6.9 1.7 6.2 2.4 7.2 ns
ten enable time DIR to A - 17.4 - 14.7 - 14.6 - 13.4 - 14.3 ns
DIR to B - 17.8 - 15.6 - 14.9 - 14.5 - 14.9 ns
VCC(A) = 1.4 V to 1.6 V
tpd propagation
delay A to B 1.0 8.0 0.7 5.4 0.6 4.6 0.5 3.7 0.5 3.5 ns
B to A 1.0 6.8 0.8 5.4 0.7 5.1 0.6 4.7 0.5 4.5 ns
tdis disable time DIR to A 1.6 6.3 1.6 6.3 1.6 6.3 1.6 6.3 1.6 6.3 ns
DIR to B 2.0 7.6 1.8 5.9 1.6 6.0 1.2 4.8 1.7 5.5 ns
ten enable time DIR to A - 14.4 - 11.3 - 11.1 - 9.5 - 10.0 ns
DIR to B - 14.3 - 11.7 - 10.9 - 10.0 - 9.8 ns
VCC(A) = 1.65 V to 1.95 V
tpd propagation
delay A to B 1.0 7.7 0.6 5.1 0.5 4.3 0.5 3.4 0.5 3.1 ns
B to A 1.0 6.1 0.7 4.6 0.5 4.4 0.5 3.9 0.5 3.7 ns
tdis disable time DIR to A 1.6 5.5 1.6 5.5 1.6 5.5 1.6 5.5 1.6 5.5 ns
DIR to B 1.8 7.7 1.8 5.7 1.4 5.8 1.0 4.5 1.5 5.2 ns
ten enable time DIR to A - 13.8 - 10.3 - 10.2 - 8.4 - 8.9 ns
DIRtoB -13.2-10.6-9.8-8.9-8.6ns
VCC(A) = 2.3V to 2.7V
tpd propagation
delay A to B 1.0 7.2 0.5 4.7 0.5 3.9 0.5 3.0 0.5 2.6 ns
B to A 1.0 5.7 0.6 3.8 0.5 3.4 0.5 3.0 0.5 2.8 ns
tdis disable time DIR to A 1.5 4.2 1.5 4.2 1.5 4.2 1.5 4.2 1.5 4.2 ns
DIR to B 1.7 7.3 2.0 5.2 1.5 5.1 0.6 4.2 1.1 4.8 ns
ten enable time DIR to A - 13.0 - 9.0 - 8.5 - 7.2 - 7.6 ns
DIR to B - 11.4 - 8.9 - 8.1 - 7.2 - 6.8 ns
VCC(A) = 3.0V to 3.6V
tpd propagation
delay A to B 1.0 7.1 0.5 4.5 0.5 3.7 0.5 2.8 0.5 2.4 ns
B to A 1.0 6.1 0.6 3.6 0.5 3.1 0.5 2.6 0.5 2.4 ns
tdis disable time DIR to A 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 ns
DIR to B 1.7 7.2 0.7 5.5 0.6 5.5 0.7 4.1 1.7 4.7 ns
ten enable time DIR to A - 13.3 - 9.1 - 8.6 - 6.7 - 7.1 ns
DIR to B - 11.8 - 9.2 - 8.4 - 7.5 - 7.1 ns
74AVC1T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 22 June 2012 10 of 23
NXP Semiconductors 74AVC1T45
Dual-supply voltage level translator/transceiver; 3-state
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.
ten is a calculated value using the formula shown in Section 13.4 “Enable times”
Table 13 . Dynam ic characteristics for temperature range −40 °C to +125 °C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 an d Figure 7
Symbol Parameter Conditions VCC(B) Unit
1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V
Min Max Min Max Min Max Min Max Min Max
VCC(A) = 1.1 V to 1.3 V
tpd propagation
delay A to B 1.0 9.9 0.7 7.5 0.6 6.8 0.5 6.3 0.5 6.8 ns
B to A 1.0 9.9 0.8 8.8 0.7 8.5 0.6 8.0 0.5 7.9 ns
tdis disable time DIR to A 2.2 9.7 2.2 9.7 2.2 9.7 2.2 9.7 2.2 9.7 ns
DIR to B 2.2 9.2 1.8 7.4 2.0 7.6 1.7 6.9 2.4 8.0 ns
ten enable time DIR to A - 19.1 - 16.2 - 16.1 - 14.9 - 15.9 ns
DIR to B - 19.6 - 17.2 - 16.5 - 16.0 - 16.5 ns
VCC(A) = 1.4 V to 1.6 V
tpd propagation
delay A to B 1.0 8.8 0.7 6.0 0.6 5.1 0.5 4.1 0.5 3.9 ns
B to A 1.0 7.5 0.8 6.0 0.7 5.7 0.6 5.2 0.5 5.0 ns
tdis disable time DIR to A 1.6 7.0 1.6 7.0 1.6 7.0 1.6 7.0 1.6 7.0 ns
DIR to B 2.0 8.3 1.8 6.5 1.6 6.6 1.2 5.3 1.7 6.1 ns
ten enable time DIR to A - 15.8 - 12.5 - 12.3 - 10.5 - 11.1 ns
DIR to B - 15.8 - 13.0 - 12.1 - 11.1 - 10.9 ns
VCC(A) = 1.65 V to 1.95 V
tpd propagation
delay A to B 1.0 8.5 0.6 5.7 0.5 4.8 0.5 3.8 0.5 3.5 ns
B to A 1.0 6.8 0.7 5.1 0.5 4.9 0.5 4.3 0.5 4.1 ns
tdis disable time DIR to A 1.6 6.1 1.6 6.1 1.6 6.1 1.6 6.1 1.6 6.1 ns
DIR to B 1.8 8.5 1.8 6.3 1.4 6.4 1.0 5.0 1.5 5.8 ns
ten enable time DIR to A - 15.3 - 11.4 - 11.3 - 9.3 - 9.9 ns
DIR to B - 14.6 - 11.8 - 10.9 - 9.9 - 9.6 ns
VCC(A) = 2.3V to 2.7V
tpd propagation
delay A to B 1.0 8.0 0.5 5.2 0.5 4.3 0.5 3.3 0.5 2.9 ns
B to A 1.0 6.3 0.6 4.2 0.5 3.8 0.5 3.3 0.5 3.1 ns
tdis disable time DIR to A 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 ns
DIR to B 1.7 8.0 2.0 5.8 1.5 5.7 0.6 4.7 1.1 5.3 ns
ten enable time DIR to A - 14.3 - 10.0 - 9.5 - 8.0 - 8.4 ns
DIR to B - 12.7 - 9.9 - 9.0 - 8.0 - 7.6 ns
VCC(A) = 3.0V to 3.6V
tpd propagation
delay A to B 1.0 7.9 0.5 5.0 0.5 4.1 0.5 3.1 0.5 2.7 ns
B to A 1.0 6.8 0.6 4.0 0.5 3.5 0.5 2.9 0.5 2.7 ns
tdis disable time DIR to A 1.5 5.2 1.5 5.2 1.5 5.2 1.5 5.2 1.5 5.2 ns
DIR to B 1.7 7.9 0.7 6.1 0.6 6.1 0.7 4.6 1.7 5.2 ns
ten enable time DIR to A - 14.7 - 10.1 - 9.6 - 7.5 - 7.9 ns
DIR to B - 13.1 - 10.2 - 9.3 - 8.3 - 7.9 ns
74AVC1T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 22 June 2012 11 of 23
NXP Semiconductors 74AVC1T45
Dual-supply voltage level translator/transceiver; 3-state
12. Waveforms
[1] VCCI is the supply voltage associated with the data input port.
[2] VCCO is the supply voltage associated with the output port.
Measurement points are given in Table 14.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 6. The data input (A, B) to output (B, A) propagatio n delay times
001aae967
A, B input
B, A output
tPLH
tPHL
GND
VI
VOH
VM
VM
VOL
Measurement points are given in Table 14.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 7. Enable and disable times
001aae968
t
PZL
t
PZH
t
PHZ
t
PLZ
GND
GND
V
I
V
CCO
V
OL
V
OH
V
M
V
M
V
M
V
X
V
Y
outputs
disabled outputs
enabled
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
DIR input
Table 14 . Measurement points
Supply voltage Input[1] Output[2]
VCC(A), VCC(B) VMVMVXVY
1.1 V to 1.6 V 0.5VCCI 0.5VCCO VOL +0.1V V
OH −0.1 V
1.65 V to 2.7 V 0.5VCCI 0.5VCCO VOL +0.15V V
OH −0.15 V
3.0 V to 3.6 V 0.5VCCI 0.5VCCO VOL +0.3V V
OH −0.3 V
74AVC1T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 22 June 2012 12 of 23
NXP Semiconductors 74AVC1T45
Dual-supply voltage level translator/transceiver; 3-state
[1] VCCI is the supply voltage associated with the data input port.
[2] dV/dt ≥ 1.0 V/ns
[3] VCCO is the supply voltage associated with the output port.
Test data is given in Table 15.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance.
VEXT = External voltage for measuring switching times.
Fig 8. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aae331
V
EXT
V
CC
V
I
V
O
DUT
CL
RT
RL
RL
G
Table 15 . Test data
Supply voltage Input Load VEXT
VCC(A), VCC(B) VI[1] Δt/ΔV[2] CLRLtPLH, tPHL tPZH, tPHZ tPZL, tPLZ[3]
1.1 V to 1.6 V VCCI ≤ 1.0ns/V 15pF 2kΩopen GND 2VCCO
1.65 V to 2.7 V VCCI ≤ 1.0ns/V 15pF 2kΩopen GND 2VCCO
3.0 V to 3.6 V VCCI ≤ 1.0ns/V 15pF 2kΩopen GND 2VCCO
74AVC1T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 22 June 2012 13 of 23
NXP Semiconductors 74AVC1T45
Dual-supply voltage level translator/transceiver; 3-state
13. Application information
13.1 Unidirectional logic level-shifting application
The circuit given in Figure 9 is an example of the 74AVC1T45 being used in an
unidirectional logic level-shifting application.
Fig 9. Unidirectional logic le vel-shifting application
Table 16. Description un idirectional logic level-shifting application
Pin Name Function Description
1V
CC(A) VCC1 supply voltage of system-1 (0.8 V to 3.6 V)
2 GND GND device GND
3 A OUT output level depends on VCC1 voltage
4 DIR DIR the GND (LOW level) determines B port to A port direction
5 B IN inpu t threshold value depends on VCC2 voltage
6V
CC(B) VCC2 supply voltage of system-2 (0.8 V to 3.6 V)
001aag973
74AVC1T45
1
V
CC(A)
2
GND
3
6
5
4
A
V
CC(B)
V
CC2
V
CC2
DIR
system-2
system-1
B
V
CC1
V
CC1
74AVC1T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 22 June 2012 14 of 23
NXP Semiconductors 74AVC1T45
Dual-supply voltage level translator/transceiver; 3-state
13.2 Bidirectional logic level-shifting application
Figure 10 shows the 74AVC1T45 being used in a bidirectional logic level-shifting
application. Sinc e th e de vice does no t ha ve an output enable pin, the system designer
should take precautions to avoid bus contention between system-1 and system-2 when
changing directions.
Table 17 gives a sequence that will illustrate dat a transmission from system-1 to system-2
and then from system-2 to system-1.
[1] H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
Fig 10. Bidirectional logic level-shifting application
Tabl e 17. Description bidirectional logic level-shi fting applicat ion[1]
State DIR CTRL I/O-1 I/O-2 Description
1 H output input system-1 data to system-2
2 H Z Z system-2 is getting ready to send data to system-1.
I/O-1 and I/O-2 are disabled. The bus-line state
depends on bus hold.
3 L Z Z DIR bit is set LOW. I/O-1 and I/O-2 still are disabled.
The bus-line state depends on bus hold.
4 L input output system-2 data to system-1
001aag974
DIR CTRL
I/O-1
V
CC1
I/O-2
74AVC1T45
1
V
CC(A)
V
CC1
V
CC2
2
GND
3
6
5
4
A
V
CC(B)
DIR
B
PULL-UP/DOWN
system-1 system-2
PULL-UP/DOWN
V
CC2
74AVC1T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 22 June 2012 15 of 23
NXP Semiconductors 74AVC1T45
Dual-supply voltage level translator/transceiver; 3-state
13.3 Power-up considerations
The device is designed such that no special power-up sequence is required other than
GND being applied first.
13.4 Enable times
Calculate the enable times for the 74AVC1T45 using the following formulas:
•ten (DIR to A) = tdis (DIR to B) + tpd (B to A)
•ten (DIR to B) = tdis (DIR to A) + tpd (A to B)
In a bidirectional application, these enable times provide the maximum delay from the
time the DIR bit is switched until an output is expected. For example, if the 74AVC1T45
initially is transmitting from A to B, then the DIR bit is switched, the B port of the device
must be disabled before presen ting it with an input. Afte r the B port has been disabled, an
input signal applied to it appears on the corresponding A port after the specified
propagation delay.
Table 18. Typical total supply current (ICC(A) + ICC(B))
VCC(A) VCC(B) Unit
0 V 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V
0 V0 0.10.10.10.10.10.1μA
0.8 V 0.1 0.1 0.1 0.1 0.1 0.7 2.3 μA
1.2 V 0.1 0.1 0.1 0.1 0.1 0.3 1.4 μA
1.5 V 0.1 0.1 0.1 0.1 0.1 0.1 0.9 μA
1.8 V 0.1 0.1 0.1 0.1 0.1 0.1 0.5 μA
2.5 V 0.1 0.7 0.3 0.1 0.1 0.1 0.1 μA
3.3 V 0.1 2.3 1.4 0.9 0.5 0.1 0.1 μA
74AVC1T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 22 June 2012 16 of 23
NXP Semiconductors 74AVC1T45
Dual-supply voltage level translator/transceiver; 3-state
14. Package outline
Fig 11. Package outline SOT3 63 (SC-88 )
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT363 SC-88
wBM
bp
D
e1
e
pin 1
index A
A1
Lp
Q
detail X
HE
E
vMA
AB
y
0 1 2 mm
scale
c
X
132
456
Plastic surface-mounted package; 6 leads SOT363
UNIT A1
max bpcDEe1HELpQywv
mm 0.1 0.30
0.20 2.2
1.8
0.25
0.10 1.35
1.15 0.65
e
1.3 2.2
2.0 0.2 0.10.2
DIMENSIONS (mm are the original dimensions)
0.45
0.15 0.25
0.15
A
1.1
0.8
04-11-08
06-03-16
74AVC1T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 22 June 2012 17 of 23
NXP Semiconductors 74AVC1T45
Dual-supply voltage level translator/transceiver; 3-state
Fig 12. Package outline SOT886 (XSON6)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT886 MO-252
sot886_po
04-07-22
12-01-05
Unit
mm max
nom
min
0.5 0.04 1.50
1.45
1.40
1.05
1.00
0.95
0.35
0.30
0.27
0.40
0.35
0.32
0.6
A(1)
Dimensions (mm are the original dimensions)
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886
A1b
0.25
0.20
0.17
DEee
1
0.5
LL
1
terminal 1
index area
D
E
e1
e
A1
b
L
L1
e1
0 1 2 mm
scale
1
6
2
5
3
4
6x
(2)
4x
(2)
A
74AVC1T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 22 June 2012 18 of 23
NXP Semiconductors 74AVC1T45
Dual-supply voltage level translator/transceiver; 3-state
Fig 13. Package outline SOT1115 (XSON6)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT1115
sot1115_po
10-04-02
10-04-07
Unit
mm max
nom
min
0.35 0.04 0.95
0.90
0.85
1.05
1.00
0.95 0.55 0.3 0.40
0.35
0.32
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON6: extremely thin small outline package; no leads;
6 terminals; body 0.9 x 1.0 x 0.35 mm SOT1115
A1b
0.20
0.15
0.12
DEee
1L
0.35
0.30
0.27
L1
0 0.5 1 mm
scale
terminal 1
index area
D
E
(4×)(2)
e1e1
e
L
L1
b
321
6 5 4
(6×)(2) A1A
74AVC1T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 22 June 2012 19 of 23
NXP Semiconductors 74AVC1T45
Dual-supply voltage level translator/transceiver; 3-state
Fig 14. Package outline SOT1202 (XSON6)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT1202
sot1202_po
10-04-02
10-04-06
Unit
mm max
nom
min
0.35 0.04 1.05
1.00
0.95
1.05
1.00
0.95 0.55 0.35 0.40
0.35
0.32
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON6: extremely thin small outline package; no leads;
6 terminals; body 1.0 x 1.0 x 0.35 mm SOT1202
A1b
0.20
0.15
0.12
DEee
1L
0.35
0.30
0.27
L1
0 0.5 1 mm
scale
terminal 1
index area
D
E
(4×)(2)
e1e1
e
L
b
123
L1
6 5 4
(6×)(2)
A
A1
74AVC1T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 22 June 2012 20 of 23
NXP Semiconductors 74AVC1T45
Dual-supply voltage level translator/transceiver; 3-state
15. Abbreviations
16. Revision history
Table 19. Abbreviations
Acronym Description
CDM Charged Device Mo del
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
Table 20. Revision history
Document ID Release date Data sheet st atus Change notice Supersedes
74AV C1T45 v.4 20120622 Product data sheet - 74AVC1T45 v.3
Modifications: •Package outline drawing of SOT886 (Figure 12) modifi ed.
74AV C1T45 v.3 20111021 Product data sheet - 74AVC1T45 v.2
Modifications: •Added type number 74AVC1T45GN (SOT1115/XSON6 package).
•Added type number 74AVC1T45GS (SOT1202/XSON6 package).
74AV C1T45 v.2 20090505 Product data sheet - 74AVC1T45 v.1
74AV C1T45 v.1 20080118 Product data sheet - -
74AVC1T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 22 June 2012 21 of 23
NXP Semiconductors 74AVC1T45
Dual-supply voltage level translator/transceiver; 3-state
17. Legal information
17.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short dat a sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
17.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidenta l ,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semi conductors’ aggreg ate and cumulative liabil ity towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe prop erty or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for il lustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconduc tors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly object s to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Not hing in this document may be interpret ed or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyri ghts, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
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Product data sheet Rev. 4 — 22 June 2012 22 of 23
NXP Semiconductors 74AVC1T45
Dual-supply voltage level translator/transceiver; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It i s neit her qua lified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equ ipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever cust omer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
17.4 Trademarks
Notice: All refe renced brands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74AVC1T45
Dual-supply voltage level translator/transceiver; 3-state
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 22 June 2012
Document identifier: 74AVC1T45
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
19. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 3
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
9 Recommended operating conditions. . . . . . . . 4
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
13 Application information. . . . . . . . . . . . . . . . . . 13
13.1 Unidirectional logic level-shifting application . 13
13.2 Bidirectional logic level-shifting application. . . 14
13.3 Power-up considerations . . . . . . . . . . . . . . . . 15
13.4 Enable times. . . . . . . . . . . . . . . . . . . . . . . . . . 15
14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
15 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20
16 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20
17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
17.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
17.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
17.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
18 Contact information. . . . . . . . . . . . . . . . . . . . . 22
19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
