© Semiconductor Components Industries, LLC, 2011
August, 2011 − Rev. 0
1Publication Order Number:
NL17SHT32/D
NL17SHT32
2-Input OR Gate /
CMOS Logic Level Shifter
The NL17SHT32 is an advanced high speed CMOS 2−input OR
gate fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and
the output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic−level translator from 3 V
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V
CMOS Logic while operating at the high−voltage power supply.
The NL17SHT32 input structure provides protection when voltages
up to 7 V are applied, regardless of the supply voltage. This allows the
NL17SHT32 to be used to interface 5 V circuits to 3 V circuits. The
output structures also provide protection when VCC = 0 V. These input
and output structures help prevent device destruction caused by supply
voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
Features
•High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V
•Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C
•TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2 V
•CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
•Power Down Protection Provided on Inputs and Outputs
•Balanced Propagation Delays
•Pin and Function Compatible with Other Standard Logic Families
•These are Pb−Free Devices
Figure 1. Pinout (Top View)
VCC
IN B
IN A
OUT Y
GND
IN A
IN B OUT Y
≥ 1
Figure 2. Logic Symbol
1
2
34
5
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MARKING
DIAGRAM
PIN ASSIGNMENT
1
2
3IN B
IN A
GND
4
5V
CC
OUT Y
L
L
H
H
L
H
L
H
FUNCTION TABLE
Inputs Output
AB
L
H
H
H
Y
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
SOT−953
CASE 527AE
Q = Specific Device Code
M = Month Code
QM
1
NL17SHT32
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2
MAXIMUM RATINGS
Symbol Characteristics Value Unit
VCC DC Supply Voltage −0.5 to +7.0 V
VIN DC Input Voltage −0.5 to +7.0 V
VOUT DC Output Voltage VCC = 0
High or Low State
−0.5 to 7.0
−0.5 to VCC + 0.5
V
IIK Input Diode Current −20 mA
IOK Output Diode Current VOUT < GND; VOUT > VCC ±20 mA
IOUT DC Output Current ±25 mA
ICC DC Supply Current, VCC and GND 50 mA
PDPower dissipation in still air 50 mW
TLLead temperature, 1 mm from case for 10 s 260 °C
TJJunction temperature under bias +150 °C
Tstg Storage temperature −65 to +150 °C
ILatchup Latchup Performance Above VCC and Below GND at 125°C (Note 1) ±100 mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol Characteristics Min Max Unit
VCC DC Supply Voltage 3.0 5.5 V
VIN DC Input Voltage 0.0 5.5 V
VOUT DC Output Voltage VCC = 0
High or Low State
0.0
0.0
5.5
VCC
V
TAOperating Temperature Range −55 +125 °C
tr , tfInput Rise and Fall Time VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V
0
0
100
20
ns/V
Device Junction Temperature versus
Time to 0.1% Bond Failures
Junction
Temperature °CTime, Hours Time, Years
80 1,032,200 117.8
90 419,300 47.9
100 178,700 20.4
110 79,600 9.4
120 37,000 4.2
130 17,800 2.0
140 8,900 1.0
1
1 10 100 1000
TIME, YEARS
NORMALIZED FAILURE RATE
TJ= 80 C°
TJ= 90 C°
TJ= 100 C°
TJ= 110 C°
TJ= 130 C°
TJ= 120 C°
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Figure 3. Failure Rate vs. Time Junction Temperature
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3
DC ELECTRICAL CHARACTERISTICS
VCC TA = 25°C TA ≤ 85°C−55 ≤ TA ≤ 125°C
Symbol Parameter Test Conditions (V) Min Typ Max Min Max Min Max Unit
VIH Minimum High−Level
Input Voltage
3.0
4.5
5.5
1.4
2.0
2.0
1.4
2.0
2.0
1.4
2.0
2.0
V
VIL Maximum Low−Level
Input Voltage
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
VOH Minimum High−Level
Output Voltage
VIN = VIH or VIL
VIN = VIH or VIL
IOH = −50 mA
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.4
V
VIN = VIH or VIL
IOH = −4 mA
IOH = −8 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
VOL Maximum Low−Level
Output Voltage
VIN = VIH or VIL
VIN = VIH or VIL
IOL = 50 mA
3.0
4.5
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN = VIH or VIL
IOL = 4 mA
IOL = 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
V
IIN Maximum Input
Leakage Current
VIN = 5.5 V or GND 0 to
5.5
±0.1 ±1.0 ±1.0 mA
ICC Maximum Quiescent
Supply Current
VIN = VCC or GND 5.5 2.0 20 40 mA
ICCT Quiescent Supply
Current
Input: VIN = 3.4 V 5.5 1.35 1.50 1.65 mA
IOPD Output Leakage
Current
VOUT = 5.5 V 0.0 0.5 5.0 10 mA
AC ELECTRICAL CHARACTERISTICS (Cload = 50 pF, Input tr = tf = 3.0ns)
Symbol Parameter Test Conditions
TA = 25°C TA ≤ 85°C−55 ≤ TA ≤ 125°C
Unit
Min Typ Max Min Max Min Max
tPLH,
tPHL
Maximum
Propagation Delay,
Input A or B to Y
VCC = 3.3 ± 0.3 V CL = 15 pF
CL = 50 pF
4.8
6.1
7.9
11.4
9.5
13.0
11.5
15.5
ns
VCC = 5.0 ± 0.5 V CL = 15 pF
CL = 50 pF
3.7
4.4
5.5
7.5
6.5
8.5
8.0
10.0
CIN Maximum Input
Capacitance
5.5 10 10 10 pF
CPD Power Dissipation Capacitance (Note 2)
Typical @ 25°C, VCC = 5.0 V
pF
11
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
NL17SHT32
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4
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 4. Switching Waveforms
Figure 5. Test Circuit
GND
50%
50% VCC
Input A or B
Output Y
tPHL
tPLH
50% VCC
VOL
VOH
ORDERING INFORMATION
Device Package Shipping†
NL17SHT32P5T5G SOT−953
(Pb−Free)
8000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NL17SHT32
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5
PACKAGE DIMENSIONS
SOT−953
CASE 527AE
ISSUE E
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
E
D
C
A
HE
123
45
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF THE BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
DIM MIN NOM MAX
MILLIMETERS
A0.34 0.37 0.40
b0.10 0.15 0.20
C0.07 0.12 0.17
D0.95 1.00 1.05
E0.75 0.80 0.85
e0.35 BSC
L
0.95 1.00 1.05
HE
X
Y
PIN ONE
INDICATOR
b
5X
X0.08 Y
L
5X
L3
L2
e
5X
5X
L2 0.05 0.10 0.15
L3 −−− −−− 0.15
0.175 REF
TOP VIEW
SIDE VIEW
BOTTOM VIEW 1.20
DIMENSIONS: MILLIMETERS
0.20
5X
1
PACKAGE
OUTLINE
0.35
PITCH
0.35
5X
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Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
NL17SHT32/D
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