CBTL02043ABQ,115\"\" - NXP SEMICONDUCTORS

1. General description

CBTL02043A/B is a 2 diff erential channel, 2-to-1 multiplexer/demultiplexer switch for

USB 3.1, PCI Express Generatio n 3, or other high- speed serial interface applications. The

CBTL02043A/B can switch two dif fe rential sign als to one of two loca tions. Using a unique

design technique, NXP has minimized the impedance of the switch such that the

attenuation observed through the switch is negligible, and also minimized the

channel-to-channel skew as well as channel-to-channel crosstalk, as required by the

high-speed seria l interface. CBTL02043A/B al lows expansion of existing high- speed ports

for extremely low power.

The device's pinouts are optimized to match different application layouts. CBTL02043A

has input and output pins on the opposite of the package, and is suitable for edge

connector(s) with different signal sources on the motherboa rd. CBTL02043B has outputs

on both sides of the package, and the device can be placed between two connectors to

multiplex differential signals from a controller. Please refer to Section 8 for layout

examples.

2. Features and benefits

2 bidirectional differential channel, 2 : 1 multiplexer/demultiplexer

High-speed signal switching for 10 Gbps applications

High bandwidth: 10 GHz at 3dB

Low insertion loss:

0.5 dB at 100 MHz

1.3 dB at 4.0 GHz

Low return loss: 13.5dB at 4GHz

Low crosstalk: 35 dB at 4 GHz

Low off-state isolation: 20 dB at 4 GHz

Low intra-pair skew: 5 ps typical

Low inter-pair skew: 35 ps maximum

VDD operating range: 3.3 V 10 %

Shutdown pin (XSD) for power-saving mode

Standby current less than 1 A

ESD tolerance:

2000 V HBM

1000 V CDM

DHVQFN20 package

CBTL02043A; CBTL02043B

3.3 V, 2 differential channel, 2 : 1 multiplexer/demultiplexer

switch

Rev. 4.1 — 30 March 2015 Product data sheet

Product data sheet Rev. 4.1 — 30 March 2015 2 of 19

NXP Semiconductors CBTL02043A; CBTL02043B

3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch

3. Applications

Routing of high-speed differential signals with low signal attenuation

PCIe Gen3

DisplayPort 1.2

USB 3.1

SATA 6 Gbit/s

4. Ordering information

[1] Total height after printed-circuit board mounting = 1.0 mm maximum.

4.1 Ordering options

Table 1. Ordering information

Type number Topside

marking Package

Name Description Version

CBTL02043ABQ TL02043A DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad

flat package; no leads; 20 terminals;

body 2.5 4.5 0.85 mm[1]

SOT764-1

CBTL02043BBQ TL02043B DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad

flat package; no leads; 20 terminals;

body 2.5 4.5 0.85 mm[1]

SOT764-1

Table 2. Ordering options

Type number Orderable

part number Package Packing method Minimum

order

quantity

Temperature

CBTL02043ABQ CBTL02043ABQ,115 DHVQFN20 Reel 7” Q1/T1

*standard mark SMD 3000 Tamb =40 Cto+85C

CBTL02043BBQ CBTL02043BBQ,115 DHVQFN20 Reel 7” Q1/T1

*standard mark SMD 3000 Tamb =40 Cto+85C

Product data sheet Rev. 4.1 — 30 March 2015 3 of 19

NXP Semiconductors CBTL02043A; CBTL02043B

3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch

5. Functional diagram

6. Pinning information

6.1 Pinning

Fig 1. Functional diagram of CBTL02043A; CBTL02043B

002aaf073

B0_P

B0_N

B1_P

B1_N

A0_P

A0_N

A1_P

A1_N

C0_P

C0_N

C1_P

C1_N

SEL

XSD

a. CBTL02043A b. CBTL02043B

Fig 2. Pin configuration for DHVQFN20

002aaf912

CBTL02043A

Transparent top view

C1_N

A1_N

SEL

C1_P

A1_P C0_N

VDD C0_P

GND B1_N

A0_N B1_P

A0_P B0_N

XSD B0_P

VDD

GND

VDD

GND

912

8 13

7 14

6 15

5 16

4 17

3 18

2 19

terminal 1

index area

002aaf913

CBTL02043B

Transparent top view

SEL

C1_P

C1_N

B1_N

A1_N B1_P

A1_P GND

C0_N VDD

C0_P B0_N

A0_N B0_P

A0_P XSD

GND

VDD

GND

VDD

912

8 13

7 14

6 15

5 16

4 17

3 18

2 19

terminal 1

index area

Product data sheet Rev. 4.1 — 30 March 2015 4 of 19

NXP Semiconductors CBTL02043A; CBTL02043B

3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch

6.2 Pin description

[1] DHVQFN20 package die supply ground is connected to both GND pins and exposed center pad. GND pins

and the exposed center pad must be connected to supply ground for proper device operation. For

enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the

board using a corresponding thermal pad on the board and for proper heat conduction through the board,

thermal vias need to be incorporated in the printed-circuit board in the thermal pad region.

Table 3. Pin description

Symbol Pin Type Description

CBTL02043A CBTL02043B

A0_P 3 2 I/O channel 0, port A differential signal

input/output

A0_N 4 3 I/O

A1_P 7 6 I/O channel 1, port A differential signal

input/output

A1_N 8 7 I/O

B0_P 19 18 I/O channel 0, port B differential signal

input/output

B0_N 18 17 I/O

B1_P 17 14 I/O channel 1, port B differential signal

input/output

B1_N 16 13 I/O

C0_P 15 4 I/O channel 0, port C differential signal

input/output

C0_N 14 5 I/O

C1_P 13 8 I/O channel 1, port C differential signal

input/output

C1_N 12 9 I/O

SEL 9 12 CMOS

single-ended

input

operation mode select

SEL = LOW: A B

SEL = HIGH: A C

XSD 2 19 CMOS

single-ended

input

Shutdown pin; should be driven

LOW or connected to VSS for

normal operation. When HIGH, all

paths are switched off

(non-conducting high-imped ance

state), and supply current

consumption is minimized.

VDD 1, 6, 10 11, 16, 20 power positive supply voltage,

3.3 V (10 %)

GND[1] 5, 11, 20,

center pad 1, 10, 15,

center pad power supply ground

Product data sheet Rev. 4.1 — 30 March 2015 5 of 19

NXP Semiconductors CBTL02043A; CBTL02043B

3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch

7. Functional description

Refer to Figure 1 “Functional diagram of CBTL02043A; CBTL02043B”.

7.1 Function selection and shutdown function

The CBTL02043A/B provides a shutdown function to minimize power consumption when

the application is not active, but power to the CBTL02043A/B is provided. The XSD pin

(active HIGH) places all channels in high-impedance state (non-conducting) while

reducing current consumption to near-zero. When XSD pin is LOW, the device operates

normally.

Table 4. Function selection

X = Don’t care.

XSD SEL Function

HIGH X An, Bn and Cn pins are high-Z

LOW LOW An to Bn and vice versa

LOW HIGH An to Cn and vice versa

Product data sheet Rev. 4.1 — 30 March 2015 6 of 19

NXP Semiconductors CBTL02043A; CBTL02043B

3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch

8. Application design-in information

Fig 3. Applications using CBTL02043A

Fig 4. Application using CBTL02043B

002aaf914

MINI CARD/

mSATA

CONNECTOR

CBTL02043A

eSATA

CONTROLLER

PCIe

CONTROLLER

eSATA/USB 3.1

COMBO

CONNECTOR

CBTL02043A

eSATA

CONTROLLER

USB 3.1

CONTROLLER

002aaf915

USB 3.1

CONNECTOR

CBTL02043B

USB 3.1

CONTROLLER

USB 3.1

CONNECTOR

Product data sheet Rev. 4.1 — 30 March 2015 7 of 19

NXP Semiconductors CBTL02043A; CBTL02043B

3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch

9. Limiting values

[1] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model -

Component level; Electrostatic Discharge Association, Rome, NY, USA.

[2] Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device

Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.

10. Recommended operating conditions

11. Static characteristics

[1] Typical values are at VDD = 3.3 V, Tamb =25C, and maximum loading.

[2] Input leakage current is 50 A if differential pairs are pulled to HIGH and LOW.

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 0.3 +4.6 V

Tcase case temperature 40 +85 C

Tstg storage temperature 65 +150 C

VESD electrostatic discharge voltage HBM [1] - 2000 V

CDM [2] - 1000 V

Table 6. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

VDD supply voltage 3.0 3.3 3.6 V

VIinput voltage - - VDD V

Tamb ambient temperature operating in free air 40 - +85 C

Table 7. Static characteristics

VDD = 3.3 V



10 %; Tamb =





C to +85



C; unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

IDD supply current operating mode;

VDD = max.; XSD = LOW -1.352.5mA

shutdown mode;

VDD = max.; XSD = HIGH --1A

IIH HIGH-level input current VDD = max.; VI=V

DD --5[2] A

IIL LOW-level input current VDD = max.; VI=GND - - 5[2] A

VIH HIGH-level input voltage SEL, XSD pins 0.65VDD -- V

VIL LOW-level input voltage SEL, XSD pins - - 0.35VDD V

VIinput voltage differential pins - - 2.4 V

SEL, XSD pins - - VDD V

VIC common-mode input

voltage 0-2V

VID differential input voltage peak-to-peak - - 1.6 V

Product data sheet Rev. 4.1 — 30 March 2015 8 of 19

NXP Semiconductors CBTL02043A; CBTL02043B

3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch

12. Dynamic characteristics

[1] Typical values are at VDD = 3.3 V; Tamb =25C, and maximum loading.

Table 8. Dynamic characteristics

VDD =3.3V



10 %; Tamb =





C to +85



C; unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

DDIL differential insertion loss channel is OFF

f=4GHz - 20 - dB

f=100MHz - 50 - dB

channel is ON

f=4GHz - 1.3 - dB

f=100MHz - 0.5 - dB

DDNEXT differential near-end crosstalk adjacent channels are ON

f=4GHz - 35 - dB

f=100MHz - 65 - dB

B3dB 3 dB bandwidth - 10 - GHz

DDRL differential return loss f = 4 GHz - 13.5 - dB

f=100MHz - 25 - dB

Ron ON-state resistance VDD =3.3V; V

I=2V;

II=19mA -6-

Cio(on) on-state input/output capacitance - 1.5 - pF

tPD propagation delay from Port A to Port B, or

Port A to Port C, or vice versa -60-ps

Switching characteristics

tstartup start-up time supply voltage valid or

XSD goin g LO W to cha nn e l

specified operating conditions

--10ms

tPZH OFF-state to HIGH propagation delay - - 300 ns

tPZL OFF-state to LOW propagation delay - - 70 ns

tPHZ HIGH to OFF-state propagation delay - - 50 ns

tPLZ LOW to OFF-state propagation delay - - 50 ns

tsk(dif) differential skew time intra-pair - 5 - ps

tsk skew time inter-pair - - 35 ps

Product data sheet Rev. 4.1 — 30 March 2015 9 of 19

NXP Semiconductors CBTL02043A; CBTL02043B

3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch

Output 1 is for an output with internal conditions such that the output is LOW except when disabled

by the output control.

Output 2 is for an output with internal conditions such that the output is HIGH except when disabled

by the output control.

The outputs are measured one at a time with one transition per measurement.

Fig 5. Voltage waveforms for enable and disable times

002aag013

VDD

tPLZ

0.5VDD 0.5VDD

SEL

output 1

tPZL

VOL

0 V

0.85VOH

VOH

0.25VOH

output 2

tPZH tPHZ

VOL

VOH

0.85VOH

0.25VOH

Product data sheet Rev. 4.1 — 30 March 2015 10 of 19

NXP Semiconductors CBTL02043A; CBTL02043B

3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch

13. Test information

CL= load capacitance; includes jig and probe capacitance.

RT= termination resistance; should be equal to Zo of the pulse generator.

All input pulses are supplied by generators having the following characteristics: PRR 5MHz;

Zo=50; tr2.5 ns; tf2.5 ns.

Fig 6. Test circuitry for sw itching times

Fig 7. Test circuit

Table 9. Test data

Test Load Switch

CLRL

tPLZ, tPZL (output on B side) 50 pF 200 2VIC

tPHZ, tPZH (output on B side) 50 pF 200 GND

tPD -200open

PULSE

GENERATOR

50 pF

200 Ω

002aag014

VIC

VDD

DUT

200 Ω

2 × VIC

open

GND

002aae655

4-PORT, 20 GHz

NETWORK ANALYZER

PORT 1 PORT 4

DUT

PORT 2 PORT 3

Product data sheet Rev. 4.1 — 30 March 2015 11 of 19

NXP Semiconductors CBTL02043A; CBTL02043B

3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch

14. Package outline

Fig 8. Package outline SOT764-1 (DHVQFN20)

References

Outline

version European

projection Issue date

IEC JEDEC JEITA

SOT764-1 - - -

MO-241

- - -

sot764-1_po

03-01-27

14-12-12

Unit

mm max

nom

min

1.00 0.05 4.6 3.15 2.6 0.5 3.5 0.1

A(1)

Dimensions (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

A1b

0.30

(1) DhE(1) Eh

1.00

0.4

0.05

0.90 0.02 0.2 4.5 3.00 2.50.25 0.05 0.1

0.85 0.30.80 0.00 4.4 2.85 2.40.18

1.15 0.5

detail X

B A

AC B

scale

AA1c

19 12

terminal 1

index area

terminal 1

index area

05 mm2.5

DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

20 terminals; body 2.5 x 4.5 x 0.85 mm SOT764-1

Product data sheet Rev. 4.1 — 30 March 2015 12 of 19

NXP Semiconductors CBTL02043A; CBTL02043B

3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch

15. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

15.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on on e printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

15.2 Wave and reflow soldering

W ave soldering is a joining te chnology in which the joints are m ade by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solde r lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads ha ving a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded pa ckages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering ve rsus SnPb soldering

15.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

Product data sheet Rev. 4.1 — 30 March 2015 13 of 19

NXP Semiconductors CBTL02043A; CBTL02043B

3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch

15.4 Reflow soldering

Key characteristics in reflow soldering are :

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 9) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) an d cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on p ackage thickness and volume and is classified in accordance with

Table 10 and 11

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 9.

Table 10. SnPb eutectic process (from J-STD-0 20D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350  350

< 2.5 235 220

 2.5 220 220

Table 11. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 4.1 — 30 March 2015 14 of 19

NXP Semiconductors CBTL02043A; CBTL02043B

3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch

For further informa tion on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

MSL: Moisture Sensitivity Level

Fig 9. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Product data sheet Rev. 4.1 — 30 March 2015 15 of 19

NXP Semiconductors CBTL02043A; CBTL02043B

3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch

16. Soldering: PCB footprints

Fig 10. PCB footprint for SOT764-1 (DHVQFN20); reflow soldering

SOT764-1Footprint information for reflow soldering of DHVQFN20 package

Refer to the package outline drawing for actual layout

occupied area

solder land plus solder paste

solder land

solder paste deposit

0.400

0.650 0.025

4.800

5.750

0.5000.290

1.700

2.900

3.500

5.500

0.900 1.700 3.7003.750 2.800 0.105

0.025

Product data sheet Rev. 4.1 — 30 March 2015 16 of 19

NXP Semiconductors CBTL02043A; CBTL02043B

3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch

17. Abbreviations

18. Revision history

Table 12. Abbreviations

Acronym Description

CDM Charged-Device Model

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

I/O Input/Output

PCI Peripheral Component Interconnect

PCIe PCI Express

PRR Pulse Repetition Rate

SATA Serial Advanced Technology Attachment

USB Universal Serial Bus

Table 13. Revision history

Document ID Release

date Data sheet status Change

notice Supersedes

CBTL02043A_CBTL02043B v.4.1 20150330 Product data sheet - CBTL02043A_CBTL02043B v.4

Modifications: •Changed “USB 3.0” to “USB 3.1” throughout

CBTL02043A_CBTL02043B v.4 20141219 Product dat a sheet - CBTL02043A_CBTL02043B v.3

CBTL02043A_CBTL02043B v.3 20130305 Product dat a sheet - CBTL02043A_CBTL02043B v.2

CBTL02043A_CBTL02043B v.2 20111110 Product data sheet - CBTL02043 A_CBTL02043B v.1

CBTL02043A_CBTL02043B v.1 20110310 Product data sheet - -

Product data sheet Rev. 4.1 — 30 March 2015 17 of 19

NXP Semiconductors CBTL02043A; CBTL02043B

3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch

19. Legal information

19.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device (s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

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damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party custo mer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or inte llectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contain s data from the objective specification for product develop ment.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.

Product [short] data sheet Production This document contains the product specification.

Product data sheet Rev. 4.1 — 30 March 2015 18 of 19

NXP Semiconductors CBTL02043A; CBTL02043B

3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It i s neit her qua lif ied nor test ed

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standards, custome r

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such au tomotive applications, use and specifica tions, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed product claims resulting from customer design an d

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

19.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

20. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors CBTL02043A; CBTL02043B

3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 30 March 2015

Document identifier: CBTL02043A_CBTL02043B

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

21. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 Functional description . . . . . . . . . . . . . . . . . . . 5

7.1 Function selection and shutdown function . . . . 5

8 Application design-in information . . . . . . . . . . 6

9 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . 7

10 Recommended operating conditions. . . . . . . . 7

11 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7

12 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8

13 Test information. . . . . . . . . . . . . . . . . . . . . . . . 10

14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11

15 Soldering of SMD packages . . . . . . . . . . . . . . 12

15.1 Introduction to soldering . . . . . . . . . . . . . . . . . 12

15.2 Wave and reflow soldering . . . . . . . . . . . . . . . 12

15.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 12

15.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 13

16 Soldering: PCB footprints. . . . . . . . . . . . . . . . 15

17 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16

18 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16

19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17

19.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17

19.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

19.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

19.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

20 Contact information. . . . . . . . . . . . . . . . . . . . . 18

21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19