11C06DCQBNOPB - National Semiconductor

TL/F/9890

11C06 750 MHz D-Type Flip-Flop

Not Intended For New Designs

August 1992

11C06

750 MHz D-Type Flip-Flop

General Description

The 11C06 is a high-speed ECL D-Type Master-Slave Flip-

Flop capable of toggle rates over 750 MHz. Designed pri-

marily for high-speed prescaling, it can also be used in any

application which does not require preset inputs. The circuit

is voltage-compensated, which makes input thresholds and

output levels insensitive to VEE variations. Complementary

Q and Q outputs are provided, as are two Data inputs, Clock

and Clock Enable inputs. The 11C06 is pin-compatible with

the Motorola MC1690L but is a higher-frequency replace-

ment.

Logic Symbol Connection Diagrams

TL/F/9890–3

16-Pin DIP

TL/F/9890–1

16-Pin Flatpak

TL/F/9890–2

Pin Names Description

DnData Input

CP Clock Input

CE Clock Enable (Active LOW)

Q, Q Outputs

Truth Table

CE CP D Qn

LLXQ

LHXQ

LLLL

LLHH

HXXQ

HIGH Voltage Level

LeLOW Voltage Level

XeDon’t Care

LeLOW to HIGH Transition

Qnb1ePrevious State

C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Absolute Maximum Ratings

Above which the useful life may be impaired

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Storage Temperature b65§Ctoa

150§C

Maximum Junction Temperature (TJ)a150§C

Supply Voltage Range b7.0V to GND

Input Voltage (DC) VEE to GND

Output Current (DC Output HIGH) b50 mA

Operating Range b5.7V to b4.7V

Lead Temperature (Soldering, 10 sec.) 300§C

Recommended Operating

Conditions

Min Typ Max

Supply Voltage (VEE)b5.7V b5.2V b4.7V

Ambient Temperature (TA)0

75§C

DC Electrical Characteristics

VEE eb

5.2V, VCC eGND

Symbol Parameter Min Typ Max Units TAConditions

VOH Output Voltage HIGH b1000 b840 mV 0§CV

IN eVIH (Max) or VIL (Min) per Truth

b960 b810 mV a25§C Table Loading 50Xto b2V

b900 b720 mV a75§C

VOL Output Voltage LOW b1870 b1635 mV 0§C

b1850 b1620 mV a25§C

b1830 b1595 mV a75§C

VOHC Output Voltage HIGH b1020 mV 0§CV

IN eVIH (Min) or VIL (Max) for DnInputs

b980 mV a25§C Loading 50Xto b2V

b920 mV a75§C

VOLC Output Voltage LOW b1615 mV 0§C

b1600 mV a25§C

b1575 mV a75§C

VIH Input Voltage HIGH b1135 b840 mV 0§C Guaranteed Input Voltage HIGH

b1095 b810 mV a25§C for All Inputs

b1035 b720 mV a75§C

VIL Input Voltage LOW b1870 b1500 mV 0§C Guaranteed Input Voltage LOW

b1850 b1485 mV a25§C for All Inputs

b1830 b1460 mV a75§C

IIH Input Current HIGH VIN eVIH (Max)

Clock Input 250 mAa25§C

Data Input 270 mAa25§C

IIL Input Current LOW 0.5 mAa25§CV

IN eVIH (Min)

IEE Power Supply Current b59 b40 mA a25§C All Inputs Open

AC Electrical Characteristics

VEE eb

5.2V, VCC eGND, TAea

25§C

Symbol Parameter Min Typ Max Units Conditions

tPHL Propagation Delay (CP-Q) 0.7 1.0 1.2 ns

tPLH Propagation Delay (CP-Q) 0.7 1.0 1.2 ns

tTLH Transition Time 20% to 80% 0.5 0.8 1.0 ns See

Figure 1

tTHL Transition Time 80% to 20% 0.5 0.8 1.0 ns

tSSet-up Time 0.2 ns

tHHold Time 0.2 ns

fTOG (MAX) Toggle Frequency (CP) 650 750 MHz See

Figure 2

, Note

Note: The device is guaranteed for fTOG (CP) t600 MHz, fTOG(CE) t550 MHz over the 0§Ctoa

75§C temperature range.

Functional Description

While the clock is LOW, the slave is held steady and the

information on the D input is permitted to enter the master.

The next transition from LOW to HIGH locks the master in

its present state making it insensitive to the D input. This

transition simultaneously connects the slave to the master

causing the new information to appear on the outputs. Mas-

ter and slave clock thresholds are internally offset in oppo-

site directions to avoid race conditions or simultaneous

master-slave changes when the clock has slow rise or fall

times.

The CP and CE inputs are logically identical, but physical

constraints associated with the Dual-In-Line package make

the CE input slower at the upper end of the toggle range. To

prevent new data from entering the master on the next CP

LOW cycle, CE should go HIGH while CP is still HIGH.

TL/F/9890–4

RTe50Xtermination of scope

L1e50Ximpedance lines

All input transition times are 2.0 ns g0.2 ns

FIGURE 1. Propagation Delay (CP to Q)

TL/F/9890–5

RTe50Xtermination of scope

L1e50Ximpedance lines

Adjust VBIAS for a0.7V baseline of

800 mV peak-to-peak sinewave input.

All input transition times are 2.0 ns g0.2 ns

FIGURE 2. Toggle Frequency Test Circuit

Typical Waveforms

TL/F/9890–6

Horizontal Scale e1.0 ns/div

Vertical Scale e200 mV/div

Ordering Information

The device number is used to form part of a simplified purchasing code where the package type and temperature range are

defined as follows:

11C06 D C QR

Device Number Special Variations

(basic) QR eCommercial grade device

with burn-in

Package Code

DeCeramic Dual-In-Line Temperature Range

FeFlatpak CeCommercial (0§Ctoa

85§C)

Physical Dimensions inches (millimeters)

16 Lead Ceramic Dual-In-Line Package (D)

NS Package Number J16A

11C06 750 MHz D-Type Flip-Flop

Physical Dimensions inches (millimeters) (Continued)

16 Lead Ceramic Flatpak (F)

NS Package Number W16A

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with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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