A
2
B and the A
2
B logo are registered trademarks of Analog Devices, Inc.
Automotive Audio Bus A
2
B Transceiver
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Rev. B Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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Tel: 781.329.4700 ©2020 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
A
2
B BUS FEATURES
Line topology
Single master, multiple slave
Up to 15 m between nodes and up to 40 m overall cable
length (see Table 9)
Communication over distance
Synchronous data
Multichannel I
2
S/TDM to I
2
S/TDM
Synchronous clock, phase aligned in all nodes
Low latency slave to slave communication
Control and status information I
2
C to I
2
C
GPIO and interrupt
Bus power or local power slave nodes
Configurable with SigmaStudio graphical software tool
AEC-Q100 qualified for automotive applications
A
2
B TRANSCEIVER FEATURES
Configurable A
2
B bus master or slave operation
I
2
C interface
8-bit to 32-bit multichannel I
2
S/TDM interface
Programmable I
2
S/TDM data rate
Up to 32 upstream and 32 downstream channels
PDM interface
Programmable PDM clock rate
Up to 4 high dynamic range microphone inputs
Simultaneous reception of I
2
S data with up to 4 PDM
microphones
Unique ID register for each transceiver
Crossover or straight-through cabling
Programmable settings to optimize EMC performance
APPLICATIONS
Audio communication link
Microphone arrays
Beamforming
Hands free and in car communication
Active and road noise cancellation
Audio/video conferencing systems
Figure 1. Functional Block Diagram
DTX0/IO3
IRQ/IO0
SDA
SCL
ADR1/IO1
IOVDD
BCM
AP
ACM
BN
DVDD BTRXVDD
VSS
SWP
VIN
ADR2/IO2
ATRXVDD
AN
BP
A2B
TRX B
(Towards
Last Slave)
SENSE
DIAGNOSTICS
PDMCLK/IO7
A2B
TRX A
(Towards
Master)
DTX1/IO4
DRX0/IO5
DRX1/IO6
BCLK SYNC VSSN
VREG1PLL
PLLVDD VOUT1
VREG2
VOUT2
I2S/TDM
PDM
I2C
Rev. B | Page 2 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
TABLE OF CONTENTS
A
2
B Bus Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
A
2
B Transceiver Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
A
2
B Bus Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
I
2
C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
I
2
S/TDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pulse Density Modulation (PDM) Interface . . . . . . . . . . . . . . . . . 6
GPIO Over Distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Slot Exchange Between Slaves . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Clock Sustain State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Programmable Settings to Optimize EMC
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power Supply Rejection Ratio (PSRR) . . . . . . . . . . . . . . . . . . . . . . 11
Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power-Up Sequencing Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 16
A
2
B Bus System Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PDM Typical Performance Characteristics . . . . . . . . . . . . . . . . 18
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ESD Caution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Test Circuits and Switching Characteristics . . . . . . . . . . . . . . . 21
Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Pin Configuration and Function Descriptions . . . . . . . . . . . . . . . 24
Power Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Current Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
VREG1 and VREG2 Output Currents . . . . . . . . . . . . . . . . . . . . . . 29
Current at VIN (IVIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Resistance Between Nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Voltage Regulator Current in Master Node or Local
Powered Slave Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power Dissipation of A
2
B Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power Analysis of Bus Powered System . . . . . . . . . . . . . . . . . . . . 31
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Reducing Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Power Estimation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Thermal Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Designer Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
VSENSE and Considerations for Diodes . . . . . . . . . . . . . . . . . . . 36
Optional Add On Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Automotive Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
REVISION HISTORY
1/2020—Rev. A to Rev. B
Updated All Products to Released Status . . . . . . . Throughout
Deleted Product Status Table. . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to Automotive Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Changes to Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Deleted Pending Products Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Rev. B | Page 3 of 38 | January 2020
GENERAL DESCRIPTION
The Automotive Audio Bus (A
2
B
®
) provides a multichannel,
I
2
S/TDM link over distances of up to 15 m between nodes. It
embeds bidirectional synchronous pulse-code modulation
(PCM) data (for example, digital audio), clock, and synchroni-
zation signals onto a single differential wire pair. A
2
B supports a
direct point to point connection and allows multiple, daisy-
chained nodes at different locations to contribute and/or con-
sume time division multiplexed (TDM) channel content.
A
2
B is a single-master, multiple-slave system where the trans-
ceiver at the host controller is the master. The master generates
clock, synchronization, and framing for all slave nodes. The
master A
2
B transceiver is programmable over a control port
(I
2
C) for configuration and read back. An extension of the con-
trol port protocol is embedded in the A
2
B data stream, which
grants direct access of registers and status information on slave
transceivers as well as I
2
C to I
2
C communication over distance.
The transceiver can connect directly to general-purpose digital
signal processors (DSPs), field-programmable gate arrays
(FPGAs), application specific integrated circuits (ASICs),
microphones, analog-to-digital converters (ADCs), digital-to-
analog converters (DACs), and codecs through a multichannel
I
2
S/TDM interface. It also provides a pulse density modulation
(PDM) interface for direct connection of up to four PDM digital
microphones.
Finally, the transceiver also supports an A
2
B bus powering fea-
ture, where the master node supplies voltage and current to the
slave nodes over the same daisy-chained, twisted pair wire cable
as used for the communication link.
Table 1. Product Comparison Guide
Feature AD2420/
AD2420W
AD2426/
AD2426W
AD2427/
AD2427W
AD2428/
AD2428W
AD2429/
AD2429W
Master capable No No No Yes Yes
Number of slaves discoverable
1
N/A N/A N/A Up to 10 Up to 2
Functional TRX blocks A only A only A + B A + B B only
I
2
S/TDM support No No No Yes Yes
PDM microphone inputs 2 mics
2
4 mics 4 mics 4 mics 4 mics
Max node to node cable length 5 m 15 m 15 m 15 m 5 m
1
N/A means not applicable.
2
PDM microphones must be connected to the DRX0/IO5 pin.
Rev. B | Page 4 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
A
2
B BUS DETAILS
Figure 2 shows a single-master, multiple-slave A
2
B communica-
tions system with the master transceiver controlled by the host.
The host generates a periodic synchronization signal on the
I
2
S/TDM interface at a fixed frequency (typically 48 kHz) to
which all A
2
B nodes synchronize.
Communications along the A
2
B bus occur in periodic super-
frames. The superframe frequency is the same as the
synchronization signal frequency, and data is transferred at a bit
rate that is 1024 times faster (typically 49.152 MHz). Each
superframe is divided into periods of downstream transmission,
upstream transmission, and no transmission (where the bus is
not driven). Data is exchanged over the A
2
B bus in up to 32
equal width slots for both upstream and downstream
transmissions.
The A
2
B bus also communicates the following control and
status information between nodes:
•I
2
C to I
2
C communication
• General-purpose input/output (GPIO)
•Interrupts
In Figure 3, a superframe is shown with an initial period of
downstream transmission and a later period of upstream
transmission.
All signals on the A
2
B bus are line coded, and the master node
forwards the synchronization signal downstream from the mas-
ter transceiver to the last slave node transceiver in the form of a
synchronization preamble. This preamble is followed by control
data to build a synchronization control frame (SCF). Down-
stream, TDM synchronous data is added directly after the
control frame. Every slave can use or consume some of the
downstream data and add data for downstream nodes. The last
slave node transceiver responds after the response time with a
synchronization response frame (SRF). Upstream synchronous
data is added by each node directly after the response frame.
Each node can also use or consume upstream data.
The embedded control and response frames allow the host to
individually address each slave transceiver in the system. The
host also enables access to remote peripheral devices that are
connected to the slave transceivers via the I
2
C or SPI ports for
I
2
C to I
2
C communication over distance between multiple
nodes.
All nodes in an A
2
B system are sampled synchronously in the
same A
2
B superframe. Synchronous I
2
S/TDM downstream data
from the master arrives at all slaves in the same A
2
B superframe,
and the upstream audio data of every node arrives synchro-
nously in the same I
2
S/TDM frame at the master. The remaining
audio phase differences between slaves can be compensated for
by register-programmable fine adjustment of the SYNC pin sig-
nal delay.
There is a sample delay incurred for data moving between the
A
2
B bus and the I
2
S/TDM interfaces because data is received
and transmitted over the I
2
S/TDM every sample period (typi-
cally 48 kHz). This timing relationship between samples over
the A
2
B bus is shown in Figure 4.
Note in Figure 4, both downstream and upstream samples are
named for the frame where they enter the A
2
B system as follows:
• Data transmitted by the master node transceiver in Super-
frame M creates Downstream Data M.
• Data transmitted by the slave node transceivers in Super-
frame N creates Upstream Data N.
• Data received over the I
2
S/TDM interface by the A
2
B trans-
ceiver is transmitted over the A
2
B bus in the next
superframe.
•D
ata on the A
2
B bus is transmitted over the I
2
S/TDM inter-
face of an A
2
B transceiver in the next superframe.
• Data transmitted across the A
2
B bus (master to slave or
slave to master) has two frames of latency plus any internal
delay that has accumulated in the transceivers as well as
delays due to wire length. Therefore, overall latency is
slightly over two samples (<50 s at 48 kHz sample periods)
from the I
2
S/TDM interface in one A
2
B transceiver to the
I
2
S/TDM interface of another A
2
B transceiver.
To support and extend the A
2
B bus functions and performance,
the transceivers have additional features, as described in the fol-
lowing sections.
Figure 2. Communication System Block Diagram
A2B
HOST
DSP
I2C
MASTER
A2B
TRANSCEIVER
SLAVE A2B
TRANSCEIVER
I2S/TDM
A2B
A2B
SLAVE A2B
TRANSCEIVER
SLAVE A2B
TRANSCEIVER
I2S/TDM
I2S/TDM
I2S/TDM
I2C
I2C
I2C
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Rev. B | Page 5 of 38 | January 2020
I
2
C INTERFACE
The I
2
C interface in the transceiver provides access to the inter-
nal registers. Operation is not guaranteed above the V
I2C_VBUS
specification. The I
2
C interface has the following features:
• Slave functionality in the A
2
B master
• Master or slave functionality in the A
2
B slave
• Multimaster support in the A
2
B slave
• 100 kbps or 400 kbps rate operation
• 7-bit addressing
• Single-word and burst mode read and write operations
•Clock stretching
All transceivers can be accessed by a locally connected processor
using the 7-bit I
2
C device address (BASE_ADDR) established by
the logic levels applied to the ADR2/IO2 and ADR1/IO1 pins at
power-on reset, thus providing for up to four master devices
connecting to the same I
2
C bus. A slave configured transceiver
recognizes only this I
2
C device address. A master configured
transceiver, however, also recognizes a second I
2
C device
address for remote access to slave nodes over the A
2
B bus
(BUS_ADDR). The least significant bit (LSB) of the 7-bit device
address determines whether an I
2
C data exchange uses the
BASE_ADDR (Bit 1 = 0) to access the transceiver or
BUS_ADDR (Bit 1 = 1) to access a bus node slave transceiver
through a master configured AD2425W transceiver. See the
AD2420(W)/6(W)/7(W)/8(W)/9(W) Automotive Audio Bus A
2
B
Transceiver Technical Reference for details.
I
2
S/TDM INTERFACE
The I
2
S/TDM serial port operates in full-duplex mode, where
both the transmitter and receiver operate simultaneously using
the same critical timing bit clock (BCLK) and synchronization
(SYNC) pins. A
2
B slave transceivers generate the timing signals
on the BCLK and SYNC output pins. A
2
B master transceivers
use the same BCLK and SYNC pins as inputs, which are driven
by the host device. The I
2
S/TDM port includes the following
features:
• Programmable clock and frame sync timing and polarity
• Numerous TDM operating modes
• 16- or 32-bit data width
• Simultaneous operation with PDM port
• Single- or dual-pin input/output (I/O)
Figure 3. A
2
B Superframe
Figure 4. A
2
B Bus Synchronous Data Exchange
SYNCH
CONTROL
FRAME
DOWNSTREAM
A2B DATA SLOTS
SYNCH
RESPONSE
FRAME
UPSTREAM
A2B DATA SLOTS
SYNCH
CONTROL
FRAME
SUPERFRAME: 20.83ȝs FOR 48kHz SAMPLING RATE
MASTER NODE
I2S TX
DATA
I2S RX
DATA
A2B DATA
I2S UPSTREAM DATA N
-
2
SLAVE NODE
I2S UPSTREAM DATA N
-
1I
2S UPSTREAM DATA N
I2S DOWNSTREAM DATA M I2S DOWNSTREAM DATA M
+
1I
2S DOWNSTREAM DATA M
+
2
I2S UPSTREAM DATA N I2S UPSTREAM DATA N + 1 I2S UPSTREAM DATA N + 2
I2S DOWNSTREAM DATA M
-
2I
2S DOWNSTREAM DATA M
-
1I
2S DOWNSTREAM DATA M
SCF
DNSTREAM
A2B DATA
M
-
1
SRF
UPSTREAM
A2B DATA
N
-
1
SCF
DNSTREAM
A2B DATA
M
SRF
UPSTREAM
A2B DATA
N
SCF
DNSTREAM
A2B DATA
M+1
SRF
UPSTREAM
A2B DATA
N+1
SCF
SUPERFRAME
I2S RX
DATA
I2S TX
DATA
Rev. B | Page 6 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
I
2
S Reduced Rate
Slave transceivers can run the I
2
S/TDM/PDM interface at a
reduced rate frequency, with respect to the superframe rate. The
reduced rate frequency is derived by dividing the superframe
rate from a programmable set of values. Different slave nodes
can be configured to run at different reduced I
2
S/TDM rates.
The transceiver provides an option for a processor to track the
full rate audio frame, which contains new reduced rate samples.
The IO7 pin can be used as a strobe, and the direction can be
configured as an input or output.
PULSE DENSITY MODULATION (PDM) INTERFACE
The PDM block on the transceiver converts a PDM input
stream into pulse code modulated (PCM) data to be sent over
the A
2
B bus and/or out to the local node through the I
2
S/TDM
port. It supports high dynamic range microphones with high
signal-to-noise ratio (SNR) and extended maximum sound
pressure level. The PDM interface supports 12 kHz and 24 kHz
frame rates in addition to a 48 kHz frame rate and can be used
on both master and slave transceivers.
Even lower PDM sampling rates (for example, down to 375 Hz)
are possible in combination with the reduced rate feature of the
transceiver. The cutoff frequency of the high-pass filter in the
transceiver PDM block is fixed to 1 Hz.
BCLK can be used to clock PDM microphones on a slave, but if
PDMCLK/IO7 is used instead, the BCLK frequency can be set to
a different frequency using the I
2
S/TDM registers. In this case,
PDMCLK/IO7 is used as the PDM clock (PDMCLK) to capture
PDM input on DRX0/DRX1. The clock rate from PDMCLK is
64× the SYNC frequency.
On a master node, BCLK is always an input, so the clock to
PDM microphones that are attached to a master typically comes
from PDMCLK/IO7. It is possible to use BCLK to drive the
PDM clock inputs on a master node, but this restricts the possi-
ble TDM settings because BCLK is required to fall within the
f
BCLK
specification in Table 4.
BCLK and PDMCLK/IO7 can also be used concurrently to
clock PDM microphones at the same frequency and phase
alignment, but with opposite polarity. Additionally, a register
setting selects whether rising edge data or falling edge data is
sampled first.
GPIO OVER DISTANCE
The transceiver supports general-purpose input/output (GPIO)
between multiple nodes without host intervention after initial
programming. The host is required only for initial setup of the
GPIO bus ports. I/O pins of different nodes can be logically OR
or AND gate combined.
MAILBOXES
The transceiver supports interrupt driven, bidirectional mes-
sage exchange between I
2
C master devices (microcontrollers) at
different slave nodes and the host connected to the master node
transceiver in two dedicated mailboxes. The mailboxes can be
used to customize handshaking among numerous nodes in a
system to coordinate system events, such as synchronizing
audio.
DATA SLOT EXCHANGE BETWEEN SLAVES
Using the DTX0 and DTX1 pins, slave transceivers can selec-
tively output upstream or downstream data that originates from
other nodes without the need for data slots to be routed through
the master node. Receive data channels can be skipped based on
a programmable offset, when the data is presented as upstream
or downstream slots to the A
2
B bus.
CLOCK SUSTAIN STATE
In the clock sustain state, audio signals of locally powered slave
nodes are attenuated in the event of lost bus communication.
When the bus loses communication and a reliable clock cannot
be recovered by the slave node, the slave node transceiver enters
the sustain state and, if enabled, signals this event to a GPIO pin.
In the clock sustain state, the phase-locked loop (PLL) of the
slave node transceiver continues to run for 1024 SYNC periods,
while attenuating the I
2
S DTX0 to DTX1 data from the current
value to 0. After the 1024 SYNC periods, the slave node trans-
ceiver resets and reenters the power-up state.
PROGRAMMABLE SETTINGS TO OPTIMIZE EMC
PERFORMANCE
The following programmable features can be used to improve
electromagnetic compatibility (EMC) performance.
Programmable LVDS Transmit Levels
The low voltage differential signal (LVDS) transmitter can be set
to transmit the signal at high, medium, or low levels. Higher
transmit levels yield greater immunity to EMI, whereas lower
transmit levels can reduce emissions from the twisted-pair
cables that link A
2
B bus nodes together. The improved LVDS
receiver (compared to other members of the AD242xW family)
maintains robust operation when transmit levels are lowered.
Spread-Spectrum Clocking
Spread-spectrum clocking can be used to reduce narrow-band
emissions on a printed circuit board (PCB). Spread-spectrum
clocking is disabled on the transceiver by default, but spread-
spectrum clocking for all internal clocks can be enabled during
discovery by a register write.
If spread-spectrum clocking support is enabled for the internal
clocks, spread-spectrum clocking can also be enabled for both
the I
2
S interface and the programmed CLKOUTs. Enabling
spread-spectrum clocking for internal clocks, CLKOUTs, and
the I
2
S interface may reduce narrow-band emissions by several
dB on a particular node. When spread-spectrum clocking is
enabled on a clock output, the time interval error (TIE) jitter on
that clock increases.
Unique ID
Each transceiver contains a unique ID, which can be read from
registers using software. If a read of the unique ID fails, an inter-
rupt can be generated.
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Rev. B | Page 7 of 38 | January 2020
Support for Crossover or Straight Through Cabling
Straight through cables can be supported by swapping the dc
coupling at the B-side connector. See the Designer Reference
section for details about the reference schematics.
Data Only and Power Only Bus Operation
The A
2
B bus can be operated without closing the PMOS switch
to send a dc bias downstream. Conversely, a dc bias can also be
sent downstream without the presence of data. These features
are available for debug purposes only.
Rev. B | Page 8 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
SPECIFICATIONS
For information about product specifications, contact your
Analog Devices, Inc. representative.
OPERATING CONDITIONS
Parameter Conditions Min Nominal Max Unit
Power Supplies
V
DVDD
Digital Core Logic Supply Voltage 1.70 1.90 1.98 V
V
IOVDD
Digital Input/Output (I/O) Supply
Voltage
3.3 V I/O 3.0 3.3 3.63 V
1.8 V I/O 1.7 1.9 1.98 V
V
PLLVDD
Phased-Locked Loops (PLL) Supply
Voltage
1.7 1.9 1.98 V
V
TRXVDD
Transceiver Supply Voltage Applies to the ATRXVDD and BTRXVDD pins 3.0 3.3 3.63 V
V
I2C_VBUS
External I
2
C Bus Voltage 3.3 V V
IOVDD
, 1.8 V V
IOVDD
1.7 1.9/3.3 3.63 V
Voltage Regulator (VREG1, VREG2)
V
VIN
Regulator Input Supply Voltage Specification must be met at the VIN pin of
each A
2
B bus transceiver
3.7 9.0 V
V
RST
V
VIN
Chip Reset Assertion Voltage
Threshold
V
VIN
dropping 2.65 2.97 V
V
RSTN
V
VIN
Chip Reset Deassertion Voltage
Threshold
V
VIN
rising 3.11 3.25 V
Digital I/O
V
IH1
1
Applies to PDMCLK/IO7, BCLK, SYNC, DTX0/IO3, DTX1/IO4, DRX0/IO5, DRX1/IO6, ADR1/IO1, ADR2/IO2, IRQ/IO0 pins.
High Level Input Voltage V
IOVDD
= 1.98 V 0.7 × V
IOVDD
V
V
IOVDD
= 3.63 V 2.2 V
V
IL1
Low Level Input Voltage V
IOVDD
= 1.70 V 0.3 × V
IOVDD
V
V
IOVDD
= 3.00 V 0.8 V
V
IH_I2C2
2
Applies to SDA and SCL pins.
V
IOVDD
= 3.63 V, 1.98 V 0.7 × V
IOVDD
V
V
IL_I2C
V
IOVDD
= 3.00 V, 1.70 V 0.3 × V
IOVDD
V
Temperature
T
J
Junction Temperature T
AMBIENT
= 0°C to 70°C 0 105 °C
T
J
Junction Temperature T
AMBIENT
= –40°C to +85°C –40 +105 °C
AUTOMOTIVE USE ONLY
T
J
Junction Temperature
(Automotive Grade)
T
AMBIENT
= –40°C to +105°C –40 +125
3
3
Automotive application use profile only. Not supported for nonautomotive use. Contact Analog Devices, Inc. for more information.
°C
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Rev. B | Page 9 of 38 | January 2020
ELECTRICAL CHARACTERISTICS
Parameter Conditions Min Typ Max Unit
Current
I
DVDD
Digital Core Logic Supply Current V
DVDD
= 1.98 V 9.0 10.5 12.0 mA
I
PLLVDD
PLL Supply Current V
PLLVDD
= 1.98 V 0.5 1.1 1.5 mA
I
TRXVDD1
1
Master and last slave only consume half the transceiver current because only one of the two TRX blocks is used.
Transceiver Supply Current TX enabled, RX disabled, 100% duty cycle
(I
TXVDD
), V
TRXVDD
= 3.63 V
9.5 12.0 13.0 mA
TX disabled, RX enabled, 100% duty cycle
(I
RXVDD
), V
TRXVDD
= 3.63 V
2.22.8 3.5mA
TX disabled, RX disabled, 0% activity level,
V
TRXVDD
= 3.63 V
1.01.7 2.5mA
Voltage Regulator (VREG1, VREG2)
V
VOUT1
V
REG1
Output Voltage 1.80 1.90 1.98 V
V
VOUT2
V
REG2
Output Voltage 3.15 3.30 3.45 V
I
VOUT12
2
In a bus powered system, I
VOUT
has a direct impact on I
VSSN
and V
VIN
in other nodes. For more information, see the Power Analysis section.
V
REG1
Output Current 40.0 mA
I
VOUT22
V
REG2
Output Current 50.0 mA
I
VEXT13, 4
3
Consider the package thermal limits when dissipating current above typical limits. For more information, see the Thermal Characteristics section.
4
Must comply with I
VOUT1
and I
VOUT2
maximum.
V
REG1
External Device Current I
VOUT1
– I
PLLVDD
– I
DVDD
– I
IOVDD
current
available to external device
20 mA
I
VEXT23, 4
V
REG2
External Device Current I
VOUT2
– I
TRXVDD
current available to external
device
20 mA
V
OUT1
/V
IN
Line Regulation V
VIN
= 3.7 V to VIN 0 0.017 0.055 %/V
V
OUT2
/V
IN
Line Regulation V
VIN
= 3.7 V to VIN 0.013 0.030 0.060 %/V
V
VIN
= 5.0 V to 8 V –0.025 +0.005 +0.055 %/V
V
OUT1
/I
OUT1
Load Regulation V
VIN
= 5.0 V, I
VOUT1
= 1 mA to 40 mA 0.009 0.017 %/mA
V
OUT2
/I
OUT2
Load Regulation V
VIN
= 5.0 V, I
VOUT2
= 1 mA to 50 mA 0.008 0.015 %/mA
I
VINQ
Quiescent Current V
VIN
=V
IN
, I
VOUT1
= 0 mA, I
VOUT2
= 0 mA 530 600 750 A
I
VIN
Operational Current V
VIN
= V
IN
, I
VOUT1
= 8 mA, I
VOUT2
= 20 mA 29 mA
C
Load1
V
REG1
Load Capacitance 1.0 25 F
C
Load2
V
REG2
Load Capacitance 2.2 25 F
Digital I/O
I
IH
Input Leakage, High V
IOVDD
= 3.63 V, V
IN
= 3.63 V 10.0 A
I
IL
Input Leakage, Low V
IOVDD
= 3.63 V, V
IN
= 0 V 10.0 A
I
OZH_I2C5
5
Applies to SDA and SCL pins.
Three-State Leakage Current V
IOVDD
= 1.9 V, V
IN
= 3.63 V 10.0 A
V
OH1.9
High Level Output Voltage V
IOVDD
= 1.70 V, I
OH
= 1 mA 1.35 V
V
OH3.3
High Level Output Voltage V
IOVDD
= 3.00 V, I
OH
= 1 mA 2.40 V
V
OL6
6
Applies to BCLK, SYNC, DTX0/IO3, DTX1/IO4, DRX0/IO5, DRX1/IO6, ADR1/IO1, ADR2/IO2, IRQ/IO0, PDMCLK/IO7 pins.
Low Level Output Voltage V
IOVDD
= 3.00 V, I
OL
= 1 mA 0.40 V
V
OL6
Low Level Output Voltage V
IOVDD
= 1.70 V, I
OL
= 1 mA 0.40 V
V
OL_I2C5,
7
7
The minimum I
OL
current is lower than the I
2
C specification because the SDA and SCL pins are designed for a limited number of I
2
C attached slave devices.
I
2
C Low Level Output Voltage V
IOVDD
= 3.00 V, I
OL
= 1.5 mA 0.40 V
V
OL_I2C5,
7
I
2
C Low Level Output Voltage V
IOVDD
= 1.70 V, I
OL
= 1.5 mA 0.40 V
C
PD
Pin Capacitance 4.8 5 pF
Negative Bias Switch
I
VSSN
Internal V
SSN
Switch Current AD2426(W)/AD2427(W)/AD2428(W) 300 mA
I
VSSN
Internal V
SSN
Switch Current AD2420(W)/AD2429W 100 mA
R
VSSN
Internal V
SSN
On Resistance 1.2 Ω
Rev. B | Page 10 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Table 2. Differential Input/Output
Parameter Conditions Min Typ Max Unit
LVDS
|V
OD
| Differential Output Voltage Magnitude See Figure 19
High Transmit Level 425 545 mV
Medium Transmit Level 315 415 mV
Low Transmit Level 210 305 mV
Receiver
V
TH
Differential Input Threshold Voltage –52 +52 mV
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Rev. B | Page 11 of 38 | January 2020
POWER SUPPLY REJECTION RATIO (PSRR)
Typical PSRR at T
J
= 40°C with load capacitance
C
LOAD
= 4.7 µF || 100 µF.
Figure 5. VOUT1 PSRR, I
VOUT1
= 10 mA
Figure 6. VOUT1 PSRR, I
VOUT1
= 40 mA
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
FREQUENCY (Hz)
1 10 100 1k 10k 100k 1M 10M
PSRR (dB)
VIN = 4.0V
VIN = 5.0V
VIN = 6.0V
VIN = 7.0V
VIN = 8.0V
VIN = 9.0V
VIN = 3.7V
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
FREQUENCY (Hz)
1 10 100 1k 10k 100k 1M 10M
PSRR (dB)
VIN = 4.0V
VIN = 5.0V
VIN = 6.0V
VIN = 7.0V
VIN = 8.0V
VIN = 9.0V
VIN = 3.7V
Figure 7. VOUT2 PSRR, I
VOUT2
= 10 mA
Figure 8. VOUT2 PSRR, I
VOUT2
= 50 mA
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
FREQUENCY (Hz)
1 10 100 1k 10k 100k 1M 10M
PSRR (dB)
VIN = 4.0V
VIN = 5.0V
VIN = 6.0V
VIN = 7.0V
VIN = 8.0V
VIN = 9.0V
VIN = 3.7V
–120
–110
–100
–90
–80
–70
–60
–50
–40
–20
–10
0
FREQUENCY (Hz)
1 10 100 1k 10k 100k 1M 10M
PSRR (dB)
VIN = 4.0V
VIN = 5.0V
VIN = 6.0V
VIN = 7.0V
VIN = 8.0V
VIN = 9.0V
VIN = 3.7V
–30
Rev. B | Page 12 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
TIMING SPECIFICATIONS
Table 3. Clock and Reset Timing (A
2
B Master)
Parameter Min Typ Max Unit
Timing Requirements
f
SYNCM
SYNC Pin Input Frequency Continuous Clock 43.6 44.1, 48.0 48.5 kHz
t
SYNCIJ
SYNC Pin Input Jitter RMS TIE 0.29 1.0 ns
t
SYNCOJ
SYNC Pin Output Jitter RMS TIE 2.6 ns
f
SYSBCLK
Bus Clock 1024 × f
SYNCM
kHz
t
DNSYNCR1
Delay from First Missed SYNC to Reset (A
2
B Master) 0.64 0.74 ms
t
DNSCFR1
Delay from First Missed SCF to Reset (A
2
B Slave) 0.64 0.74 ms
t
PLK
PLL Lock Time 7.5 ms
1
Only consecutive missed SYNC or SCF transitions for the specified duration result in a reset.
Table 4. Pulse Density Modulation Microphone Input Timing
Parameter Min Typ Max Unit
Timing Requirements
t
RISS
DRXn Input Setup Before BCLK 12.0 ns
t
RIHS
DRXn Input Hold After BCLK 0 ns
t
RISS
DRXn Input Setup Before PDMCLK 12.5 ns
t
RIHS
DRXn Input Hold After PDMCLK 0 ns
Switching Characteristics
f
BCLK
BCLK/PDMCLK Output Frequency 3.05 3.18 MHz
t
BCLKOJ
BCLK/PDMCLK Output Jitter RMS Cycle to Cycle 175 ps
t
SOL
BCLK/PDMCLK Output Pulse Width Low 161.0 ns
Table 5. GPIO Timing
Parameter Min Typ Max Unit
Timing Requirement
t
FIPW
Input Pulse Width t
SYSBCLK
+ 1 ns
Switching Characteristic
t
FOPW
Output Pulse Width t
SYSBCLK
– 1 ns
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Rev. B | Page 13 of 38 | January 2020
Table 6. I
2
C Port Timing
Parameter Min Typ Max Unit
Timing Requirements
f
SCL
SCL Clock Frequency 0 400 kHz
t
SCLH
SCL Pulse Width High 0.6 s
t
SCLL
SCL Pulse Width Low 1.3 s
t
SCS
Start and Repeated Start Condition Setup Time 0.6 s
t
SCH
Start Condition Hold Time 0.6 s
t
SPS
Stop Condition Hold Time 0.6 s
t
DS
Data Setup Time 100 ns
t
DH
Data Hold Time 0.0 0.9 s
t
SCLR
SCL Rise Time 300 ns
t
SCLF
SCL Fall Time 300 ns
t
SDR
SDA Rise Time 300 ns
t
SDF
SDA Fall Time 300 ns
t
BFT
Bus-Free Time Between Stop and Start 1.3 s
Figure 9. I
2
C Port Timing
SSr
SDA
SCL
PS
t
SCLR
t
SCLF
t
SCLL
t
SCH
t
DH
t
SCLH
t
DS
t
SPS
t
BFT
t
SCS
t
SDR
t
SDF
t
SCS
t
SCH
Rev. B | Page 14 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Table 7. I
2
S Timing
1.8 V 3.3 V
Unit
Parameter Min Max Min Max
I
2
S Slave Timing Requirements (A
2
B Master)
t
BCLKW
BCLK Width 19.5 9.5 ns
t
BCLKS
BCLK Period 39.0 19.0 ns
t
SIS1
SYNC Input Setup Before BCLK Sample Edge 2.25 2.25 ns
t
SIH1
SYNC Input Hold After BCLK Sample Edge 2.0 3.0 ns
t
RISM1
DRXn Input Setup Before BCLK Sample Edge 0.5 0.5 ns
t
RIHM1
DRXn Input Hold After BCLK Sample Edge 2.0 1.5 ns
t
RISM1
DRX1 on DTX1 Input Setup Before BCLK Sample Edge 4.0 4.5 ns
t
RIHM1
DRX1 on DTX1 Input Hold After BCLK Sample Edge 0.5 0.5 ns
I
2
S Slave Switching Characteristics (A
2
B Master)
t
DODM2
DTXn Output Delay After BCLK Drive Edge 15.25 12.0 ns
t
DOHM2
DTXn Output Hold After BCLK Drive Edge 3.0 3.0 ns
t
DOENM2
DTXn Data Enable Delay After BCLK Drive Edge 2.0 2.0 ns
t
DODIM2
DTXn Data Disable Delay After BCLK Drive Edge 13.0 8.0 ns
I
2
S Master Timing Requirements (A
2
B Slave)
t
RISS1
DRXn Input Setup Before BCLK Sample Edge 0.0 0.0 ns
t
RIHS1
DRXn Input Hold After BCLK Sample Edge 5.8 2.0 ns
t
RISS1
DRX1 on DTX1 Input Setup Before BCLK Sample Edge 2.5 4.5 ns
t
RIHS1
DRX1 on DTX1 Input Hold After BCLK Sample Edge 2.5 0.5 ns
I
2
S Master Switching Characteristics (A
2
B Slave)
f
BCLK
BCLK Output Frequency
3
25.0 50.0 MHz
t
BCLKMOJ
BCLK Output Jitter (RMS Cycle to Cycle, f
BCLKS
= 12.288 MHz) 100 100 ps
t
SOL
/t
SOH
Transmit or Receive BCLK Duty Cycle 0.450.550.450.55t
BCLK
t
SOJ
SYNC Output Jitter (RMS Cycle to Cycle f
SYNCM
= 48 kHz) 2.2 2.2 ns
t
SOD2
SYNC Output Delay After BCLK Drive Edge 6.5 6.5 ns
t
SOHD2
SYNC Output Hold After BCLK Drive Edge 2.8 4.5 ns
t
DODS2
DTXn Output Delay After BCLK Drive Edge 10.8 9.25 ns
t
DOHS2
DTXn Output Hold After BCLK Drive Edge 5.5 6.0 ns
1
Referenced to sample edge.
2
Referenced to drive edge.
3
When V
IOVDD
= 3.3 V, the setup and hold timing at the 50 MHz maximum bit clock rate can be violated when interfacing with other I
2
S devices. The timing violations are seen
when the A
2
B slave node is receiving and A
2
B master node is transmitting. In these modes, the maximum BCLK frequency of 50 MHz cannot be achieved.
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Rev. B | Page 15 of 38 | January 2020
Figure 10. I
2
S Slave (A
2
B Master) Timing
Figure 11. I
2
S Master (A
2
B Slave) Timing
Figure 12. I
2
S Slave (A
2
B Master) Enable and Three-State Timing
tDOHM
tDODM
DRIVE EDGE SAMPLE EDGE
SYNC
BCLK/PDMCLK
tSIH
tRIHM
tBCLKW
tSIS
tRISM
MSB
-
1
MSB
-
1
MSB
MSB
TRANSMIT DATA
(DTXn) CHANNEL
RECEIVE DATA
(DRXn) CHANNEL
DRIVE EDGE SAMPLE EDGE
tSOHD
tRIHS
tDODS
tDOHS
tSOL
tSOD
tRISS
TRANSMIT DATA
(DTXn) CHANNEL
RECEIVE DATA
(DRXn) CHANNEL
SYNC
BCLK/PDMCLK
MSB
-
1
MSB
-
1
MSB
MSB
/tSOH
DRIVE EDGE DRIVE EDGE
tDOENM tDODIM
TRANSMIT DATA
(DTXn) CHANNEL
BCLK
Rev. B | Page 16 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
POWER-UP SEQUENCING RESTRICTIONS
When externally supplied, V
DVDD
and V
IOVDD
must reach at least
90% of specification before V
VIN
begins ramping. To avoid dam-
age to input pins and to ensure correct sampling of the
ADR1/ADR2 pins at start-up, V
IOVDD
must be within specifica-
tion before input signals are driven by external devices.
Table 8. Power-Up Timing
Parameter Min Max Unit
Timing Requirements
t
VIN
When Externally Supplied, V
DVDD
and V
IOVDD
Must Reach 90% of Specification
Before V
VIN
Begins Ramping
>0 ms
t
PORST
Minimum Time Required for V
VIN
to be Held Below V
RST
to Assert Power on Reset 25 ms
Figure 13. Power-Up Sequencing Timing with Externally Supplied V
DVDD
and V
IOVDD
V
DVDD
|
V
IOVDD
V
VIN
t
VIN
t
PORST
V
RST
MIN V
RSTN
MAX
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Rev. B | Page 17 of 38 | January 2020
A
2
B BUS SYSTEM SPECIFICATION
Table 9. A
2
B System Specifications
Parameter System Specification
Cable Unshielded, single, twisted pair wire (UTP) with 100 Ω differential impedance. EMC performance
and full functionality under worst-case environmental conditions is confirmed with Leoni Dacar
545 cable (76D00305).
Maximum Cable Length
AD2428(W)Mastered System 40 m total, 15 m between nodes.
AD2429(W) Mastered System 10 m total, 5 m between nodes.
Maximum Number of Nodes
AD2428(W) Mastered System 11 nodes (1 master node and 10 slave nodes).
AD2429(W) Mastered System Three nodes (1 master node and 2 slave nodes).
Maximum Number of Audio Slots
AD2426(W)/AD2427(W)/AD2428(W)
1
64 total, up to 32 upstream and 32 downstream slots, depending upon system design.
AD2420(W)/AD2429(W)
1
AD2429(W): 4 upstream and 2 downstream slots, depending upon system design.
AD2420(W): 2 upstream slots, depending upon system design.
Number of Audio Channels per Slave Node Individually programmable 0 to 32 upstream channels and 0 to 32 downstream channels.
Synchronous A
2
B Data Slot Size 8, 12, 16, 20, 24, 28, or 32 bits to match I
2
S/TDM data-word lengths. Same slot size for all nodes.
Upstream and downstream can choose different slot sizes. 12-, 16-, or 20-bit slot sizes can carry
compressed data over the A
2
B bus for 16-, 20-, or 24-bit I
2
S/TDM word lengths.
Audio Sampling Frequency 44.1 kHz to 48 kHz. All nodes sample synchronously. Slave node transceivers support sample rates
(f
S
) of 1× (48 kHz), 2× (96 kHz) or 4× (192 kHz), individually configured per slave.
To support 2× and 4× sampling rates in slaves, the master uses two and four times the number of
I
2
S/TDM data channels as the 1× sampling frequency (f
SYNCM
) interface to the host.
Transceivers also support reduced rate sampling for 24 kHz, 12 kHz, 6 kHz, 4 kHz, 3 kHz, 2.4 kHz,
2 kHz, 1.71 kHz, or 1.5 kHz at a low latency 48 kHz superframe rate.
Discovery Time Less than 35 ms per node. Much less than 350 ms for total system startup in a system with 10 nodes.
Includes register initialization.
Bit Error Detection Robust error detection for control data and status data with 16-bit cyclic redundancy check (CRC).
Error Correction Parity and line code error detection on synchronous data slots with audio error correction (repeat
of last known good data).
For 24-bit and 32-bit data channels, single error correction and double error detection (SECDED) of
synchronous data slots is possible.
Failure Diagnostics
1
Location and cause of failure can be detected for A
2
B wires shorted to a high voltage (for example,
positive terminal of car battery), shorted to ground, wires shorted to each other, wires reversed or
open connection.
System EMI/EMC Meets or exceeds industry specifications for robustness (ISO 11452-2, ISO 11452-4,
ISO 7637-3) and emissions (CISPR25).
System ESD See IEC ESD ratings in Table 12 for terminals.
1
See the AD2420(W)/6(W)/7(W)/8(W)/9(W) Automotive Audio Bus A
2
B Transceiver Technical Reference for more information.
Rev. B | Page 18 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
RMS Time Interval Error (TIE) Jitter
Clocks in an A
2
B system are passed from the master to Slave 0,
from Slave 0 to Slave 1, and so on. Each transceiver adds self jit-
ter to the incoming jitter, which results in jitter growth from the
master to the n
th
slave. Table 10 illustrates typical rms TIE jitter
growth.
PDM TYPICAL PERFORMANCE CHARACTERISTICS
Figure 14 through Figure 18 and Table 11 describe typical PDM
performance characteristics.
Table 10. SYNC Output RMS TIE Jitter at Each Slave
Slave Node Typ Max Unit
1 1.57 ns
2 1.79 ns
3 1.91 ns
4 2.04 ns
5 2.15 ns
6 2.27 ns
7 2.44 ns
8 2.47 ns
9 2.58 ns
10 2.70 5.50 ns
Figure 14. PDM FFT, f
SYNCM
= 48 kHz, –60 dB Frame Sync Input
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
–190
LEVEL (dBFS)
FREQUENCY (Hz)
20 100 1k 10k 20k
CH1
CH2
Figure 15. PDM Frequency Response
Figure 16. PDM Group Delay vs. Frequency, f
SYNCM
= 48 kHz
Figure 17. PDM Total Harmonic Distortion + Noise (THD + N) vs. Normal-
ized Frequency (Relative to f
SYNCM
)
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.0001 0.001 0.01 0.1 1
LEVEL (dBFS)
NORMALIZED FREQUENCY (RELATIVE TO
f
S
YN
C
M) (Hz)
0
20
40
60
80
120
100
140
160
GROUP DELAY (μs)
FREQUENCY (Hz)
10 100 1k 10k 100k
0.0001 0.001 0.01 0.1 1
–140
–120
–100
–80
–60
–20
–40
0
THD + N (dBFS)
NORMALIZED FREQUENCY (RELATIVE TO
f
SYNCM
) (Hz)
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Rev. B | Page 19 of 38 | January 2020
Figure 18. PDM Out of Band Frequency Response (48 kHz Output)
0
–20
–40
–60
–80
–100
–120
–140
–160
MAGNITUDE (dB)
FREQUENCY (MHz)
00.51.01.5
Table 11. PDM Interface Performance Specifications
Parameter Conditions Min Typ Max Unit
Dynamic Range 20 Hz to 20 kHz, –60 dB input
With A-Weighted Filter (RMS) 120 dB
SNR A-weighted, fourth-order input 120 dB
Decimation Ratio Default is 64× 64× 128× 256×
Frequency Response DC to 0.45 f
SYNCM
–0.1 +0.01 dB
Stop Band 0.566 f
SYNCM
Attenuation 74 dB
Group Delay 0.02 f
SYNCM
input signal 3.80 f
SYNCM
cycles
Gain PDM to PCM 0 dB
Start-Up Time
1
48 f
SYNCM
cycles
Bit Width Internal and output 24 Bits
1
The PDM start-up time is the time for the filters to settle after the PDM block is enabled. It is the time to wait before data is guaranteed to meet the specified performance.
Rev. B | Page 20 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
ABSOLUTE MAXIMUM RATINGS
Stresses at or above those listed in Table 12 can cause perma-
nent damage to the product. This is a stress rating only;
functional operation of the product at these or any other condi-
tions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum
operating conditions for extended periods may affect product
reliability.
Permanent damage can occur if the digital pin output current
per pin group value is exceeded. For example, if three pins from
Group 2 in Table 13 are sourcing or sinking 2 mA each, the total
current for those pins is 6 mA. Up to 9 mA can be sourced or
sunk by the remaining pins in the group without damaging the
device.
THERMAL CHARACTERISTICS
To determine the junction temperature on the application
printed circuit board (PCB), use the following equations:
T
J
= T
CASE
+ Ψ
JT
× P
D
where:
T
J
= junction temperature (°C).
T
CASE
= case temperature (°C) measured by customer at top cen-
ter of package.
Ψ
JT
= values in Table 14.
P
D
= power dissipation.
Values of
JA
are provided for package comparison and PCB
design considerations. Use
JA
for a first-order approximation
of T
J
by the following equation:
T
J
= T
A
+
JA
× P
D
where T
A
= ambient temperature (°C).
Values of
JC
are provided for package comparison and PCB
design considerations when an external heat sink is required.
Values of
JB
are provided for package comparison and PCB
design considerations.
Thermal characteristics of the LFCSP_SS package are shown in
Table 14. See JESD51-13 for detailed parameter definitions.
The junction to board measurement complies with JESD51-8.
The junction to case measurement complies with MIL-STD-883
(Method 1012.1). All measurements use a 2S2P JEDEC test
board.
Table 12. Absolute Maximum Ratings
Parameter Rating
VIN to VSS –0.7 V to +30 V
Power Supply IOVDD to VSS –0.3 V to +3.63 V
Power Supply DVDD to VSS –0.3 V to +1.98 V
Power Supply PLLVDD to VSS –0.3 V to +1.98 V
Power Supply TRXVDD to VSS –0.3 V to +3.63 V
Digital Pin Output Voltage Swing
1
1
Applies to BCLK, SYNC, DTX0/IO3, DTX1/DRX1/IO4, DRX0/IO5, DRX1/IO6,
IRQ/IO0, ADR1/IO1, ADR2/IO2, PDMCLK/IO7.
–0.3 V to V
IOVDD
+ 0.5 V
Input Voltage
2,
3
2
Only applies when the related power supply (V
IOVDD
) is within specification. When
the power supply is below specification, the range is the voltage being applied to
that power domain ± 0.2 V.
3
Applies when nominal V
IOVDD
is 3.3 V.
–0.33 V to +3.63 V
Input Voltage
2,
4
4
Applies when nominal V
IOVDD
is 1.8 V.
–0.33 V to +2.10 V
I
2
C Input Voltage
2,
5
5
Applies to SCL and SDA.
–0.33 V to +5.5 V
A
2
B Bus Terminal Voltage
AP, AN, BP, and BN Pins –0.5 V to +4.1 V
SENSE, SWP, VSSN Voltage to V
SS
+30 V maximum
Storage Temperature Range –65°C to +150°C
Junction Temperature While Biased –40°C to +125°C
ESD Rating HBM
VIN and SWP Pins ±2.5 kV
AP, AN, BP, and BN Pins ±2.5 kV
All Other Pins ±2.5 kV
ESD Rating FICDM
All Pins ±1.25 kV
System ESD Rating CON1-A and CON1-B
Terminals
6
6
CON1-A and CON1-B are connectors.
IEC 61000-4-2, Air Discharge ±15 kV
IEC 61000-4-2, Contact Discharge ±12 kV
Digital Pin Output Current per Pin Group
7
7
For more information, see the following description and Table 13.
15 mA
Table 13. Total Current Pin Groups
Group Pins in Group
1 IRQ/IO0, ADR1/IO1, ADR2/IO2
2 BCLK, SYNC, DTX0/IO3, DTX1/DRX1/IO4, DRX0/IO5,
DRX1/IO6, IO7
Table 14. Thermal Characteristics
Parameter Conditions Typical (°C/W)
JA
Airflow = 0 m/s 31.6
JMA
Airflow = 1 m/s 28.8
JMA
Airflow = 2 m/s 28.1
JC
Airflow = 0 m/s 4.6
JB
Airflow = 0 m/s 14.7
JT
Airflow = 0 m/s 0.20
JT
Airflow = 1 m/s 0.27
JT
Airflow = 2 m/s 0.30
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Rev. B | Page 21 of 38 | January 2020
The 32-lead LFCSP_SS package requires thermal trace squares
and thermal vias to an embedded ground plane in the PCB. The
exposed paddle must connect to ground for proper operation to
data sheet specifications. Refer to JEDEC standard JESD51-5 for
more information.
ESD CAUTION
TEST CIRCUITS AND SWITCHING
CHARACTERISTICS
Figure 19 shows a line driver voltage measurement circuit of the
differential line driver and receiver AP/AN and BP/BN pins.
OUTPUT DRIVE CURRENTS
Figure 20 through Figure 25 show typical current voltage char-
acteristics for the output drivers of the transceiver. The curves
represent the current drive capability of the output drivers as a
function of output voltage. Drive Strength 0 is DS0, and Drive
Strength 1 is DS1.
Figure 19. Differential Line Driver Voltage Measurement
Figure 20. GPIO, BCLK, and SYNC Drivers (DS0, 1.8 V IOVDD)
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
VOD ȍ
AP/BP
AN/BN
– 2.0
SOURCE CURRENT (mA)
0 0.4 0.8 1.2 2.0
4
– 6.0
VOL
IOVDD = 1.9V @ – 40
°C
IOVDD = 1.8V @ 25
°C
0
IOVDD = 1.7V @ 125
°C
– 4.0
– 8.0
2
1.60.2 0.6 1 1.4 1.8
SOURCE VOLTAGE (V)
8
6
VOH
Figure 21. GPIO, BCLK, and SYNC Drivers (DS0, 3.3 V IOVDD)
Figure 22. I
2
C Drivers (1.8 V IOVDD)
Figure 23. I
2
C Drivers (3.3 V IOVDD)
0
SOURCE CURRENT (mA)
0 1.0 2.0 3.0 4.0
– 20
VOL
10
IOVDD = 3.6V @ – 40
°C
IOVDD = 3.3V @ 25
°C
IOVDD = 3.0V @ 125
°C
– 10
– 30
20
0.5 1.5 2.5 3.5
SOURCE VOLTAGE (V)
30
VOH
– 1.5
SOURCE CURRENT (mA)
0 0.4 0.8 1.2 2.0
0
– 2.5
VOL
IOVDD = 1.9V @ – 40
°C
IOVDD = 1.8V @ 25
°C
– 1.0 IOVDD = 1.7V @ 125
°C
– 2.0
– 3.0
– 0.5
1.60.2 0.6 1 1.4 1.8
SOURCE VOLTAGE (V)
– 3.5
– 4.5
– 4.0
– 5.0
– 8
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
0 1.0 3.0 4.0
0
– 16
V
OL
IOVDD = 3.6V @ – 40
°C
IOVDD = 3.3V @ 25
°C
– 4 IOVDD = 3.0V @ 125
°C
– 12
2.00.5 2.5 3.51.5
– 6
– 14
– 2
– 10
– 18
Rev. B | Page 22 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
TEST CONDITIONS
All timing parameters in this data sheet were measured under
the conditions described in this section. Figure 26 shows the
measurement point for ac measurements (except output
enable/disable). The measurement point, V
MEAS
, is V
IOVDD
/2 for
V
IOVDD
(nominal) = 3.3 V.
Output Enable Time Measurement
Output pins are considered enabled when they make a transi-
tion from a high impedance state to the point when they start
driving.
The output enable time, t
ENA
, is the interval from the point when
a reference signal reaches a high or low voltage level to the point
when the output starts driving, as shown on the right side of
Figure 27. If multiple pins are enabled, the measurement value
is that of the first pin to start driving.
Output Disable Time Measurement
Output pins are considered disabled when they stop driving,
enter a high impedance state, and start to decay from the output
high or low voltage. The output disable time, t
DIS
, is the interval
from when a reference signal reaches a high or low voltage level
to the point when the output stops driving, as shown on the left
side of Figure 27.
Capacitive Loading
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all pins (see Figure 28). V
LOAD
is equal
to V
IOVDD
/2. Figure 29 through Figure 32 show how output rise
time varies with capacitance. The delay and hold specifications
given must be derated by a factor derived from these figures.
The graphs in Figure 29 through Figure 32 cannot be linear out-
side the ranges shown.
Figure 24. GPIO, BCLK, and SYNC Drivers (DS1, 1.8 V IOVDD)
Figure 25. GPIO, BCLK, and SYNC Drivers (DS1, 3.3 V IOVDD)
Figure 26. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)
– 10
SOURCE CURRENT (mA)
0 0.4 0.8 1.2 2.0
5
VOL
IOVDD = 1.9V @ – 40
°C
IOVDD = 1.8V @ 25
°C
– 5
IOVDD = 1.7V @ 125
°C
– 15
0
1.60.2 0.6 1 1.4 1.8
SOURCE VOLTAGE (V)
15
10
VOH
0
SOURCE CURRENT (mA)
0 1.0 2.0 3.0 4.0
–40
VOL
20
IOVDD = 3.6V @ – 40
°C
IOVDD = 3.3V @ 25
°C
IOVDD = 3.0V @ 125
°C
– 20
– 60
40
0.5 1.5 2.5 3.5
SOURCE VOLTAGE (V)
60
VOH
INPUT
OR
OUTPUT
V
MEAS
V
MEAS
Figure 27. Output Enable/Disable
REFERENCE
SIGNAL
tDIS
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE
OUTPUT STOPS DRIVING
tENA
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Rev. B | Page 23 of 38 | January 2020
Figure 28. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Figure 29. GPIO Driver Typical Rise and Fall Times (10% to 90%) vs. Load
Capacitance (V
IOVDD
= 1.8 V, T
J
= 25°C)
T1
ZO = 50:(impedance)
TD = 4.04 r 1.18 ns
2pF
TESTER PIN ELECTRONICS
50:
0.5pF
70:
400:
45:
4pF
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, THE SYSTEM CAN INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
V
LOAD
DUT
OUTPUT
50:
0
2
4
6
8
10
12
14
18
16
05 10152025303540
45
tRISE
tFALL
RISE AND FALL TIMES (ns)
LOAD CAPACITANCE (pF)
DRIVE STRENGTH = 0
Figure 30. GPIO Driver Typical Rise and Fall Times (10% to 90%) vs. Load
Capacitance (V
IOVDD
= 1.8 V, T
J
= 25°C)
Figure 31. GPIO Driver Typical Rise and Fall Times (10% to 90%) vs. Load
Capacitance (V
IOVDD
= 3.3 V, T
J
= 25°C)
Figure 32. GPIO Driver Typical Rise and Fall Times (10% to 90%) vs. Load
Capacitance (V
IOVDD
= 3.3 V, T
J
= 25°C)
0
1
2
3
4
5
6
7
9
8
05 1015202530354045
tRISE
tFALL
RISE AND FALL TIMES (ns)
LOAD CAPACITANCE (pF)
DRIVE STRENGTH = 1
0
1
2
3
4
5
6
7
10
9
8
010 20 30 40 50 60
tRISE
tFALL
RISE AND FALL TIMES (ns)
LOAD CAPACITANCE (pF)
DRIVE STRENGTH = 0
0
1
2
3
4
5
6
7
8
010 20 30 40 50 60 70 80 90
tRISE
tFALL
RISE AND FALL TIMES (ns)
LOAD CAPACITANCE (pF)
DRIVE STRENGTH = 1
Rev. B | Page 24 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
The 32-lead LFCSP_SS package pin configuration is shown in
Figure 33. The pin function descriptions are shown in Table 15.
All digital inputs and digital outputs are three-stated with inputs
disabled during reset.
Figure 33. 32-Lead LFCSP_SS and LFCSP Package Pin Configuration
Table 15. AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) Pin Function Descriptions
Pin
No. Pin Name Type
Alternate
Functions
1
Description
1 PLLVDD PWR None Power Supply for PLL. PLLVDD can be supplied by V
VOUT1
.
2, 3 DVDD PWR None Power Supply for Digital Core Logic. DVDD can be supplied by V
VOUT1
.
4
2
SCL D_IO None Serial Clock for I
2
C Data Transfers. Digital input in A
2
B master mode. Digital input (I
2
C slave) or
output (I
2
C master) in A
2
B slave mode. This pin uses open-drain I/O cells and must be pulled up
to V
I2C_VBUS
through a resistor (consult Version 2.1 of the I
2
C bus specification for the proper
resistor value). Connect the pin to ground when the I
2
C interface is not used.
5
2
SDA D_IO None I
2
C Mode Serial Data. This pin is a bidirectional open-drain input/output and must be pulled up
to V
I2C_VBUS
through a resistor (consult Version 2.1 of the I
2
C bus specification for the proper
resistor value). Connect the pin to ground if the I
2
C interface is not used.
6
2
IRQ/IO0 D_IO None Interrupt Request Output. In master mode, A
2
B transceivers create event driven interrupt
requests towards the host controller.
In slave mode, this pin indicates mailbox empty/full status to the slave node processor when
mailbox interrupts are enabled.
When not serving as an interrupt output pin, this pin serves as a general-purpose I/O pin with
interrupt request input capability. The IRQ/IO0 pin must be initialized to become either an input
or an output. This pin is high impedance by default.
7
2
ADR1/IO1 D_IO CLKOUT1 The ADR1/IO1 and ADR2/IO2 pins set the I
2
C slave device address during power-on reset; up to
four A
2
B master transceiver chips connect to the same I
2
C bus. The ADR1/IO1 pin is high
impedance by default. The ADR1/IO1 pin can then be initialized to become a general-purpose
input/output (GPIO) pin with interrupt request capability.
This pin can be programmed to become a clock output (CLKOUT1). The clock output can be used
as a master clock for connected ADCs and DACs or to synchronize switching voltage regulators.
In this table, the Type is defined as follows: PWR = power/ground, A_IN = analog input, D_OUT = digital output, A_IO = analog input/output,
D_IO = digital input/output, N/A = not applicable.
VOUT1
VSS
VIN
VOUT2
SENSE
SWP
VSSN
VSS
910111213141516
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32 31 30 29 28 27 26 25
PLLVDD
DVDD
DVDD
SCL
SDA
IRQ/IO0
ADR1/IO1
ADR2/IO2
IOVDD
BCLK
SYNC
DTX0/IO3
DTX1/IO4
DRX0/IO5
DRX1/IO6
PDMCLK/IO7
BCM
BN
BP
BTRXVDD
ATRXVDD
AP
AN
ACM
EPAD
(PIN 33)
TOP VIEW
PIN 33 IS THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE. THIS PIN MUST BE CONNECTED TO GND.
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Rev. B | Page 25 of 38 | January 2020
8
2
ADR2/IO2 D_IO CLKOUT2 The ADR1/IO1 and ADR2/IO2 pins set the I
2
C slave device address during power-on reset; up to
four A
2
B master transceiver chips connect to the same I
2
C bus. The ADR2/IO2 pin is high
impedance by default. The ADR2/IO2 pin can then be initialized to become a general-purpose
input/output (GPIO) pin with interrupt request capability.
This pin can be programmed to become a clock output (CLKOUT2). The clock output can be used
as a master clock for connected ADCs and DACs or to synchronize switching voltage regulators.
9 IOVDD PWR None Power Supply for Digital Input and Output Pins. The digital output pins are supplied from IOVDD,
which also sets the highest input voltage that is allowed on the digital input pins. Two I/O voltage
ranges are supported (see V
IOVDD
specifications in the Operating Conditions section). The current
draw of these pins is variable and depends on the loads of the digital outputs. IOVDD can be
sourced by either the VOUT1 or VOUT2 pin. However, if the signals do not originate from logic
supplied by the VOUT1 pin or VOUT2 pin, source IOVDD with an external supply.
10 BCLK D_IO PDMCLK Bit Clock. Digital input in master mode. Digital output in slave mode.
When using the PDM interface in slave mode, this pin can operate as the clock output (PDMCLK)
for PDM microphones (the PDMCLK/IO7 pin can also be used).
11 SYNC D_IO None Synchronization Signal. Digital input in master mode. Digital output in slave mode.
For the AD2428W and AD2429W, the SYNC signal frames a multichannel I
2
S/TDM data stream.
An A
2
B master node must have a continuous signal because the A
2
B master transceiver derives
all clocking information for itself and for the A
2
B bus from this input.
When this pin stops toggling, the A
2
B bus resets after a delay. For more information, see Table 3.
12
2
DTX0/IO3 D_IO None For the AD2428W and ADW2429W, serial I
2
S/TDM data is driven to the DTX0/IO3 pin in multi-
channel I
2
S/TDM format.
This pin serves as the IO3 general-purpose I/O pin when DTX0 function is disabled. The DTX0/IO3
pin is high impedance by default until configured. The pin returns to high impedance when the
chip resets due to a missing synchronization signal or low supply voltage.
For the ADW2420W, AD2426W, and AD2427W, this pin is GPIO only (IO3).
13
2
DTX1/IO4 D_IO DRX1 For the AD2428W and AD2429W, serial I
2
S/TDM data is driven to the DTX1/IO4 pin in multi-
channel I
2
S/TDM format.
When configured as the alternate DRX1 location, the DTX1/IO4 pin receives data presented in
multichannel I
2
S/TDM format. This alternate location can be used when the DRX0/IO5 and
DRX1/IO6 pins are used to receive PDM microphone data.
This pin serves as the IO4 general-purpose I/O pin when DTX1 and DRX1 functions are disabled.
The DTX1/IO4 pin is high impedance by default until configured. The pin returns to high
impedance when the chip resets due to a missing synchronization signal or low supply voltage.
For the AD2420W, AD2426W, and AD2427W, this pin is GPIO only (IO4).
14
2
DRX0/IO5 D_IO PDM0 For the AD2428W and AD2429W, serial I
2
S/TDM data is received on the DRX0/IO5 pin in multi-
channel I
2
S/TDM format. This pin is an input for microphone data when enabled as a PDM input
(PDM0). This pin serves as the IO5 GPIO pin when DRX0 and PDM0 functions are disabled. The
DRX0/IO5 pin is high impedance by default until configured. The pin returns to high impedance
when the chip resets due to a missing synchronization signal or low supply voltage.
For the AD2420W, AD2426W, and AD2427W, the DRX0 function is not supported.
Table 15. AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) Pin Function Descriptions (Continued)
Pin
No. Pin Name Type
Alternate
Functions
1
Description
In this table, the Type is defined as follows: PWR = power/ground, A_IN = analog input, D_OUT = digital output, A_IO = analog input/output,
D_IO = digital input/output, N/A = not applicable.
Rev. B | Page 26 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
15
2
DRX1/IO6 D_IO PDM1 For the AD2428W and AD2429W, serial I
2
S/TDM data is received on the DRX1/IO6 pin in multi-
channel I
2
S/TDM format. This pin is an input for microphone data when enabled as a PDM input
(PDM1). This pin serves as the IO6 GPIO pin when DRX1 and PDM1 functions are disabled. The
DRX1/IO6 pin is high impedance by default until configured. The pin returns to high impedance
when the chip resets due to a missing synchronization signal or low supply voltage.
For the AD2420W, AD2426W, and AD2427W, the DRX1 function is not supported.
16
2
PDMCLK/IO7 D_IO RRSTRB PDM Microphone Clock Output.
In master mode, the PDM clock output (PDMCLK) is used to clock PDM microphones. This pin
runs at 64× the SYNC frequency regardless of the BCLK rate used by the host.
When using the PDM interface in slave mode, this pin can still operate as the clock output for
PDM microphones (PDMCLK), but BCLK can also be used.
When PDM functions are disabled, this pin serves as the IO7 GPIO pin. The PDMCLK/IO7 pin can
also be used as a strobe to indicate when reduced rate data is updated (RRSTRB). The
PDMCLK/IO7 pin is high impedance by default until configured. The pin returns to high
impedance when the chip resets due to a missing synchronization signal or low supply voltage.
17 ACM A_IN None Common-Mode Input for Bidirectional, Differential A
2
B Line Transceiver A.
18 AN A_IO None Inverted Pin of Bidirectional, Differential A
2
B Line Driver and Receiver A. Pin 18 is directed
towards the master. Pin 18 is self biased.
19 AP A_IO None Noninverted Pin of Bidirectional, Differential A
2
B Line Driver and Receiver A. Pin 19 is directed
towards the master. Pin 19 is self biased.
20 ATRXVDD PWR None Power Supply for A
2
B Line Driver and Receiver Circuit. Decouple these pins to VSS with one
shared 100 nF capacitor and a shared 10 nF capacitor closest to the pin. The pins can be supplied
by VOUT2. Supply the ATRXVDD pin for a master, last slave, or daisy-chained slave.
21 BTRXVDD PWR None Power Supply for A
2
B Line Driver and Receiver Circuit. Decouple these pins to VSS with one
shared 100 nF capacitor and a shared 10 nF capacitor closest to the pin. The pins can be supplied
by VOUT2. Supply the BTRXVDD pin for a master, last slave, or daisy-chained slave
22 BP A_IO None For the AD2427W, AD2428W, and AD2429W, this is the noninverted pin of bidirectional, differ-
ential A
2
B l i ne dr i ver a nd Re ce i ve r B, wh i ch is d ire c te d towards the last slave. This pin is self biased.
23 BN A_IO None For the AD2427W, AD2428W, and AD2429W, this is the inverted pin of bidirectional, differential
A
2
B line driver and Receiver B, which is directed towards the last slave. This pin is self biased.
24 BCM A_IN None For the AD2427W, AD2428W, and AD2429W, this is the common-mode input for bidirectional,
differential A
2
B Line Transceiver B.
25 VSS PWR None Power Supply Pin for Return Currents. Connect the VSS pin to a low impedance local VSS ground
plane.
26 VSSN PWR None For the AD2427W, AD2428W, and AD2429W, this is the power supply return current connection
for the next slave device. Connect to the inductor that provides the negative bias for the next
slave device. The AD2427W, AD2428W, and AD2429W connect VSSN to the local VSS potential
to sequence power to the next slave devices in the chain. VSSN automatically disconnects under
critical fault conditions.
27 SWP D_OUT None For the AD2427W, AD2428W, and AD2429W, this is the active low open-drain output to drive
the gate of a PMOS switch. The switch is open (SWP pin is high) by default. The switch can be
closed (SWP pin goes low) to sequence power to the next slave devices in the chain. The switch
automatically opens (SWP goes high) under critical fault conditions.
28 SENSE A_IN None Analog input to sense the power supplied to the next slave device. For the AD2420W, AD2426W,
or a last in line AD2427W/AD2428W/AD2429W, connect this pin to local ground through a 33 kΩ
pull-down resistor.
Table 15. AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) Pin Function Descriptions (Continued)
Pin
No. Pin Name Type
Alternate
Functions
1
Description
In this table, the Type is defined as follows: PWR = power/ground, A_IN = analog input, D_OUT = digital output, A_IO = analog input/output,
D_IO = digital input/output, N/A = not applicable.
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Rev. B | Page 27 of 38 | January 2020
29 VOUT2 PWR None Second Output of the On-Chip low Dropout Voltage Regulator. The voltage output on this pin
provides a regulated supply to the TRXVDD supply pins. External devices also can be powered
by this supply if the current consumption is within the specification. Decouple VOUT2 to VSS
with a 4.7 µF capacitor.
30 VIN PWR None Power supply pin that accepts a wide input voltage range (see the V
VIN
specification in the
Operating Conditions section) for an on-chip low dropout voltage regulator.
31 VSS PWR None Power Supply Pin for Return Currents. Connect the VSS pin to a low impedance local VSS ground
plane.
32 VOUT1 PWR None First Output of the On-Chip Low Dropout Voltage Regulator. The voltage output on this pin
provides a regulated supply to the DVDD and PLLVDD power supply pins. External devices can
be powered by this supply if the current consumption is within the specification. Decouple
VOUT1 to VSS with a 4.7 µF capacitor.
33 EPAD PWR None Power Supply Pin for Return Currents. See other VSS pin description in this table. This pin is the
exposed pad on the bottom of the package and must be connected to GND.
1
See the AD2420(W)/6(W)/7(W)/8(W)/9(W) Automotive Audio Bus A
2
B Transceiver Technical Reference for more information about configuring pins for alternate functions.
2
If the listed functions for this pin are not required, do not connect this pin.
Table 15. AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) Pin Function Descriptions (Continued)
Pin
No. Pin Name Type
Alternate
Functions
1
Description
In this table, the Type is defined as follows: PWR = power/ground, A_IN = analog input, D_OUT = digital output, A_IO = analog input/output,
D_IO = digital input/output, N/A = not applicable.
Rev. B | Page 28 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
POWER ANALYSIS
This section provides information on power consumption of the
A
2
B system. The intent of power dissipation calculations is to
assist board designers in estimating power requirements for
power supply and thermal relief designs.
Power dissipation on an A
2
B node depends on various factors,
such as the required external peripheral supply current and bus
activity. An A
2
B system can be comprised of a mix of bus pow-
ered slaves and local powered slaves. A bus powered slave
derives power from the A
2
B bus wires. A local powered slave
derives power from separate power wires. Power estimation for
a bus powered system is more complex when compared to a
local powered system. For power analysis, A
2
B systems with
both local and bus powered slaves must be divided into seg-
ments of nodes that draw from the same power supply.
CURRENT FLOW
Figure 34 describe key parameters and equations to calculate
power dissipation on the transceiver. The current flow on an
A
2
B node incorporates the described current paths.
•Constant current
•I
PLLVDD
— PLL supply current
•I
VINQ
— VIN quiescent current
•I
2
C I/O current
•I
IOVDD
— I
2
S/TDM/PDM I/O current
•I
VEXT1
or I
VEXT2
— peripheral supply currents
•I
DVDD
— digital logic supply current
•I
TRXVDD
— A
2
B bus TX/RX current
• LVDS transceiver supply currents of A and B trans-
ceivers — transmit LVDS TX and receive LVDS RX
I
2
C activity and the resulting I/O current is considered negligi-
ble when compared to other currents. Therefore, the on-chip
I
2
C I/O current is not considered when calculating the current
consumption.
Constant Current
All currents that are not influenced directly by A
2
B bus activity
on other nodes fall under the category of constant current.
PLL Supply Current
The PLL supply current is specified as I
PLLVDD
, which is the static
current in an active transceiver.
VIN Quiescent Current
The VIN quiescent current is specified as the static current
I
VINQ
. It is independent of the load and does not include any
power drawn from the voltage regulator output pins.
IOVDD Current
The on-chip I
2
S/TDM/PDM I/O current I
IOVDD
is based on
dynamic switching currents on the BCLK, SYNC, DTX0, DTX1,
DRX0, and DRX1 pins.
The dynamic current, due to switching activity on an output
pin, is calculated using the following equation:
Output Dynamic Current = (C
PDout
+ C
L
) × V
IOVDD
× f
where:
C
PDout
= dynamic, transient power dissipation capacitance inter-
nal to the transceiver output pins.
C
L
= total load capacitance that an output pin sees outside the
transceiver.
V
IOVDD
= voltage on a digital pin.
f = frequency of switching on the pin.
The dynamic current, due to switching activity on an input pin,
is calculated using the following equation:
Input Dynamic Current = C
PDin
× V
IOVDD
× f
where:
C
PDin
= dynamic, transient power-dissipation capacitance inter-
nal to the input pins of the transceiver.
I
IOVDD
= the sum of input and output dynamic currents of all
pins internally supplied by the IOVDD pin.
f = frequency of switching on the pin.
Figure 34. Current Flow Model
I
VINQ
VSS
I
IOVDD
I
VOUT1
IOVDD DVDD ATRXVDDPLLVDD VINVOUT1
A2B TRANSCEIVER
3.3V1.9V
VOUT2 BTRXVDD
I
VOUT2
I
VIN
I
ATRXVDD
I
BTRXVDD
I
DVDD
I
PLLVDD
I
VEXT1
I
VEXT2
Peripheral
Device(s)
I
VEXT2
+ I
VEXT1
VREG1/2
IVSSN VSSN
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Rev. B | Page 29 of 38 | January 2020
Peripheral Supply Current
Peripheral components that are external to the transceiver also
can be supplied through the voltage regulator outputs of V
VOUT1
and V
VOUT2
. V
VOUT1
can supply the current specified as I
VEXT1
to
external devices. V
VOUT2
can supply the current specified as
I
VEXT2
to external devices.
When bus powered, peripheral supply current draw has a direct
impact on other nodes in the system. It is important to stay
within the thermal package limits and not exceed the specifica-
tion limits of I
VSSN
and V
VIN
in any of the A
2
B bus nodes.
Digital Logic Supply Current
The digital logic supply current I
DVDD
is a combination of static
current consumption and digital TX/RX current.
A
2
B Bus TX/RX Current
The level of A
2
B bus activity directly influences current con-
sumption on both the LVDS transceivers related to A
2
B
transmitter and receiver processing.
LVDS Transmitter and Receiver Supply Currents
The current I
TRXVDD
depends on I
TXVDD
and I
RXVDD
at 100% activ-
ity level and A
2
B bus activity:
• Downstream LVDS transceiver current
•B transceiver I
BTXVDD
LVDS TX current results from
downstream TX activity level of the current node.
•A transceiver I
ARXVDD
LVDS RX current results from
downstream activity level of the previous node.
• Upstream LVDS transceiver current
•A transceiver I
ATXVDD
LVDS TX current results from
A side upstream activity level of the current node.
•B transceiver I
BRXVDD
LVDS RX current results from
upstream activity level of the next in line node.
Downstream/Upstream Activity Level
The activity level for downstream data of TRX B is determined
by the following:
• Header bits for downstream. A
2
B systems use 64 down-
stream header bits referred to as a synchronization control
frame (SCF).
• The number of downstream data bits transmitted in
a node = the number of downstream transmitted slots ×
(bits per slot + parity bit) where the parity bit = 1. The
number of downstream transmitted slots does not include
the locally consumed slots.
• B side downstream transmitter activity level of a node.
(SCF bits + number of downstream transmitted data bits) ÷
1024.
The activity level for upstream data of TRX A is determined by
the following:
• Header bits for upstream. (SRF bits + total number of
received downstream data bits) ÷ 1024.
• The number of upstream data bits transmitted in a node =
number of upstream transmitted slots × (bits per slot +
parity bit) where the parity bit = 1. The number of
upstream transmitted slots is the sum of received upstream
slots and locally contributed slots.
• A side upstream transmitter activity level of a node.
(SRF bits + number of transmitted upstream data bits) ÷
1024.
LVDS Transmitter and Receiver Idle Current
The idle current, I
TRXVDD_IDLE
, depends on I
TXVDD
and I
RXVDD
at
0% activity level and A
2
B bus idle time.
• B transceiver idle current. B Transceiver I
BTRXVDD_IDLE
LVDS current results from B transceiver idle time.
•A transceiver idle current. A Transceiver I
ATRXVDD_IDLE
LVDS current results from A transceiver idle time.
• B transceiver idle time. B transceiver idle time is the time
when both the TX and RX of the B transceiver are idle.
The idle time of the B transceiver is derived by eliminating
the following activity levels from the B transceiver frame
cycle:
• B transceiver downstream activity level of the current
node.
• A transceiver upstream activity level of the next in line
node.
• A transceiver idle time is the time when both the TX and
RX of the A transceiver are idle.
The idle time of the A transceiver is derived by eliminating
the following activity from the A transceiver frame cycle:
• A transceiver upstream activity level of the current
node.
• B transceiver downstream activity level of previous
node.
The sum of the LVDS transceiver currents is
I
TRXVDD
= I
BRXVDD
+ I
BTXVDD
+ I
ARXVDD
+ I
ATXVDD
+
I
BTRXVDD_IDLE
+ I
ATRXVDD_IDLE
VREG1 AND VREG2 OUTPUT CURRENTS
Voltage regulator output currents are governed by the following
equations:
I
VOUT2
is the current from V
VOUT2
which is the sum of the LVDS
transmitter and receiver supply currents, peripheral supply cur-
rents, and I/O current.
I
VOUT2
= I
TRXVDD
+ I
IOVDD
+ I
VEXT2
I
VOUT1
is the current from the V
OUT1
pin which is the sum of PLL
supply current, I
PLLVDD
, digital logic supply current I
DVDD
,
peripheral supply current, I
VEXT1
, and I
2
S/TDM/PDM I/O cur-
rent I
IOVDD
.
I
VOUT1
= I
PLLVDD
+ I
VEXT1
+ I
DVDD
+ I
IOVDD
I
IOVDD
in a slave node can be sourced by either I
VOUT1
or I
VOUT2
but not both, depending on whether I
IOVDD
is supplied from
V
VOUT1
or V
VOUT2
.
Rev. B | Page 30 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
CURRENT AT VIN (I
VIN
)
The current at the VIN pin (I
VIN
) of the transceiver is the sum of
currents I
VOUT1
and I
VOUT2
and the quiescent current, shown in
Figure 34 and in the following equation:
I
VIN
= I
VOUT1
+ I
VOUT2
+ I
VINQ
The A side node current is the line bias current from an earlier
node. In a bus powered node, it is also the power supply current
and a portion of this current supplies the next in line nodes.
I
A
= I
VIN
+ I
B
+ I
VREGPERI
where:
I
B
= B side current to the next node (= I
VSSN
return current and
I
A
of the next in line node).
I
VREGPERI
= peripheral current supplied from I
A
by extra voltage
regulator, external to the transceiver (not illustrated in Figure 35
and Figure 36).
POWER DISSIPATION
The power dissipation of the transceiver is calculated using the
following equation:
Power =
I
VIN
× V
VIN
+ (I
VSSN
)
2
× R
VSSN
– I
VEXT1
× V
VOUT1
– I
VEXT2
× V
VOUT2
where:
I
VIN
= current at VIN pin.
V
VIN
= voltage at VIN pin.
I
VSSN
= B side current I
B
to the next node and return current
from the next node. The next node is the node connected to the
B terminal of the current node. See Figure 35.
R
VSSN
= internal V
SSN
on resistance (see Table 16).
I
VEXT1
= peripheral supply current from V
VOUT1
.
I
VEXT2
= peripheral supply current from V
VOUT2
.
V
VOUT1
= output voltage from V
REG1
.
V
VOUT2
= output voltage from V
REG2
.
RESISTANCE BETWEEN NODES
Figure 35 shows the dc model of a system with a combination of
local and bus powered A
2
B slaves.
A voltage drop of the dc bias is observed between the A
2
B nodes,
due to resistance and current consumption. Table 16 lists the
causes of the dc resistance between nodes (R
BETWEEN
) with exam-
ple resistance values.
Both bias supply and return currents are subject to resistance.
Therefore, some resistance values must be doubled (for exam-
ple, wire length resistance).
Table 16. Breakdown/Budget of Typical DC Resistance
Between Nodes
Resistance Each Qty Total Unit
Inductor DC Resistance 0.26 4 1.04 Ω
Short Circuit Protection Resistor 1.05 1 1.05 Ω
Positive Bias PMOS Switch
On-Resistance
0.11 1 0.11 Ω
Negative Bias Switch
On-Resistance R
VSSN
1.2 1 1.2 Ω
Resistance of Connections 0.01 4 0.04 Ω
Total R
SUM
N/A
1
1
N/A means not applicable.
N/A
1
2.39 Ω
Wire Length Resistance of Cable 0.121 2 0.242 Ω/m
Figure 35. A
2
B DC Power Model for a System with Local and Bus Powered Slaves
Master Node
IB
IVIN
IVSSN
IA
FB
PMOS
FB
Connections
FB
Cable
VREG
IA
B
ISUM
<VVIN max
IB
ISUM
VNODE0
VNODEM
LOCAL POWER
Connections
Cable
Slave Node 0
FB
PMOS
FB
Connections
FB
Cable
VREG
B
<VVIN min
Connections
Cable
R8
FB
Slave Node n
AD2426(W)/
AD2427(W)/
AD2428(W)
VSS
VIN
VSSN
VNODEn
BAA
A
BUS POWER
AD2428(W)
VSS VSSN VSS VSSN
VIN VIN
AD2427(W)/
AD2428(W)
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Rev. B | Page 31 of 38 | January 2020
VOLTAGE REGULATOR CURRENT IN MASTER NODE
OR LOCAL POWERED SLAVE NODE
The bus power, required from a local powered node (master
node) for powering all nodes in the system, is calculated using
the following equation:
I
SUM
= I
VIN
+ I
VSSN
+ I
INRUSH
+ I
VREGPERI
where:
I
VIN
is the current to V
VIN
of the local powered mode.
I
VSSN
is the return current from next in line slave node. It is equal
to the I
A
current supplied to the next in line node.
I
INRUSH
is the inrush current required to charge capacitors on the
VIN pin at power-up.
I
VREGPERI
is the input current of extra V
REG
for peripherals (not
illustrated in Figure 35 and Figure 36).
Analog Devices recommends a minimum I
INRUSH
of 150 mA
to support the components shown in the reference schematics.
The selected voltage regulator must be sized to meet I
SUM
for the
application.
I
VSSN
current is below 2 mA when the next in line node is a local
powered slave with a circuit-based on the Designer Reference
section. The I
SUM
current in most applications is less than 100 mA
if the next in line node is a local powered slave node.
More current, I
VSSN
, is drawn if the next in line node uses bus
power.The I
VSSN
maximum specification limits the bus power
draw of slave nodes, especially in a line of bus powered slaves.
POWER DISSIPATION OF A
2
B BUS
The power dissipation of an A
2
B system is calculated as follows:
Power Dissipation = I
SUM
× V
VIN
of master.
POWER ANALYSIS OF BUS POWERED SYSTEM
Figure 36 shows the dc model for a bus powered A
2
B system.
Power equations in this data sheet are used for power calcula-
tions in the SigmaStudio
®
software. The power equations are
also available in an Excel spreadsheet, provided by technical
support upon request.
SUPPLY VOLTAGE
The supply voltage (V
VIN
) level on a bus powered transceiver is
predictable and can be calculated using the following equations
derived from Figure 36.
For the master node, the supply voltage is calculated as,
V
NODEM
= V
REGM
– V
DIODE3
V
VIN
= V
REGM
– V
DIODE1
for master
For a slave node, the supply voltage is calculated as,
V
NODE
= V
NODE
' – I
A
× R
BETWEEN
V
VIN
= V
NODE
– V
DIODE1
where:
V
NODE
' is the V
NODE
voltage potential of the earlier node. The ear-
lier node is the node connected to the A side transceiver of the
current node.
R
BETWEEN
is the connection resistance between the current and
earlier node, described in the Resistance Between Nodes section.
V
DIODE
is the voltage drop of the Shottkey reverse polarity pro-
tection diode.
I
A
is the current that a bus powered slave node draws from an
earlier node.
Figure 36. A
2
B Power Model for Bus Powered System
Master Node Slave Node 0 Slave Node n
IB
Connection
Cable
IVIN
IB
IA
PMOS
FB
FB
FB
FB
Cable
VSS
VIN
PMOS
FB
Connections
FB
Cable
Cable
VREG
FB
IA
BABA
Connections
ISUM
>VVIN min
<VVIN max
FB
IVSSN
ISUM
B
VNODE0VNODEn
VNODE
M
Connections
Connections
D3
D1
AD2428(W)
VSS
VSS
VSSN VSSN VSSN
VIN VIN
AD2427(W)/
AD2428(W)
AD2426(W)/
AD2427(W)/
AD2428(W)
A
Rev. B | Page 32 of 38 | December 2019
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
For a system with all in-line bus powered nodes, I
A
is calculated
cumulatively from the last in-line node as
I
A
= I
VIN
+ I
B
where:
I
A
= current that a bus powered slave node draws from an earlier
node.
I
VIN
= current at VIN pin.
I
B
= B side return current from the next in line node. The next in
line node is the node connected to the B terminal of the current
node.
REDUCING POWER CONSUMPTION
The following sections describe three methods that reduce
power consumption.
Power-Down Mode
Any node in an A
2
B bus powered system can be shut down by
disconnecting the power supply in the previous slave node
(towards the master). Disconnecting a slave from the power
supply also powers down all of the following slaves (towards the
last slave).
Standby Mode
The A
2
B bus enters standby mode by setting the
AD242X_DATCTL.STANDBY bit of the master. The SCF in
standby mode is 19 bits long, instead of 64 bits. In standby
mode, there is no upstream and no downstream traffic on the
A
2
B bus, and only a minimal SCF keeps all the slave nodes syn-
chronized. This keeps the A
2
B bus power in the lowest power
state while maintaining clock synchronization between nodes.
Using the equations in the Downstream/Upstream Activity
Level section, the bus activity level in standby mode is,
• Downstream activity level = 19 ÷ 1024 = 1.9%
•Upstream activity level = 0%
The digital transceiver current, including the LVDS TX and RX
current, are subject to the activity levels. The LVDS TX and RX
current also are subject to idle current during the bus idle time.
Control Mode
In control mode, there are no data channels in a superframe.
The superframe only has the 64-bit SCF and SRF in the frame
with the control data embedded in the header bits. Therefore,
the A
2
B bus power is less when compared to normal mode,
which has data channels in the superframe. Using the equations
in the Downstream/Upstream Activity Level section, the bus
activity level in control mode is,
• Bus activity level downstream = 64 ÷ 1024 = 6.3%
• Bus activity level upstream = 64 ÷ 1024 = 6.3%
The LVDS TX and RX current also are subject to idle current
during the bus idle time.
THERMAL POWER
When calculating power, system designers must consider ther-
mal power. Thermal power calculations are based on the
package thermal characteristics, shown in the following
equation:
JA
= thermal resistance
(T
J
– T
A
) ÷ power [°C/W] with airflow = 0 m/s
Table 17 provides the thermal power allowance example. These
values are derived from a JEDEC standard 2S2P test board.
JA
values vary significantly and depend on system design and con-
ditions. For the example calculation in Table 17, the
JA
value
provided is determined using the JEDEC standard conditions.
In this example (Table 17), a slave node with 292 mW of power
dissipation is used to provide the maximum estimated power.
The margin is calculated by subtracting the maximum estimated
power from the thermal power allowance.
Table 17. Thermal Power Allowance Example
Parameter Example Value Unit
T
A
105 °C
T
J
125 °C
Delta (T
J
– T
A
)20°C
Example
JA
31.6 °C/W
Maximum Allowed Thermal Power 633 mW
Maximum Estimated Power 292 mW
Power Margin 341 mW
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Rev. B | Page 33 of 38 | January 2020
DESIGNER REFERENCE
The following sections provide descriptions and layouts of some
typical node configurations.
An A
2
B-compliant master transceiver requires external compo-
nents to pass EMC and ESD tests in the automotive
environment and support full line diagnostics functionality.
Diodes are required for correct line diagnostics and to prevent
damage under line fault conditions. The master circuit must
also supply bias voltage for line diagnostics and power supply to
bus powered slaves.
An A
2
B-compliant, last in the line, local powered, slave node
transceiver requires external components to pass EMC and ESD
tests in the automotive environment. The circuit must allow for
full line diagnostics with properly terminated A
2
B bus bias and
properly terminated signals. The circuit must also electrically
isolate the local powered slave node from the earlier node to
prevent line faults triggered by the formation of ground loops
across power and communication wires.
An A
2
B-compliant, local powered, slave node transceiver
requires external components to pass EMC and ESD tests in the
automotive environment. The circuit must allow for full line
diagnostics with properly terminated A
2
B bus bias and properly
terminated signals (A-side). The local powered slave node
regenerates the bias voltage from its local supply and provides it
to the next node (B-side) for line diagnostics and as a voltage
supply for bus powered nodes. Diodes are required for correct
line diagnostics and damage prevention under line fault
conditions.
An A
2
B-compliant, bus powered, slave node transceiver
requires external components to pass EMC and ESD tests in the
automotive environment. The circuit must use the A
2
B bias (A-
side) as its low-pass filtered supply voltage (using inductors and
capacitors). A
2
B communication signals must be separated from
the dc content at the A-side transceiver by high-pass filtering
with ac coupling capacitors. Capacitors must also be used on the
B-side where the ac-coupled signal is merged with the recovered
bias, which is supplied through ac signal blocking inductors.
The bus powered slave node must include circuitry to forward
the recovered bias voltage to the next node and to perform line
diagnostics. A diode is required for correct line diagnostics and
damage prevention under line fault conditions.
Contact your local Analog Devices representative for the latest
schematic circuit recommendations and bill of materials for
each of these node configurations. The recommended circuit
and component selection must be followed for A
2
B automotive-
grade compliance.
V
SENSE
AND CONSIDERATIONS FOR DIODES
The relative difference between the voltage on the VIN pin,
V
VIN
, and the A
2
B bus bias voltage, V
SENSE
, is monitored by the
SENSE pin under steady state normal operating conditions. The
range must be within the values described in Table 18 for all line
diagnostics to function correctly.
The difference between V
VIN
and V
SENSE
is primarily influenced
by diode voltage drops and the on resistance of the PMOS.
(Contact your local Analog Devices representative for the latest
schematic circuit recommendations and bill of materials.)
Table 19 identifies which diodes cause voltage drops for each
node type.
OPTIONAL ADD ON CIRCUITS
An earlier node in the sequence can remotely power up the next
locally powered slave node over the A
2
B bus by switching the
bias voltage onto the A
2
B bus. The local powered slave node can
sense this bias voltage and use it as an enable input for power
switches or voltage regulators to awake the device from a very
low current sleep mode.
An optocoupler, shown in Figure 37, can differentiate input of
the bias voltage and ensures that the locally powered slave node
is electrically isolated. This avoids ground loops that can induce
noise and also trigger line fault detection. Current during sleep
is determined by the optocoupler transistor off current, the
resistor to ground (R12), and the power switch enable circuit.
Table 18. V
VIN
to V
SENSE
Range
Range Min Max Unit
V
VIN
to V
SENSE
– 0.6 +0.5 V
Table 19. V
VIN
to V
SENSE
Voltage Dependencies
Node Type V
VIN
to V
SENSE
Diode Dependencies
Master D1, D3
Locally Powered Slave D1, D3
Bus Powered Slave D1
Figure 37. Optional Power Supply Enable Circuit with Optocoupler
VBAT ABIASN
ENABLE
ABIASPR12 R9
OPT1
Rev. B | Page 34 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
LAYOUT GUIDELINES
The transceivers are highly integrated devices, comprising both
digital sections for audio data, clocks, PLL, and analog A
2
B
transceiver sections. Use the following design rules to maximize
performance and signal integrity:
• Solder the exposed paddle underneath the transceiver
effectively to the PCB where it is locally connected to the
ground plane. Figure 38 shows transceiver foot print, rec-
ommended solder mask (matching exposed paddle), paste
mask (dividing exposed paddle), and stitching of the
ground plane.
The solder paste under the exposed paddle is split into four
square areas, which minimizes solder wicking through
uncovered thermal vias and prevents sliding or tilting of
the chip during solder reflow. See Soldering Considerations
for Exposed-Pad Packages (EE-352), on the Analog Devices
web site. The exposed paddle is used for a thermal pathway
as well as for electrical connection.
• Place power supply decoupling capacitors as close as possi-
ble to the transceiver chip with the smallest value capacitor
being closest to the pin.
• Route all traces as short as possible, especially the AP/AN
and BP/BN signals.
•Symmetrically route the AP/AN and BP/BN signals to sup-
press EMC. Match routing parasitic capacitance and
inductance.
• Symmetrically shield the AP/AN and BP/BN signals with
ground. Use shields that are at least 0.5 mm wide and
stitched generously with vias to the GND plane. Symmetry
is best achieved with flooded plane areas.
• Do not route switching signals or power supply traces next
to or underneath the AP/AN and BP/BN signals.
• Avoid using trace stubs, especially if they create an asym-
metry on the AP/AN and BP/BN signals. Symmetrically
route into and out of pads rather than branch out.
• Differential impedance trace of the AP/AN and BP/BN sig-
nals should be 100 ± 10% (10 MHz to 100 MHz) on both
sides of the common-mode choke.
• Avoid unnecessary layer transitions for the AP/AN and
BP/BN signals. Match necessary layer transitions for differ-
ential signals.
• Use an impedance of 50 ± 10% to ground on all traces.
• Magnetically separate common-mode chokes from each
other by at least 2 mm.
• Do not route ground or other signals on any layer under-
neath the common-mode chokes. Extend this exclusion at
least 2 mm from between the pads.
•For shielded wires, connect the shield to the local ground.
• Place one side of the inductors in the signal path and bridge
dc signals to the power and ground nets.
• Place termination resistors symmetrically and close to the
common-mode chokes.
•Where possible, flood unused PCB areas with connected
ground planes on all layers.
• Stitch ground planes at least every 5 mm.
• Do not obstruct power supply and ground return paths by
vias.
• Use series resistors (≥33 ) near the source of clock and
fast data signals. Also consider footprints for small filter
capacitors for such signal traces.
• Avoid using right angle bends in signal routing. Use
rounded or 45 degree mitered bends instead.
• Use shortest possible signal path on connectors (inner row
of multirow, right angled connectors).
• On multipin connectors, provide at least 3 mm spacing
around differential A
2
B pin pairs to ensure that A
2
B signal
pairs are closer to each other than to adjacent signals. The
spacing improves EMC performance.
Use low impedance static signals (ground) symmetrically
on connector pins adjacent to the A
2
B bus pairs when tight
spacing is required.
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Rev. B | Page 35 of 38 | January 2020
Figure 38. Transceiver Footprint
EPAD Pastemask Areas
4 × 1.5 mm × 1.5 mm
EPAD 3.6 mm × 3.6 mm
Soldermask Opening
0.0508 mm larger than pads where
clearance permits, else 0.0254 mm
Pad 0.304 mm × 0.889 mm
Thermal Vias
0.254 mm drill
0.5334 mm
Pads preferably tented/plugged
and no relief to plane layers
0.4 mm
0.5 mm
Pad Pitch
0.7 mm
1.5 mm
1.5 mm
5.7 mm
5.0 mm
Rev. B | Page 36 of 38 | January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
OUTLINE DIMENSIONS
Figure 39 shows the outline dimensions for the 32-Lead
LFCSP_SS (CS-32-2).
Figure 40 shows the outline dimensions for the 32-Lead
LFCSP (CP-32-12).
Figure 39. 32-Lead Lead Frame Chip Scale Package [LFCSP_SS]
5 mm x 5 mm Body, With Side Solderable Leads
(CS-32-2)
Dimensions shown in millimeters
Figure 40. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm x 5 mm Body and 0.75 mm Package Height
(CP-32-12)
Dimensions shown in millimeters
1
0.50
BSC
BOTTOM VIEWTOP VIEW
PIN 1
INDICATOR
32
9
16
17
24
25
8
EXPOSED
PAD
0.05 MAX
0.02 NOM
0.203 REF
0.075~0.150
(Step dimension)
COPLANARITY
0.08
0.30
0.25
0.20
5.10
5.00 SQ
4.90
0.80
0.75
0.70
0.50
0.40
0.30
0.20 MIN
3.70
3.60 SQ
3.50
3.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
PIN 1
INDICATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
SEATING
PLANE
0.50
0.40
0.30
1
0.50
BSC
BOTTOM VIEWTOP VIEW
TOP VIEW
PIN 1
INDICATOR 32
9
16
17
24
25
8
EXPOSED
PAD
SEATING
PLANE
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
0.30
0.25
0.18
5.10
5.00 SQ
4.90
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.20 MIN
3.75
3.60 SQ
3.55
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5
PIN 1
INDICATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Rev. B | Page 37 of 38 | January 2020
AUTOMOTIVE PRODUCTS
The AD2420W/AD2426W/AD2427W/AD2428W/AD2429W
models are available with controlled manufacturing to support
the quality and reliability requirements of automotive applica-
tions. Note that these automotive models may have
specifications that differ from the nonautomotive models;
therefore, designers should review the Specifications section of
this data sheet carefully. Only the automotive grade products
shown in Table 20 are available for use in automotive applica-
tions. Contact your local Analog Devices account representative
for specific product ordering information and to obtain the spe-
cific Automotive Reliability reports for these models.
Table 20. Automotive Products
Model
1,
2, 3, 4
Temperature Range
5
Description Package Option
AD2420WCCPZxx –40°C to +105°C 32-Lead Frame Chip Scale Package [LFCSP] CP-32-12
AD2420WCCPZxx-RL –40°C to +105°C 32-Lead Frame Chip Scale Package [LFCSP] CP-32-12
AD2426WCCSZ –40°C to +105°C 32-Lead Frame Chip Scale Package [LFCSP_SS] CS-32-2
AD2426WCCSZ-RL –40°C to +105°C 32-Lead Frame Chip Scale Package [LFCSP_SS] CS-32-2
AD2426WCCSZxx –40°C to +105°C 32-Lead Frame Chip Scale Package [LFCSP_SS] CS-32-2
AD2426WCCSZxx-RL –40°C to +105°C 32-Lead Frame Chip Scale Package [LFCSP_SS] CS-32-2
AD2427WCCSZ –40°C to +105°C 32-Lead Frame Chip Scale Package [LFCSP_SS] CS-32-2
AD2427WCCSZ-RL –40°C to +105°C 32-Lead Frame Chip Scale Package [LFCSP_SS] CS-32-2
AD2427WCCSZxx –40°C to +105°C 32-Lead Frame Chip Scale Package [LFCSP_SS] CS-32-2
AD2427WCCSZxx-RL –40°C to +105°C 32-Lead Frame Chip Scale Package [LFCSP_SS] CS-32-2
AD2428WCCSZ –40°C to +105°C 32-Lead Frame Chip Scale Package [LFCSP_SS] CS-32-2
AD2428WCCSZ-RL –40°C to +105°C 32-Lead Frame Chip Scale Package [LFCSP_SS] CS-32-2
AD2428WCCSZxx –40°C to +105°C 32-Lead Frame Chip Scale Package [LFCSP_SS] CS-32-2
AD2428WCCSZxx-RL –40°C to +105°C 32-Lead Frame Chip Scale Package [LFCSP_SS] CS-32-2
AD2429WCCPZxx –40°C to +105°C 32-Lead Frame Chip Scale Package [LFCSP] CP-32-12
AD2429WCCPZxx-RL –40°C to +105°C 32-Lead Frame Chip Scale Package [LFCSP] CP-32-12
1
Z = RoHS Compliant Part.
2
W = Qualified for Automotive Applications.
3
RL = Supplied on Tape and Reel.
4
For model numbers ending in xx or xx-RL, xx denotes the die revision.
5
Referenced temperature is ambient temperature. The ambient temperature is not a specification. See the Operating Conditions section for junction temperature (T
J
)
specification which is the only temperature specification.
Rev. B | Page 38 of 38 | January 2020
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16813-0-1/20(B)
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
I
2
CreferstoacommunicationsprotocoloriginallydevelopedbyPhilipsSemiconductors(nowNXPSemiconductors).
ORDERING GUIDE
Model
1
1
Z = RoHS Compliant Part.
Temperature Range
2
2
Referenced temperature is ambient temperature. The ambient temperature is not a specification. See the Operating Conditions section for junction temperature (T
J
)
specification which is the only temperature specification.
Description Package Option
AD2420KCPZ 0°C to +70°C 32-Lead Frame Chip Scale Package [LFCSP] CP-32-12
AD2420BCPZ –40°C to +85°C 32-Lead Frame Chip Scale Package [LFCSP] CP-32-12
AD2426KCPZ 0°C to +70°C 32-Lead Frame Chip Scale Package [LFCSP] CP-32-12
AD2426BCPZ –40°C to +85°C 32-Lead Frame Chip Scale Package [LFCSP] CP-32-12
AD2427KCPZ 0°C to +70°C 32-Lead Frame Chip Scale Package [LFCSP] CP-32-12
AD2427BCPZ –40°C to +85°C 32-Lead Frame Chip Scale Package [LFCSP] CP-32-12
AD2428KCPZ 0°C to +70°C 32-Lead Frame Chip Scale Package [LFCSP] CP-32-12
AD2428BCPZ –40°C to +85°C 32-Lead Frame Chip Scale Package [LFCSP] CP-32-12
AD2429KCPZ 0°C to +70°C 32-Lead Frame Chip Scale Package [LFCSP] CP-32-12
AD2429BCPZ –40°C to +85°C 32-Lead Frame Chip Scale Package [LFCSP] CP-32-12
