Automotive Audio Bus A2B Transceiver AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) A2B BUS FEATURES A2B TRANSCEIVER FEATURES Line topology Single master, multiple slave Up to 15 m between nodes and up to 40 m overall cable length (see Table 9) Communication over distance Synchronous data Multichannel I2S/TDM to I2S/TDM Synchronous clock, phase aligned in all nodes Low latency slave to slave communication Control and status information I2C to I2C GPIO and interrupt Bus power or local power slave nodes Configurable with SigmaStudio graphical software tool AEC-Q100 qualified for automotive applications Configurable A2B bus master or slave operation I2C interface 8-bit to 32-bit multichannel I2S/TDM interface Programmable I2S/TDM data rate Up to 32 upstream and 32 downstream channels PDM interface Programmable PDM clock rate Up to 4 high dynamic range microphone inputs Simultaneous reception of I2S data with up to 4 PDM microphones Unique ID register for each transceiver Crossover or straight-through cabling Programmable settings to optimize EMC performance APPLICATIONS Audio communication link Microphone arrays Beamforming Hands free and in car communication Active and road noise cancellation Audio/video conferencing systems IOVDD SCL SDA IRQ/IO0 ADR1/IO1 ADR2/IO2 I2C DTX0/IO3 DTX1/IO4 DRX0/IO5 DRX1/IO6 I2S/TDM PDM DVDD PLLVDD VOUT1 PLL VREG1 VIN VOUT2 VREG2 BTRXVDD A2 B TRX B (Towards Last Slave) DIAGNOSTICS PDMCLK/IO7 A2 B TRX A (Towards Master) BCLK SYNC VSSN VSS BP BCM BN SWP SENSE AP ACM AN ATRXVDD Figure 1. Functional Block Diagram A2B and the A2B logo are registered trademarks of Analog Devices, Inc. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 (c)2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) TABLE OF CONTENTS A2B Bus Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Test Circuits and Switching Characteristics . . . . . . . . . . . . . . . 21 A2B Transceiver Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Configuration and Function Descriptions . . . . . . . . . . . . . . . 24 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Power Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Current Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2 A B Bus Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 VREG1 and VREG2 Output Currents . . . . . . . . . . . . . . . . . . . . . . 29 2 Current at VIN (IVIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2 I S/TDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Pulse Density Modulation (PDM) Interface . . . . . . . . . . . . . . . . . 6 Resistance Between Nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 GPIO Over Distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Voltage Regulator Current in Master Node or Local Powered Slave Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Data Slot Exchange Between Slaves . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Power Dissipation of A2B Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Clock Sustain State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Power Analysis of Bus Powered System . . . . . . . . . . . . . . . . . . . . 31 Programmable Settings to Optimize EMC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power Estimation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Designer Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Power Supply Rejection Ratio (PSRR) . . . . . . . . . . . . . . . . . . . . . . 11 VSENSE and Considerations for Diodes . . . . . . . . . . . . . . . . . . . 36 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Optional Add On Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Power-Up Sequencing Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 16 Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 I C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Reducing Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 A B Bus System Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 PDM Typical Performance Characteristics . . . . . . . . . . . . . . . . 18 Automotive Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ESD Caution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 REVISION HISTORY 1/2020--Rev. A to Rev. B Updated All Products to Released Status . . . . . . . Throughout Deleted Product Status Table. . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to Automotive Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Changes to Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Deleted Pending Products Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Rev. B | Page 2 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) GENERAL DESCRIPTION The Automotive Audio Bus (A2B(R)) provides a multichannel, I2S/TDM link over distances of up to 15 m between nodes. It embeds bidirectional synchronous pulse-code modulation (PCM) data (for example, digital audio), clock, and synchronization signals onto a single differential wire pair. A2B supports a direct point to point connection and allows multiple, daisychained nodes at different locations to contribute and/or consume time division multiplexed (TDM) channel content. The transceiver can connect directly to general-purpose digital signal processors (DSPs), field-programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), microphones, analog-to-digital converters (ADCs), digital-toanalog converters (DACs), and codecs through a multichannel I2S/TDM interface. It also provides a pulse density modulation (PDM) interface for direct connection of up to four PDM digital microphones. A2B is a single-master, multiple-slave system where the transceiver at the host controller is the master. The master generates clock, synchronization, and framing for all slave nodes. The master A2B transceiver is programmable over a control port (I2C) for configuration and read back. An extension of the control port protocol is embedded in the A2B data stream, which grants direct access of registers and status information on slave transceivers as well as I2C to I2C communication over distance. Finally, the transceiver also supports an A2B bus powering feature, where the master node supplies voltage and current to the slave nodes over the same daisy-chained, twisted pair wire cable as used for the communication link. Table 1. Product Comparison Guide Feature Master capable Number of slaves discoverable1 Functional TRX blocks I2S/TDM support PDM microphone inputs Max node to node cable length 1 2 AD2420/ AD2420W No N/A A only No 2 mics2 5m AD2426/ AD2426W No N/A A only No 4 mics 15 m AD2427/ AD2427W No N/A A+B No 4 mics 15 m N/A means not applicable. PDM microphones must be connected to the DRX0/IO5 pin. Rev. B | Page 3 of 38 | January 2020 AD2428/ AD2428W Yes Up to 10 A+B Yes 4 mics 15 m AD2429/ AD2429W Yes Up to 2 B only Yes 4 mics 5m AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) A2B BUS DETAILS Figure 2 shows a single-master, multiple-slave A2B communications system with the master transceiver controlled by the host. The host generates a periodic synchronization signal on the I2S/TDM interface at a fixed frequency (typically 48 kHz) to which all A2B nodes synchronize. Communications along the A2B bus occur in periodic superframes. The superframe frequency is the same as the synchronization signal frequency, and data is transferred at a bit rate that is 1024 times faster (typically 49.152 MHz). Each superframe is divided into periods of downstream transmission, upstream transmission, and no transmission (where the bus is not driven). Data is exchanged over the A2B bus in up to 32 equal width slots for both upstream and downstream transmissions. The A2B bus also communicates the following control and status information between nodes: * I2C to I2C communication * General-purpose input/output (GPIO) HOST DSP MASTER A2B TRANSCEIVER I2C A2B I2S/TDM I2S/TDM * Data received over the I2S/TDM interface by the A2B transceiver is transmitted over the A2B bus in the next superframe. * Data on the A2B bus is transmitted over the I2S/TDM interface of an A2B transceiver in the next superframe. I2C A2B SLAVE A2B TRANSCEIVER * Data transmitted by the master node transceiver in Superframe M creates Downstream Data M. * Data transmitted by the slave node transceivers in Superframe N creates Upstream Data N. I2C SLAVE A2B TRANSCEIVER All nodes in an A2B system are sampled synchronously in the same A2B superframe. Synchronous I2S/TDM downstream data from the master arrives at all slaves in the same A2B superframe, and the upstream audio data of every node arrives synchronously in the same I2S/TDM frame at the master. The remaining audio phase differences between slaves can be compensated for by register-programmable fine adjustment of the SYNC pin signal delay. Note in Figure 4, both downstream and upstream samples are named for the frame where they enter the A2B system as follows: A2B SLAVE A2B TRANSCEIVER The embedded control and response frames allow the host to individually address each slave transceiver in the system. The host also enables access to remote peripheral devices that are connected to the slave transceivers via the I2C or SPI ports for I2C to I2C communication over distance between multiple nodes. There is a sample delay incurred for data moving between the A2B bus and the I2S/TDM interfaces because data is received and transmitted over the I2S/TDM every sample period (typically 48 kHz). This timing relationship between samples over the A2B bus is shown in Figure 4. * Interrupts I2S/TDM control frame. Every slave can use or consume some of the downstream data and add data for downstream nodes. The last slave node transceiver responds after the response time with a synchronization response frame (SRF). Upstream synchronous data is added by each node directly after the response frame. Each node can also use or consume upstream data. I2S/TDM I2C Figure 2. Communication System Block Diagram In Figure 3, a superframe is shown with an initial period of downstream transmission and a later period of upstream transmission. * Data transmitted across the A2B bus (master to slave or slave to master) has two frames of latency plus any internal delay that has accumulated in the transceivers as well as delays due to wire length. Therefore, overall latency is slightly over two samples (<50 s at 48 kHz sample periods) from the I2S/TDM interface in one A2B transceiver to the I2S/TDM interface of another A2B transceiver. To support and extend the A2B bus functions and performance, the transceivers have additional features, as described in the following sections. All signals on the A2B bus are line coded, and the master node forwards the synchronization signal downstream from the master transceiver to the last slave node transceiver in the form of a synchronization preamble. This preamble is followed by control data to build a synchronization control frame (SCF). Downstream, TDM synchronous data is added directly after the Rev. B | Page 4 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) SUPERFRAME: 20.83s FOR 48kHz SAMPLING RATE SYNCH CONTROL FRAME SYNCH RESPONSE FRAME DOWNSTREAM A2B DATA SLOTS SYNCH CONTROL FRAME UPSTREAM A2B DATA SLOTS Figure 3. A2B Superframe MASTER NODE I2 S TX DATA I2 S UPSTREAM DATA N - 2 I2 S RX DATA I2 S DOWNSTREAM DATA M I2 S UPSTREAM DATA N - 1 I2 S UPSTREAM DATA N I2 S DOWNSTREAM DATA M + 1 I2 S DOWNSTREAM DATA M + 2 UPSTREAM A2B DATA N+1 SCF DNSTREAM A2B DATA M+1 SRF UPSTREAM A2B DATA N SCF DNSTREAM A2B DATA M SRF UPSTREAM A2B DATA N-1 SCF DNSTREAM A2B DATA M-1 SRF A2 B DATA SCF SUPERFRAME SLAVE NODE I2 S RX DATA I2 S UPSTREAM DATA N I2 S UPSTREAM DATA N + 1 I2 S UPSTREAM DATA N + 2 I2 S TX DATA I2 S DOWNSTREAM DATA M - 2 I2 S DOWNSTREAM DATA M - 1 I2 S DOWNSTREAM DATA M Figure 4. A2B Bus Synchronous Data Exchange I2C INTERFACE 2 The I C interface in the transceiver provides access to the internal registers. Operation is not guaranteed above the VI2C_VBUS specification. The I2C interface has the following features: BUS_ADDR (Bit 1 = 1) to access a bus node slave transceiver through a master configured AD2425W transceiver. See the AD2420(W)/6(W)/7(W)/8(W)/9(W) Automotive Audio Bus A2B Transceiver Technical Reference for details. * Slave functionality in the A2B master I2S/TDM INTERFACE * Master or slave functionality in the A2B slave The I2S/TDM serial port operates in full-duplex mode, where both the transmitter and receiver operate simultaneously using the same critical timing bit clock (BCLK) and synchronization (SYNC) pins. A2B slave transceivers generate the timing signals on the BCLK and SYNC output pins. A2B master transceivers use the same BCLK and SYNC pins as inputs, which are driven by the host device. The I2S/TDM port includes the following features: * Multimaster support in the A2B slave * 100 kbps or 400 kbps rate operation * 7-bit addressing * Single-word and burst mode read and write operations * Clock stretching All transceivers can be accessed by a locally connected processor using the 7-bit I2C device address (BASE_ADDR) established by the logic levels applied to the ADR2/IO2 and ADR1/IO1 pins at power-on reset, thus providing for up to four master devices connecting to the same I2C bus. A slave configured transceiver recognizes only this I2C device address. A master configured transceiver, however, also recognizes a second I2C device address for remote access to slave nodes over the A2B bus (BUS_ADDR). The least significant bit (LSB) of the 7-bit device address determines whether an I2C data exchange uses the BASE_ADDR (Bit 1 = 0) to access the transceiver or * Programmable clock and frame sync timing and polarity * Numerous TDM operating modes * 16- or 32-bit data width * Simultaneous operation with PDM port * Single- or dual-pin input/output (I/O) Rev. B | Page 5 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) I2S Reduced Rate 2 Slave transceivers can run the I S/TDM/PDM interface at a reduced rate frequency, with respect to the superframe rate. The reduced rate frequency is derived by dividing the superframe rate from a programmable set of values. Different slave nodes can be configured to run at different reduced I2S/TDM rates. used to customize handshaking among numerous nodes in a system to coordinate system events, such as synchronizing audio. DATA SLOT EXCHANGE BETWEEN SLAVES The transceiver provides an option for a processor to track the full rate audio frame, which contains new reduced rate samples. The IO7 pin can be used as a strobe, and the direction can be configured as an input or output. Using the DTX0 and DTX1 pins, slave transceivers can selectively output upstream or downstream data that originates from other nodes without the need for data slots to be routed through the master node. Receive data channels can be skipped based on a programmable offset, when the data is presented as upstream or downstream slots to the A2B bus. PULSE DENSITY MODULATION (PDM) INTERFACE CLOCK SUSTAIN STATE The PDM block on the transceiver converts a PDM input stream into pulse code modulated (PCM) data to be sent over the A2B bus and/or out to the local node through the I2S/TDM port. It supports high dynamic range microphones with high signal-to-noise ratio (SNR) and extended maximum sound pressure level. The PDM interface supports 12 kHz and 24 kHz frame rates in addition to a 48 kHz frame rate and can be used on both master and slave transceivers. In the clock sustain state, audio signals of locally powered slave nodes are attenuated in the event of lost bus communication. When the bus loses communication and a reliable clock cannot be recovered by the slave node, the slave node transceiver enters the sustain state and, if enabled, signals this event to a GPIO pin. Even lower PDM sampling rates (for example, down to 375 Hz) are possible in combination with the reduced rate feature of the transceiver. The cutoff frequency of the high-pass filter in the transceiver PDM block is fixed to 1 Hz. BCLK can be used to clock PDM microphones on a slave, but if PDMCLK/IO7 is used instead, the BCLK frequency can be set to a different frequency using the I2S/TDM registers. In this case, PDMCLK/IO7 is used as the PDM clock (PDMCLK) to capture PDM input on DRX0/DRX1. The clock rate from PDMCLK is 64x the SYNC frequency. On a master node, BCLK is always an input, so the clock to PDM microphones that are attached to a master typically comes from PDMCLK/IO7. It is possible to use BCLK to drive the PDM clock inputs on a master node, but this restricts the possible TDM settings because BCLK is required to fall within the fBCLK specification in Table 4. BCLK and PDMCLK/IO7 can also be used concurrently to clock PDM microphones at the same frequency and phase alignment, but with opposite polarity. Additionally, a register setting selects whether rising edge data or falling edge data is sampled first. GPIO OVER DISTANCE The transceiver supports general-purpose input/output (GPIO) between multiple nodes without host intervention after initial programming. The host is required only for initial setup of the GPIO bus ports. I/O pins of different nodes can be logically OR or AND gate combined. MAILBOXES The transceiver supports interrupt driven, bidirectional message exchange between I2C master devices (microcontrollers) at different slave nodes and the host connected to the master node transceiver in two dedicated mailboxes. The mailboxes can be In the clock sustain state, the phase-locked loop (PLL) of the slave node transceiver continues to run for 1024 SYNC periods, while attenuating the I2S DTX0 to DTX1 data from the current value to 0. After the 1024 SYNC periods, the slave node transceiver resets and reenters the power-up state. PROGRAMMABLE SETTINGS TO OPTIMIZE EMC PERFORMANCE The following programmable features can be used to improve electromagnetic compatibility (EMC) performance. Programmable LVDS Transmit Levels The low voltage differential signal (LVDS) transmitter can be set to transmit the signal at high, medium, or low levels. Higher transmit levels yield greater immunity to EMI, whereas lower transmit levels can reduce emissions from the twisted-pair cables that link A2B bus nodes together. The improved LVDS receiver (compared to other members of the AD242xW family) maintains robust operation when transmit levels are lowered. Spread-Spectrum Clocking Spread-spectrum clocking can be used to reduce narrow-band emissions on a printed circuit board (PCB). Spread-spectrum clocking is disabled on the transceiver by default, but spreadspectrum clocking for all internal clocks can be enabled during discovery by a register write. If spread-spectrum clocking support is enabled for the internal clocks, spread-spectrum clocking can also be enabled for both the I2S interface and the programmed CLKOUTs. Enabling spread-spectrum clocking for internal clocks, CLKOUTs, and the I2S interface may reduce narrow-band emissions by several dB on a particular node. When spread-spectrum clocking is enabled on a clock output, the time interval error (TIE) jitter on that clock increases. Unique ID Each transceiver contains a unique ID, which can be read from registers using software. If a read of the unique ID fails, an interrupt can be generated. Rev. B | Page 6 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) Support for Crossover or Straight Through Cabling Straight through cables can be supported by swapping the dc coupling at the B-side connector. See the Designer Reference section for details about the reference schematics. Data Only and Power Only Bus Operation The A2B bus can be operated without closing the PMOS switch to send a dc bias downstream. Conversely, a dc bias can also be sent downstream without the presence of data. These features are available for debug purposes only. Rev. B | Page 7 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) SPECIFICATIONS For information about product specifications, contact your Analog Devices, Inc. representative. OPERATING CONDITIONS Parameter Power Supplies Digital Core Logic Supply Voltage VDVDD Digital Input/Output (I/O) Supply VIOVDD Voltage Conditions Min Nominal Max Unit 3.3 V I/O 1.70 3.0 1.90 3.3 1.98 3.63 V V 1.7 1.7 1.9 1.9 1.98 1.98 V V 3.0 1.7 3.3 1.9/3.3 3.63 3.63 V V 3.7 9.0 V 2.65 2.97 V 3.11 3.25 V 0.3 x VIOVDD 0.8 0.3 x VIOVDD V V V V V V 0 -40 105 +105 C C -40 +1253 C 1.8 V I/O Phased-Locked Loops (PLL) Supply Voltage VTRXVDD Transceiver Supply Voltage Applies to the ATRXVDD and BTRXVDD pins External I2C Bus Voltage 3.3 V VIOVDD, 1.8 V VIOVDD VI2C_VBUS Voltage Regulator (VREG1, VREG2) Regulator Input Supply Voltage Specification must be met at the VIN pin of VVIN each A2B bus transceiver VVIN Chip Reset Assertion Voltage VVIN dropping VRST Threshold VVIN Chip Reset Deassertion Voltage VVIN rising VRSTN Threshold Digital I/O VIH1 High Level Input Voltage VIOVDD = 1.98 V VIOVDD = 3.63 V 1 Low Level Input Voltage VIOVDD = 1.70 V VIL VIOVDD = 3.00 V VIOVDD = 3.63 V, 1.98 V VIH_I2C2 VIOVDD = 3.00 V, 1.70 V VIL_I2C Temperature Junction Temperature TAMBIENT = 0C to 70C TJ Junction Temperature TAMBIENT = -40C to +85C TJ AUTOMOTIVE USE ONLY Junction Temperature TAMBIENT = -40C to +105C TJ (Automotive Grade) VPLLVDD 1 0.7 x VIOVDD 2.2 0.7 x VIOVDD Applies to PDMCLK/IO7, BCLK, SYNC, DTX0/IO3, DTX1/IO4, DRX0/IO5, DRX1/IO6, ADR1/IO1, ADR2/IO2, IRQ/IO0 pins. Applies to SDA and SCL pins. 3 Automotive application use profile only. Not supported for nonautomotive use. Contact Analog Devices, Inc. for more information. 2 Rev. B | Page 8 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) ELECTRICAL CHARACTERISTICS Parameter Current IDVDD IPLLVDD ITRXVDD1 Conditions Digital Core Logic Supply Current VDVDD = 1.98 V PLL Supply Current VPLLVDD = 1.98 V Transceiver Supply Current TX enabled, RX disabled, 100% duty cycle (ITXVDD), VTRXVDD = 3.63 V TX disabled, RX enabled, 100% duty cycle (IRXVDD), VTRXVDD = 3.63 V TX disabled, RX disabled, 0% activity level, VTRXVDD = 3.63 V Voltage Regulator (VREG1, VREG2) VVOUT1 VREG1 Output Voltage VVOUT2 VREG2 Output Voltage VREG1 Output Current IVOUT12 IVOUT22 VREG2 Output Current IVEXT13, 4 VREG1 External Device Current IVOUT1 - IPLLVDD - IDVDD - IIOVDD current available to external device VREG2 External Device Current IVOUT2 - ITRXVDD current available to external IVEXT23, 4 device VOUT1/VIN Line Regulation VVIN = 3.7 V to VIN VOUT2/VIN Line Regulation VVIN = 3.7 V to VIN VVIN = 5.0 V to 8 V VOUT1/IOUT1 Load Regulation VVIN = 5.0 V, IVOUT1 = 1 mA to 40 mA VOUT2/IOUT2 Load Regulation VVIN = 5.0 V, IVOUT2 = 1 mA to 50 mA IVINQ Quiescent Current VVIN =VIN, IVOUT1 = 0 mA, IVOUT2 = 0 mA IVIN Operational Current VVIN = VIN, IVOUT1 = 8 mA, IVOUT2 = 20 mA CLoad1 VREG1 Load Capacitance CLoad2 VREG2 Load Capacitance Digital I/O IIH Input Leakage, High VIOVDD = 3.63 V, VIN = 3.63 V IIL Input Leakage, Low VIOVDD = 3.63 V, VIN = 0 V IOZH_I2C5 Three-State Leakage Current VIOVDD = 1.9 V, VIN = 3.63 V VOH1.9 High Level Output Voltage VIOVDD = 1.70 V, IOH = 1 mA VOH3.3 High Level Output Voltage VIOVDD = 3.00 V, IOH = 1 mA VOL6 Low Level Output Voltage VIOVDD = 3.00 V, IOL = 1 mA VOL6 Low Level Output Voltage VIOVDD = 1.70 V, IOL = 1 mA VOL_I2C5, 7 I2C Low Level Output Voltage VIOVDD = 3.00 V, IOL = 1.5 mA I2C Low Level Output Voltage VIOVDD = 1.70 V, IOL = 1.5 mA VOL_I2C5, 7 CPD Pin Capacitance Negative Bias Switch IVSSN Internal VSSN Switch Current AD2426(W)/AD2427(W)/AD2428(W) IVSSN Internal VSSN Switch Current AD2420(W)/AD2429W RVSSN Internal VSSN On Resistance 1 Min Typ Max Unit 9.0 0.5 9.5 10.5 1.1 12.0 12.0 1.5 13.0 mA mA mA 2.2 2.8 3.5 mA 1.0 1.7 2.5 mA 1.80 3.15 1.90 3.30 1.98 3.45 40.0 50.0 20 V V mA mA mA 20 mA 0 0.013 -0.025 530 0.017 0.030 +0.005 0.009 0.008 600 1.0 2.2 0.055 0.060 +0.055 0.017 0.015 750 29 25 25 %/V %/V %/V %/mA %/mA A mA F F 10.0 10.0 10.0 0.40 0.40 0.40 0.40 5 A A A V V V V V V pF 300 100 1.2 mA mA 1.35 2.40 4.8 Master and last slave only consume half the transceiver current because only one of the two TRX blocks is used. In a bus powered system, IVOUT has a direct impact on IVSSN and VVIN in other nodes. For more information, see the Power Analysis section. 3 Consider the package thermal limits when dissipating current above typical limits. For more information, see the Thermal Characteristics section. 4 Must comply with IVOUT1 and IVOUT2 maximum. 5 Applies to SDA and SCL pins. 6 Applies to BCLK, SYNC, DTX0/IO3, DTX1/IO4, DRX0/IO5, DRX1/IO6, ADR1/IO1, ADR2/IO2, IRQ/IO0, PDMCLK/IO7 pins. 7 The minimum IOL current is lower than the I2C specification because the SDA and SCL pins are designed for a limited number of I2C attached slave devices. 2 Rev. B | Page 9 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) Table 2. Differential Input/Output Parameter LVDS |VOD| Receiver VTH Conditions Differential Output Voltage Magnitude High Transmit Level Medium Transmit Level Low Transmit Level Min Typ Max Unit 425 315 210 545 415 305 mV mV mV -52 +52 mV See Figure 19 Differential Input Threshold Voltage Rev. B | Page 10 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) POWER SUPPLY REJECTION RATIO (PSRR) Typical PSRR at TJ = 40C with load capacitance CLOAD = 4.7 F || 100 F. 0 0 VIN = 3.7V VIN = 4.0V VIN = 5.0V VIN = 6.0V VIN = 7.0V VIN = 8.0V VIN = 9.0V -10 -20 -30 -20 -30 -40 PSRR (dB) PSRR (dB) -40 VIN = 3.7V VIN = 4.0V VIN = 5.0V VIN = 6.0V VIN = 7.0V VIN = 8.0V VIN = 9.0V -10 -50 -60 -70 -80 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M -120 10M 1 Figure 5. VOUT1 PSRR, IVOUT1 = 10 mA -30 1k 10k FREQUENCY (Hz) 100k 1M 10M VIN = 3.7V VIN = 4.0V VIN = 5.0V VIN = 6.0V VIN = 7.0V VIN = 8.0V VIN = 9.0V -10 -20 -30 -40 PSRR (dB) -40 PSRR (dB) 0 VIN = 3.7V VIN = 4.0V VIN = 5.0V VIN = 6.0V VIN = 7.0V VIN = 8.0V VIN = 9.0V -20 100 Figure 7. VOUT2 PSRR, IVOUT2 = 10 mA 0 -10 10 -50 -60 -70 -80 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M 10M -120 1 Figure 6. VOUT1 PSRR, IVOUT1 = 40 mA 10 100 1k 10k FREQUENCY (Hz) 100k Figure 8. VOUT2 PSRR, IVOUT2 = 50 mA Rev. B | Page 11 of 38 | January 2020 1M 10M AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) TIMING SPECIFICATIONS Table 3. Clock and Reset Timing (A2B Master) Parameter Timing Requirements fSYNCM SYNC Pin Input Frequency Continuous Clock tSYNCIJ SYNC Pin Input Jitter RMS TIE tSYNCOJ SYNC Pin Output Jitter RMS TIE fSYSBCLK Bus Clock tDNSYNCR1 Delay from First Missed SYNC to Reset (A2B Master) tDNSCFR1 Delay from First Missed SCF to Reset (A2B Slave) tPLK PLL Lock Time 1 Min Typ Max Unit 43.6 44.1, 48.0 0.29 48.5 1.0 2.6 kHz ns ns kHz ms ms ms 1024 x fSYNCM 0.64 0.64 0.74 0.74 7.5 Only consecutive missed SYNC or SCF transitions for the specified duration result in a reset. Table 4. Pulse Density Modulation Microphone Input Timing Parameter Timing Requirements tRISS DRXn Input Setup Before BCLK tRIHS DRXn Input Hold After BCLK tRISS DRXn Input Setup Before PDMCLK tRIHS DRXn Input Hold After PDMCLK Switching Characteristics fBCLK BCLK/PDMCLK Output Frequency tBCLKOJ BCLK/PDMCLK Output Jitter RMS Cycle to Cycle tSOL BCLK/PDMCLK Output Pulse Width Low Min Typ Max 12.0 0 12.5 0 Unit ns ns ns ns 3.05 3.18 175 MHz ps ns Max Unit 161.0 Table 5. GPIO Timing Parameter Timing Requirement tFIPW Input Pulse Width Switching Characteristic tFOPW Output Pulse Width Min Typ tSYSBCLK + 1 ns tSYSBCLK - 1 ns Rev. B | Page 12 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) Table 6. I2C Port Timing Parameter Timing Requirements fSCL SCL Clock Frequency SCL Pulse Width High tSCLH tSCLL SCL Pulse Width Low tSCS Start and Repeated Start Condition Setup Time tSCH Start Condition Hold Time tSPS Stop Condition Hold Time tDS Data Setup Time tDH Data Hold Time SCL Rise Time tSCLR tSCLF SCL Fall Time tSDR SDA Rise Time tSDF SDA Fall Time tBFT Bus-Free Time Between Stop and Start Min Typ 0 0.6 1.3 0.6 0.6 0.6 100 0.0 Max Unit 400 kHz s s s s s ns s ns ns ns ns s 0.9 300 300 300 300 1.3 SDA tSDF tSCLL tSCLR tDS tSCLF tSCH tSPS tBFT tSDR SCL S tSCH tDH tSCLH tSCS Sr Figure 9. I2C Port Timing Rev. B | Page 13 of 38 | January 2020 tSCS P S AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) Table 7. I2S Timing Parameter I2S Slave Timing Requirements (A2B Master) tBCLKW BCLK Width tBCLKS BCLK Period 1 tSIS SYNC Input Setup Before BCLK Sample Edge SYNC Input Hold After BCLK Sample Edge tSIH1 tRISM1 DRXn Input Setup Before BCLK Sample Edge tRIHM1 DRXn Input Hold After BCLK Sample Edge 1 tRISM DRX1 on DTX1 Input Setup Before BCLK Sample Edge tRIHM1 DRX1 on DTX1 Input Hold After BCLK Sample Edge I2S Slave Switching Characteristics (A2B Master) DTXn Output Delay After BCLK Drive Edge tDODM2 tDOHM2 DTXn Output Hold After BCLK Drive Edge tDOENM2 DTXn Data Enable Delay After BCLK Drive Edge 2 tDODIM DTXn Data Disable Delay After BCLK Drive Edge I2S Master Timing Requirements (A2B Slave) tRISS1 DRXn Input Setup Before BCLK Sample Edge 1 DRXn Input Hold After BCLK Sample Edge tRIHS tRISS1 DRX1 on DTX1 Input Setup Before BCLK Sample Edge tRIHS1 DRX1 on DTX1 Input Hold After BCLK Sample Edge I2S Master Switching Characteristics (A2B Slave) fBCLK BCLK Output Frequency3 tBCLKMOJ BCLK Output Jitter (RMS Cycle to Cycle, fBCLKS = 12.288 MHz) tSOL/tSOH Transmit or Receive BCLK Duty Cycle tSOJ SYNC Output Jitter (RMS Cycle to Cycle fSYNCM = 48 kHz) tSOD2 SYNC Output Delay After BCLK Drive Edge tSOHD2 SYNC Output Hold After BCLK Drive Edge 2 tDODS DTXn Output Delay After BCLK Drive Edge tDOHS2 DTXn Output Hold After BCLK Drive Edge Min 1.8 V Max 19.5 39.0 2.25 2.0 0.5 2.0 4.0 0.5 Min 9.5 19.0 2.25 3.0 0.5 1.5 4.5 0.5 15.25 3.0 2.0 0.0 5.8 2.5 2.5 12.0 8.0 0.0 2.0 4.5 0.5 25.0 100 0.55 2.2 6.5 2.8 0.45 1 50.0 100 0.55 2.2 6.5 9.25 6.0 ns ns ns ns ns ns ns ns 4.5 10.8 5.5 Unit ns ns ns ns ns ns ns ns 3.0 2.0 13.0 0.45 3.3 V Max MHz ps tBCLK ns ns ns ns ns Referenced to sample edge. Referenced to drive edge. 3 When VIOVDD = 3.3 V, the setup and hold timing at the 50 MHz maximum bit clock rate can be violated when interfacing with other I2S devices. The timing violations are seen when the A2B slave node is receiving and A2B master node is transmitting. In these modes, the maximum BCLK frequency of 50 MHz cannot be achieved. 2 Rev. B | Page 14 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) DRIVE EDGE SAMPLE EDGE tBCLKW BCLK/PDMCLK tSIS tSIH SYNC tRISM RECEIVE DATA (DRXn) CHANNEL tRIHM MSB MSB - 1 MSB MSB - 1 tDODM tDOHM TRANSMIT DATA (DTXn) CHANNEL Figure 10. I2S Slave (A2B Master) Timing DRIVE EDGE SAMPLE EDGE tSOL/tSOH BCLK/PDMCLK tSOD tSOHD SYNC tRISS RECEIVE DATA (DRXn) CHANNEL tRIHS MSB MSB - 1 MSB MSB - 1 tDODS tDOHS TRANSMIT DATA (DTXn) CHANNEL Figure 11. I2S Master (A2B Slave) Timing DRIVE EDGE DRIVE EDGE BCLK tDOENM TRANSMIT DATA (DTXn) CHANNEL Figure 12. I2S Slave (A2B Master) Enable and Three-State Timing Rev. B | Page 15 of 38 | January 2020 tDODIM AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) POWER-UP SEQUENCING RESTRICTIONS When externally supplied, VDVDD and VIOVDD must reach at least 90% of specification before VVIN begins ramping. To avoid damage to input pins and to ensure correct sampling of the ADR1/ADR2 pins at start-up, VIOVDD must be within specification before input signals are driven by external devices. Table 8. Power-Up Timing Parameter Min Max Unit Timing Requirements tVIN When Externally Supplied, VDVDD and VIOVDD Must Reach 90% of Specification Before VVIN Begins Ramping >0 ms tPORST Minimum Time Required for VVIN to be Held Below VRST to Assert Power on Reset 25 ms VDVDD | VIOVDD tPORST tVIN VVIN MIN VRST MAX VRSTN Figure 13. Power-Up Sequencing Timing with Externally Supplied VDVDD and VIOVDD Rev. B | Page 16 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) A2B BUS SYSTEM SPECIFICATION Table 9. A2B System Specifications Parameter Cable Maximum Cable Length AD2428(W)Mastered System AD2429(W) Mastered System Maximum Number of Nodes AD2428(W) Mastered System AD2429(W) Mastered System Maximum Number of Audio Slots AD2426(W)/AD2427(W)/AD2428(W)1 AD2420(W)/AD2429(W)1 System Specification Unshielded, single, twisted pair wire (UTP) with 100 differential impedance. EMC performance and full functionality under worst-case environmental conditions is confirmed with Leoni Dacar 545 cable (76D00305). 40 m total, 15 m between nodes. 10 m total, 5 m between nodes. 11 nodes (1 master node and 10 slave nodes). Three nodes (1 master node and 2 slave nodes). 64 total, up to 32 upstream and 32 downstream slots, depending upon system design. AD2429(W): 4 upstream and 2 downstream slots, depending upon system design. AD2420(W): 2 upstream slots, depending upon system design. Number of Audio Channels per Slave Node Individually programmable 0 to 32 upstream channels and 0 to 32 downstream channels. 8, 12, 16, 20, 24, 28, or 32 bits to match I2S/TDM data-word lengths. Same slot size for all nodes. Synchronous A2B Data Slot Size Upstream and downstream can choose different slot sizes. 12-, 16-, or 20-bit slot sizes can carry compressed data over the A2B bus for 16-, 20-, or 24-bit I2S/TDM word lengths. Audio Sampling Frequency 44.1 kHz to 48 kHz. All nodes sample synchronously. Slave node transceivers support sample rates (fS) of 1x (48 kHz), 2x (96 kHz) or 4x (192 kHz), individually configured per slave. To support 2x and 4x sampling rates in slaves, the master uses two and four times the number of I2S/TDM data channels as the 1x sampling frequency (fSYNCM) interface to the host. Transceivers also support reduced rate sampling for 24 kHz, 12 kHz, 6 kHz, 4 kHz, 3 kHz, 2.4 kHz, 2 kHz, 1.71 kHz, or 1.5 kHz at a low latency 48 kHz superframe rate. Discovery Time Less than 35 ms per node. Much less than 350 ms for total system startup in a system with 10 nodes. Includes register initialization. Bit Error Detection Robust error detection for control data and status data with 16-bit cyclic redundancy check (CRC). Error Correction Parity and line code error detection on synchronous data slots with audio error correction (repeat of last known good data). For 24-bit and 32-bit data channels, single error correction and double error detection (SECDED) of synchronous data slots is possible. Failure Diagnostics1 Location and cause of failure can be detected for A2B wires shorted to a high voltage (for example, positive terminal of car battery), shorted to ground, wires shorted to each other, wires reversed or open connection. System EMI/EMC Meets or exceeds industry specifications for robustness (ISO 11452-2, ISO 11452-4, ISO 7637-3) and emissions (CISPR25). System ESD See IEC ESD ratings in Table 12 for terminals. 1 See the AD2420(W)/6(W)/7(W)/8(W)/9(W) Automotive Audio Bus A2B Transceiver Technical Reference for more information. Rev. B | Page 17 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) RMS Time Interval Error (TIE) Jitter Table 10. SYNC Output RMS TIE Jitter at Each Slave Typ 1.57 1.79 1.91 2.04 2.15 2.27 2.44 2.47 2.58 2.70 Max 5.50 Unit ns ns ns ns ns ns ns ns ns ns -0.2 -0.4 -0.5 0.0001 0.001 0.01 0.1 1 NORMALIZED FREQUENCY (RELATIVE TO fSYNCM) (Hz) Figure 15. PDM Frequency Response 160 140 Figure 14 through Figure 18 and Table 11 describe typical PDM performance characteristics. 120 100 80 60 40 20 0 10 100 1k 10k 100k FREQUENCY (Hz) Figure 16. PDM Group Delay vs. Frequency, fSYNCM = 48 kHz CH1 CH2 0 -20 20 100 1k FREQUENCY (Hz) 10k -40 20k Figure 14. PDM FFT, fSYNCM = 48 kHz, -60 dB Frame Sync Input THD + N (dBFS) LEVEL (dBFS) -0.1 -0.3 PDM TYPICAL PERFORMANCE CHARACTERISTICS 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 0 GROUP DELAY (s) Slave Node 1 2 3 4 5 6 7 8 9 10 0.1 LEVEL (dBFS) Clocks in an A2B system are passed from the master to Slave 0, from Slave 0 to Slave 1, and so on. Each transceiver adds self jitter to the incoming jitter, which results in jitter growth from the master to the nth slave. Table 10 illustrates typical rms TIE jitter growth. -60 -80 -100 -120 -140 0.0001 0.001 0.01 0.1 1 NORMALIZED FREQUENCY (RELATIVE TO fSYNCM) (Hz) Figure 17. PDM Total Harmonic Distortion + Noise (THD + N) vs. Normalized Frequency (Relative to fSYNCM) Rev. B | Page 18 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) 0 -20 MAGNITUDE (dB) -40 -60 -80 -100 -120 -140 -160 0 0.5 1.0 FREQUENCY (MHz) 1.5 Figure 18. PDM Out of Band Frequency Response (48 kHz Output) Table 11. PDM Interface Performance Specifications Parameter Dynamic Range With A-Weighted Filter (RMS) SNR Decimation Ratio Frequency Response Stop Band Attenuation Group Delay Gain Start-Up Time1 Bit Width 1 Conditions 20 Hz to 20 kHz, -60 dB input A-weighted, fourth-order input Default is 64x DC to 0.45 fSYNCM Min 64x -0.1 Typ 120 120 128x 0.566 74 0.02 fSYNCM input signal PDM to PCM Internal and output 3.80 0 48 24 Max Unit dB dB 256x +0.01 dB fSYNCM dB fSYNCM cycles dB fSYNCM cycles Bits The PDM start-up time is the time for the filters to settle after the PDM block is enabled. It is the time to wait before data is guaranteed to meet the specified performance. Rev. B | Page 19 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) ABSOLUTE MAXIMUM RATINGS Stresses at or above those listed in Table 12 can cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 12. Absolute Maximum Ratings Parameter Rating VIN to VSS -0.7 V to +30 V Power Supply IOVDD to VSS -0.3 V to +3.63 V Power Supply DVDD to VSS -0.3 V to +1.98 V Power Supply PLLVDD to VSS -0.3 V to +1.98 V Power Supply TRXVDD to VSS Digital Pin Output Voltage Swing -0.3 V to +3.63 V 1 Input Voltage2, 3 -0.33 V to +3.63 V Input Voltage2, 4 2 I C Input Voltage -0.3 V to VIOVDD + 0.5 V -0.33 V to +2.10 V 2, 5 -0.33 V to +5.5 V 2 A B Bus Terminal Voltage AP, AN, BP, and BN Pins -0.5 V to +4.1 V SENSE, SWP, VSSN Voltage to VSS +30 V maximum Storage Temperature Range -65C to +150C Junction Temperature While Biased -40C to +125C VIN and SWP Pins 2.5 kV AP, AN, BP, and BN Pins 2.5 kV All Other Pins 2.5 kV ESD Rating FICDM 1.25 kV System ESD Rating CON1-A and CON1-B Terminals6 IEC 61000-4-2, Air Discharge 15 kV IEC 61000-4-2, Contact Discharge 12 kV Group 1 2 Pins in Group IRQ/IO0, ADR1/IO1, ADR2/IO2 BCLK, SYNC, DTX0/IO3, DTX1/DRX1/IO4, DRX0/IO5, DRX1/IO6, IO7 THERMAL CHARACTERISTICS To determine the junction temperature on the application printed circuit board (PCB), use the following equations: TJ = TCASE + JT x PD where: TJ = junction temperature (C). TCASE = case temperature (C) measured by customer at top center of package. JT = values in Table 14. PD = power dissipation. Values of JA are provided for package comparison and PCB design considerations. Use JA for a first-order approximation of TJ by the following equation: TJ = TA + JA x PD Values of JC are provided for package comparison and PCB design considerations when an external heat sink is required. Values of JB are provided for package comparison and PCB design considerations. Thermal characteristics of the LFCSP_SS package are shown in Table 14. See JESD51-13 for detailed parameter definitions. The junction to board measurement complies with JESD51-8. The junction to case measurement complies with MIL-STD-883 (Method 1012.1). All measurements use a 2S2P JEDEC test board. Table 14. Thermal Characteristics Digital Pin Output Current per Pin Group7 15 mA 1 Table 13. Total Current Pin Groups where TA = ambient temperature (C). ESD Rating HBM All Pins Permanent damage can occur if the digital pin output current per pin group value is exceeded. For example, if three pins from Group 2 in Table 13 are sourcing or sinking 2 mA each, the total current for those pins is 6 mA. Up to 9 mA can be sourced or sunk by the remaining pins in the group without damaging the device. Applies to BCLK, SYNC, DTX0/IO3, DTX1/DRX1/IO4, DRX0/IO5, DRX1/IO6, IRQ/IO0, ADR1/IO1, ADR2/IO2, PDMCLK/IO7. 2 Only applies when the related power supply (VIOVDD) is within specification. When the power supply is below specification, the range is the voltage being applied to that power domain 0.2 V. 3 Applies when nominal VIOVDD is 3.3 V. 4 Applies when nominal VIOVDD is 1.8 V. 5 Applies to SCL and SDA. 6 CON1-A and CON1-B are connectors. 7 For more information, see the following description and Table 13. Parameter JA JMA JMA JC JB JT JT JT Rev. B | Page 20 of 38 | January 2020 Conditions Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Airflow = 0 m/s Airflow = 0 m/s Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Typical (C/W) 31.6 28.8 28.1 4.6 14.7 0.20 0.27 0.30 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) ESD CAUTION ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. 30 IOVDD = 3.6V @ - 40C IOVDD = 3.3V @ 25C 20 SOURCE CURRENT (mA) The 32-lead LFCSP_SS package requires thermal trace squares and thermal vias to an embedded ground plane in the PCB. The exposed paddle must connect to ground for proper operation to data sheet specifications. Refer to JEDEC standard JESD51-5 for more information. IOVDD = 3.0V @ 125C 10 VOH 0 - 10 VOL - 20 - 30 0 1.5 1.0 2.5 2.0 3.5 3.0 4.0 SOURCE VOLTAGE (V) TEST CIRCUITS AND SWITCHING CHARACTERISTICS Figure 21. GPIO, BCLK, and SYNC Drivers (DS0, 3.3 V IOVDD) Figure 19 shows a line driver voltage measurement circuit of the differential line driver and receiver AP/AN and BP/BN pins. 0 IOVDD = 1.9V @ - 40C SOURCE CURRENT (mA) AP/BP VOD 0.5 AN/BN - 0.5 IOVDD = 1.8V @ 25C - 1.0 IOVDD = 1.7V @ 125C - 1.5 - 2.0 - 2.5 - 3.0 - 3.5 VOL - 4.0 Figure 19. Differential Line Driver Voltage Measurement - 4.5 - 5.0 OUTPUT DRIVE CURRENTS 0 0.2 0.4 0.6 0.8 1 1.2 IOVDD = 3.6V @ - 40C 4 VOH 2 0 SOURCE CURRENT (mA) SOURCE CURRENT (mA) IOVDD = 1.7V @ 125C IOVDD = 3.0V @ 125C -6 -8 - 10 - 12 VOL - 14 - 2.0 - 16 - 4.0 - 18 VOL 0 - 6.0 0.5 1.0 1.5 2.0 2.5 SOURCE VOLTAGE (V) - 8.0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2.0 IOVDD = 3.3V @ 25C -4 IOVDD = 1.8V @ 25C 1.8 0 8 6 1.6 Figure 22. I2C Drivers (1.8 V IOVDD) -2 IOVDD = 1.9V @ - 40C 1.4 SOURCE VOLTAGE (V) Figure 20 through Figure 25 show typical current voltage characteristics for the output drivers of the transceiver. The curves represent the current drive capability of the output drivers as a function of output voltage. Drive Strength 0 is DS0, and Drive Strength 1 is DS1. 2.0 SOURCE VOLTAGE (V) Figure 20. GPIO, BCLK, and SYNC Drivers (DS0, 1.8 V IOVDD) Rev. B | Page 21 of 38 | January 2020 Figure 23. I2C Drivers (3.3 V IOVDD) 3.0 3.5 4.0 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) 15 IOVDD = 1.9V @ - 40C IOVDD = 1.8V @ 25C SOURCE CURRENT (mA) 10 IOVDD = 1.7V @ 125C VOH 5 The output enable time, tENA, is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving, as shown on the right side of Figure 27. If multiple pins are enabled, the measurement value is that of the first pin to start driving. 0 REFERENCE SIGNAL -5 VOL - 10 tDIS - 15 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 tENA 2.0 SOURCE VOLTAGE (V) Figure 24. GPIO, BCLK, and SYNC Drivers (DS1, 1.8 V IOVDD) 60 IOVDD = 3.6V @ - 40C SOURCE CURRENT (mA) OUTPUT STOPS DRIVING IOVDD = 3.3V @ 25C 40 IOVDD = 3.0V @ 125C OUTPUT STARTS DRIVING HIGH IMPEDANCE STATE 20 Figure 27. Output Enable/Disable VOH 0 Output Disable Time Measurement - 20 VOL -40 - 60 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 SOURCE VOLTAGE (V) Figure 25. GPIO, BCLK, and SYNC Drivers (DS1, 3.3 V IOVDD) TEST CONDITIONS All timing parameters in this data sheet were measured under the conditions described in this section. Figure 26 shows the measurement point for ac measurements (except output enable/disable). The measurement point, VMEAS, is VIOVDD/2 for VIOVDD (nominal) = 3.3 V. INPUT OR OUTPUT VMEAS Output pins are considered disabled when they stop driving, enter a high impedance state, and start to decay from the output high or low voltage. The output disable time, tDIS, is the interval from when a reference signal reaches a high or low voltage level to the point when the output stops driving, as shown on the left side of Figure 27. Capacitive Loading Output delays and holds are based on standard capacitive loads of an average of 6 pF on all pins (see Figure 28). VLOAD is equal to VIOVDD/2. Figure 29 through Figure 32 show how output rise time varies with capacitance. The delay and hold specifications given must be derated by a factor derived from these figures. The graphs in Figure 29 through Figure 32 cannot be linear outside the ranges shown. VMEAS Figure 26. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) Output Enable Time Measurement Output pins are considered enabled when they make a transition from a high impedance state to the point when they start driving. Rev. B | Page 22 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) 9 TESTER PIN ELECTRONICS 50: T1 DUT OUTPUT 45: 70: ZO = 50:(impedance) TD = 4.04 r 1.18 ns 50: 0.5pF 4pF 2pF 400: RISE AND FALL TIMES (ns) 8 VLOAD 7 6 tRISE 5 tFALL 4 3 2 1 DRIVE STRENGTH = 1 NOTES: THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS. ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN SYSTEM REQUIREMENT. IF NECESSARY, THE SYSTEM CAN INCORPORATE EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES. 0 0 5 10 15 20 25 30 35 40 45 LOAD CAPACITANCE (pF) Figure 30. GPIO Driver Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance (VIOVDD = 1.8 V, TJ = 25C) 10 Figure 28. Equivalent Device Loading for AC Measurements (Includes All Fixtures) 9 RISE AND FALL TIMES (ns) 8 18 RISE AND FALL TIMES (ns) 16 14 12 tRISE 10 7 6 tRISE 5 tFALL 4 3 2 8 tFALL 1 DRIVE STRENGTH = 0 6 0 10 0 4 20 30 40 50 60 LOAD CAPACITANCE (pF) 2 DRIVE STRENGTH = 0 0 0 5 10 15 20 25 30 35 40 45 Figure 31. GPIO Driver Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance (VIOVDD = 3.3 V, TJ = 25C) LOAD CAPACITANCE (pF) 8 Figure 29. GPIO Driver Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance (VIOVDD = 1.8 V, TJ = 25C) RISE AND FALL TIMES (ns) 7 6 5 tRISE 4 tFALL 3 2 1 DRIVE STRENGTH = 1 0 0 10 20 30 40 50 60 70 80 90 LOAD CAPACITANCE (pF) Figure 32. GPIO Driver Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance (VIOVDD = 3.3 V, TJ = 25C) Rev. B | Page 23 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) PIN CONFIGURATION AND FUNCTION DESCRIPTIONS All digital inputs and digital outputs are three-stated with inputs disabled during reset. VOUT1 VSS VIN VOUT2 SENSE SWP VSSN VSS The 32-lead LFCSP_SS package pin configuration is shown in Figure 33. The pin function descriptions are shown in Table 15. PLLVDD DVDD DVDD SCL SDA IRQ/IO0 ADR1/IO1 ADR2/IO2 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 EPAD (PIN 33) TOP VIEW 17 BCM BN BP BTRXVDD ATRXVDD AP AN ACM PDMCLK/IO7 DTX1/IO4 DRX0/IO5 DRX1/IO6 IOVDD BCLK SYNC DTX0/IO3 9 10 11 12 13 14 15 16 PIN 33 IS THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE. THIS PIN MUST BE CONNECTED TO GND. Figure 33. 32-Lead LFCSP_SS and LFCSP Package Pin Configuration Table 15. AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) Pin Function Descriptions Pin No. 1 2, 3 42 Pin Name PLLVDD DVDD SCL Type PWR PWR D_IO Alternate Functions1 None None None Description Power Supply for PLL. PLLVDD can be supplied by VVOUT1. Power Supply for Digital Core Logic. DVDD can be supplied by VVOUT1. Serial Clock for I2C Data Transfers. Digital input in A2B master mode. Digital input (I2C slave) or output (I2C master) in A2B slave mode. This pin uses open-drain I/O cells and must be pulled up to VI2C_VBUS through a resistor (consult Version 2.1 of the I2C bus specification for the proper resistor value). Connect the pin to ground when the I2C interface is not used. SDA D_IO None I2C Mode Serial Data. This pin is a bidirectional open-drain input/output and must be pulled up 52 to VI2C_VBUS through a resistor (consult Version 2.1 of the I2C bus specification for the proper resistor value). Connect the pin to ground if the I2C interface is not used. 62 IRQ/IO0 D_IO None Interrupt Request Output. In master mode, A2B transceivers create event driven interrupt requests towards the host controller. In slave mode, this pin indicates mailbox empty/full status to the slave node processor when mailbox interrupts are enabled. When not serving as an interrupt output pin, this pin serves as a general-purpose I/O pin with interrupt request input capability. The IRQ/IO0 pin must be initialized to become either an input or an output. This pin is high impedance by default. 2 7 ADR1/IO1 D_IO CLKOUT1 The ADR1/IO1 and ADR2/IO2 pins set the I2C slave device address during power-on reset; up to four A2B master transceiver chips connect to the same I2C bus. The ADR1/IO1 pin is high impedance by default. The ADR1/IO1 pin can then be initialized to become a general-purpose input/output (GPIO) pin with interrupt request capability. This pin can be programmed to become a clock output (CLKOUT1). The clock output can be used as a master clock for connected ADCs and DACs or to synchronize switching voltage regulators. In this table, the Type is defined as follows: PWR = power/ground, A_IN = analog input, D_OUT = digital output, A_IO = analog input/output, D_IO = digital input/output, N/A = not applicable. Rev. B | Page 24 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) Table 15. AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) Pin Function Descriptions (Continued) Pin No. Pin Name 82 ADR2/IO2 Alternate Functions1 Description CLKOUT2 The ADR1/IO1 and ADR2/IO2 pins set the I2C slave device address during power-on reset; up to four A2B master transceiver chips connect to the same I2C bus. The ADR2/IO2 pin is high impedance by default. The ADR2/IO2 pin can then be initialized to become a general-purpose input/output (GPIO) pin with interrupt request capability. This pin can be programmed to become a clock output (CLKOUT2). The clock output can be used as a master clock for connected ADCs and DACs or to synchronize switching voltage regulators. 9 IOVDD PWR None Power Supply for Digital Input and Output Pins. The digital output pins are supplied from IOVDD, which also sets the highest input voltage that is allowed on the digital input pins. Two I/O voltage ranges are supported (see VIOVDD specifications in the Operating Conditions section). The current draw of these pins is variable and depends on the loads of the digital outputs. IOVDD can be sourced by either the VOUT1 or VOUT2 pin. However, if the signals do not originate from logic supplied by the VOUT1 pin or VOUT2 pin, source IOVDD with an external supply. 10 BCLK D_IO PDMCLK Bit Clock. Digital input in master mode. Digital output in slave mode. When using the PDM interface in slave mode, this pin can operate as the clock output (PDMCLK) for PDM microphones (the PDMCLK/IO7 pin can also be used). 11 SYNC D_IO None Synchronization Signal. Digital input in master mode. Digital output in slave mode. For the AD2428W and AD2429W, the SYNC signal frames a multichannel I2S/TDM data stream. An A2B master node must have a continuous signal because the A2B master transceiver derives all clocking information for itself and for the A2B bus from this input. When this pin stops toggling, the A2B bus resets after a delay. For more information, see Table 3. 2 12 DTX0/IO3 D_IO None For the AD2428W and ADW2429W, serial I2S/TDM data is driven to the DTX0/IO3 pin in multichannel I2S/TDM format. This pin serves as the IO3 general-purpose I/O pin when DTX0 function is disabled. The DTX0/IO3 pin is high impedance by default until configured. The pin returns to high impedance when the chip resets due to a missing synchronization signal or low supply voltage. For the ADW2420W, AD2426W, and AD2427W, this pin is GPIO only (IO3). 132 DTX1/IO4 D_IO DRX1 For the AD2428W and AD2429W, serial I2S/TDM data is driven to the DTX1/IO4 pin in multichannel I2S/TDM format. When configured as the alternate DRX1 location, the DTX1/IO4 pin receives data presented in multichannel I2S/TDM format. This alternate location can be used when the DRX0/IO5 and DRX1/IO6 pins are used to receive PDM microphone data. This pin serves as the IO4 general-purpose I/O pin when DTX1 and DRX1 functions are disabled. The DTX1/IO4 pin is high impedance by default until configured. The pin returns to high impedance when the chip resets due to a missing synchronization signal or low supply voltage. For the AD2420W, AD2426W, and AD2427W, this pin is GPIO only (IO4). 142 DRX0/IO5 D_IO PDM0 For the AD2428W and AD2429W, serial I2S/TDM data is received on the DRX0/IO5 pin in multichannel I2S/TDM format. This pin is an input for microphone data when enabled as a PDM input (PDM0). This pin serves as the IO5 GPIO pin when DRX0 and PDM0 functions are disabled. The DRX0/IO5 pin is high impedance by default until configured. The pin returns to high impedance when the chip resets due to a missing synchronization signal or low supply voltage. For the AD2420W, AD2426W, and AD2427W, the DRX0 function is not supported. In this table, the Type is defined as follows: PWR = power/ground, A_IN = analog input, D_OUT = digital output, A_IO = analog input/output, D_IO = digital input/output, N/A = not applicable. Type D_IO Rev. B | Page 25 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) Table 15. AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) Pin Function Descriptions (Continued) Pin No. Pin Name 152 DRX1/IO6 Alternate Functions1 Description PDM1 For the AD2428W and AD2429W, serial I2S/TDM data is received on the DRX1/IO6 pin in multichannel I2S/TDM format. This pin is an input for microphone data when enabled as a PDM input (PDM1). This pin serves as the IO6 GPIO pin when DRX1 and PDM1 functions are disabled. The DRX1/IO6 pin is high impedance by default until configured. The pin returns to high impedance when the chip resets due to a missing synchronization signal or low supply voltage. For the AD2420W, AD2426W, and AD2427W, the DRX1 function is not supported. 2 PDMCLK/IO7 D_IO RRSTRB PDM Microphone Clock Output. 16 In master mode, the PDM clock output (PDMCLK) is used to clock PDM microphones. This pin runs at 64x the SYNC frequency regardless of the BCLK rate used by the host. When using the PDM interface in slave mode, this pin can still operate as the clock output for PDM microphones (PDMCLK), but BCLK can also be used. When PDM functions are disabled, this pin serves as the IO7 GPIO pin. The PDMCLK/IO7 pin can also be used as a strobe to indicate when reduced rate data is updated (RRSTRB). The PDMCLK/IO7 pin is high impedance by default until configured. The pin returns to high impedance when the chip resets due to a missing synchronization signal or low supply voltage. 17 ACM A_IN None Common-Mode Input for Bidirectional, Differential A2B Line Transceiver A. 18 AN A_IO None Inverted Pin of Bidirectional, Differential A2B Line Driver and Receiver A. Pin 18 is directed towards the master. Pin 18 is self biased. 19 AP A_IO None Noninverted Pin of Bidirectional, Differential A2B Line Driver and Receiver A. Pin 19 is directed towards the master. Pin 19 is self biased. 20 ATRXVDD PWR None Power Supply for A2B Line Driver and Receiver Circuit. Decouple these pins to VSS with one shared 100 nF capacitor and a shared 10 nF capacitor closest to the pin. The pins can be supplied by VOUT2. Supply the ATRXVDD pin for a master, last slave, or daisy-chained slave. 21 BTRXVDD PWR None Power Supply for A2B Line Driver and Receiver Circuit. Decouple these pins to VSS with one shared 100 nF capacitor and a shared 10 nF capacitor closest to the pin. The pins can be supplied by VOUT2. Supply the BTRXVDD pin for a master, last slave, or daisy-chained slave 22 BP A_IO None For the AD2427W, AD2428W, and AD2429W, this is the noninverted pin of bidirectional, differential A2B line driver and Receiver B, which is directed towards the last slave. This pin is self biased. 23 BN A_IO None For the AD2427W, AD2428W, and AD2429W, this is the inverted pin of bidirectional, differential A2B line driver and Receiver B, which is directed towards the last slave. This pin is self biased. 24 BCM A_IN None For the AD2427W, AD2428W, and AD2429W, this is the common-mode input for bidirectional, differential A2B Line Transceiver B. 25 VSS PWR None Power Supply Pin for Return Currents. Connect the VSS pin to a low impedance local VSS ground plane. 26 VSSN PWR None For the AD2427W, AD2428W, and AD2429W, this is the power supply return current connection for the next slave device. Connect to the inductor that provides the negative bias for the next slave device. The AD2427W, AD2428W, and AD2429W connect VSSN to the local VSS potential to sequence power to the next slave devices in the chain. VSSN automatically disconnects under critical fault conditions. 27 SWP D_OUT None For the AD2427W, AD2428W, and AD2429W, this is the active low open-drain output to drive the gate of a PMOS switch. The switch is open (SWP pin is high) by default. The switch can be closed (SWP pin goes low) to sequence power to the next slave devices in the chain. The switch automatically opens (SWP goes high) under critical fault conditions. 28 SENSE A_IN None Analog input to sense the power supplied to the next slave device. For the AD2420W, AD2426W, or a last in line AD2427W/AD2428W/AD2429W, connect this pin to local ground through a 33 k pull-down resistor. In this table, the Type is defined as follows: PWR = power/ground, A_IN = analog input, D_OUT = digital output, A_IO = analog input/output, D_IO = digital input/output, N/A = not applicable. Type D_IO Rev. B | Page 26 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) Table 15. AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) Pin Function Descriptions (Continued) Pin No. Pin Name 29 VOUT2 Alternate Functions1 Description None Second Output of the On-Chip low Dropout Voltage Regulator. The voltage output on this pin provides a regulated supply to the TRXVDD supply pins. External devices also can be powered by this supply if the current consumption is within the specification. Decouple VOUT2 to VSS with a 4.7 F capacitor. 30 VIN PWR None Power supply pin that accepts a wide input voltage range (see the VVIN specification in the Operating Conditions section) for an on-chip low dropout voltage regulator. 31 VSS PWR None Power Supply Pin for Return Currents. Connect the VSS pin to a low impedance local VSS ground plane. 32 VOUT1 PWR None First Output of the On-Chip Low Dropout Voltage Regulator. The voltage output on this pin provides a regulated supply to the DVDD and PLLVDD power supply pins. External devices can be powered by this supply if the current consumption is within the specification. Decouple VOUT1 to VSS with a 4.7 F capacitor. 33 EPAD PWR None Power Supply Pin for Return Currents. See other VSS pin description in this table. This pin is the exposed pad on the bottom of the package and must be connected to GND. In this table, the Type is defined as follows: PWR = power/ground, A_IN = analog input, D_OUT = digital output, A_IO = analog input/output, D_IO = digital input/output, N/A = not applicable. 1 2 Type PWR See the AD2420(W)/6(W)/7(W)/8(W)/9(W) Automotive Audio Bus A2B Transceiver Technical Reference for more information about configuring pins for alternate functions. If the listed functions for this pin are not required, do not connect this pin. Rev. B | Page 27 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) POWER ANALYSIS This section provides information on power consumption of the A2B system. The intent of power dissipation calculations is to assist board designers in estimating power requirements for power supply and thermal relief designs. Constant Current Power dissipation on an A2B node depends on various factors, such as the required external peripheral supply current and bus activity. An A2B system can be comprised of a mix of bus powered slaves and local powered slaves. A bus powered slave derives power from the A2B bus wires. A local powered slave derives power from separate power wires. Power estimation for a bus powered system is more complex when compared to a local powered system. For power analysis, A2B systems with both local and bus powered slaves must be divided into segments of nodes that draw from the same power supply. PLL Supply Current All currents that are not influenced directly by A2B bus activity on other nodes fall under the category of constant current. The PLL supply current is specified as IPLLVDD, which is the static current in an active transceiver. VIN Quiescent Current The VIN quiescent current is specified as the static current IVINQ. It is independent of the load and does not include any power drawn from the voltage regulator output pins. IOVDD Current The on-chip I2S/TDM/PDM I/O current IIOVDD is based on dynamic switching currents on the BCLK, SYNC, DTX0, DTX1, DRX0, and DRX1 pins. CURRENT FLOW Figure 34 describe key parameters and equations to calculate power dissipation on the transceiver. The current flow on an A2B node incorporates the described current paths. The dynamic current, due to switching activity on an output pin, is calculated using the following equation: * Constant current Output Dynamic Current = (CPDout + CL) x VIOVDD x f * IPLLVDD -- PLL supply current where: CPDout = dynamic, transient power dissipation capacitance internal to the transceiver output pins. CL = total load capacitance that an output pin sees outside the transceiver. VIOVDD = voltage on a digital pin. f = frequency of switching on the pin. * IVINQ -- VIN quiescent current * I2C I/O current * IIOVDD -- I2S/TDM/PDM I/O current * IVEXT1 or IVEXT2 -- peripheral supply currents * IDVDD -- digital logic supply current The dynamic current, due to switching activity on an input pin, is calculated using the following equation: * ITRXVDD -- A2B bus TX/RX current * LVDS transceiver supply currents of A and B transceivers -- transmit LVDS TX and receive LVDS RX Input Dynamic Current = CPDin x VIOVDD x f where: CPDin = dynamic, transient power-dissipation capacitance internal to the input pins of the transceiver. IIOVDD = the sum of input and output dynamic currents of all pins internally supplied by the IOVDD pin. f = frequency of switching on the pin. I2C activity and the resulting I/O current is considered negligible when compared to other currents. Therefore, the on-chip I2C I/O current is not considered when calculating the current consumption. Peripheral Device(s) IVEXT2 IVEXT1 IIOVDD IVIN IDVDD IPLLVDD I VEXT2 + I VEXT1 IOVDD DVDD IVOUT1 PLLVDD VOUT1 IATRXVDD IVOUT2 1.9V VIN VOUT2 ATRXVDD BTRXVDD VREG1/2 IVINQ A2B TRANSCEIVER VSS IBTRXVDD 3.3V IVSSN Figure 34. Current Flow Model Rev. B | Page 28 of 38 | January 2020 VSSN AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) Peripheral Supply Current Peripheral components that are external to the transceiver also can be supplied through the voltage regulator outputs of VVOUT1 and VVOUT2. VVOUT1 can supply the current specified as IVEXT1 to external devices. VVOUT2 can supply the current specified as IVEXT2 to external devices. When bus powered, peripheral supply current draw has a direct impact on other nodes in the system. It is important to stay within the thermal package limits and not exceed the specification limits of IVSSN and VVIN in any of the A2B bus nodes. Digital Logic Supply Current * The number of upstream data bits transmitted in a node = number of upstream transmitted slots x (bits per slot + parity bit) where the parity bit = 1. The number of upstream transmitted slots is the sum of received upstream slots and locally contributed slots. * A side upstream transmitter activity level of a node. (SRF bits + number of transmitted upstream data bits) / 1024. LVDS Transmitter and Receiver Idle Current The idle current, ITRXVDD_IDLE, depends on ITXVDD and IRXVDD at 0% activity level and A2B bus idle time. The digital logic supply current IDVDD is a combination of static current consumption and digital TX/RX current. * B transceiver idle current. B Transceiver IBTRXVDD_IDLE LVDS current results from B transceiver idle time. A2B Bus TX/RX Current * A transceiver idle current. A Transceiver IATRXVDD_IDLE LVDS current results from A transceiver idle time. The level of A2B bus activity directly influences current consumption on both the LVDS transceivers related to A2B transmitter and receiver processing. LVDS Transmitter and Receiver Supply Currents The current ITRXVDD depends on ITXVDD and IRXVDD at 100% activity level and A2B bus activity: * Downstream LVDS transceiver current * B transceiver IBTXVDD LVDS TX current results from downstream TX activity level of the current node. * A transceiver IARXVDD LVDS RX current results from downstream activity level of the previous node. * Upstream LVDS transceiver current * A transceiver IATXVDD LVDS TX current results from A side upstream activity level of the current node. * B transceiver IBRXVDD LVDS RX current results from upstream activity level of the next in line node. Downstream/Upstream Activity Level The activity level for downstream data of TRX B is determined by the following: * B transceiver idle time. B transceiver idle time is the time when both the TX and RX of the B transceiver are idle. The idle time of the B transceiver is derived by eliminating the following activity levels from the B transceiver frame cycle: * B transceiver downstream activity level of the current node. * A transceiver upstream activity level of the next in line node. * A transceiver idle time is the time when both the TX and RX of the A transceiver are idle. The idle time of the A transceiver is derived by eliminating the following activity from the A transceiver frame cycle: * A transceiver upstream activity level of the current node. * B transceiver downstream activity level of previous node. The sum of the LVDS transceiver currents is ITRXVDD = IBRXVDD + IBTXVDD + IARXVDD + IATXVDD + IBTRXVDD_IDLE + IATRXVDD_IDLE * Header bits for downstream. A2B systems use 64 downstream header bits referred to as a synchronization control frame (SCF). VREG1 AND VREG2 OUTPUT CURRENTS * The number of downstream data bits transmitted in a node = the number of downstream transmitted slots x (bits per slot + parity bit) where the parity bit = 1. The number of downstream transmitted slots does not include the locally consumed slots. IVOUT2 is the current from VVOUT2 which is the sum of the LVDS transmitter and receiver supply currents, peripheral supply currents, and I/O current. * B side downstream transmitter activity level of a node. (SCF bits + number of downstream transmitted data bits) / 1024. The activity level for upstream data of TRX A is determined by the following: * Header bits for upstream. (SRF bits + total number of received downstream data bits) / 1024. Rev. B | Page 29 of 38 | Voltage regulator output currents are governed by the following equations: IVOUT2 = ITRXVDD + IIOVDD+ IVEXT2 IVOUT1 is the current from the VOUT1 pin which is the sum of PLL supply current, IPLLVDD, digital logic supply current IDVDD, peripheral supply current, IVEXT1, and I2S/TDM/PDM I/O current IIOVDD. IVOUT1 = IPLLVDD + IVEXT1 + IDVDD + IIOVDD IIOVDD in a slave node can be sourced by either IVOUT1 or IVOUT2 but not both, depending on whether IIOVDD is supplied from VVOUT1 or VVOUT2. January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) CURRENT AT VIN (IVIN) IVEXT2 = peripheral supply current from VVOUT2. VVOUT1 = output voltage from VREG1. VVOUT2 = output voltage from VREG2. The current at the VIN pin (IVIN) of the transceiver is the sum of currents IVOUT1 and IVOUT2 and the quiescent current, shown in Figure 34 and in the following equation: RESISTANCE BETWEEN NODES IVIN = IVOUT1 + IVOUT2 + IVINQ Figure 35 shows the dc model of a system with a combination of local and bus powered A2B slaves. The A side node current is the line bias current from an earlier node. In a bus powered node, it is also the power supply current and a portion of this current supplies the next in line nodes. A voltage drop of the dc bias is observed between the A2B nodes, due to resistance and current consumption. Table 16 lists the causes of the dc resistance between nodes (RBETWEEN) with example resistance values. IA = IVIN + IB + IVREGPERI where: IB = B side current to the next node (= IVSSN return current and IA of the next in line node). IVREGPERI = peripheral current supplied from IA by extra voltage regulator, external to the transceiver (not illustrated in Figure 35 and Figure 36). Both bias supply and return currents are subject to resistance. Therefore, some resistance values must be doubled (for example, wire length resistance). Table 16. Breakdown/Budget of Typical DC Resistance Between Nodes POWER DISSIPATION Resistance Inductor DC Resistance Short Circuit Protection Resistor Positive Bias PMOS Switch On-Resistance Negative Bias Switch On-Resistance RVSSN Resistance of Connections Total RSUM Wire Length Resistance of Cable The power dissipation of the transceiver is calculated using the following equation: Power = IVIN x VVIN + (IVSSN)2 x RVSSN - IVEXT1 x VVOUT1 - IVEXT2 x VVOUT2 where: IVIN = current at VIN pin. VVIN = voltage at VIN pin. IVSSN = B side current IB to the next node and return current from the next node. The next node is the node connected to the B terminal of the current node. See Figure 35. RVSSN = internal VSSN on resistance (see Table 16). IVEXT1 = peripheral supply current from VVOUT1. 1 Connections Cable FB 1 1.2 0.04 2.39 0.242 /m 0.01 4 N/A1 N/A1 0.121 2 Connections IB VNODE0 FB PMOS Cable FB FB VNODEn <V VIN min PMOS IVIN <VVIN max VIN VIN VIN AD2428(W) B A AD2427(W)/ AD2428(W) R8 B AD2426(W)/ AD2427(W)/ AD2428(W) A IVSSN VSSN FB ISUM 1.2 Slave Node n IA VNODEM VSS Unit VREG ISUM A Total 1.04 1.05 0.11 BUS POWER Slave Node 0 VREG Qty 4 1 1 N/A means not applicable. LOCAL POWER Master Node Each 0.26 1.05 0.11 Connections VSS VSSN Cable FB IA VSS Connections Cable FB IB Figure 35. A2B DC Power Model for a System with Local and Bus Powered Slaves Rev. B | Page 30 of 38 | January 2020 VSSN B AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) VOLTAGE REGULATOR CURRENT IN MASTER NODE OR LOCAL POWERED SLAVE NODE POWER ANALYSIS OF BUS POWERED SYSTEM The bus power, required from a local powered node (master node) for powering all nodes in the system, is calculated using the following equation: Power equations in this data sheet are used for power calculations in the SigmaStudio(R) software. The power equations are also available in an Excel spreadsheet, provided by technical support upon request. Figure 36 shows the dc model for a bus powered A2B system. ISUM = IVIN + IVSSN + IINRUSH + IVREGPERI where: IVIN is the current to VVIN of the local powered mode. IVSSN is the return current from next in line slave node. It is equal to the IA current supplied to the next in line node. SUPPLY VOLTAGE The supply voltage (VVIN) level on a bus powered transceiver is predictable and can be calculated using the following equations derived from Figure 36. IINRUSH is the inrush current required to charge capacitors on the VIN pin at power-up. IVREGPERI is the input current of extra VREG for peripherals (not illustrated in Figure 35 and Figure 36). For the master node, the supply voltage is calculated as, VNODEM = VREGM - VDIODE3 VVIN = VREGM - VDIODE1 for master Analog Devices recommends a minimum IINRUSH of 150 mA to support the components shown in the reference schematics. The selected voltage regulator must be sized to meet ISUM for the application. For a slave node, the supply voltage is calculated as, VNODE = VNODE' - IA x RBETWEEN VVIN = VNODE - VDIODE1 where: VNODE' is the VNODE voltage potential of the earlier node. The earlier node is the node connected to the A side transceiver of the current node. RBETWEEN is the connection resistance between the current and earlier node, described in the Resistance Between Nodes section. VDIODE is the voltage drop of the Shottkey reverse polarity protection diode. IVSSN current is below 2 mA when the next in line node is a local powered slave with a circuit-based on the Designer Reference section. The ISUM current in most applications is less than 100 mA if the next in line node is a local powered slave node. More current, IVSSN, is drawn if the next in line node uses bus power.The IVSSN maximum specification limits the bus power draw of slave nodes, especially in a line of bus powered slaves. IA is the current that a bus powered slave node draws from an earlier node. POWER DISSIPATION OF A2B BUS The power dissipation of an A2B system is calculated as follows: Power Dissipation = ISUM x VVIN of master. Master Node Slave Node 0 Slave Node n VREG ISUM Connections V NODEM IA Cable FB Connections IB VNODE0 FB Cable FB VNODEn Connection D3 PMOS PMOS D1 IVIN <VVIN max VIN A VSS >VVIN min VIN B AD2428(W) VSSN FB ISUM FB A VSS Connections Cable VIN AD2427(W)/ AD2428(W) IVSSN B VSSN FB FB IA AD2426(W)/ AD2427(W)/ AD2428(W) A VSS Connections Cable IB Figure 36. A2B Power Model for Bus Powered System Rev. B | Page 31 of 38 | January 2020 FB VSSN B AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) For a system with all in-line bus powered nodes, IA is calculated cumulatively from the last in-line node as IA = IVIN + IB where: IA = current that a bus powered slave node draws from an earlier node. IVIN = current at VIN pin. IB = B side return current from the next in line node. The next in line node is the node connected to the B terminal of the current node. REDUCING POWER CONSUMPTION The following sections describe three methods that reduce power consumption. Power-Down Mode Any node in an A2B bus powered system can be shut down by disconnecting the power supply in the previous slave node (towards the master). Disconnecting a slave from the power supply also powers down all of the following slaves (towards the last slave). Standby Mode The A2B bus enters standby mode by setting the AD242X_DATCTL.STANDBY bit of the master. The SCF in standby mode is 19 bits long, instead of 64 bits. In standby mode, there is no upstream and no downstream traffic on the A2B bus, and only a minimal SCF keeps all the slave nodes synchronized. This keeps the A2B bus power in the lowest power state while maintaining clock synchronization between nodes. Using the equations in the Downstream/Upstream Activity Level section, the bus activity level in standby mode is, THERMAL POWER When calculating power, system designers must consider thermal power. Thermal power calculations are based on the package thermal characteristics, shown in the following equation: JA = thermal resistance (TJ - TA) / power [C/W] with airflow = 0 m/s Table 17 provides the thermal power allowance example. These values are derived from a JEDEC standard 2S2P test board. JA values vary significantly and depend on system design and conditions. For the example calculation in Table 17, the JA value provided is determined using the JEDEC standard conditions. In this example (Table 17), a slave node with 292 mW of power dissipation is used to provide the maximum estimated power. The margin is calculated by subtracting the maximum estimated power from the thermal power allowance. Table 17. Thermal Power Allowance Example Parameter TA TJ Delta (TJ - TA) Example JA Maximum Allowed Thermal Power Maximum Estimated Power Power Margin * Downstream activity level = 19 / 1024 = 1.9% * Upstream activity level = 0% The digital transceiver current, including the LVDS TX and RX current, are subject to the activity levels. The LVDS TX and RX current also are subject to idle current during the bus idle time. Control Mode In control mode, there are no data channels in a superframe. The superframe only has the 64-bit SCF and SRF in the frame with the control data embedded in the header bits. Therefore, the A2B bus power is less when compared to normal mode, which has data channels in the superframe. Using the equations in the Downstream/Upstream Activity Level section, the bus activity level in control mode is, * Bus activity level downstream = 64 / 1024 = 6.3% * Bus activity level upstream = 64 / 1024 = 6.3% The LVDS TX and RX current also are subject to idle current during the bus idle time. Rev. B | Page 32 of 38 | December 2019 Example Value 105 125 20 31.6 633 292 341 Unit C C C C/W mW mW mW AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) DESIGNER REFERENCE The following sections provide descriptions and layouts of some typical node configurations. An A2B-compliant master transceiver requires external components to pass EMC and ESD tests in the automotive environment and support full line diagnostics functionality. Diodes are required for correct line diagnostics and to prevent damage under line fault conditions. The master circuit must also supply bias voltage for line diagnostics and power supply to bus powered slaves. An A2B-compliant, last in the line, local powered, slave node transceiver requires external components to pass EMC and ESD tests in the automotive environment. The circuit must allow for full line diagnostics with properly terminated A2B bus bias and properly terminated signals. The circuit must also electrically isolate the local powered slave node from the earlier node to prevent line faults triggered by the formation of ground loops across power and communication wires. An A2B-compliant, local powered, slave node transceiver requires external components to pass EMC and ESD tests in the automotive environment. The circuit must allow for full line diagnostics with properly terminated A2B bus bias and properly terminated signals (A-side). The local powered slave node regenerates the bias voltage from its local supply and provides it to the next node (B-side) for line diagnostics and as a voltage supply for bus powered nodes. Diodes are required for correct line diagnostics and damage prevention under line fault conditions. 2 An A B-compliant, bus powered, slave node transceiver requires external components to pass EMC and ESD tests in the automotive environment. The circuit must use the A2B bias (Aside) as its low-pass filtered supply voltage (using inductors and capacitors). A2B communication signals must be separated from the dc content at the A-side transceiver by high-pass filtering with ac coupling capacitors. Capacitors must also be used on the B-side where the ac-coupled signal is merged with the recovered bias, which is supplied through ac signal blocking inductors. The bus powered slave node must include circuitry to forward the recovered bias voltage to the next node and to perform line diagnostics. A diode is required for correct line diagnostics and damage prevention under line fault conditions. VSENSE AND CONSIDERATIONS FOR DIODES The relative difference between the voltage on the VIN pin, VVIN, and the A2B bus bias voltage, VSENSE, is monitored by the SENSE pin under steady state normal operating conditions. The range must be within the values described in Table 18 for all line diagnostics to function correctly. Table 18. VVIN to VSENSE Range Range VVIN to VSENSE Min - 0.6 Max +0.5 Unit V The difference between VVIN and VSENSE is primarily influenced by diode voltage drops and the on resistance of the PMOS. (Contact your local Analog Devices representative for the latest schematic circuit recommendations and bill of materials.) Table 19 identifies which diodes cause voltage drops for each node type. Table 19. VVIN to VSENSEVoltage Dependencies Node Type Master Locally Powered Slave Bus Powered Slave VVIN to VSENSE Diode Dependencies D1, D3 D1, D3 D1 OPTIONAL ADD ON CIRCUITS An earlier node in the sequence can remotely power up the next locally powered slave node over the A2B bus by switching the bias voltage onto the A2B bus. The local powered slave node can sense this bias voltage and use it as an enable input for power switches or voltage regulators to awake the device from a very low current sleep mode. An optocoupler, shown in Figure 37, can differentiate input of the bias voltage and ensures that the locally powered slave node is electrically isolated. This avoids ground loops that can induce noise and also trigger line fault detection. Current during sleep is determined by the optocoupler transistor off current, the resistor to ground (R12), and the power switch enable circuit. Contact your local Analog Devices representative for the latest schematic circuit recommendations and bill of materials for each of these node configurations. The recommended circuit and component selection must be followed for A2B automotivegrade compliance. VBAT ABIASN ENABLE OPT1 R12 R9 ABIASP Figure 37. Optional Power Supply Enable Circuit with Optocoupler Rev. B | Page 33 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) LAYOUT GUIDELINES The transceivers are highly integrated devices, comprising both digital sections for audio data, clocks, PLL, and analog A2B transceiver sections. Use the following design rules to maximize performance and signal integrity: * Solder the exposed paddle underneath the transceiver effectively to the PCB where it is locally connected to the ground plane. Figure 38 shows transceiver foot print, recommended solder mask (matching exposed paddle), paste mask (dividing exposed paddle), and stitching of the ground plane. The solder paste under the exposed paddle is split into four square areas, which minimizes solder wicking through uncovered thermal vias and prevents sliding or tilting of the chip during solder reflow. See Soldering Considerations for Exposed-Pad Packages (EE-352), on the Analog Devices web site. The exposed paddle is used for a thermal pathway as well as for electrical connection. * Place power supply decoupling capacitors as close as possible to the transceiver chip with the smallest value capacitor being closest to the pin. * Where possible, flood unused PCB areas with connected ground planes on all layers. * Stitch ground planes at least every 5 mm. * Do not obstruct power supply and ground return paths by vias. * Use series resistors (33 ) near the source of clock and fast data signals. Also consider footprints for small filter capacitors for such signal traces. * Avoid using right angle bends in signal routing. Use rounded or 45 degree mitered bends instead. * Use shortest possible signal path on connectors (inner row of multirow, right angled connectors). * On multipin connectors, provide at least 3 mm spacing around differential A2B pin pairs to ensure that A2B signal pairs are closer to each other than to adjacent signals. The spacing improves EMC performance. Use low impedance static signals (ground) symmetrically on connector pins adjacent to the A2B bus pairs when tight spacing is required. * Route all traces as short as possible, especially the AP/AN and BP/BN signals. * Symmetrically route the AP/AN and BP/BN signals to suppress EMC. Match routing parasitic capacitance and inductance. * Symmetrically shield the AP/AN and BP/BN signals with ground. Use shields that are at least 0.5 mm wide and stitched generously with vias to the GND plane. Symmetry is best achieved with flooded plane areas. * Do not route switching signals or power supply traces next to or underneath the AP/AN and BP/BN signals. * Avoid using trace stubs, especially if they create an asymmetry on the AP/AN and BP/BN signals. Symmetrically route into and out of pads rather than branch out. * Differential impedance trace of the AP/AN and BP/BN signals should be 100 10% (10 MHz to 100 MHz) on both sides of the common-mode choke. * Avoid unnecessary layer transitions for the AP/AN and BP/BN signals. Match necessary layer transitions for differential signals. * Use an impedance of 50 10% to ground on all traces. * Magnetically separate common-mode chokes from each other by at least 2 mm. * Do not route ground or other signals on any layer underneath the common-mode chokes. Extend this exclusion at least 2 mm from between the pads. * For shielded wires, connect the shield to the local ground. * Place one side of the inductors in the signal path and bridge dc signals to the power and ground nets. * Place termination resistors symmetrically and close to the common-mode chokes. Rev. B | Page 34 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) 5.0 mm 0.4 mm EPAD Pastemask Areas 4 x 1.5 mm x 1.5 mm 0.5 mm Pad Pitch EPAD 3.6 mm x 3.6 mm Soldermask Opening 0.0508 mm larger than pads where clearance permits, else 0.0254 mm Pad 0.304 mm x 0.889 mm 1.5 mm Thermal Vias 0.254 mm drill 0.5334 mm Pads preferably tented/plugged and no relief to plane layers 1.5 mm 0.7 mm 5.7 mm Figure 38. Transceiver Footprint Rev. B | Page 35 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) OUTLINE DIMENSIONS Figure 40 shows the outline dimensions for the 32-Lead LFCSP (CP-32-12). Figure 39 shows the outline dimensions for the 32-Lead LFCSP_SS (CS-32-2). DETAIL A PIN 1 INDICATOR 5.10 5.00 SQ 4.90 (JEDEC 95) 0.30 0.25 0.20 0.80 0.75 0.70 SEATING PLANE 16 9 0.075~0.150 8 0.20 MIN BOTTOM VIEW 3.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF (Step dimension) 3.70 3.60 SQ 3.50 EXPOSED PAD 17 0.50 0.40 0.30 (SEE DETAIL A) 1 0.50 BSC TOP VIEW PIN 1 INDICATOR AREA OPTIONS 32 25 24 Figure 39. 32-Lead Lead Frame Chip Scale Package [LFCSP_SS] 5 mm x 5 mm Body, With Side Solderable Leads (CS-32-2) Dimensions shown in millimeters DETAIL A (JEDEC 95) PIN 1 INDICATOR 5.10 5.00 SQ 4.90 0.30 0.25 0.18 PIN 1 INDICATOR AREA OPTIONS 32 25 (SEE DETAIL A) 1 24 0.50 BSC 3.75 3.60 SQ 3.55 EXPOSED PAD 8 17 TOP VIEW 0.80 0.75 0.70 SEATING PLANE TOP VIEW 0.50 0.40 0.30 9 16 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5 Figure 40. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm x 5 mm Body and 0.75 mm Package Height (CP-32-12) Dimensions shown in millimeters Rev. B | Page 36 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) AUTOMOTIVE PRODUCTS The AD2420W/AD2426W/AD2427W/AD2428W/AD2429W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the nonautomotive models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown in Table 20 are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Table 20. Automotive Products Model1, 2, 3, 4 AD2420WCCPZxx AD2420WCCPZxx-RL AD2426WCCSZ AD2426WCCSZ-RL AD2426WCCSZxx AD2426WCCSZxx-RL AD2427WCCSZ AD2427WCCSZ-RL AD2427WCCSZxx AD2427WCCSZxx-RL AD2428WCCSZ AD2428WCCSZ-RL AD2428WCCSZxx AD2428WCCSZxx-RL AD2429WCCPZxx AD2429WCCPZxx-RL Temperature Range5 -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C Description 32-Lead Frame Chip Scale Package [LFCSP] 32-Lead Frame Chip Scale Package [LFCSP] 32-Lead Frame Chip Scale Package [LFCSP_SS] 32-Lead Frame Chip Scale Package [LFCSP_SS] 32-Lead Frame Chip Scale Package [LFCSP_SS] 32-Lead Frame Chip Scale Package [LFCSP_SS] 32-Lead Frame Chip Scale Package [LFCSP_SS] 32-Lead Frame Chip Scale Package [LFCSP_SS] 32-Lead Frame Chip Scale Package [LFCSP_SS] 32-Lead Frame Chip Scale Package [LFCSP_SS] 32-Lead Frame Chip Scale Package [LFCSP_SS] 32-Lead Frame Chip Scale Package [LFCSP_SS] 32-Lead Frame Chip Scale Package [LFCSP_SS] 32-Lead Frame Chip Scale Package [LFCSP_SS] 32-Lead Frame Chip Scale Package [LFCSP] 32-Lead Frame Chip Scale Package [LFCSP] 1 Package Option CP-32-12 CP-32-12 CS-32-2 CS-32-2 CS-32-2 CS-32-2 CS-32-2 CS-32-2 CS-32-2 CS-32-2 CS-32-2 CS-32-2 CS-32-2 CS-32-2 CP-32-12 CP-32-12 Z = RoHS Compliant Part. W = Qualified for Automotive Applications. 3 RL = Supplied on Tape and Reel. 4 For model numbers ending in xx or xx-RL, xx denotes the die revision. 5 Referenced temperature is ambient temperature. The ambient temperature is not a specification. See the Operating Conditions section for junction temperature (TJ) specification which is the only temperature specification. 2 Rev. B | Page 37 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) ORDERING GUIDE Model1 AD2420KCPZ AD2420BCPZ AD2426KCPZ AD2426BCPZ AD2427KCPZ AD2427BCPZ AD2428KCPZ AD2428BCPZ AD2429KCPZ AD2429BCPZ 1 2 Temperature Range2 0C to +70C -40C to +85C 0C to +70C -40C to +85C 0C to +70C -40C to +85C 0C to +70C -40C to +85C 0C to +70C -40C to +85C Description 32-Lead Frame Chip Scale Package [LFCSP] 32-Lead Frame Chip Scale Package [LFCSP] 32-Lead Frame Chip Scale Package [LFCSP] 32-Lead Frame Chip Scale Package [LFCSP] 32-Lead Frame Chip Scale Package [LFCSP] 32-Lead Frame Chip Scale Package [LFCSP] 32-Lead Frame Chip Scale Package [LFCSP] 32-Lead Frame Chip Scale Package [LFCSP] 32-Lead Frame Chip Scale Package [LFCSP] 32-Lead Frame Chip Scale Package [LFCSP] Package Option CP-32-12 CP-32-12 CP-32-12 CP-32-12 CP-32-12 CP-32-12 CP-32-12 CP-32-12 CP-32-12 CP-32-12 Z = RoHS Compliant Part. Referenced temperature is ambient temperature. The ambient temperature is not a specification. See the Operating Conditions section for junction temperature (TJ) specification which is the only temperature specification. I2CreferstoacommunicationsprotocoloriginallydevelopedbyPhilipsSemiconductors(nowNXPSemiconductors). (c)2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16813-0-1/20(B) Rev. B | Page 38 of 38 | January 2020