SN74GTLPH1645
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D – OCTOBER 1999 – REVISED SEPTEMBER 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus Family
D
TI-OPC Circuitry Limits Ringing on
Unevenly Loaded Backplanes
D
OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
D
Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
D
LVTTL Interfaces Are 5-V Tolerant
D
High-Drive GTLP Outputs (100 mA)
D
LVTTL Outputs (–24 mA/24 mA)
D
Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
D
Ioff, Power-Up 3-State, and BIAS VCC
Support Live Insertion
D
Bus Hold on A-Port Data Inputs
D
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
description
The SN74GTLPH1645 is a high-drive, 16-bit bus
transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. It is
partitioned as two 8-bit transceivers. The device
provides a high-speed interface between cards
operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times
faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP’s reduced output swing
(<1 V), reduced input threshold levels, improved differential input, OECcircuitry, and TI-OPCcircuitry.
Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using
several backplane models. The high drive allows incident-wave switching in heavily loaded backplanes with
equivalent load impedance down to 11 Ω.
GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.
The ac specification of the SN74GTLPH1645 is given only at the preferred higher noise-margin GTLP, but the
user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V
and VREF = 1 V) signal levels.
Normally , the B port operates at GTLP signal levels. The A-port and control inputs operate at L VTTL logic levels
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input
reference voltage.
Copyright 2001, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC, TI-OPC, and Widebus are trademarks of Texas Instruments.
DGG OR DGV PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
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28
56
55
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30
29
1DIR
1A1
1A2
GND
1A3
1A4
VCC
GND
1A5
1A6
GND
1A7
1A8
GND
ERC
2A1
2A2
GND
2A3
2A4
GND
VCC
2A5
2A6
GND
2A7
2A8
2DIR
1OE
1B1
1B2
GND
1B3
1B4
VCC
GND
1B5
1B6
GND
1B7
1B8
BIAS VCC
VREF
2B1
2B2
GND
2B3
2B4
GND
VCC
2B5
2B6
GND
2B7
2B8
2OE
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74GTLPH1645
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D – OCTOBER 1999 – REVISED SEPTEMBER 2001
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS V CC. The Ioff
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly
terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This
improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies.
High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC
input voltage between GND and VCC adjusts the B-port output rise and fall times. This allows the designer to
optimize system data-transfer rate and signal integrity to the backplane load.
Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However , to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
terminal assignments
123456
A1A2 1A1 1DIR 1OE 1B1 1B2
B1A4 1A3 GND GND 1B3 1B4
C1A5 GND VCC VCC GND 1B5
D1A7 1A6 GND GND 1B6 1B7
EGND 1A8 1B8 BIAS VCC
FERC 2A1 2B1 VREF
G2A2 2A3 GND GND 2B3 2B2
H2A4 GND VCC VCC GND 2B4
J2A5 2A6 GND GND 2B6 2B5
K2A7 2A8 2DIR 2OE 2B8 2B7
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
TSSOP – DGG Tape and reel SN74GTLPH1645DGGR GTLPH1645
–40°C to 85°CTVSOP – DGV Tape and reel SN74GTLPH1645DGVR GL45
VFBGA – GQL Tape and reel SN74GTLPH1645GQLR GL45
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
GQL PACKAGE
(TOP VIEW)
A
B
C
D
E
F
G
H
J
K
123456
SN74GTLPH1645
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D – OCTOBER 1999 – REVISED SEPTEMBER 2001
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional description
The SN74GTLPH1645 is a high-drive (100 mA), 16-bit bus transceiver partitioned as two 8-bit segments and
is designed for asynchronous communication between data buses. The device transmits data from the A port
to the B port or from the B port to the A port, depending on the logic level at the direction-control (DIR) input.
OE can be used to disable the device so the buses are effectively isolated. Data polarity is noninverting.
For A-to-B data flow, when OE is low and DIR is high, the B outputs take on the logic value of the A inputs. When
OE is high, the outputs are in the high-impedance state.
The data flow for B to A is similar to A to B, except OE and DIR are low.
Function Tables
OUTPUT CONTROL
INPUTS
OUTPUT
MODE
OE DIR
OUTPUT
MODE
H X Z Isolation
L L B data to A port
True trans
p
arent
L H A data to B port
True
transparent
B-PORT EDGE-RATE CONTROL (ERC)
INPUT ERC OUTPUT
LOGIC
LEVEL NOMINAL
VOLTAGE B-PORT
EDGE RATE
L GND Slow
HVCC Fast
SN74GTLPH1645
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D – OCTOBER 1999 – REVISED SEPTEMBER 2001
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1DIR
1OE
1A1 1B1
1
2
56
55
VREF
42
2DIR
2OE
2A1 2B1
To Seven Other Channels
28
16
29
41
ERC 15
To Seven Other Channels
Pin numbers shown are for the DGG and DGV packages.
SN74GTLPH1645
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D – OCTOBER 1999 – REVISED SEPTEMBER 2001
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC and BIAS VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1): A port, ERC, and control inputs –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . .
B port and VREF –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1): A port –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: A port 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port 200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any A port output in the high state, IO (see Note 2) 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): DGG package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 48°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GQL package 42°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
SN74GTLPH1645
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D – OCTOBER 1999 – REVISED SEPTEMBER 2001
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Notes 4 through 7)
MIN NOM MAX UNIT
VCC,
BIAS VCC Supply voltage 3.15 3.3 3.45 V
VTT
Termination voltage
GTL 1.14 1.2 1.26
V
V
TT
Termination
voltage
GTLP 1.35 1.5 1.65
V
VREF
Reference voltage
GTL 0.74 0.8 0.87
V
V
REF
Reference
voltage
GTLP 0.87 1 1.1
V
VI
In
p
ut voltage
B port VTT
V
V
I
Input
voltage
Except B port VCC 5.5
V
B port VREF+0.05
VIH High-level input voltage ERC VCC–0.6 VCC 5.5 V
Except B port and ERC 2
B port VREF–0.05
VIL Low-level input voltage ERC GND 0.6 V
Except B port and ERC 0.8
IIK Input clamp current –18 mA
IOH High-level output current A port –24 mA
IOL
Low level out
p
ut current
A port 24
mA
I
OL
Low
-
level
output
current
B port 100
mA
∆t/∆vInput transition rise or fall rate Outputs enabled 10 ns/V
∆t/∆VCC Power-up ramp rate 20 µs/V
TAOperating free-air temperature –40 85 °C
NOTES: 4. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and
VCC = 3.3 V last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs
can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection
sequence is acceptable, but generally, GND is connected first.
6. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded.
7. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction
and is activated when VTT > 0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to
minimize current drain.
SN74GTLPH1645
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D – OCTOBER 1999 – REVISED SEPTEMBER 2001
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range for GTLP
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK VCC = 3.15 V, II = –18 mA –1.2 V
VCC = 3.15 V to 3.45 V, IOH = –100 µA VCC–0.2
VOH A port
VCC = 3 15 V
IOH = –12 mA 2.4 V
V
CC =
3
.
15
V
IOH = –24 mA 2
VCC = 3.15 V to 3.45 V, IOL = 100 µA 0.2
A port
VCC = 3 15 V
IOL = 12 mA 0.4
VOL
V
CC =
3
.
15
V
IOL = 24 mA 0.5
V
V
OL IOL = 10 mA 0.2
V
B port VCC = 3.15 V IOL = 64 mA 0.4
IOL = 100 mA 0.55
IIControl inputs VCC = 3.45 V, VI = 0 or 5.5 V ±10 µA
I‡
A port
VCC = 3 45 V
VO = VCC 10
µA
I
OZH
‡
B port
V
CC =
3
.
45
V
VO = 1.5 V 10 µ
A
IOZL‡A and B ports VCC = 3.45 V, VO = GND –10 µA
IBHL§A port VCC = 3.15 V, VI = 0.8 V 75 µA
IBHH¶A port VCC = 3.15 V, VI = 2 V –75 µA
IBHLO#A port VCC = 3.45 V, VI = 0 to VCC 500 µA
IBHHO|| A port VCC = 3.45 V, VI = 0 to VCC –500 µA
VCC
=
3.45 V, IO
=
0,
Outputs high 40
ICC A or B port
VCC
=
3
.
45
V
,
IO
=
0
,
VI (A or control input) = VCC or GND, Outputs low 40 mA
VI (B port) = VTT or GND Outputs disabled 40
∆ICC
k
VCC = 3.45 V, One A-port or control input at VCC – 0.6 V,
Other A or control inputs at VCC or GND 1.5 mA
CiControl inputs VI = 3.15 V or 0 4 5 pF
Ci
A port VO = 3.15 V or 0 6.5 7.5 p
F
C
io B port VO = 1.5 V or 0 9.5 11
pF
†All typical values are at VCC = 3.3 V, TA = 25°C.
‡For I/O ports, the parameters IOZH and IOZL include the input leakage current.
§The bus-hold circuit can sink at least the minimum low sustaining current at VILmax. IBHL should be measured after lowering VIN to GND and
then raising it to VILmax.
¶The bus-hold circuit can source at least the minimum high sustaining current at VIHmin. IBHH should be measured after raising VIN to VCC and
then lowering it to VIHmin.
#An external driver must source at least IBHLO to switch this node from low to high.
|| An external driver must sink at least IBHHO to switch this node from high to low.
k
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
hot-insertion specifications for A port over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN MAX UNIT
Ioff VCC = 0, BIAS VCC = 0, VI or VO = 0 to 5.5 V 10 µA
IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = 0 ±30 µA
IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = 0 ±30 µA
SN74GTLPH1645
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D – OCTOBER 1999 – REVISED SEPTEMBER 2001
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
live-insertion specifications for B port over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN MAX UNIT
Ioff VCC = 0, BIAS VCC = 0, VI or VO = 0 to 1.5 V 10 µA
IOZPU VCC = 0 to 1.5 V, BIAS VCC = 0, VO = 0.5 V to 1.5 V, OE = 0 ±30 µA
IOZPD VCC = 1.5 V to 0, BIAS VCC = 0, VO = 0.5 V to 1.5 V, OE = 0 ±30 µA
ICC (BIAS VCC)
VCC = 0 to 3.15 V
BIAS VCC =315Vto345V
VO(B
p
ort)=0to15V
5 mA
I
CC
(BIAS
V
CC
)
VCC = 3.15 V to 3.45 V
BIAS
V
CC =
3
.
15
V
to
3
.
45
V
,
V
O
(B
port)
=
0
to
1
.
5
V
10 µA
VOVCC = 0, BIAS VCC = 3.3 V, IO = 0 0.95 1.05 V
IOVCC = 0, BIAS VCC = 3.15 V to 3.45 V, VO (B port) = 0.6 V –1µA
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1)
PARAMETER FROM
(INPUT) TO
(OUTPUT) EDGE RATE†MIN TYP‡MAX UNIT
tPLH
A
B
Slow
3.9 7.2
ns
tPHL
A
B
Slow
3.1 8.4
ns
tPLH
A
B
Fast
2.6 5.7
ns
tPHL
A
B
Fast
2.1 5.8
ns
ten
OE
B
Slow
4.1 7.3
ns
tdis
OE
B
Slow
4 9.4
ns
ten
OE
B
Fast
2.9 5.9
ns
tdis
OE
B
Fast
4 6.9
ns
t
Rise time B out
p
uts (20% to 80%)
Slow 3
ns
t
r
Rise
time
,
B
outputs
(20%
to
80%)
Fast 1.5
ns
tf
Fall time B out
p
uts (80% to 20%)
Slow 4
ns
t
f
Fall
time
,
B
outputs
(80%
to
20%)
Fast 2.5
ns
tPLH
B
A
0.5 6.7
ns
tPHL
B
A
—1.2 4.5
ns
ten
OE
A
1.1 6.3
ns
tdis
OE
A
—1.7 5.1
ns
†Slow (ERC = GND) and Fast (ERC = VCC)
‡All typical values are at VCC = 3.3 V, TA = 25°C.
SN74GTLPH1645
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D – OCTOBER 1999 – REVISED SEPTEMBER 2001
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
S1 Open
GND
500 Ω
500 Ω
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
6 V
GND
tPLH tPHL
Output
Control
Output
W aveform 1
S1 at 6 V
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
3 V
0 V
VOH
VOL
0 V
VOL + 0.3 V
VOH – 0.3 V
≈0 V
Input
3 V
3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(A port to B port)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(A port)
Output
1.5 V
Test
Point
CL = 30 pF
(see Note A)
From Output
Under Test
12.5 Ω
LOAD CIRCUIT FOR B OUTPUTS
0 V
VOH
VOL
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to A port)
Output
1.5 V
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω, tr ≈2 ns, tf ≈2 ns.
D. The outputs are measured one at a time with one transition per measurement.
6 V
tPLH tPHL
1.5 V 1.5 V
1.5 V
1.5 V
1.5 V
1.5 V 1.5 V
1.5 V
1 V 1 V
1 V 1 V
Figure 1. Load Circuits and Voltage Waveforms
SN74GTLPH1645
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D – OCTOBER 1999 – REVISED SEPTEMBER 2001
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
The preceding switching characteristics table shows the switching characteristics of the device into a lumped load
(Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation
is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a resistor inductance
capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum performance in this RLC
circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC
load, to help the designer better understand the performance of the GTLP device in this typical backplane. See
www.ti.com/sc/gtlp for more information.
Drvr
1.5 V
.25”1”
1”1”
1.5 V
1”1”
1”.25”
Rcvr Rcvr Rcvr
Figure 2. High-Drive Test Backplane
Slot 1 Slot 2 Slot 19 Slot 20
Conn. Conn. Conn. Conn.
ZO = 50 Ω
22Ω
22Ω
From Output
Under Test Test
Point
1.5 V
CL = 18 pF
11 Ω
LL = 14 nH
Figure 3. High-Drive RLC Network
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 3)
PARAMETER FROM
(INPUT) TO
(OUTPUT) EDGE RATE†TYP‡UNIT
tPLH
A
B
Slow
4.9
ns
tPHL
A
B
Slow
4.9
ns
tPLH
A
B
Fast
3.7
ns
tPHL
A
B
Fast
3.7
ns
ten
OE
B
Slow
5.1
ns
tdis
OE
B
Slow
5.4
ns
ten
OE
B
Fast
4.1
ns
tdis
OE
B
Fast
4.1
ns
t
Rise time B out
p
uts (20% to 80%)
Slow 2
ns
t
r
Rise
time
,
B
outputs
(20%
to
80%)
Fast 1.2
ns
tf
Fall time B out
p
uts (80% to 20%)
Slow 2.5
ns
t
f
Fall
time
,
B
outputs
(80%
to
20%)
Fast 1.8
ns
†Slow (ERC = GND) and Fast (ERC = VCC)
‡All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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