1
2
3
4
16
15
14
13
PVDD2
BOOT2
SW2
PGND2
PVDD1
BOOT1
SW1
PGND1
TPS54290
5
6
7
12
11
10
BP
GND
FB2
EN1
EN2
FB1
VOUT1
VIN
UDG-09130
GND
8 9COMP1 COMP2
VOUT2
TPS54290, TPS54291, TPS54292
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SLUS973 –OCTOBER 2009
1.5-A/2.5-A Dual, Fully-Synchronous Buck Converter With Integrated MOSFET
Check for Samples :TPS54290 TPS54291 TPS54292
1FEATURES APPLICATIONS
• Set Top Box
2• 4.5 V to 18 V Input Range • Digital TV
• Output Voltage Range 0.8 V to DMAX × VIN • Power for DSP
• Fully Integrated Dual Buck, 1.5 A/2.5 A • Consumer Electronics
• Three Fixed Switching Frequency Versions:
– TPS54290 – 300 kHz DESCRIPTION
– TPS54291 – 600 kHz TPS54290/1/2 is a dual output fully synchronous buck
– TPS54292 – 1.2 MHz converter capable of supporting applications with a
• Integrated UVLO minimal number of external components. It operates
from a 4.5 V to 18 V input supply voltage, and
• 0.8 VREF With 1% Accuracy (0°C to 85°C) supports output voltages as low as 0.8 V and as high
• Internal Soft-Start as 90% of the input voltage.
– TPS54290 – 5.2 ms Both high-side and low-side MOSFETs are integrated
– TPS54291 – 2.6 ms to provide fully synchronous conversion with higher
– TPS54292 – 1.3 ms efficiency. Channel1 can provide up to 1.5 A of
continuous current, meanwhile, Channel2 supports
• Dual PWM Outputs 180° Out-of-Phase up to 2.5 A.
• Dedicated Enable for Each Channel Current mode control simplifies the compensation.
• Current Mode Control for Simplified The external compensation adds flexibility for the
Compensation user to choose different type of output capacitors.
• External Compensation 180° out-of-phase operation reduces the ripple
• Pulse-by-Pulse Overcurrent Protection, current through the input capacitor, providing the
2.2 A/3.8 A Overcurrent Limit benefit of reducing input capacitance, alleviating EMI
• Integrated Bootstrap Switch and increasing capacitor life.
• Thermal Shutdown Protection at 145°C
• 16-Pin PowerPAD™ HTSSOP Package
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS54290, TPS54291, TPS54292
SLUS973 –OCTOBER 2009
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
ORDERABLE OPERATING PACKING PACKING
TJDEVICE FREQUENCY PACKAGE MEDIA QUANTITY
NUMBER (kHz)
TPS54290PWP Tube 90
300
TPS54290PWPR Tape and Reel 2500
TPS54291PWP Tube 90
16-Pin
–40°C to 145°C 600 HTTSOP
TPS54291PWPR Tape and Reel 2500
TPS54292PWP Tube 90
1200
TPS54292PWPR Tape and Reel 2500
ABSOLUTE MAXIMUM RATINGS (operating in a typical application circuit)
over operating free-air temperature range, all voltages are with respect to GND (unless otherwise noted)
VALUE UNIT
PVDD1, PVDD2, EN1, EN2 –0.3 to 20
SW1, SW2 –1 to 20
BOOT1, BOOT2 –0.3 to SW+7 V
SW1, SW2 transient (< 50 ns) –3 to 20
BP 7
FB1, FB2 –0.3 to 3
Operating junction temperature –40 to 145
Storage junction temperature –55 to 155 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260
PACKAGE DISSIPATION RATINGS(1) (2) (3)
THERMAL IMPEDANCE TA= 25°C TA= 85°C
PACKAGE JUNCTION TO THERMAL PAD POWER RATING POWER RATING
16 Pin HTSSOP (PWP) 2.07°/W 1.6 W 1.0 W
(1) For more information on the PWP package, refer to TI technical brief (SLMA002A)
(2) TI device packages are modeled and tested for thermal performance using PWB designs outlined in JEDEC standards JESD 51-3 and
JESD 51-7.
(3) For Application information see Power Derating section
RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT
VDD Input voltage 4.5 18 V
TJJunction temperature –40 125 °C
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
PARAMETER MIN UNIT
Human Body Model 2k V
CDM 1.5k V
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SLUS973 –OCTOBER 2009
ELECTRICAL CHARACTERISTICS
TJ= –40°C to 125°C, PVDD1 and 2 = 12V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY
PVDD1, PVDD2 Input voltage range 4.5 18 V
IDDSDN Shutdown current EN1=EN2 = PVDD2 (4.5-18V) 80 160 µA
IDDQQuiescent, non-switching FB1 = FB2 = 1 V, Outputs Off 1.65 3.00 mA
IDDSW Quiescent, while switching FB1 = FB2 = 0.75V, measured at BP 10 mA
UVLO Minimum turn-on voltage PVDD2 only 3.8 4.1 4.4 V
UVLOHYS Hysteresis 460 600 mV
Time from startup to soft start CBP=10µF, EN1 and EN2 go low
tstart (1) (2) 1.5 ms
begin simultaneously
ENABLE (ACTIVE LOW)
Enable threshold voltage 0.9 1.2 1.5 V
VENx Hysteresis 70 mV
IENx Enable pull-up current 10 µA
Time from enable to soft-start
tENx (1) Other enable pin = GND 10 µs
begin
BP REGULATOR
BP Regulator voltage 8 V ≤VPVDD2 ≤18 V 5.0 5.2 5.6 V
BPLDO Dropout voltage VPVDD2 = 4.5 V 400 mV
IBPS Regulator short current 4.5 V ≤VPVDD2 ≤18 V 25 mA
OSCILLATOR
TPS54290 260 300 360 kHz
fSW Oscillator frequency TPS54291 520 600 720
TPS54292 1040 1200 1440 kHz
tDEAD (1) Clock dead time 140 ns
gMTRANSCONDUCTANCE AMPLIFIER AND VOLTAGE REFERENCE (Applies to both channels)
0°C < TJ< 85°C 792 800 808 mV
VFB Feedback input voltage –40ºC < TJ< 125°C 786 800 812 mV
IFB Feedback Input bias current VFB=0.8 V 5 50 nA
gM(1) Transconductance 200 325 450 µS
Error amplifier source current 15 30 40 µA
ISOURCE VFB1=VFB2=0.7 V, VCOMP=0 V
capability
Error amplifier sink current
ISINK VFB1=VFB2=0.9 V, VCOMP=2 V 15 30 40 µA
capability
SOFT-START (Applies to both channels)
TPS54290 0 V ≤VFB ≤0.8 V 4.0 5.2 6.0
tSS Soft-start time TPS54291 2.0 2.6 3.0 ms
TPS54292 1.0 1.3 1.6
OVERCURRENT PROTECTION
ICL1 Current limit CH1 1.8 2.2 2.6 A
ICL2 Current limit CH2 3.2 3.8 4.6 A
TPS54290 30 ms
THICCUP (1) Hiccup timeout TPS54291 16
TPS54292 8
tONOC (1) Minimum overcurrent pulse 150 200 ns
(1) Specified by design. Not tested in production.
(2) When both outputs are started simultaneously, a 20-mA current source charges the BP capacitor. Faster times are possible with a lower
BP capacitor value. See Input UVLO and Startup.
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SLUS973 –OCTOBER 2009
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ELECTRICAL CHARACTERISTICS (continued)
TJ= –40°C to 125°C, PVDD1 and 2 = 12V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BOOTSTRAP (Applied to both channels)
RBOOT Bootstrap switch resistance R(BP to BOOT), I external = 10 mA 33 Ω
PGOOD
VUV Feedback voltage limit for PGOOD 660 730 mV
VPG-HYST (3) PGOOD hysteresis voltage on FB 40 mV
OUTPUT STAGE (Applied to both channels)
On resistance of high-side FET
RDS(on1)(HS)(3) 170 265 mΩ
and bondwire on CH1
On resistance of high-side FET
RDS(on2)(HS)(3) 120 190 mΩ
and bondwire on CH2
On resistance of low-side FET and mΩ
RDS(on1)(LS)(3) 120 190
bondwire on CH1
On resistance of low-side FET and
RDS(on2)(LS)(3) 90 150 mΩ
bondwire on CH2
tON_MIN (3) Miimum controllable pulse width 150 ns
Minimum duty VFB = 0.9 V 0%
cycle HDRV off to LDRV on 20 ns
tDEAD (3) Output driver dead time LDRV off to HDRV on 20 ns
TPS54290 90% 96%
DMAX Maximum duty cycle TPS54291 85% 91%
TPS54292 78% 82%
THERMAL SHUTDOWN
TSD (3) Shutdown temperature 145 °C
TSD_HYS (3) Hysteresis 20 °C
(3) Specified by design. Not tested in production.
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–40
1.55
1.50
20
–25 35–10 505 65 95 110 12580
1.65
1.60
1.75
1.70
IDDQ – Quiescent Current – mA
TJ– Junction Temperature – °C
Non-Switching
40
0
–40 20–25 35–10 505 65 95 110 12580
TJ– Junction Temperature – °C
60
20
120
80
140
100
VIN = 4.5 V
VIN = 12 V
VIN = 18 V
ISD – Shutdown Current – mA
3.6
–40 20–25 35–10 505 65 95 110 12580
TJ– Junction Temperature – °C
3.7
3.8
4.1
3.9
4.2
4.0
VUVLO – Undervoltage Lockout Threshold Voltage – V
UVLO OFF
UVLO ON
–40
1.14
1.12
20–25 35–10 505 65 95 110 12580
1.20
1.18
1.26
1.24
VEN – Enable Voltage Threshold – V
TJ– Junction Temperature – °C
Enable ON
Enable OFF
1.16
1.22
TPS54290, TPS54291, TPS54292
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SLUS973 –OCTOBER 2009
TYPICAL PERFORMANCE CHARACTERISTICS
QUIESCENT CURRENT SHUTDOWN CURRENT
vs vs
TEMPERATURE TEMPERATURE
Figure 1. Figure 2.
UVLO TURN-ON AND TURN-OFF THRESHOLDS ENx TURN ON AND OFF THRESHOLD
vs vs
TEMPERATURE TEMPERATURE
Figure 3. Figure 4.
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0
–40 20–25 35–10 505 65 95 110 12580
TJ– Junction Temperature – °C
0.2
0.4
1.2
0.6
1.4
0.8
1.0
fSW = 600 kHz
fSW = 1.2 MHz
fSW = 300 kHz
fSW – Switching Frequency – MHz
2
0
–40 20–25 35–10 505 65 95 110 12580
TJ– Junction Temperature – °C
3
1
5
6
4
tSS – Soft-Start Time – ms
fSW = 300 kHz
fSW = 600 kHz
fSW = 1.2 MHz
2.00
–40 20–25 35–10 505 65 95 110 12580
TJ– Junction Temperature – °C
2.25
2.75
4.25
3.25
4.50
3.75
Channel1
Channel2
IILIMx – Current Limit – A
2.50
3.00
3.50
4.00
–40
792
788
20–25 35–10 505 65 95 110 12580
800
796
808
804
VFB – Feedback Voltage – mV
TJ– Junction Temperature – °C
790
798
794
806
802
TPS54290, TPS54291, TPS54292
SLUS973 –OCTOBER 2009
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
SOFT START TIME OSCILLATOR FREQUENCY
vs vs
TEMPERATURE TEMPERATURE
Figure 5. Figure 6.
FEEDBACK VOLTAGE CURRENT LIMIT
vs vs
TEMPERATURE TEMPERATURE
Figure 7. Figure 8.
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–40
5.00
20–25 35–10 505 65 95 110 12580
5.10
5.20
VBP – BP Regulation Voltage – V
TJ– Junction Temperature – °C
5.05
5.15
VVDD = 12 V
1
-1
–40 20–25 35–10 505 65 95 110 12580
TJ– Junction Temperature – °C
3
0
8
5
9
7
ISW(off) – Switch-Node Current – mA
4
2
6
TPS54290, TPS54291, TPS54292
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SLUS973 –OCTOBER 2009
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
BP VOLTAGE SW NODE LEAKAGE CURRENT
vs vs
TEMPERARURE TEMPERATURE
Figure 9. Figure 10.
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16
15
PVDD2
BOOT2
14
13
12
11
SW2
PGND2
BP
GND
10
9
FB2
COMP2
Thermal Pad
(bottom side)
HTSSOP (PWP)
(Top View)
1
2
3
4
PVDD1
BOOT1
SW1
PGND1
5
6
7
EN1
EN2
FB1
8COMP1
TPS54290, TPS54291, TPS54292
SLUS973 –OCTOBER 2009
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DEVICE INFORMATION
PIN FUNCTIONS
PIN I/O DESCRIPTION
NAME NO.
Input supply to the high-side gate driver for Output1. Connect a 22 nF to 68 nF capacitor from this pin to
SW1. This capacitor is charged from the BP pin voltage through an internal switch. The switch is turned ON
BOOT1 2 I during the off time of the converter. To slow down the turn ON of the internal FET, a small resistor (2 Ωto 5
Ω) may be placed in series with the bootstrap capacitor.
Input supply to the high-side gate driver for Output2. Connect a 22 nF to 68 nF capacitor from this pin to
SW2. This capacitor is charged from the BP pin voltage through an internal switch. The switch is turned ON
BOOT2 15 I during the off time of the converter. To slow down the turn ON of the internal FET, a small resistor (2 Ωto 5
Ω) may be placed in series with the bootstrap capacitor.
Regulated voltage to charge the bootstrap capacitors. Bypass this pin to GND with a low-ESR 4.7-µF (10-µF
BP 12 – preferred) ceramic capacitor.
Active-low enable input for Output1. If the voltage on this pin is greater than 1.5 V, Output1 is disabled
(high-side switch is OFF). A voltage of less than 0.9 V enables Output1 and allow soft start of Output1 to
EN1 5 I begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND to bypass
the enable function.
Active-low enable input for Output2. If the voltage on this pin is greater than 1.5 V, Output2 is disabled
(high-side switch is OFF). A voltage of less than 0.9 V enables Output2 and allow soft-start of Output2 to
EN2 6 I begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND to bypass
the enable function.
FB1 7 I Voltage feedback pin for Outputx. The internal transconductance error amplifier adjusts the PWM for Outputx
to regulate the voltage at this pin to the internal 0.8 V reference. A series resistor divider from Outputx to
FB2 10 I ground, with the center connection tied to this pin, determines the value of the regulated output voltage.
COMP1 8 O Output of the transconductance (gM) amplifier. A R-C compensation network is connected from COMPx to
GND.
COMP2 9 O
PGND1 4 – Power ground for Outputx. It is separated from GND to prevent the switching noise coupled to the internal
logic circuits.
PGND2 13 –
GND 11 – Analog ground pin for the device.
Power input to the Output1 high-side MOSFET only. This pin should be locally bypassed to PGND1 with a
PVDD1 1 I low ESR ceramic capacitor of 10 µF or greater. PVDD1 and PVDD2 could be tied externally together.
The PVDD2 pin provides power to the device control circuitry, provides the pull-up for the EN1 and EN2 pins
and provides power to the Output2 high-side MOSFET. This pin should be locally bypassed to PGND2 with
PVDD2 16 I a low ESR ceramic capacitor of 10 µF or greater. The UVLO function monitors PVDD2 and enables the
device when PVDD2 is greater than 4.2 V.
SW1 3 O Source (switching) output for Output1 PWM.
SW2 14 O Source (switching) output for Output2 PWM.
Thermal Pad – This pad must be tied externally to a ground plane.
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11GND
UDG-09124
5EN1
6EN2
10 mA
(max)
10 mA
(max)
Internal
Control
Output
Undervoltage
Detect
FB1
FB2
TSD
SD1
SD2
UVLO 2.4 MHz
Oscilator
Divide by
2/4/8
Ramp
Gen 1
Ramp
Gen 2
CLK1
CLK2
f(ISLOPE1)
f(ISLOPE2)
7FB1
+
Soft Start
1
0.8 VREF
SD1
8COMP1
10FB2
+
Soft Start
2
0.8 VREF
SD2
9COMP2
f(IDRAIN1) + DC(ofst)
+
S Q
QR
R
+
Current
Comparator
BP 2
1
3
Anti-Cross
Conduction
BP
CLK1
BOOT1
PVDD1
SW1
f(IDRAIN1)
f(IMAX1)
Overcurrent Comp
f(ISLOPE1)
IDRAIN1
FET
Switch
CLK1
4 PGND1
f(IDRAIN2) + DC(ofst)
+
S Q
QR
R
+
Current
Comparator
BP 15
16
14
Anti-Cross
Conduction
BP
CLK2
BOOT2
PVDD2
SW2
f(IDRAIN2)
f(IMAX2)
Overcurrent Comp
f(ISLOPE2)
IDRAIN2
FET
Switch
CLK2
13 PGND2
12BP 5.25-V
Regulator References
PVDD2
FET
Switch
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SLUS973 –OCTOBER 2009
BLOCK DIAGRAM
Figure 11. Block Diagram
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( ) ( )
TH ENx
START
IN ENx
V I R
t R C ln s
V 2 I R
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- ´
ç ÷
= - ´ ´ ç ÷
- ´ ´
è ø
uuuuur
TPS54290, TPS54291, TPS54292
SLUS973 –OCTOBER 2009
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APPLICATION INFORMATION
FUNCTIONAL DESCRIPTION
The TPS54290/1/2 is a dual output fully synchronous buck converter. Each PWM channel contains an error
amplifier, current mode pulse width modulator (PWM), switching and rectifying MOSFETs, enable, and fault
protection circuitry. Common to the two channels are the internal voltage regulator, voltage reference, and clock
oscillator.
VOLTAGE REFERENCE
The band gap cell common to both outputs, trimmed to 800 mV. The reference voltage is 1% accurate in the
temperature range from 0°C to 85°C.
OSCILLATOR
The oscillator frequency is internally fixed at 2.4 MHz which is divided by 8/4/2 to generate the ramps for
TPS54290/1/2 respectively. The two outputs are internally configured to operate on alternating switch cycles (i.e.,
180° out-of-phase).
INPUT UVLO AND STARTUP
When the voltage at the PVDD2 pin is less than 4.4 V, a portion of the internal bias circuitry is operational, and
all other functions are held OFF. All of the internal MOSFETs are also held OFF. When the PVDD2 voltage rises
above the UVLO turn on threshold, the state of the enable pins determines the remainder of the internal startup
sequence. If either output is enabled (ENx pulled low), the BP regulator turns on, charging the BP capacitor with
a 20 mA current. When the BP pin is greater than 4 V, PWM is enabled and soft-start commences.
Note that the internal regulator and control circuitry are powered from PVDD2. The voltage on PVDD1 may be
higher or lower than PVDD2.
ENABLE AND TIMED TURN ON OF THE OUTPUTS
Each output has a dedicated (active low) enable pin. If left floating, an internal current source pulls the pin to
PVDD2. By grounding, or by pulling the ENx pin to below approximately 1.25 V with an external circuit, the
associated output is enabled and soft-start is initiated.
If both enable pins are left in the “high” state, the device operates in a shutdown mode, where the BP regulator is
shut down and minimal house keeping functions are active. The total standby current from both PVDD pins is
80 µA at 12 V input supply.
An R-C connect to an ENx pin may be used to delay the turn on of the associated output after power is applied
to PVDDx (see Figure 12). After power is applied to PVDD2, the voltage on the ENx pin slowly decays towards
ground. Once the voltage decays to approximately 1.25 V, then the output is enabled and the startup sequence
begins. If it is desired to enable the outputs of the device immediately upon the application of power to the
PVDD2 pin, then omit these two components and tie the ENx pin to GND directly.
If an R-C circuit is used to delay the turn on of the output, the resistor value must be an order of magnitude less
than 1.25 V/10 µA or 120 kΩ. A suggested value is 51 kΩ. This allows the ENx voltage to decay below the 1.25
V threshold while the 10-µA bias current flows.
The time to start (after the application of PVDD2) is
(1)
where
• R and C are the timing components
• VTH is the 1.25 V enable threshold voltage
• IEN is the 10-µA maximum enable pin biasing current
Figure 12 and Figure 13 illustrate startup delay with an R-C filter on the enable pin(s).
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TPS5429x
ENxC
R
+
PVDD2
PVDDx
10 mA (max)
1.25 V
UDG-09125
X
Time
tDELAY
0tDELAY + tSS
PVDDx
ENxB
VOUTx
1.25-V
Threshold
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SLUS973 –OCTOBER 2009
Figure 12. Startup Delay Schematic Figure 13. Startup Delay Timing Diagram
NOTE
If delayed output voltage startup is not necessary, simply connect EN1 and EN2 to
GND. This allows the outputs to “start” immediately on the valid application of PVDD2.
If ENx is allowed to go “high” after the outputx has been in regulation, the upper and
lower MOSFETs shut off, and the output decays at a rate determined by the output
capacitor and the load.
SOFT START
Each output has a dedicated soft start circuit. The soft start voltage is an internal digital reference ramp to one of
the two non-inverting inputs of the error amplifier. The other input is the internal precise 0.8-V reference. The
total ramp time for the FB voltage to charge from 0 V to 0.8 V is about 5.2 ms, 2.6 ms and 1.3 ms for
TPS54190/1/2 respectively. During a soft start interval, the TPS5429x output slowly increases the voltage to the
non-inverting input of the error amplifier. In this way, the output voltage slowly ramps up until the voltage on the
non-inverting input to the error amplifier reaches the internal 0.8V reference voltage. At that time, the voltage at
the non-inverting input to the error amplifier remains at the reference voltage.
During the soft-start interval, pulse-by-pulse current limiting is in effect. If an over-current pulse is detected, six
PWM pulses is skipped to allow the inductor current to decay before another PWM pulse is applied (See Output
Overload Protection). There is no pulse skipping if a current limit pulse is not detected.
If the rate of rise of the input voltage (PVDDx) is such that the input voltage is too low to support the desired
regulation voltage by the time soft-start has completed, then the output UV circuit may trip and cause a hiccup in
the output voltage. In this case, use a timed delay startup from the ENx pin to delay the startup of the output until
the PVDDx voltage has the capability of supporting the desired regulation voltage.
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1
2
3
4
16
15
14
13
PVDD2
BOOT2
SW2
PGND2
PVDD1
BOOT1
SW1
PGND1
TPS54290
5
6
7
12
11
10
BP
GND
FB2
EN1
EN2
FB1
R1
VOUT1
R2
UDG-09131
8 9COMP1 COMP2
IN OUT
OUT
V V
L
I
-
=
D
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SLUS973 –OCTOBER 2009
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OUTPUT VOLTAGE REGULATION
The regulation output voltage is determined by a resistor divider connecting the output node, the FBx pin, and
GND (Figure 14). The value of the output voltage is shown in Equation 2.
(2)
where
• VREF is the internal 0.8-V reference voltage
Figure 14. Feedback Network for Channel1
INDUCTOR SELECTION
Equation 3 calculates the inductance value so that the output ripple current falls from 20% to 40% of the full load
current.
(3)
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SS RIPPLE
OUT(max) LOAD
OUT
tI
C ILIM I
V 2
æ ö
æ ö
= ´ - -
ç ÷
ç ÷
è ø
è ø
FB
11.5 kW
+
Error
Amplifier
0.8 VREF
BP
GND
+Offset f(IDRAIN)
PWM to
Switch
ISLOPE
ICOMP
UDG-09128
ICOMP – ISLOPE
x 2
CCOMP
RCOMP
COMP
TPS54290, TPS54291, TPS54292
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SLUS973 –OCTOBER 2009
MAXIMUM OUTPUT CAPACITANCE
With internal pulse-by-pulse current limiting and a fixed soft-start time, there is a maximum output capacitance
which may be used before startup problems begin to occur. If the output capacitance is large enough so that the
device enters a current-limit protection mode during startup, then there is a possibility that the output never
reaches regulation. Instead, the TPS5429x simply shuts down and attempts a restart as if the output were
short-circuited to ground. The maximum output capacitance (including bypass capacitance distributed at the
load) is given by
(4)
where
• tSS is the soft start time
• ILIM is the current limit level
FEEDBACK LOOP COMPENSATION
In the feedback signal path, the output voltage setting divider is followed by an internal gM-type error amplifier
with a typical transconductance of 325 µS. An external series connected R-C circuit from the gMamplifier output
(COMPx pin) to ground serves as the compensation network for the converter. The signal from the error amplifier
output is then buffered and combined with a slope compensation signal before it is mirrored to be referenced to
the SW node. Here, it is compared with the current feedback signal to create a pulse-width-modulated (PWM)
signal-fed to drive the upper MOSFET switch. A simplified equivalent circuit of the signal control path is depicted
in Figure 15.
NOTE
Noise coupling from the SWx node to internal circuitry of BOOTx may impact narrow
pulse width operation, especially at load currents less than 1 A.
Figure 15. Feedback Loop Equivalent Circuit
A more conventional small-signal equivalent block diagram is shown in Figure 16. Here, the full closed-loop
signal path is shown. Because the TPS5429x contains internal slope compensation, the external L-C filter must
be selected appropriately so that the resulting control loop meets criteria for stability.
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VREF
VIN
VOUT
Compensation
Network
+
_
Modulator
Filter
Current
Feedback
Network
+
_
VC
( ) ( )
ON
SW
TPS5429 x
K t IN OUT
6
f
FM
V V
19.7 e 95 10
L
´-
=æ ö
æ ö
-
ç ÷
´ + ´ ´ ç ÷
ç ÷
ç ÷
è ø
è ø
( )
4
IN
C6
IN
LOAD
V FM 2 10
f
V FM 95 10
1
2 R
-
-
´ ´ ´
=æ ö
æ ö
´ ´ ´
ç ÷
ç ÷
+
ç ÷
ç ÷
´
ç ÷
ç ÷
è ø
è ø
( )
( )
C
EA
CO LOAD OUT
f
K 20 log 1 2 f 2 R C
æ ö
ç ÷
= - ´ ç ÷
+ ´ p´ ´ ´ ´
è ø
TPS54290, TPS54291, TPS54292
SLUS973 –OCTOBER 2009
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Figure 16. Small Signal Equivalent Block Diagram
To determine the components necessary for compensating the feedback loop, the controller frequency response
characteristics must be understood and the desired crossover frequency selected. The best results are obtained
if 10% of the switching frequency is used as this closed loop crossover frequency. In some cases, up to 20% of
the switching frequency is also possible.
With the output filter components selected, the next step is to calculate the DC gain of the modulator. For
TPS5429x:
(5)
where
• K = 5.6 ×105for TPS54290
• K = 1.5 × 106for TPS54291
• K = 3.6 × 106for TPS54292
The overall DC gain of the converter control-to-output transfer function is approximated Equation 6.
(6)
The next step is to find the desired gain of the error amplifier at the desired crossover frequency. Assuming a
single-pole roll-off, us Equation 6 to evaluate the following expression at the desired crossover frequency.
(7)
where
• ƒCO is the desired crossover frequency
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R1
VOUT1
R2
C1
(Optional)
1
2
3
4
16
15
14
13
PVDD2
BOOT2
SW2
PGND2
PVDD1
BOOT1
SW1
PGND1
TPS54290
5
6
7
12
11
10
BP
GND
FB2
EN1
EN2
FB1
8 9COMP1 COMP2
C2
(Optional)
ZUPPER
ZLOWER
CCOMP
RCOMP
UDG-09129
OUT
L C
C1
R1
´
=
( )
( )
OUT
ESR R1 R2
C2 C
R1 R2
´ +
= ´ ´
( )
KEA
20
LOWER UPPER
COMP
M LOWER
10 Z Z
Rg Z
´ +
=´
COMP
POLE COMP
1
C
2 f R
=
´ p ´ ´
( )
POLE
LOAD OUT
1
f
2 2 R C
=´ p ´ ´ ´
TPS54290, TPS54291, TPS54292
www.ti.com
SLUS973 –OCTOBER 2009
Figure 17. Loop Compensation Network
If operating at wide duty cycles (over 50%), a capacitor may be necessary across the upper resistor of the
voltage setting divider. If duty cycles are less than 50%, this capacitor may be omitted.
(8)
If a high ESR capacitor is used in the output filter, a zero appears in the loop response that could lead to
instability. To compensate, a small capacitor is placed in parallel with the lower voltage setting divider resistor.
The value of the capacitor is determined such that a pole is placed at the same frequency as the ESR zero. If
low ESR capacitors are used, this capacitor may be omitted.
(9)
Next, calculate the value of the error amplifier gain setting resistor and capacitor using Equation 10.
(10)
(11)
where
•
NOTE
Once the filter and compensation component values have been established,
laboratory measurements of the physical design should be performed to confirm
converter stability.
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BOOTSTRAP FOR N-CHANNEL MOSFET
A bootstrap circuit provides a voltage source higher than the input voltage and of sufficient energy to fully
enhance the switching MOSFET each switching cycle. The PWM duty cycle is limited to maximum, i.e., 90% for
TPS54291, allowing an external bootstrap capacitor to charge through an internal synchronous switch (between
BP and BOOTx) during every cycle. When the PWM switch is commanded to turn ON, the energy used to drive
the MOSFET gate is derived from the voltage on this capacitor.
Because this is a charge transfer circuit, care must be taken in selecting the value of the bootstrap capacitor. It
must be sized such that the energy stored in the capacitor on a per cycle basis is greater than the gate charge
requirement of the MOSFET being used. Typically a ceramic capacitor with a value between 22nF and 68nF is
selected for the bootstrap capacitor.
OUTPUT OVERLOAD PROTECTION
In the event of an overcurrent on either output after the output reaches regulation, pulse-by-pulse current limit is
in effect for that output. In addition, an output under-voltage (UV) comparator monitors the FBx voltage (which
follows the output voltage) to declare a fault if the output drops below 85% of regulation. During this fault
condition, both PWM outputs are disabled. This ensures that both outputs discharge to GND, in the event that
over-current is on one output while the other is not loaded. The converter enters a hiccup mode timeout before
attempting to restart.
If an over-current condition exists during soft start, pulse-by-pulse current limiting reduces the pulse width of the
affected output’s PWM. In addition, if an overcurrent pulse is detected, six clock cycles are skipped before a next
PWM pulse is enabled, effectively dividing the PWM frequency by six and preventing excessive current build up
in the indictor. At the end of the soft start time, a UV fault is declared and the operation is the same as described
above.
The overcurrent threshold for Output1 and Output2 are set nominally 2.2 A and 3.8 A respectively.
DESIGN HINT: The OCP Threshold refers to the peak current in the internal switch. Be sure to add the 1/2
of the peak inductor ripple current to the DC load current in determining how close the actual operating point
is to the OCP Threshold.
OPERATING NEAR MAXIMUM DUTY CYCLE
If the TPS5429x is operated at maximum duty cycle, and if the input voltage is insufficient to support the output
voltage (at full load or during a load current transient) then there is a possibility that the output voltage falls from
regulation and trip the output UV comparator. If this should occur, the TPS5429x protection circuitry declares a
fault and enter hiccup mode.
DESIGN HINT: Ensure that under ALL conditions of line and load regulation that there is sufficient duty cycle
to maintain output voltage regulation.
DUAL SUPPLY OPERATION
It is possible to operate a TPS5429x from two supply voltages. If this application is desired, then the sequencing
of the supplies must be such that PVDD2 is above the UVLO voltage before PVDD1 begins to rise. This is to
ensure the internal regulator and the control circuitry is in operation before PVDD1 supplies energy to the output.
In addition, Output1 must be held in the disabled state (EN1 high) until there is sufficient voltage on PVDD1 to
support Output1 in regulation. (See Operating near Maximum Duty Cycle)
The preferred sequence of events follows:
1. PVDD2 rises above the input UVLO voltage
2. PVDD1 rises with Output1 disabled until PVDD1 rises above level to support Output1 regulation
With the two conditions above satisfied, there is no restriction on PVDD2 to be greater than, or less than PVDD1.
DESIGN HINT: An R-C delay on EN1 may be used to delay the startup of Output1 for a long enough period
of time to ensure PVDD1 can support Output1 load.
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( ) ( )
()2
2O
D(cond) DS(on)LS O
DS on HS
I
P R D R 1 D I 12
æ ö
D
ç ÷
= ´ + ´ - ´ +
ç ÷
è ø
( ) ( )
( )
2
IN OSS OSS S
D(SW )
V C HS C LS f
P2
´ + ´
=
D D(cond)output1 D(SW )output1 D(cond)output2 D(SW )output2 IN
P P P P P V Iq= + + + + ´
( )
J A D TH(pkg) TH(pad amb)
T T P -
= + ´ q + q
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SLUS973 –OCTOBER 2009
OVER-TEMPERATURE PROTECTION AND JUNCTION TEMPERATURE RISE
The over temperature thermal protection limits the maximum power to be dissipated at a given operating ambient
temperature. In other words, at a given device power dissipation, the maximum ambient operating temperature is
limited by the maximum allowable junction operating temperature. The device junction temperature is a function
of power dissipation, and the thermal impedance from the junction to the ambient. If the internal die temperature
should reach the thermal shutdown level, the TPS5429x shuts off both PWMs and remain in this state until the
die temperature drops below 125°C, at which time the device restarts.
The first step in determining the device junction temperature is to calculate the power dissipation. The power
dissipation is dominated by the two switching MOSFETs and the BP internal regulator. The power dissipated by
each MOSFET is composed of conduction losses and switching losses. The total conduction loss in the high side
and low side MOSFETs for each channel is given by Equation 12.
(12)
where
• IOis the DC output current,
•ΔIOis the peak-to-peak ripple current in the inductor
Notice the impact of operating duty cycle on the result.
The switching loss for each channal is approximated by Equation 13.
(13)
where
• COSS(HS) is the output capacitance of the high-side MOSFET
• COSS(LS) is the output capacitance of the low-side MOSFET
• ƒSis the switching frequency
The total power dissipation is found by summing the power loss for both MOSFETs plus the loss in the internal
regulator.
(14)
The temperature rise of the device junction is dependent on the thermal impedance from junction to the mounting
pad (See Package Dissipation Ratings), plus the thermal impedance from the thermal pad to ambient. The
thermal impedance from the thermal pad to ambient is dependent on the PCB layout (PowerPAD interface to the
PCB, the exposed pad area) and airflow (if any). See PCB Layout Guidelines, Additional References.
The operating junction temperature is shown in Equation 15.
(15)
where
•θth is the thermal impedance
BYPASSING AND FILTERING
As with any integrated circuit, supply bypassing is important for jitter free operation. To improve the noise
immunity of the converter, ceramic bypass capacitors must be placed as close to the package as possible.
• PVDD1 to GND – Use a 10 µF ceramic capacitor
• PVDD2 to GND – Use a 10 µF ceramic capacitor
• BP to GND – Use a 4.7 µF Ceramic capacitor
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0
0.4
0.6
0.8
1.0
1.8
0.2
0 20 40 60 14080 100 120
TA– Ambient Temperature – °C
PD– Power Dissipation – W
0
150
250
500
LFM
1.2
1.6
1.4
LFM = 0
LFM = 150
LFM = 250
LFM = 500
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SLUS973 –OCTOBER 2009
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POWER DERATING
The TPS5429x delivers full current at wide duty cycles at ambient temperatures up to 85°C if the thermal
impedance from the thermal pad is sufficient to maintain the junction temperature below the thermal shut down
level. At higher ambient temperatures, the device power dissipation must be reduced to maintain the junction
temperature at or below the thermal shutdown level. Figure 18 illustrates the power derating for elevated ambient
temperature under various air flow conditions. Note that these curves assume the PowerPAD is soldered to the
recommended thermal pad. See References for further information.
Figure 18. Power Derating Curves
PowerPAD PACKAGE
The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD
derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit
board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depend
on the size of the PowerPAD package. Thermal vias connect this area to internal or external copper planes and
should have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the via
is plated with copper. This plug is needed to prevent wicking the solder away from the interface between the
package body and the solder-tinned area under the device during solder reflow. Drill diameters of 0.33 mm (13
mils) works well when 1-oz copper is plated at the surface of the board while simultaneously plating the barrel of
the via. If the thermal vias are not plugged when the copper plating is performed, then a solder mask material
should be used to cap the vias with a diameter equal to the via diameter of 0.1 mm minimum. This capping
prevents the solder from being wicked through the thermal vias and potentially creating a solder void under the
package. (See Additional References)
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SLUS973 –OCTOBER 2009
LAYOUT RECOMMENDATIONS
• The PowerPad must be connected to the low-current ground with available surface copper to dissipate heat.
Extending ground land beyond the device package area between PVDD1 (pin 1) and PVDD2 (pin 16) and
between COMP1 (pin 8) and COMP2( pin 9) is recommended..
• Connect PGND1 and PGND2 to the PowerPad through a 10-mil wide trace.
• Place the ceramic input capacitors near PVDD1 and PVDD2 and bypass to PGND1 and PGND2 respectively.
• Locate the inductor near the SW1 or SW2 pin.
• Connect the output capacitor grounds to PGND1 or PGND2 with wide, tight loops.
• Use a wide ground connection from input capacitor PGND1 or PGND2 as close to power path as possible. It
is recommend they be placed directly underneath.
• Locate the bootstrap capacitor near the BOOT pin to minimize gate drive loop.
• Locate the feedback and compensation components far from switch node and input capacitor ground
connection.
• Locate the snubber components from SW1 or SW2 to PGND1 or PGND2 close to the device, minimizing the
loop area.
• Locate the BP bypass capacitor very close to device and bypass to PowerPad. Locate output ceramic
capacitor close to inductor output terminal and between inductor and electrolytic capacitors if used.
Figure 19. Top Layer
Figure 20. Bottom Layer
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DESIGN EXAMPLES
Design Example 1
The following example illustrates the design process and component selection for a 12-V to 5-V and 3.3-V dual
non-synchronous buck regulator using the TPS54291 converter. A definition of symbols used can be found in
Table 1 of the appendix
Table 1. Design Example Electrical Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CHARACTERSTICS
VIN Input voltage 8 12 14 V
IIN Input current VIN = Nom, IOUT = Max A
No load input current VIN = Nom, IOUT = 0 A 12 20 mA
VIN(UVLO) Input UVLO IOUT = Min to Max 4 4.2 4.4 V
OUTPUT CHARACTERSTICS
VOUT1 Output voltage 1 VIN = Nom, IOUT = Nom 3.2 3.3 3.4 V
VOUT2 Output voltage 2 VIN = Nom, IOUT = Nom 1.15 1.20 1.25 V
Line regulation VIN = Min to Max 1%
Load regulation IOUT = Min to Max 1%
VOUT1(ripple) Output1 voltage Ripple VIN = Nom, IOUT1 = Max 50 mVPP
VOUT2(ripple) Output2 voltage Ripple VIN = Nom, IOUT2 = Max 24 mVPP
IOUT1 Output current 1 VIN = Min to Max 0 1.5 A
IOUT2 Output current 2 VIN = Min to Max 0 2.5 A
IOCP1 Output overcurrent Channel 1 VIN = Nom, VOUT = (VOUT1 – 5%) 1.8 2.2 2.6 A
IOCP2 Output overcurrent Channel 2 VIN = Nom, VOUT = (VOUT2 – 5%) 3.2 3.8 4.6 A
TRANSIENT RESPONSE
ΔVOUT Change from load transient ΔIOUT = 1 A @ 3 µA/s 200 mV
Settling time to 1% of VOUT 1 ms
SYSTEMS CHARACTERSTICS
fSW Switching frequency 500 600 700 kHz
ηPEAK Peak efficiency VIN = Nom 90%
ηFull load efficiency VIN = Nom, IOUT = Max 80%
TOP Operating temperature range VIN = Min to Max, IOUT = Min to Max 0 25 60 °C
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( ) ( )
OUT OUT
MAX1 MAX2
IN m in IN m in
V V
3.3 1.2
D 0.413 D 0.15
V 8.0 V 8.0
» = = ¾¾® » = =
( ) ( )
OUT OUT
MIN1 MIN2
IN max IN max
V V
3.3 1.2
D 0.236 D 0.086
V 14 V 14
» = = ¾¾® » = =
( ) ( )
Lrip1 max OUT max
I 0.30 I 0.3 1.5 A 0.450 A= ´ = ´ =
( ) ( )
Lrip2 max OUT max
I 0.30 I 0.3 2.5 A 0.750 A= ´ = ´ =
( )
( ) f
OUT
IN max
MIN1 MIN
SW
LRIP max
V V 1 14 3.3 1
L D 0.236 9.35 H
I 0.45 A 600 kHz
--
» ´ ´ = ´ ´ = m
( )
( ) f
OUT
IN m ax
MIN2 MIN
SW
LRIP m ax
V V 1 14 1.2 1
L D 0.086 2.45 H
I 0.75 A 600 kHz
--
» ´ ´ = ´ ´ = m
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www.ti.com
SLUS973 –OCTOBER 2009
The list of materials for this application is shown below in Table 2. The efficiency, line regulation and load
regulation from printed circuit boards built using this design are shown in Figure 23 and Figure 24.
Figure 21. TPS54291 Design Example 1 Schematic
Step by Step Design Procedure
Duty Cycle Estimation
The duty cycle of the main switching FET is estimated by Equation 16 and Equation 17.
(16)
(17)
Inductor Selection
The peak to peak ripple should be limited to between 20% and 30% of the maximum output current.
(18)
(19)
The minimum inductor size can be estimated by Equation 20 and Equation 21.
(20)
(21)
The standard inductor values of 8.2 µH and 3.3 µH are selected for Channel 1 and Channel 2 respectively. The
actual ripple currents are estimated by Equation 22 and Equation 23.
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( )
f
OUT
IN max
RIPPLE1 MIN
SW
V V 1 14 3.3 1
I D 0.236 0.513 A
L1 8.2 H 600 kHz
--
» ´ ´ = ´ ´ =
m
( )
f
OUT
IN max
RIPPLE2 MIN
SW
V V 1 14 1.2 1
I D 0.086 0.556A
L2 3.3 H 600 kHz
--
» ´ ´ = ´ ´ =
m
( ) ( ) ( ) ( ) ( )
2 2
2 2 2 2
1 1 1
RIPPLE RIPPLE
L rms L avg OUT max
12 12 12
I I I I I 1.5 0.513 A 1.51A= + » + = + =
( ) ( ) ( ) ( ) ( )
2 2
2 2 2 2
1 1 1
RIPPLE RIPPLE
L rms L avg OUT max
12 12 12
I I I I I 2.5 0.556 A 2.51A= + » + = + =
( ) ( ) 1 1
RIPPLE
L peak OUT max 2 2
I I I 1.5 A 0.513A 1.76 A» + = + =
( ) ( ) 1 1
RIPPLE
L peak OUT max 2 2
I I I 2.5 A 0.556A 2.78 A» + = + =
( )
( )
( )
22
TRAN max
OUT1 min
OUT OVER
I L 1A 8.2 H
C 12.4 F
3.3 V 0.2 V
V V
´´ m
= = = m
´
´
( )
( )
( )
22
TRAN m ax
OUT 2 m in
OUT OVER
I L 1A 3.3 H
C 13.7 F
1.2 V 0.2 V
V V
´´ m
= = = m
´
´
f
RIPPLE
RIPPLE(total)
OUT SW
MAX
RIPPLE
I0.513 A
V0.050 V
8 C 8 12.4 F 600kHz
ESR 0.081
I 0.513 A
æ ö æ ö
--
ç ÷ ç ÷
´ ´ ´ m ´
è ø è ø
= = = W
f
RIPPLE
RIPPLE(total)
OUT SW
MAX
RIPPLE
I0.556 A
V0.024 V
8 C 8 13.7 F 600kHz
ESR 0.028
I 0.556 A
æ ö æ ö
--
ç ÷ ç ÷
´ ´ ´ m ´
è ø è ø
= = = W
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SLUS973 –OCTOBER 2009
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(22)
(23)
The RMS current through the inductor is approximated by Equation 24 and Equation 25.
(24)
(25)
A DC current with 30% peak-to-peak ripple has an RMS current approximately 0.4% above the average current.
The peak inductor current is estimated by Equation 26 and Equation 27.
(26)
(27)
A 8.2-µH inductor with a minimum RMS current rating of 1.51 A and minimum saturation current rating of 3.7 A
must be selected. A Coilcraft MSS1048-822ML 8.2-µH, 4.38-A inductor is chosen for Channel 1 and a Coilcraft
MSS1048-332 3.3-µH inductor is chosen for Channel 2.
Output Capacitor Selection
Output capacitors are selected to support load transients and output ripple current. The minimum output
capacitance to meet the transient specification is given by Equation 28 and Equation 29.
(28)
(29)
The maximum ESR to meet the ripple specification is given by Equation 30 and Equation 31.
(30)
(31)
A single 22-µF ceramic capacitor with approximately 2.5 mΩof ESR is selected to provide sufficient margin for
capacitance loss due to DC voltage bias.
Input Capacitor Selection
A minimum 10-µF ceramic input capacitor on each PVDD pin is recommended. The ceramic capacitor must
handle the RMS ripple current in the input capacitor.
The RMS current in the input capacitors is estimated by Equation 32 and Equation 33.
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( ) ( ) ( )
OUT1 1 1
RMS CIN1
I I D 1 D 1.5 A 0.413 1 0.413 0.74 A= ´ ´ - = ´ ´ - =
( ) ( ) ( )
OUT1 2 2
RMS CIN2
I I D 1 D 2.5 A 0.15 1 0.15 0.89 A= ´ ´ - = ´ ´ - =
FB FB
BIAS
OUT FB
V R
R
V V
´
=
-
( ) ( )
f
6
ON
SW
TPS5429x
1.5 10 393ns
K t 6IN OUT 6
600 kHz
FM 3762
V V 14 3.3
19.7 e 95 10 19.7 e 95 10
L8.2 H
´ ´
´--
= = =
é ù é ù
-
æ ö æ ö
-
´ + ´ ´ ´ + ´ ´
ê ú ê ú
ç ÷ ç ÷
m
è ø
ë û è ø
ê ú
ë û
44
IN
C6 6
IN
LOAD
V FM 2 10 14 V 3762 2 10 4.293
V FM 95 10 14 V 3762 95 10
1
14.4
2 R
--
- -
´ ´ ´ ´ ´ ´
= = =
é ù é ù
æ ö æ ö
´ ´ ´ ´ ´ ´
ê ú ê ú
+
ç ÷ ç ÷
+ç ÷
ç ÷ W
´
ê ú ê ú
è ø
è ø ë û
ë û
f
( )
C
EA
CO LOAD OUT
3.22
K 20 log 20 log 11.83 dB
1 2 30kHz 4.4 22 F
1 2 f 2 R C
æ ö æ ö
= - ´ = - ´ =
ç ÷ ç ÷
ç ÷ + ´ p ´ ´ W ´ m
+ ´ p´ ´ ´ ´ è ø
è ø
f
TPS54290, TPS54291, TPS54292
www.ti.com
SLUS973 –OCTOBER 2009
(32)
(33)
One 1210 10-µF, 25-V, X5R, ceramic capacitor with 2-mΩESR and a 2-A RMS current rating are selected for
each PVDD input. Higher voltage capacitors are selected to minimize capacitance loss at the DC bias voltage to
ensure the capacitors will have sufficient capacitance at the working voltage.
Feedback
The primary feedback divider resistor (RFB) from VOUT to FB should be selected between 10-kΩand 100-kΩto
maintain a balance between power dissipation and noise sensitivity. For a 3.3-V and 5-V output, 20.5 kΩis
selected and the lower resistor is given by Equation 34.
(34)
For RFB = 20.5kΩand VFB = 0.80 V, RBIAS = 6.56 kΩand 41.0 kΩ(6.49 kΩand 40.2 kΩselected) for 3.3 V and
1.2 V respectively. It is common to select the next lower available resistor value for the bias resistor. This biases
the nominal output voltage slightly higher, allowing additional tolerance for load regulation.
Compensation Components
The TPS54291 controller uses a transconductance error amplifier, which is compensated with a series capacitor
and resistor to ground plus a high-frequency capacitor to reduce the gain at high frequency. To select the
component, the following equations define the control loop and power stage gain and transfer function:
(35)
where
• K = 5.6 × 105for TPS54290
• K = 1.5 × 106for TPS54291
• K = 3.6 × 106for TPS54292
The overall DC gain of the converter control-to-output transfer function is approximated by Equation 36.
(36)
With the power stage DC gain, it is possible to estimate the required mid-band gain to program a desired
cross-over frequency.
(37)
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s) :TPS54290 TPS54291 TPS54292
( )
KEA 11.83dB
20 20
LOWER UPPER
COMP
M LOWER
10 Z Z 10 (6.49k 20.5k )
R 50.42k 53.6k
g Z 325 S 6.49k
´ + ´ W + W
= = = W » W
´ m ´ W
POLE
LOAD OUT
1 1
f 1.644 kHz
2 R C 2 4.4 22 F
= = =
´ p ´ ´ ´ p ´ W ´ m
COMP
POLE COMP
1 1
C 1.80 nF
2 f R 2 1.644kHz 53.6k
= = =
´ p ´ ´ ´ p ´ ´ W
( ) ( ) ( )
()( ) ( ) ( )
22
CON1 1 1
DS on HS DS on LS SW 1 RMS
P R D R 1 D I 150 m 0.413 100m 0.587 1.51 0.275 W
æ ö
= ´ + ´ - ´ = W ´ + W ´ ´ =
ç ÷
è ø
( ) ( ) ( )
()( ) ( ) ( )
22
CON2 1 1
DS on HS DS on LS SW 1 RMS
P R D R 1 D I 105 m 0.15 75 m 0.85 2.51 0.501W
æ ö
= ´ + ´ - ´ = W ´ + W ´ ´ =
ç ÷
è ø
( )22
OSS(HS) OSS(LS) SW
IN max
SW1
V (C C ) 14 (140pF 200pF) 600kHz
P 20mW
2 2
´ + ´ ´ + ´
» = =
f
( ) ( ) ( )
22
SW
IN max OSS HS OSS LS
SW2
V (C C ) 14 (200pF 280pF) 600kHz
P 28mW
2 2
´ + ´ ´ + ´
» = =
f
( ) ( )
()
REG DD BP BP
IN max IN max
P I V I V V 10mA 14 V 140 mW» ´ + ´ - = ´ =
TPS54290, TPS54291, TPS54292
SLUS973 –OCTOBER 2009
www.ti.com
Compensation Gain Setting Resistor
RCOMP programs the mid-band error amplifier gain to set the desired cross-over frequency in Equation 38.
(38)
Compensation Integrator Capacitor
An integrator capacitor provides maximum DC gain for the best possible DC regulation while programming the
compensation zero to match the natural pole of the output filter. CCOMP is selected by Equation 40.
(39)
(40)
Bootstap Capacitor
To ensure proper charging of the high-side FET gate and limit the ripple voltage on the boost capacitor, a 47-nF
boot strap capacitor is recommended.
Power Dissipation
The power dissipation in the TPS54291 is made from FET conduction losses, switching losses and regulator
losses.
Conduction losses are estimated by Equation 41 and Equation 42.
(41)
(42)
The switching losses are estimated by Equation 43 and Equation 44.
(43)
(44)
The regulator losses are estimated by Equation 45.
(45)
Total power dissipation in the device is the sum of conduction losses and switching losses for both channels plus
regulator losses, which is estimated to be 1.01 W.
24 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :TPS54290 TPS54291 TPS54292
50
0 1.00.5 1.5 2.0 2.5
ILOAD – Load Current – A
55
65
85
70
90
75
80
h– Efficiency – %
VIN = 12 V
VIN = 14 V
VIN = 8 V
60
VOUT = 1.2 V
50
0 0.60.3 0.9 1.2 1.5
ILOAD – Load Current – A
55
65
95
70
100
75
90
h– Efficiency – %
60
85
80
VIN = 12 V
VIN = 14 V
VIN = 8 V
VOUT = 3.3 V
TPS54290, TPS54291, TPS54292
www.ti.com
SLUS973 –OCTOBER 2009
Design Example Test Results
Figure 22. TPS54291 Design Example Switching Waveforms
Figure 23. Design Efficiency for 1.2-V Output Figure 24. Design Efficiency for 3.3-V Output
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s) :TPS54290 TPS54291 TPS54292
TPS54290, TPS54291, TPS54292
SLUS973 –OCTOBER 2009
www.ti.com
Table 2. Design Example List of Materials
REFERENCE QTY VALUE DESCRIPTION SIZE PART NUMBER MFR
DESIGNATOR
C12 1 4.7 µF Capacitor, Ceramic, 10 V, X5R, 20% 0805 Std Std
C2, C14 2 22 µF Capacitor, Ceramic, 6.3 V, X5R, 20% 1206 C3216X5R0J226M TDK
C3, C13 2 470 pF Capacitor, Ceramic, 25 V, X7R, 20% 0603 Std Std
C4, C11 2 0.047 µF Capacitor, Ceramic, 25 V, X7R, 20% 0603 Std Std
C3225X5R1E106
C5, C10 2 10 µF Capacitor, Ceramic, 25 V, X5R, 20% 1210 TDK
M
C6 2 1.8 nF Capacitor, Ceramic, 25 V, X7R, 20% 0603 Std Std
C7 1 15 pF Capacitor, Ceramic, 25 V, X7R, 20% 0603 Std Std
C8 1 47 pF Capacitor, Ceramic, 25 V, X7R, 20% 0603 Std Std
C9 1 1.2 nF Capacitor, Ceramic, 25 V, X7R, 20% 0603 Std Std
0.402 x
L1 1 8.2 µH Inductor, SMT, 4.38 A, 20 mΩMSS1048-822L Coilcraft
0.394 inch
0.402 x
L2 1 3.3 µH Inductor, SMT, 5.04 A, 10 mΩMSS1048-332L Coilcraft
0.394 inch
R10 1 40.2 kΩResistor, Chip, 1/16W, 1% 0603 Std Std
R2, R11 2 10 ΩResistor, Chip, 1/16W, 5% 0603 Std Std
R3, R12 2 20.5 kΩResistor, Chip, 1/16W, 1% 0603 Std Std
R4 1 6.49 kΩResistor, Chip, 1/16W, 1% 0603 Std Std
R6 1 7.87 kΩResistor, Chip, 1/16W, 1% 0603 Std Std
R7 1 4.64 kΩResistor, Chip, 1/16W, 1% 0603 Std Std
2.5 A/1.5 A, Dual Output Fully Synchronous Buck
U1 1 CSP TPS54291PWP TI
600 Hz Converter w/Integrated FET
26 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :TPS54290 TPS54291 TPS54292
+
+
3.3V@1.5A
+ +
1.2V@1.5A
TPS54290, TPS54291, TPS54292
www.ti.com
SLUS973 –OCTOBER 2009
Design Example 2 (Cascading Operation)
TPS5429x can be configured as cascaded operation as shown in Figure 25. The 12-V input supply is applied to
PVDD2 and the the channel 2 output is tied to PVDD1. The channel 2 output is 3.3 V and capable of supporting
1.5 A to the load while generating power for the 1.2-V input for channel 1.
Figure 25. Cascading Operation
Design Example 2 Test Results
For Figure 26, Ch1: 12-V supply; Ch2: VOUT1 (1.2 V); Ch3: VOUT2(3.3 V). For Figure 27, Ch1: Channel 1 SW
node; Ch2: Channel 1 output ripple Ch3: Channel 2 output ripple; Ch2: Channel 2 SW node.
Figure 26. Start-Up Waveforms Figure 27. Output Ripple and SW Nodes
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s) :TPS54290 TPS54291 TPS54292
TPS54290, TPS54291, TPS54292
SLUS973 –OCTOBER 2009
www.ti.com
ADDITIONAL REFERENCES
RELATED DEVICES
The following devices have characteristics similar to the TPS54290/1/2 and may be of interest.
DEVICE DESCRIPTION
TPS40222 5-V input, 1.5-A, Non-Synchronous Buck Converter
TPS54283/TPS54286 2-A DUAL NON-SYNCHRONOUS CONVERTER WITH INTEGRATED HIGH-SIDE FET
TPS55383/TPS55386 3-A DUAL NON-SYNCHRONOUS CONVERTER WITH INTEGRATED HIGH-SIDE FET
REFERENCES
These references, design tools and links to additional references, including design software, may be found at
www.power.ti.com.
1. Additional PowerPAD™ information may be found in Applications Briefs (SLMA002A) and (SLMA004).
2. Under The Hood Of Low Voltage DC/DC Converters – SEM1500 Topic 5 – 2002 Seminar Series
3. Understanding Buck Power Stages in Switchmode Power Supplies, (SLVA057), March 1999
4. Designing Stable Control Loops – SEM 1400 – 2001 Seminar Series
Package Outline and Recommended PCB Footprint
The following pages outline the mechanical dimensions of the 16-pin PWP package and provide
recommendations for PCB layout.
28 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :TPS54290 TPS54291 TPS54292
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS54290PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS54290PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS54291PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS54291PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS54292PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS54292PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 20-Nov-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS54290PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TPS54292PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS54290PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0
TPS54292PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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