ADC084S021CIMM/NOPB - Texas Instruments High-Performance Analog

ADC084S021

www.ti.com

SNAS279E –APRIL 2005–REVISED MARCH 2013

ADC084S021 4-Channel, 50 ksps to 200 Ksps, 8-Bit A/D Converter

Check for Samples: ADC084S021

1FEATURES DESCRIPTION

2• Specified Over a Range of Sample Rates. The ADC084S021 is a low-power, four-channel

• Four Input Channels CMOS 8-bit analog-to-digital converter with a high-

• Variable Power Management speed serial interface. Unlike the conventional

practice of specifying performance at a single sample

• Single Power Supply with 2.7V - 5.25V Range rate only, the ADC084S021 is fully specified over a

sample rate range of 50 ksps to 200 ksps. The

APPLICATIONS converter is based upon a successive-approximation

• Portable Systems register architecture with an internal track-and-hold

circuit. It can be configured to accept up to four input

• Remote Data Acquisition signals at inputs IN1 through IN4.

• Instrumentation and Control Systems The output serial data is straight binary, and is

KEY SPECIFICATIONS compatible with several standards, such as SPI™,

QSPI™, MICROWIRE, and many common DSP

• DNL: ±0.04 LSB (typ) serial interfaces.

• INL: ±0.04 LSB (typ) The ADC084S021 operates with a single supply that

• SNR: 49.6 dB (typ) can range from +2.7V to +5.25V. Normal power

• Power Consumption consumption using a +3V or +5V supply is 1.6 mW

and 5.8 mW, respectively. The power-down feature

– 3V Supply: 1.6 mW (typ) reduces the power consumption to just 0.12 µW using

– 5V Supply: 5.8 mW (typ) a +3V supply, or 0.35 µW using a +5V supply.

The ADC084S021 is packaged in a 10-lead VSSOP

package. Operation over the industrial temperature

range of −40°C to +85°C is ensured.

Table 1. Pin-Compatible Alternatives by Resolution and Speed

Resolution Specified for Sample Rate Range of:

50 to 200 ksps 200 to 500 ksps 500 ksps to 1 Msps

12-bit ADC124S021 ADC124S051 ADC124S101

10-bit ADC104S021 ADC104S051 ADC104S101

8-bit ADC084S021 ADC084S051 ADC084S101

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

IN1

IN4

MUX T/H

SCLK

GND

DIN

DOUT

CONTROL

LOGIC

SUCCESSIVE

APPROXIMATION

ADC

GND

8-Bit

CS SCLK

DOUT

DIN

IN1

GND

IN4

IN3 IN2

VAADC084S021

ADC084S021

SNAS279E –APRIL 2005–REVISED MARCH 2013

www.ti.com

Connection Diagram

Figure 1. 10-Lead VSSOP

See DGK Package

Block Diagram

Pin Descriptions and Equivalent Circuits

Pin No. Symbol Description

ANALOG I/O

4-7 IN1 to IN4 Analog inputs. These signals can range from 0V to VA.

DIGITAL I/O

10 SCLK Digital clock input. This clock directly controls the conversion and readout processes.

Digital data output. The output samples are clocked out at this pin on falling edges of the

9 DOUT SCLK pin.

Digital data input. The ADC084S021's Control Register is loaded through this pin on rising

8 DIN edges of SCLK.

Chip select. A conversion begins at the falling edge of CS. Conversions continue as long as

1 CS CS is held low.

POWER SUPPLY

Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and be

2 VAbypassed to GND with a 0.1 µF monolithic capacitor located within 1 cm of the power pin

and with a 1 µF capacitor.

3 GND Device ground return for all signals.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Product Folder Links: ADC084S021

ADC084S021

www.ti.com

SNAS279E –APRIL 2005–REVISED MARCH 2013

Absolute Maximum Ratings (1)(2)(3)

Supply Voltage VA−0.3V to 6.5V

Voltage on Any Pin to GND −0.3V to VA+0.3V

Input Current at Any Pin (4) ±10 mA

Package Input Current(4) ±20 mA

Power Consumption at TA= 25°C See (5)

ESD Susceptibility (6)

Human Body Model 2500V

Machine Model 250V

Junction Temperature +150°C

Storage Temperature −65°C to +150°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the

Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(4) When the input voltage at any pin exceeds the power supply (that is, VIN < GND or VIN > VA), the current at that pin should be limited to

10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an

input current of 10 mA to two. The Absolute Maximum Rating specification does not apply to the VApin. The current into the VApin is

limited by the Analog Supply Voltage specification.

(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by

TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula

PDMAX = (TJmax −TA)/θJA. The values for maximum power dissipation listed above will be reached only when the device is operated in

a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is

reversed). Obviously, such conditions should always be avoided.

(6) Human body model is 100 pF capacitor discharged through a 1.5 kΩresistor. Machine model is 220 pF discharged through zero ohms.

Operating Ratings (1)(2)

Operating Temperature Range −40°C ≤TA≤+85°C

VASupply Voltage +2.7V to +5.25V

Digital Input Pins Voltage Range −0.3V to VA

Clock Frequency 0.8 MHz to 3.2 MHz

Analog Input Voltage 0V to VA

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the

Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.

Package Thermal Resistance

Package θJA

10-lead VSSOP 190°C / W

Soldering process must comply with Reflow Temperature Profile specifications. Refer to http://www.ti.com/packaging.(1)

(1) Reflow temperature profiles are different for lead-free and non-lead-free packages.

Product Folder Links: ADC084S021

ADC084S021

SNAS279E –APRIL 2005–REVISED MARCH 2013

www.ti.com

ADC084S021 Converter Electrical Characteristics (1)

The following specifications apply for VA= +2.7V to 5.25V, GND = 0V, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 ksps to 200

ksps, CL= 50 pF, unless otherwise noted. Boldface limits apply for TA= TMIN to TMAX: all other limits TA= 25°C.

Symbol Parameter Conditions Typical Limits (2) Units

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 8Bits

INL Integral Non-Linearity ±0.04 ±0.2 LSB (max)

DNL Differential Non-Linearity ±0.04 ±0.2 LSB (max)

VOFF Offset Error +0.52 ±0.7 LSB (max)

OEM Channel to Channel Offset Error Match ±0.01 ±0.3 LSB (max)

FSE Full-Scale Error +0.51 ±0.7 LSB (max)

Channel to Channel Full-Scale Error

FSEM +0.01 ±0.3 LSB (max)

Match

DYNAMIC CONVERTER CHARACTERISTICS

VA= +2.7 to 5.25V

SINAD Signal-to-Noise Plus Distortion Ratio 49.6 49.1 dB (min)

fIN = 39.9 kHz, −0.02 dBFS

VA= +2.7 to 5.25V

SNR Signal-to-Noise Ratio 49.6 49.2 dB (min)

fIN = 39.9 kHz, −0.02 dBFS

VA= +2.7 to 5.25V

THD Total Harmonic Distortion −76 −62 dB (max)

fIN = 39.9 kHz, −0.02 dBFS

VA= +2.7 to 5.25V

SFDR Spurious-Free Dynamic Range 68 63 dB (min)

fIN = 39.9 kHz, −0.02 dBFS

VA= +2.7 to 5.25V

ENOB Effective Number of Bits 7.9 7.9 Bits (min)

fIN = 39.9 kHz, −0.02 dBFS

VA= +5.25V

Channel-to-Channel Crosstalk −73 dB

fIN = 39.9 kHz

Intermodulation Distortion, Second VA= +5.25V −78 dB

Order Terms fa= 40.161 kHz, fb= 41.015 kHz

IMD Intermodulation Distortion, Third Order VA= +5.25V −73 dB

Terms fa= 40.161 kHz, fb= 41.015 kHz

VA= +5V 11 MHz

FPBW -3 dB Full Power Bandwidth VA= +3V 8 MHz

ANALOG INPUT CHARACTERISTICS

VIN Input Range 0 to VAV

IDCL DC Leakage Current ±1 µA (max)

Track Mode 33 pF

CINA Input Capacitance Hold Mode 3 pF

DIGITAL INPUT CHARACTERISTICS

VA= +5.25V 2.4 V (min)

VIH Input High Voltage VA= +3.6V 2.1 V (min)

VIL Input Low Voltage 0.8 V (max)

IIN Input Current VIN = 0V or VA±10 µA (max)

CIND Digital Input Capacitance 2 4pF (max)

DIGITAL OUTPUT CHARACTERISTICS

ISOURCE = 200 µA VA−0.03 VA−0.5 V (min)

VOH Output High Voltage ISOURCE = 1 mA VA−0.1 V

ISINK = 200 µA 0.03 0.4 V (max)

VOL Output Low Voltage ISINK = 1 mA 0.1 V

IOZH, IOZL TRI-STATE® Leakage Current ±1 µA (max)

COUT TRI-STATE® Output Capacitance 2 4pF (max)

Output Coding Straight (Natural) Binary

(1) Min/max specification limits are specified by design, test, or statistical analysis.

(2) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).

Product Folder Links: ADC084S021

ADC084S021

www.ti.com

SNAS279E –APRIL 2005–REVISED MARCH 2013

ADC084S021 Converter Electrical Characteristics (1) (continued)

The following specifications apply for VA= +2.7V to 5.25V, GND = 0V, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 ksps to 200

ksps, CL= 50 pF, unless otherwise noted. Boldface limits apply for TA= TMIN to TMAX: all other limits TA= 25°C.

Symbol Parameter Conditions Typical Limits (2) Units

POWER SUPPLY CHARACTERISTICS (CL= 10 pF)

2.7 V (min)

VASupply Voltage 5.25 V (max)

VA= +5.25V, 1.1 1.7 mA (max)

fSAMPLE = 200 ksps, fIN = 40 kHz

Supply Current, Normal Mode

(Operational, CS low) VA= +3.6V, 0.45 0.8 mA (max)

fSAMPLE = 200 ksps, fIN = 40 kHz

IAVA= +5.25V, 200 nA

fSAMPLE = 0 ksps

Supply Current, Shutdown (CS high) VA= +3.6V, 200 nA

fSAMPLE = 0 ksps

VA= +5.25V 5.8 8.9 mW (max)

Power Consumption, Normal Mode

(Operational, CS low) VA= +3.6V 1.6 2.9 mW (max)

PDVA= +5.25V 1.05 µW

Power Consumption, Shutdown (CS

high) VA= +3.6V 0.72 µW

AC ELECTRICAL CHARACTERISTICS

0.8 MHz (min)

fSCLK Clock Frequency (3) 3.2 MHz (max)

50 ksps (min)

fSSample Rate (3) 200 ksps (max)

tCONV Conversion Time 13 SCLK cycles

30 % (min)

DC SCLK Duty Cycle fSCLK = 3.2 MHz 50 70 % (max)

tACQ Track/Hold Acquisition Time Full-Scale Step Input 3SCLK cycles

Throughput Time Acquisition Time + Conversion Time 16 SCLK cycles

(3) This is the frequency range over which the electrical performance is ensured. The device is functional over a wider range which is

specified under Operating Ratings.

Product Folder Links: ADC084S021

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8

Track Hold

Power Up

Track Hold

b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0

9 10

DB5 DB4 DB3 DB2 DB1 DB0 DB5 DB4 DB3

DIN

DOUT

Power Up

SCLK

Power Down

Control register Control register

DB7 DB6 DB7 DB6

ADC084S021

SNAS279E –APRIL 2005–REVISED MARCH 2013

www.ti.com

ADC084S021 Timing Specifications

The following specifications apply for VA= +2.7V to 5.25V, GND = 0V, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 ksps to 200

ksps, CL= 50 pF, Boldface limits apply for TA= TMIN to TMAX: all other limits TA= 25°C.

Symbol Parameter Conditions Typical Limits (1) Units

VA=

+3.0V

tCSU Setup Time SCLK High to CS Falling Edge (2) 10

VA= +5.0V −0.5

VA= +3.0V +4.5

tCLH Hold time SCLK Low to CS Falling Edge (2) 10 ns (min)

VA= +5.0V +1.5

VA= +3.0V +4

tEN Delay from CS Until DOUT active 30 ns (max)

VA= +5.0V +2

VA= +3.0V +16.5

tACC Data Access Time after SCLK Falling Edge 30 ns (max)

VA= +5.0V +15

tSU Data Setup Time Prior to SCLK Rising Edge +3 10 ns (min)

tHData Valid SCLK Hold Time +3 10 ns (min)

tCH SCLK High Pulse Width 0.5 x tSCLK 0.3 x tSCLK ns (min)

tCL SCLK Low Pulse Width 0.5 x tSCLK 0.3 x tSCLK ns (min)

VA= +3.0V 1.7

Output Falling VA= +5.0V 1.2

tDIS CS Rising Edge to DOUT High-Impedance 20 ns (max)

VA= +3.0V 1.0

Output Rising VA= +5.0V 1.0

(1) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).

(2) Clock may be either high or low when CS is asserted as long as setup and hold times tCSU and tCLH are strictly observed.

Timing Diagrams

Figure 2. ADC084S021 Operational Timing Diagram

Product Folder Links: ADC084S021

tCSU

tCLH

SCLK

tCONVERT

tACQ

tCL tACC

tEN

Z3 Z2 Z1 Z0 DB6

DONT DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC

DB7 DB5 DB4 DB0

87654321

DIN

DOUT

SCLK

tDIS

Zero ZeroDB1

151413

Tri-State

Zero Zero

1211

tCH

tSU

ADC084S021

www.ti.com

SNAS279E –APRIL 2005–REVISED MARCH 2013

Figure 3. Timing Test Circuit

Figure 4. ADC084S021 Serial Timing Diagram

Figure 5. SCLK and CS Timing Parameters

Specification Definitions

ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold

capacitor to charge up to the input voltage.

APERTURE DELAY is the time between the fourth falling SCLK edge of a conversion and the time when the

input signal is acquired or held for conversion.

CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input

voltage to a digital word.

CROSSTALK is the coupling of energy from one channel into the other channel, or the amount of signal energy

from one analog input that appears at the measured analog input.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB.

DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The

specification here refers to the SCLK.

Product Folder Links: ADC084S021

‡AA++A

log20=THD 

ADC084S021

SNAS279E –APRIL 2005–REVISED MARCH 2013

www.ti.com

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise

and Distortion or SINAD. ENOB is defined as (SINAD −1.76) / 6.02 and says that the converter is

equivalent to a perfect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental

drops 3 dB below its low frequency value for a full scale input.

FULL SCALE ERROR (FSE) is a measure of how far the last code transition is from the ideal 1½ LSB below

VREF+and is defined as:

VFSE = Vmax + 1.5 LSB – VREF+

where

• Vmax is the voltage at which the transition to the maximum code occurs

• FSE can be expressed in Volts, LSB or percent of full scale range (1)

GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF −1.5

LSB), after adjusting for offset error.

INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from

negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last

code transition). The deviation of any given code from this straight line is measured from the center of that

code value.

INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two

sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the

power in the second and third order intermodulation products to the sum of the power in both of the

original frequencies. IMD is usually expressed in dB.

MISSING CODES are those output codes that will never appear at the ADC outputs. These codes cannot be

reached with any input value. The ADC084S021 is ensured not to have any missing codes.

OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND +

0.5 LSB).

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal at the

converter output to the rms value of the sum of all other spectral components below one-half the sampling

frequency, not including d.c. or harmonics included in the THD specification.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of

the input signal to the rms value of all of the other spectral components below half the clock frequency,

including harmonics but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the

input signal and the peak spurious signal where a spurious signal is any signal present in the output

spectrum that is not present at the input, excluding d.c.

TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first five

harmonic components at the output to the rms level of the input signal frequency as seen at the output.

THD is calculated as

where

• Af1is the RMS power of the input frequency at the output

• Af2through Af6are the RMS power in the first 5 harmonic frequencies (2)

THROUGHPUT TIME is the minimum time required between the start of two successive conversion. It is the

acquisition time plus the conversion and read out times. In the case of the ADC084S021, this is 16 SCLK

periods.

Product Folder Links: ADC084S021

ADC084S021

www.ti.com

SNAS279E –APRIL 2005–REVISED MARCH 2013

Typical Performance Characteristics

TA= +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated.

DNL - VA= 3.0V INL - VA= 3.0V

Figure 6. Figure 7.

DNL - VA= 5.0V INL - VA= 5.0V

Figure 8. Figure 9.

DNL vs. Supply INL vs. Supply

Figure 10. Figure 11.

Product Folder Links: ADC084S021

ADC084S021

SNAS279E –APRIL 2005–REVISED MARCH 2013

www.ti.com

Typical Performance Characteristics (continued)

TA= +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated.

DNL vs. Clock Frequency INL vs. Clock Frequency

Figure 12. Figure 13.

DNL vs. Clock Duty Cycle INL vs. Clock Duty Cycle

Figure 14. Figure 15.

DNL vs. Temperature INL vs. Temperature

Figure 16. Figure 17.

Product Folder Links: ADC084S021

ADC084S021

www.ti.com

SNAS279E –APRIL 2005–REVISED MARCH 2013

Typical Performance Characteristics (continued)

TA= +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated.

SNR vs. Supply THD vs. Supply

Figure 18. Figure 19.

SNR vs. Clock Frequency THD vs. Clock Frequency

Figure 20. Figure 21.

SNR vs. Clock Duty Cycle THD vs. Clock Duty Cycle

Figure 22. Figure 23.

Product Folder Links: ADC084S021

ADC084S021

SNAS279E –APRIL 2005–REVISED MARCH 2013

www.ti.com

Typical Performance Characteristics (continued)

TA= +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated.

SNR vs. Input Frequency THD vs. Input Frequency

Figure 24. Figure 25.

SNR vs. Temperature THD vs. Temperature

Figure 26. Figure 27.

SFDR vs. Supply SINAD vs. Supply

Figure 28. Figure 29.

Product Folder Links: ADC084S021

ADC084S021

www.ti.com

SNAS279E –APRIL 2005–REVISED MARCH 2013

Typical Performance Characteristics (continued)

TA= +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated.

SFDR vs. Clock Frequency SINAD vs. Clock Frequency

Figure 30. Figure 31.

SFDR vs. Clock Duty Cycle SINAD vs. Clock Duty Cycle

Figure 32. Figure 33.

SFDR vs. Input Frequency SINAD vs. Input Frequency

Figure 34. Figure 35.

Product Folder Links: ADC084S021

ADC084S021

SNAS279E –APRIL 2005–REVISED MARCH 2013

www.ti.com

Typical Performance Characteristics (continued)

TA= +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated.

SFDR vs. Temperature SINAD vs. Temperature

Figure 36. Figure 37.

ENOB vs. Supply ENOB vs. Clock Frequency

Figure 38. Figure 39.

ENOB vs. Clock Duty Cycle ENOB vs. Input Frequency

Figure 40. Figure 41.

Product Folder Links: ADC084S021

ADC084S021

www.ti.com

SNAS279E –APRIL 2005–REVISED MARCH 2013

Typical Performance Characteristics (continued)

TA= +25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 0.8 MHz to 3.2 MHz, fIN = 39.9 kHz unless otherwise stated.

ENOB vs. Temperature Spectral Response - 3V, 200 ksps

Figure 42. Figure 43.

Spectral Response - 5V, 200 ksps Power Consumption vs. Throughput

Figure 44. Figure 45.

Product Folder Links: ADC084S021

IN1

MUX

AGND

SAMPLING

CAPACITOR

SW1 -

+CONTROL

LOGIC

CHARGE

REDISTRIBUTION

DAC

SW2

IN4

IN1

MUX

AGND

SAMPLING

CAPACITOR

SW1 -

+CONTROL

LOGIC

CHARGE

REDISTRIBUTION

DAC

SW2

IN4

ADC084S021

SNAS279E –APRIL 2005–REVISED MARCH 2013

www.ti.com

APPLICATIONS INFORMATION

ADC084S021 OPERATION

The ADC084S021 is a successive-approximation analog-to-digital converter designed around a charge-

redistribution digital-to-analog converter. Simplified schematics of the ADC084S021 in both track and hold modes

are shown in Figure 46 and Figure 47, respectively. Figure 46 shows the ADC084S021 in track mode: switch

SW1 connects the sampling capacitor to one of four analog input channels through the multiplexer, and SW2

balances the comparator inputs. The ADC084S021 is in this state for the first three SCLK cycles after CS is

brought low.

Figure 47 shows the ADC084S021 in hold mode: switch SW1 connects the sampling capacitor to ground,

maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs

the charge-redistribution DAC to add fixed amounts of charge to the sampling capacitor until the comparator is

balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of

the analog input voltage. The ADC084S021 is in this state for the fourth through sixteenth SCLK cycles after CS

is brought low.

The time when CS is low is considered a serial frame. Each of these frames should contain an integer multiple of

16 SCLK cycles, during which time a conversion is performed and clocked out at the DOUT pin and data is

clocked into the DIN pin to indicate the multiplexer address for the next conversion.

Figure 46. ADC084S021 in Track Mode

Figure 47. ADC084S021 in Hold Mode

USING THE ADC084S021

Figure 2 and Figure 4 for the ADC084S021 are shown in Timing Diagrams. CS is chip select, which initiates

conversions and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and

the timing of serial data. DOUT is the serial data output pin, where a conversion result is sent as a serial data

stream, MSB first. Data at DIN, the serial data input pin, is written to the ADC084S021's Control Register. New

data is written to DIN with each conversion.

Product Folder Links: ADC084S021

ADC084S021

www.ti.com

SNAS279E –APRIL 2005–REVISED MARCH 2013

A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain

an integer multiple of 16 rising SCLK edges. The ADC output data (DOUT) is in a high impedance state when

CS is high and is active when CS is low. CS thus acts as an output enable, in addition to being a start

conversion input. Additionally, the device goes into a power down state when CS is high and between continuous

conversion cycles.

During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13

SCLK cycles the conversion is accomplished and the data is clocked out, MSB first, starting with the 5th clock. If

there is more than one conversion in a frame, the ADC will re-enter the track mode on the falling edge of SCLK

after the N*16th rising edge of SCLK, and re-enter the hold/convert mode at the N*16+4th falling edge of SCLK,

where "N" is an integer.

SCLK is internally gated off when CS is high. If SCLK is stopped in the low state while CS is high, the

subsequent fall of CS will generate a falling edge of the internal version of SCLK, putting the ADC into the track

mode. This is seen by the ADC as the first falling edge of SCLK. If SCLK is stopped with SCLK high, the ADC

enters the track mode at the first falling edge of SCLK after the falling edge of CS.

During each conversion, data is clocked into the device at the DIN pin on the first 8 rising edges of SCLK after

the fall of CS. For each conversion, it is necessary to clock in the data indicating the input that is selected for the

conversion after the current one. That is, the conversion that is started at the fall of CS is of the voltage at the

channel that was selected when the last conversion was started. The first conversion after power up will be of the

first channel. See Table 2,Table 3, and Table 4.

If CS and SCLK go low within the times defined by tCSU and tCLH, the rising edge of SCLK that begins clocking

data in at DIN may be one clock cycle later than expected. It is, therefore, best to strictly observe the minimum

tCSU and tCLH times given in ADC084S021 Timing Specifications .

There are no power-up delays or dummy conversions required with the ADC084S021. The ADC is able to

sample and convert an input to full conversion immediately following power up. The first conversion result after

power-up will be that of IN1.

Table 2. Control Register Bits

Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC

Table 3. Control Register Bit Descriptions

Bit #: Symbol: Description

7 - 6, 2 - 0 DONTC Don't care. The value of these bits do not affect device operation.

5 ADD2 These three bits determine which input channel will be sampled and converted in the next

track/hold cycle. The mapping between codes and channels is shown in Table 4.

4 ADD1

3 ADD0

Table 4. Input Channel Selection

ADD2 ADD1 ADD0 Input Channel

x 0 0 IN1 (Default)

x 0 1 IN2

x 1 0 IN3

x 1 1 IN4

ADC084S021 TRANSFER FUNCTION

The output format of the ADC084S021 is straight binary. Code transitions occur midway between successive

integer LSB values. The LSB width for the ADC084S021 is VA/256 and the ideal transfer characteristic is shown

in Figure 48. The transition from an output code of 0000 0000 to a code of 0000 0001 is at 1/2 LSB, or a voltage

of VA/512. Other code transitions occur at steps of one LSB.

Product Folder Links: ADC084S021

IN1

IN2 MICROPROCESSOR

DSP

SCLK

DIN

DOUT

GND

ADC084S021

LP2950 5V

1 PF0.1 PF 0.1 PF1 PF

IN3

IN4

0V +VA - 1 LSB

½ LSB ANALOG INPUT

1LSB = VA/256

ADC CODE

111...111

111...110

111...000

011...111

000...010

000...001

000...000

ADC084S021

SNAS279E –APRIL 2005–REVISED MARCH 2013

www.ti.com

Figure 48. Ideal Transfer Characteristic

TYPICAL APPLICATION CIRCUIT

A typical application of the ADC084S021 is shown in Figure 50. Power is provided, in this example, by the Texas

Instruments LP2950 low-dropout voltage regulator, available in a variety of fixed and adjustable output voltages.

The power supply pin is bypassed with a capacitor network located close to the ADC084S021.

Because the reference for the ADC084S021 is the supply voltage, any noise on the supply will degrade device

noise performance. To keep noise off the supply, use a dedicated linear regulator for this device, or provide

sufficient decoupling from other circuitry to keep noise off the ADC084S021 supply pin. Because of the

ADC084S021's low power requirements, it is also possible to use a precision reference as a power supply to

maximize performance. The four-wire interface is also shown connected to a microprocessor or DSP.

Figure 49. Typical Application Circuit

ANALOG INPUTS

An equivalent circuit for one of the ADC084S021's input channels is shown in Figure 50. Diodes D1 and D2

provide ESD protection for the analog inputs. At no time should any input go beyond (VA+ 300 mV) or (GND −

300 mV), as these ESD diodes will begin conducting, which could result in erratic operation. For this reason,

these ESD diodes should NOT be used to clamp the input signal.

Product Folder Links: ADC084S021

VIN

30 pF

3 pF

Conversion Phase - Switch Open

Track Phase - Switch Closed

ADC084S021

www.ti.com

SNAS279E –APRIL 2005–REVISED MARCH 2013

The capacitor C1 in Figure 50 has a typical value of 3 pF, and is mainly the package pin capacitance. Resistor

R1 is the on resistance of the multiplexer and track / hold switch, which is typically 500 ohms. Capacitor C2 is the

ADC084S021 sampling capacitor, which is typically 30 pF. The ADC084S021 will deliver best performance when

driven by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitance.

This is especially important when using the ADC084S021 to sample AC signals. Also important when sampling

dynamic signals is a band-pass or low-pass filter to reduce harmonics and noise, improving dynamic

performance.

Figure 50. Equivalent Input Circuit

DIGITAL INPUTS AND OUTPUTS

The ADC084S021's digital output, DOUT, is limited by and cannot exceed the supply voltage, VA. The digital

input pins are not prone to latch-up and, and although not recommended, SCLK, CS and DIN may be asserted

before VAwithout any latchup risk.

POWER SUPPLY CONSIDERATIONS

The ADC084S021 is fully powered-up whenever CS is low, and fully powered-down when CS is high, with one

exception: the ADC084S021 automatically enters power-down mode between the 16th falling edge of a

conversion and the 1st falling edge of the subsequent conversion (see Timing Diagrams).

The ADC084S021 can perform multiple conversions back to back; each conversion requires 16 SCLK cycles.

The ADC084S021 will perform conversions continuously as long as CS is held low.

Power Management

When the ADC084S021 is operated continuously in normal mode, the maximum throughput is fSCLK/16.

Performance will remain as stated in ADC084S021 Electrical Characteristics as long as the SCLK frequency

remains within the range stated at the heading of those tables. Throughput may be traded for power consumption

by running fSCLK at its maximum 3.2 MHz and performing fewer conversions per unit time, putting the

ADC084S021 into shutdown mode between conversions. Figure 45 is shown in Typical Performance

Characteristics. To calculate the power consumption for a given throughput, multiply the fraction of time spent in

the normal mode by the normal mode power consumption and add the fraction of time spent in shutdown mode

multiplied by the shutdown mode power consumption. Generally, the user will put the part into normal mode and

then put the part back into shutdown mode. Note that the curve of Figure 45 is nearly linear. This is because the

power consumption in the shutdown mode is so small that it can be ignored for all practical purposes.

Power Supply Noise Considerations

The charging of any output load capacitance requires current from the power supply, VA. The current pulses

required from the supply to charge the output capacitance will cause voltage variations of the supply voltage. If

these variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore,

discharging the output capacitance when the digital output goes from a logic high to a logic low will dump current

into the die substrate. Load discharge currents will cause "ground bounce" noise in the substrate that will

degrade noise performance if that current is large enough. The larger is the output capacitance, the more current

flows through the die supply line and substrate, causing more noise to be coupled into the analog channel and

degrading noise performance.

Product Folder Links: ADC084S021

ADC084S021

SNAS279E –APRIL 2005–REVISED MARCH 2013

www.ti.com

To keep noise out of the power supply, keep the output load capacitance as small as practical. If the load

capacitance is greater than 50 pF, use a 100 Ωseries resistor at the ADC output, located as close to the ADC

output pin as practical. This will limit the charge and discharge current of the output capacitance and improve

noise performance.

Product Folder Links: ADC084S021

ADC084S021

www.ti.com

SNAS279E –APRIL 2005–REVISED MARCH 2013

REVISION HISTORY

Changes from Revision D (March 2013) to Revision E Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 20

Product Folder Links: ADC084S021

PACKAGE OPTION ADDENDUM

www.ti.com 7-Oct-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

ADC084S021CIMM/NOPB ACTIVE VSSOP DGS 10 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 X19C

ADC084S021CIMMX/NOPB ACTIVE VSSOP DGS 10 3500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 X19C

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

ADC084S021CIMM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

ADC084S021CIMMX/NOP

BVSSOP DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Sep-2013

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADC084S021CIMM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0

ADC084S021CIMMX/NOP

BVSSOP DGS 10 3500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Sep-2013

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of

non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products Applications

Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive

Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications

Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers

DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps

DSP dsp.ti.com Energy and Lighting www.ti.com/energy

Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial

Interface interface.ti.com Medical www.ti.com/medical

Logic logic.ti.com Security www.ti.com/security

Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense

Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video

RFID www.ti-rfid.com

OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com

Wireless Connectivity www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265