CY2291/CY2291F/CY2291I CY2292/CY2292F/CY2292I CY2295/CY2295I Three-PLL General Purpose EPROM Programmable Clock Generator Features Benefits * Three integrated phase-locked loops Provides all necessary system clocks in a single package * EPROM programmability Easy customization and fast turnaround time * Low skew, low jitter, high accuracy outputs Meets critical timing requirements in complex system designs * Power management options (Shutdown, OE, Suspend) Supports low power applications * Frequency select option Enables design flexibility and margin testing * Smooth slewing on CPUCLK Allows downstream PLLs to stay locked on CPUCLK output * 3.3V or 5V operation Enables application compatibility Part Number Outputs Input Frequency Range Output Frequency Range Specifics CY2291 8 10 MHz-25 MHz (external crystal) 76.923 kHz-100 MHz (5V) 1 MHz-30 MHz (reference clock) 76.923 kHz-80 MHz (3.3V) Factory Programmable Commercial Temperature CY2291I 8 10 MHz-25 MHz (external crystal) 76.923 kHz-90 MHz (5V) 1 MHz-30 MHz (reference clock) 76.923 kHz-66.6 MHz (3.3V) Factory Programmable Industrial Temperature CY2291F 8 10 MHz-25 MHz (external crystal) 76.923 kHz-90 MHz (5V) 1 MHz-30 MHz (reference clock) 76.923 kHz-66.6 MHz (3.3V) Field Programmable Commercial Temperature CY2292 6 10 MHz-25 MHz (external crystal) 76.923 kHz-100 MHz (5V) 1 MHz-30 MHz (reference clock) 76.923 kHz-80 MHz (3.3V) Factory Programmable Commercial Temperature CY2292I 6 10 MHz-25 MHz (external crystal) 76.923 kHz-90 MHz (5V) 1 MHz-30 MHz (reference clock) 76.923 kHz-66.6 MHz (3.3V) Factory Programmable Industrial Temperature CY2292F 6 10 MHz-25 MHz (external crystal) 76.923 kHz-90 MHz (5V) 1 MHz-30 MHz (reference clock) 76.923 kHz-66.6 MHz (3.3V) Field Programmable Commercial Temperature CY2295 8 10 MHz-25 MHz (external crystal) 76.923 kHz-100 MHz (5V) 1 MHz-30 MHz (reference clock) 76.923 kHz-80 MHz (3.3V) Factory Programmable Commercial Temperature CY2295I 8 10 MHz-25 MHz (external crystal) 76.923 kHz-90 MHz (5V) 1 MHz-30 MHz (reference clock) 76.923 kHz-66.6 MHz (3.3V) Factory Programmable Industrial Temperature Logic Block Diagram Available on CY2291 and CY2295 only 32XIN OSC. 32K OSC. XBUF 32XOUT XTALIN XTALOUT CLKF SYS PLL UTIL PLL CPUCLK OUTPUT MULTIPLEXER AND DIVIDERS CLKA CLKB CLKC CPU PLL CLKD S2/SUSPEND CPU EPROM CONFIGURATION EPROM AND TABLE TEST LOGIC S1 S0 SHUTDOWN/ OE Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 November 10, 1998 CY2291/CY2291F/CY2291I CY2292/CY2292F/CY2292I CY2295/CY2295I Pin Configurations CY2295 28-pin SSOP CY2291 20-pin SOIC CY2292 16-pin SOIC CLKC 1 1 20 32XIN 32K 2 19 VBATT CLKC 3 18 VDD 4 17 S2/SUSPEND 5 16 6 15 VDD S1 32XOUT SHUTDOWN/OE 16 VDD 2 15 S2/SUSPEND GND 3 14 VDD XTALIN 4 13 S1 XTALOUT XBUF 5 12 6 11 GND XTALIN S0 GND CLKD 7 10 CLKA CPUCLK 8 9 CLKB XTALOUT XBUF CLKD 7 14 8 9 13 CPUCLK 10 11 12 CY2291-3 32XOUT 1 28 32XIN 32K 2 27 VBATT GND 3 26 VDD CLKC 4 25 SHUTDOWN/OE VDD 5 24 S2/SUSPEND VDD 6 23 VDD GND GND 7 22 VDD 8 21 GND 9 10 20 S1 19 S0 XBUF CLKD 11 18 17 CLKF GND N/C 13 14 16 CLKA 15 CLKB SHUTDOWN/OE S0 CLKF CLKA XTALIN XTALOUT CLKB CY2291-1 CPUCLK 12 CY2291-4 Pin Summary Name Pin Number Pin Number Pin Number CY2291 CY2292 CY2295 Description 32XOUT 1 -- 1 32.768 kHz crystal feedback 32K 2 -- 2 32.768 kHz output (always active if VBATT is present) CLKC 3 1 4 Configurable clock output C VDD 4, 16 2, 14 5, 6, 22, 23, 26 Voltage supply GND 5 3, 11 3, 7, 8, 17, 21 Ground XTALIN[1] 6 4 9 Reference crystal input or external reference clock input XTALOUT 7 5 10 Reference crystal feedback XBUF 8 6 11 Buffered reference clock output CLKD 9 7 12 Configurable clock output D CPUCLK 10 8 14 CPU frequency clock output CLKB 11 9 15 Configurable clock output B CLKA 12 10 16 Configurable clock output A CLKF 13 -- 18 Configurable clock output F S0 14 12 19 CPU clock select input, bit 0 S1 15 13 20 CPU clock select input, bit 1 S2/SUSPEND 17 15 24 CPU clock select input, bit 2. Optionally enables suspend feature when LOW [3] SHUTDOWN/OE 18 16 25 Places outputs in three-state[4] condition and shuts down chip when LOW. Optionally, only places outputs in three-state[4] condition and does not shut down chip when LOW VBATT 19 -- 27 Battery supply for 32.768-kHz circuit 32XIN 20 -- 28 32.768-kHz crystal input [1, 2] Notes: 1. For best accuracy, use a parallel-resonant crystal, CLOAD 17 pF or 18 pF. 2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to crystal). 3. Please refer to application note "Understanding the CY2291, CY2292 and CY2295" for more information. 4. The CY2291 has weak pull-downs on all outputs (except 32K). Hence, when a three-state condition is forced on the outputs, the output pins are pulled LOW. 2 CY2291/CY2291F/CY2291I CY2292/CY2292F/CY2292I CY2295/CY2295I Operation All configurations are EPROM programmable, providing short sample and production lead times. Please refer to the application note "Understanding the CY2291, CY2292, and CY2295" for information on configuring the part. The CY2291, CY2292 and CY2295 are a third-generation family of clock generators. The CY2291 is upwardly compatible with the industry standard ICD2023 and ICD2028 and continues their tradition by providing a high level of customizable features to meet the diverse clock generation needs of modern motherboards and other synchronous systems. The CY2292 differs from the CY2291 in that it comes in a 16-pin 150-mil SOIC package, and does not provide either the 32-kHz or CLKF outputs. The CY2295 is available in a space-saving 28-pin SSOP package. Power Saving Features The SHUTDOWN/OE input three-states the outputs when pulled LOW (the 32-kHz clock output is not affected). If system shutdown is enabled (the default), a LOW on this pin also shuts off the PLLs, counters, the reference oscillator, and all other active components. The resulting current on the VDD pins will be less than 50 A (for Commercial Temp. or 100 A for Industrial Temp.) plus 15 A max. for the 32-kHz subsystem and is typically 10 A. After leaving shutdown mode, the PLLs will have to re-lock. All outputs except 32K have a weak pull-down so that the outputs do not float when three-stated.[4] All parts provide a highly configurable set of clocks for PC motherboard applications. Each of the four configurable clock outputs (CLKA-CLKD) can be assigned 1 of 30 frequencies in any combination. Multiple outputs configured for the same or related[3] frequencies will have low (<500 ps) skew, in effect providing on-chip buffering for heavily loaded signals. The S2/SUSPEND input can be configured to shut down a customizable set of outputs and/or PLLs, when LOW. All PLLs and any of the outputs except 32K can be shut off in nearly any combination. The only limitation is that if a PLL is shut off, all outputs derived from it must also be shut off. Suspending a PLL shuts off all associated logic, while suspending an output simply forces a three-state condition.[3] The CY2291, CY2292, and CY2295 can be configured for either 5V or 3.3V operation. The internal ROM tables use EPROM technology, allowing full customization of output frequencies. The reference oscillator has been designed for 10-MHz to 25-MHz crystals, providing additional flexibility. No external components are required with this crystal. Alternatively, an external reference clock of frequency between 1 MHz and 30 MHz can be used. Customers using the 32-kHz oscillator on the CY2291 or CY2295 should connect a 10-M resistor in parallel with the 32-kHz crystal. The CPUCLK can slew (transition) smoothly between 8 MHz and the maximum output frequency (100 MHz at 5V/80 MHz at 3.3V for Commercial Temp. parts or 90 MHz at 5V/66.6 MHz at 3.3V for Industrial Temp. and for field-programmed parts). This feature is extremely useful in "Green" PC and laptop applications, where reducing the frequency of operation can result in considerable power savings. This feature meets all 486 and Pentium processor slewing requirements. Output Configuration The CY2291 and CY2295 (and CY2292) have five (four) independent frequency sources on chip. These are the 32-kHz oscillator (not available on CY2292), the reference oscillator, and three Phase Locked Loops (PLLs). Each PLL has a specific function. The System PLL (SPLL) drives the CLKF output (not available on CY2292) and provides fixed output frequencies on the configurable outputs. The SPLL offers the most output frequency divider options. The CPU PLL (CPLL) is controlled by the select inputs (S0-S2) to provide eight user-selectable frequencies with smooth slewing between frequencies. The Utility PLL (UPLL) provides the most accurate clock. It is often used for miscellaneous frequencies not provided by the other frequency sources. CyClocksTM Software CyClocks is an easy-to-use application that allows you to configure any one of the EPROM programmable clocks offered by Cypress. You may specify the input frequency, PLL & output frequencies, and different functional options. Please note the output frequency ranges in this datasheet when specifying them in CyClocks to ensure that you stay within the limits. CyClocks also has a power calculation feature that allows you to see the power consumption of your specific configuration. You can download a copy of CyClocks for free on Cypress's website at www.cypress.com. 3 CY2291/CY2291F/CY2291I CY2292/CY2292F/CY2292I CY2295/CY2295I Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Max. Soldering Temperature (10 sec) ..........................260C Supply Voltage ............................................... -0.5V to +7.0V Package Power Dissipation ...................................... 750 mW DC Input Voltage............................................ -0.5V to +7.0V Static Discharge Voltage ........................................... >2000V (per MIL-STD-883, Method 3015) Junction Temperature ...................................................150C Storage Temperature ................................. -65C to +150C Operating Conditions[5] Parameter Description Part Numbers Min. Max. Unit VDD Supply Voltage, 5.0V (3.3V) operation All 4.5 (3.0) 5.5 (3.6) V VBATT Battery Backup Voltage All 2.0 5.5 V TA Operating Temperature, Ambient CY2291/CY2291F CY2292/CY2292F CY2295 0 +70 C -40 +85 C 25 (15) pF CY2291I CY2292I CY2295I CLOAD Max. Load Capacitance 5.0V (3.3V) Operation All fREF Reference Frequency All 10.0 25.0 MHz fREF Reference Frequency, External Reference Clock[6, 7] All 1 30 MHz Max. Unit Electrical Characteristics Parameter Conditions HIGH-Level Output Voltage IOH = 4.0 mA [8] VOH VOL Description [8] LOW-Level Output Voltage IOL = 4.0 mA VOH-32 32.768-kHz HIGH-Level Output Voltage IOH = 0.5 mA VOL-32 32.768-kHz LOW-Level Output Voltage IOL = 0.5 mA VIH HIGH-Level Input Voltage[9] [9] Min. Typ. 2.4 V 0.4 VBATT 0.5 V 0.4 Except crystal pins V 2.0 V V VIL LOW-Level Input Voltage Except crystal pins 0.8 V IIH Input HIGH Current VIN = VDD-0.5V <1 10 A IIL Input LOW Current VIN = +0.5V <1 10 A IOZ Output Leakage Current 250 A [10] Three-state outputs IDD VDD Supply Current VDD = VDD max., 5V (3.3V) operation IDDS VDD Power Supply Current in Shutdown Mode[10] Shutdown active, excluding VBATT IBATT VBATT Power Supply Current VBATT = 3.0V 75(50) 100(65) mA CY2291/CY2291F CY2292/CY2292F CY2295 10 50 A CY2291I CY2292I CY2295I 10 100 A 5 15 A Notes: 5. Electrical parameters are guaranteed with these operating conditions. 6. External input reference clock must have a duty cycle between 40% and 60%, measured at V DD/2. 7. Please refer to application note "Crystal Oscillator Topics" for information on AC-coupling the external input reference clock. 8. All outputs swing rail to rail. 9. Xtal inputs have CMOS thresholds. 10. Load = Max., VIN = 0V or VDD, Typical (-104) configuration, CPUCLK = 66 MHz. Other configurations will vary. Power can be approximated by the following formula (multiply by 0.65 for 3V operation): IDD=10+0.06*(FCPLL+FUPLL+2*FSPLL)+0.27*(FCLKA+FCLKB+FCLKC+FCLKD+FCPUCLK+FCLKF+FXBUF). 4 CY2291/CY2291F/CY2291I CY2292/CY2292F/CY2292I CY2295/CY2295I Switching Characteristics[11] Parameter t1 t1 Name Output Period Output Period Description Clock output range, 5V operation Clock output range, 3.3V operation Max. Unit CY2291 CY2292 CY2295 Min. 10 (100 MHz) Typ. 13000 (76.923 kHz) ns CY2291F/CY2291I CY2292F/CY2291I CY2295I 11.1 (90 MHz) 13000 (76.923 kHz) ns CY2291 CY2292 CY2295 12.5 (80 MHz) 13000 (76.923 kHz) ns 13000 (76.923 kHz) ns CY2291F/CY2291I 15 CY2292F/CY2291I (66.6 MHz) CY2295I Output Duty Cycle[12] t3 Rise Time Duty cycle for outputs, defined as t2 / t1[13] fOUT > 66 MHZ 40% 50% 60% Duty cycle for outputs, defined as t2 / t1[13] fOUT < 66 MHZ 45% 50% 55% 3 5 Output clock rise time[14] [14] ns t4 Fall Time Output clock fall time 2.5 4 ns t5 Output Disable Time Time for output to enter three-state mode after SHUTDOWN/OE goes LOW 10 15 ns t6 Output Enable Time Time for output to leave three-state mode after SHUTDOWN/OE goes HIGH 10 15 ns t7 Skew Skew delay between any identical or related outputs[3, 13] < 0.25 0.5 ns t8 CPUCLK Slew Frequency transition rate 20.0 MHz/ ms t9A Clock Jitter[15] Peak-to-peak period jitter (t9A max. - t9A min.), % of clock period (fOUT < 4 MHz) <0.5 1 % t9B Clock Jitter[15] Peak-to-peak period jitter (t9B max. - t9B min.) (4 MHz < fOUT < 16 MHz) <0.7 1 ns t9C Clock Jitter[15] Peak-to-peak period jitter (16 MHz < fOUT < 50 MHz) <400 500 ps t9D Clock Jitter[15] Peak-to-peak period jitter (fOUT > 50 MHz) <250 350 ps t10A Lock Time for CPLL Lock Time from Power-up <25 50 ms t10B Lock Time for UPLL and SPLL Lock Time from Power-up <0.25 1 ms Slew Limits CPU PLL Slew Limits 1.0 CY2291 CY2292 CY2295 8 100 (5V) 80 (3.3V) MHz CY2291F/CY2291I CY2292F/CY2291I CY2295I 8 90 (5V) 66.6 (3.3V) MHz Notes: 11. Guaranteed by design and characterization, not 100% tested in production. 12. XBUF duty cycle depends on XTALIN duty cycle. 13. Measured at 1.4V. 14. Measured between 0.4V and 2.4V. 15. Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit. For more information on jitter, please refer to the application note: "Jitter in PLL-Based Systems." 5 CY2291/CY2291F/CY2291I CY2292/CY2292F/CY2292I CY2295/CY2295I Switching Waveforms All Outputs, Duty Cycle and Rise/Fall Time t1 t2 OUTPUT t3 t4 CY2291-7 Output Three-State Timing[4] OE t6 t5 ALL THREE-STATE OUTPUTS CY2291-8 CLK Outputs Jitter and Skew t9A CLK OUTPUT t7 RELATED CLK CY2291-9 CPU Frequency Change SELECT OLD SELECT Fold NEW SELECT STABLE t8 & t10 Fnew CPU CY2291-10 6 CY2291/CY2291F/CY2291I CY2292/CY2292F/CY2292I CY2295/CY2295I Test Circuit VDD CLK out 0.1 F CLOAD OUTPUTS VDD 0.1 F GND CY2291-11 Ordering Information Ordering Code Package Name Operating Range Package Type Operating Voltage CY2291SC-XXX S5 20-Pin SOIC Commercial 5.0V CY2292SC-XXX S16 16-Pin SOIC Commercial 5.0V CY2295PVC-XXX O28 28-Pin SSOP Commercial 5.0V S5 20-Pin SOIC Commercial 3.3V CY2292SL-XXX S16 16-Pin SOIC Commercial 3.3V CY2295PVL-XXX O28 28-Pin SSOP Commercial 3.3V CY2291F S5 20-Pin SOIC Commercial 3.3V or 5.0V CY2292F S16 16-Pin SOIC Commercial 3.3V or 5.0V CY2291SI-XXX S5 20-Pin SOIC Industrial 3.3V or 5.0V CY2292SI-XXX S16 16-Pin SOIC Industrial 3.3V or 5.0V CY2295PVI-XXX O28 28-Pin SSOP Industrial 3.3V or 5.0V CY2291SL-XXX Document #: 38-00410-D Custom Configuration Request Procedure The CY229x are EPROM-programmable devices which may be configured in the factory or in the field by a Cypress Field Application Engineer (FAE). The output frequencies requested will be matched as closely as the internal PLL divider and multiplier options allow. All custom requests must be submmitted to your local Cypress FAE or sales representative. There are two methods to use to request custom configurations: 1. Use CyClocks software. This software automatically calculates the output frequencies that can be generated by the CY229x devices and provides a print-out of final pinout which can be submitted (in electronic or print format) to your local FAE or sales representative. The CyClocks software is available free-of-charge from the Cypress website (http://www.cypress.com) or from your local sales representative. 2. Use the custom configuration form attached. All areas must be filled in with the exception of shaded cells and the form submitted to the appropriate Cypress FAE or sales representative. If requesting samples through the factory: Once the custom request has been processed you will receive a part number with a 3-digit extension (e.g., CY2292SC-128) specific to the frequencies and pinout of your device. This will be the part number used for samples requests and production orders. 7 CY2291/CY2291F/CY2291I CY2292/CY2292F/CY2292I CY2295/CY2295I CY2291/2/5 CUSTOM CONFIGURATION REQUEST FORM (Please submit to your local FAE or sales representative) Company Phone# Engineer Fax# FAE/Sales Date CIRCLE ONE CY2291 CY2292 CY2295 The CY2291, CY2295, and CY2292 are the industry's most flexible frequency synthesizers, offering a high degree of configurability due to their unique internal programmable EPROM array. Of the CY2291/2/5's outputs, six (five on the CY2292) may be defined within the scope of the PLL frequencies and divider criteria described in the following. Shaded areas are for Cypress use only. Contact your local Cypress representative for assistance. 1. OPERATING VOLTAGE (Circle one) 3.3V 5.0V Crystal External Clock INPUT REFERENCE FREQUENCY (Circle one) 14.31818 MHz (Default) If a different reference is required, specify the frequency in the box to the right (must be between 10 MHz and 25 MHz for crystal, 1 MHz and 30 MHz for external clock): 3. CPU-PLL (CPLL) FREQUENCIES ("Off" is a valid selection for any address and will automatically be entered for blanks.) Select Requested Actual S2 S1 S0 If the Suspend Option is specified in #7 below, the Select MSB 0 0 0 (S2) serves a dual function as both the MSB CPU address 0 0 1 and as the Suspend select pin. The CPU frequencies speci0 1 0 fied for addresses 000-011 will be active unless the CPU-PLL is shut down during the suspend mode (CPU-PLL is circled 0 1 1 in #7). Also, any outputs derived from a non-suspended 1 0 0 CPU-PLL (assigned in #5 as options 5-8) that are not circled 1 0 1 in #7 will remain active during the suspend mode. 1 1 0 2. 1 1 1 4. Range: 8-100 MHz at 5V; 8- 80 MHz at 3.3V (Commercial) 8-90 MHz at 5V, 8-66.6 MHz at 3.3V (Industrial/Field-Prog) Default = "Off" for all selections UTILITY-PLL (UPLL) AND SYSTEM-PLL (SPLL) FREQUENCIES ("Off" is a valid frequency selection for either PLL.) To minimize harmonic effects, avoid setting any PLL to an equal or multiple frequency of another PLL. Actual Actual Requested Requested SPLL UPLL Range: 8-100 MHz at 5V; 8-80 MHz at 3.3V (Commercial) Range: 8-100 MHz at 5V; 8-80 MHz at 3.3V (Commercial) 8-90 MHz at 5V, 8-66.6 MHz at 3.3V (Industrial/Field-Prog) 8-90 MHz at 5V, 8-66.6 MHz at 3.3V (Industrial/Field-Prog) Default = 96 MHz at 5V; 48 MHz at 3.3V Default = 96 MHz at 5V; 48 MHz at 3.3V 5. OUTPUT CONFIGURATION ("Off" is a valid selection for any output and will automatically be entered for blanks.) Assign by number from the Output Options Table below and fill in the Frequency column as a double-check. Output Options Table 1.Ref 2. Ref/2 3. Ref/4 4. Ref/8 5. CPLL 6. CPLL/2 7. CPLL/4 8. CPLL/8 9. UPLL 10. UPLL/2 32K (Fixed 32 kHz) CLKF (Options 14-16, Off) XBUF (Option 1 only) CPUCLK (Options 5-7, Off) 11. UPLL/4 12. UPLL/8 13. SPLL 14. SPLL/2 15. SPLL/3 Option - 16. SPLL/4 17. SPLL/5 18. SPLL/6 19. SPLL/8 20. SPLL/10 Frequency 32.768kHz 21. SPLL/12 22. SPLL/13 23. SPLL/20 24. SPLL/24 25. SPLL/26 26. SPLL/40 27. SPLL/48 28. SPLL/52 29. SPLL/96 30. SPLL/104 Option Frequency CLKA (Options 1- 30, Off) CLKB (Options 1- 30, Off) CLKC (Options 1- 30, Off) CLKD (Options 1- 30, Off) 1 32K and CLKF are not available on the CY2292. For CLKD only: option #4 (Ref/8) is replaced with Ref/3. 6. SHUTDOWN OPTION (Circle Yes or No) Yes No 7. SUSPEND OPTION (Circle Yes or No) Yes No CPU-PLL UTIL -PLL SYS-PLL IF SUSPEND = "Yes": Circle each resource to be shut down when the Suspend mode is active (S2=0). Note that suspending a PLL automatically suspends its outputs. FOR CYPRESS USE ONLY (Shaded Areas above and below) Customer Configuration Marking Date Quantity 8 XBUF CPUCLK CLKF CLKA CLKB CLKC CLKD CY2291/CY2291F/CY2291I CY2292/CY2292F/CY2292I CY2295/CY2295I Package Diagrams 20-Lead (300-Mil) Molded SOIC S5 51-85024-A 16-Lead (150-Mil) Molded SOIC S16 51-85068-A 9 CY2291/CY2291F/CY2291I CY2292/CY2292F/CY2292I CY2295/CY2295I Package Diagrams (continued) 28-Lead (210-Mil) Shrunk Small Outline Package O28 51-85079-B (c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.