NXP Semiconductors Data Sheet: Technical Data Document Number: KL02P32M48SF0 Rev. 5 08/2017 Kinetis KL02 32 KB Flash MKL02ZxxVFG4 MKL02ZxxVFK4 MKL02ZxxVFM4 48 MHz Cortex-M0+ Based Microcontroller Designed with efficiency in mind. Features a size efficient, ultrasmall package, energy efficient ARM Cortex-M0+ 32-bit performance. Shares the comprehensive enablement and scalability of the Kinetis family. This product offers: * Run power consumption down to 36 A/MHz in very low power run mode * Static power consumption down to 2 A with full state retention and 4 s wakeup * Ultra-efficient Cortex-M0+ processor running up to 48 MHz with industry leading throughput * Memory option is up to 32 KB flash and 4 KB RAM * Energy-saving architecture is optimized for low power with 90nm TFS technology, clock and power gating techniques, and zero wait state flash memory controller 16-pin QFN (FG) 3 x 3 x 0.65 Pitch 0.5 mm 24-pin QFN (FK) 4 x 4 x 1 Pitch 0.5 mm 32-pin QFN (FM) 5 x 5 x 1 Pitch 0.5 mm Performance * 48 MHz ARM(R) Cortex(R)-M0+ core Human-machine interface * Up to 28 general-purpose input/output (GPIO) Memories and memory interfaces * Up to 32 KB program flash memory * Up to 4 KB SRAM Communication interfaces * One 8-bit SPI module * One low power UART module * Two I2C module System peripherals * Nine low-power modes to provide power optimization based on application requirements * COP Software watchdog * SWD debug interface and Micro Trace Buffer * Bit Manipulation Engine Clocks * 32 kHz to 40 kHz crystal oscillator * Multi-purpose clock source * 1 kHz LPO clock Operating Characteristics Analog Modules * 12-bit SAR ADC * Analog comparator (CMP) containing a 6-bit DAC and programmable reference input Timers * Two 2-channel Timer/PWM modules * 16-bit low-power timer (LPTMR) Security and integrity modules * 80-bit unique identification number per chip * Voltage range: 1.71 to 3.6 V * Flash write voltage range: 1.71 to 3.6 V * Temperature range (ambient): -40 to 105C NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. Ordering Information 1 Part Number Memory Maximum number of I\O's Flash (KB) SRAM (KB) MKL02Z8VFG4 8 1 14 MKL02Z16VFG4 16 2 14 MKL02Z32VFG4 32 4 14 MKL02Z16VFK4 16 2 22 MKL02Z32VFK4 32 4 22 MKL02Z16VFM4 16 2 28 MKL02Z32VFM4 32 4 28 1. To confirm current availability of ordererable part numbers, go to http://www.nxp.com and perform a part number search. Related Resources Type Description Resource Selector Guide The NXP Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector. Solution Advisor Product Brief The Product Brief contains concise overview/summary information to KL0XPB1 enable quick evaluation of a device for design suitability. Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. KL02P32M48SF0RM1 Data Sheet The Data Sheet includes electrical characteristics and signal connections. KL02P32M48SF01 Chip Errata The chip mask set Errata provides additional or corrective information for a particular device mask set. KINETIS_L_xN33H2 Package drawing Package dimensions are provided in package drawings. QFN 16-pin: 98ASA00525D1 QFN 24-pin: 98ASA00474D1 QFN 32-pin: 98ASA00473D1 1. To find the associated resource, go to http://www.nxp.com and perform a search using this term. 2. To find the associated resource, go to http://www.nxp.com and perform a search using this term with the "x" replaced by the revision of the device you are using. Figure 1 shows the functional modules in the chip. 2 NXP Semiconductors Kinetis KL02 32 KB Flash, Rev. 5 08/2017 Kinetis KL02 Family System ARM Cortex-M0+ Core Internal watchdog Debug interfaces Memories and Memory Interfaces Program flash BME Interrupt controller Clocks Frequencylocked loop Low frequency oscillator RAM Internal reference clocks MTB Security and Integrity Analog Timers Internal watchdog 12-bit ADC x1 Timers 2x2ch Analog comparator x1 Low Power Timer 6-bit DAC Communication Interfaces I2C x2 Human-Machine Interface (HMI) GPIOs with interrupt Low power UART x1 SPI x1 Figure 1. Functional block diagram Kinetis KL02 32 KB Flash, Rev. 5 08/2017 3 NXP Semiconductors Table of Contents 1 Ratings.................................................................................. 5 1.1 Thermal handling ratings............................................... 5 1.2 Moisture handling ratings...............................................5 1.3 ESD handling ratings..................................................... 5 1.4 Voltage and current operating ratings............................5 2 General................................................................................. 6 2.1 AC electrical characteristics...........................................6 2.2 Nonswitching electrical specifications............................6 2.2.1 Voltage and current operating requirements..... 7 2.2.2 LVD and POR operating requirements..............7 2.2.3 Voltage and current operating behaviors...........8 2.2.4 Power mode transition operating behaviors...... 9 2.2.5 2.2.6 2.2.7 Power consumption operating behaviors.......... 10 EMC radiated emissions operating behaviors... 15 EMC Radiated Emissions Web Search Procedure boilerplate........................................ 16 2.2.8 Capacitance attributes.......................................16 2.3 Switching specifications.................................................16 2.3.1 Device clock specifications................................16 2.3.2 General switching specifications....................... 17 2.4 Thermal specifications................................................... 17 2.4.1 Thermal operating requirements....................... 17 2.4.2 Thermal attributes..............................................17 3 Peripheral operating requirements and behaviors................ 18 3.1 Core modules................................................................ 18 3.1.1 SWD electricals ................................................ 18 3.2 System modules............................................................ 20 3.3 Clock modules............................................................... 20 3.3.1 MCG specifications............................................20 3.3.2 Oscillator electrical specifications...................... 21 3.4 Memories and memory interfaces................................. 22 3.4.1 Flash electrical specifications............................ 22 3.5 Security and integrity modules.......................................24 4 NXP Semiconductors 4 5 6 7 8 9 10 3.6 Analog............................................................................24 3.6.1 ADC electrical specifications............................. 24 3.6.2 CMP and 6-bit DAC electrical specifications..... 27 3.7 Timers............................................................................29 3.8 Communication interfaces............................................. 29 3.8.1 SPI switching specifications.............................. 29 3.8.2 Inter-Integrated Circuit Interface (I2C) timing.... 33 3.8.3 UART.................................................................35 Dimensions........................................................................... 35 4.1 Obtaining package dimensions......................................35 Pinout.................................................................................... 36 5.1 KL02 signal multiplexing and pin assignments.............. 36 5.2 KL02 pinouts..................................................................37 Ordering parts....................................................................... 40 6.1 Determining valid orderable parts..................................40 Part identification...................................................................40 7.1 Description.....................................................................40 7.2 Format........................................................................... 41 7.3 Fields............................................................................. 41 7.4 Example.........................................................................41 Small package marking.........................................................42 Terminology and guidelines.................................................. 42 9.1 Definition: Operating requirement..................................42 9.2 Definition: Operating behavior....................................... 43 9.3 Definition: Attribute........................................................ 43 9.4 Definition: Rating........................................................... 43 9.5 Result of exceeding a rating.......................................... 44 9.6 Relationship between ratings and operating requirements..................................................................44 9.7 Guidelines for ratings and operating requirements........45 9.8 Definition: Typical value.................................................45 9.9 Typical value conditions.................................................46 Revision history.....................................................................47 Kinetis KL02 32 KB Flash, Rev. 5 08/2017 Ratings 1 Ratings 1.1 Thermal handling ratings Table 1. Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature -55 150 C 1 TSDR Solder temperature, lead-free -- 260 C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.2 Moisture handling ratings Table 2. Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. Max. Unit Notes -- 3 -- 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.3 ESD handling ratings Table 3. ESD handling ratings Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 Latch-up current at ambient temperature of 105 C -100 +100 mA 3 ILAT 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. Kinetis KL02 32 KB Flash, Rev. 5 08/2017 5 NXP Semiconductors General 1.4 Voltage and current operating ratings Table 4. Voltage and current operating ratings Symbol Description Min. Max. Unit VDD Digital supply voltage -0.3 3.8 V IDD Digital supply current -- 120 mA VIO IO pin input voltage -0.3 VDD + 0.3 V Instantaneous maximum current single pin limit (applies to all port pins) -25 25 mA VDD - 0.3 VDD + 0.3 V ID VDDA Analog supply voltage 2 General 2.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. VIH Input Signal High Low 80% 50% 20% Midpoint1 Fall Time VIL Rise Time The midpoint is VIL + (VIH - VIL) / 2 Figure 2. Input signal measurement reference All digital I/O switching characteristics, unless otherwise specified, assume the output pins have the following characteristics. * CL=30 pF loads * Slew rate disabled * Normal drive strength 2.2 Nonswitching electrical specifications 6 NXP Semiconductors Kinetis KL02 32 KB Flash, Rev. 5 08/2017 General 2.2.1 Voltage and current operating requirements Table 5. Voltage and current operating requirements Symbol Description Min. Max. Unit VDD Supply voltage 1.71 3.6 V VDDA Analog supply voltage 1.71 3.6 V -- VDD - VDDA VDD-to-VDDA differential voltage -0.1 0.1 V -- VSS - VSSA VSS-to-VSSA differential voltage -0.1 0.1 V -- VIH VIL Input high voltage -- * 2.7 V VDD 3.6 V 0.7 x VDD -- V * 1.7 V VDD 2.7 V 0.75 x VDD -- V Input low voltage -- * 2.7 V VDD 3.6 V -- 0.35 x VDD V * 1.7 V VDD 2.7 V -- 0.3 x VDD V 0.06 x VDD -- V -3 -- mA VHYS Input hysteresis IICIO IO pin negative DC injection current--single pin -- 1 * VIN < VSS-0.3V IICcont Notes Contiguous pin DC injection current --regional limit, includes sum of negative injection currents of 16 contiguous pins * Negative current injection -- -25 -- mA VODPU Open drain pullup voltage level VDD VDD V 2 VRAM VDD voltage required to retain RAM 1.2 -- V -- 1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|. 2. Open drain outputs must be pulled to VDD. 2.2.2 LVD and POR operating requirements Table 6. VDD supply LVD and POR operating requirements Symbol Description Min. Typ. Max. Unit Notes VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V -- VLVDH Falling low-voltage detect threshold -- high range (LVDV = 01) 2.48 2.56 2.64 V -- Low-voltage warning thresholds -- high range 1 Table continues on the next page... Kinetis KL02 32 KB Flash, Rev. 5 08/2017 7 NXP Semiconductors General Table 6. VDD supply LVD and POR operating requirements (continued) Symbol Min. Typ. Max. Unit VLVW1H Description * Level 1 falling (LVWV = 00) 2.62 2.70 2.78 V VLVW2H * Level 2 falling (LVWV = 01) 2.72 2.80 2.88 V VLVW3H * Level 3 falling (LVWV = 10) 2.82 2.90 2.98 V VLVW4H * Level 4 falling (LVWV = 11) 2.92 3.00 3.08 V -- 60 -- mV -- 1.54 1.60 1.66 V -- VHYSH Low-voltage inhibit reset/recover hysteresis -- high range VLVDL Falling low-voltage detect threshold -- low range (LVDV=00) Low-voltage warning thresholds -- low range VLVW1L * Level 1 falling (LVWV = 00) VLVW2L * Level 2 falling (LVWV = 01) VLVW3L * Level 3 falling (LVWV = 10) VLVW4L * Level 4 falling (LVWV = 11) VHYSL Low-voltage inhibit reset/recover hysteresis -- low range Notes 1 1.74 1.80 1.86 V 1.84 1.90 1.96 V 1.94 2.00 2.06 V 2.04 2.10 2.16 V -- 40 -- mV -- VBG Bandgap voltage reference 0.97 1.00 1.03 V -- tLPO Internal low power oscillator period -- factory trimmed 900 1000 1100 s -- 1. Rising thresholds are falling threshold + hysteresis voltage 2.2.3 Voltage and current operating behaviors Table 7. Voltage and current operating behaviors Symbol VOH Description Min. Unit Output high voltage -- Normal drive pad (except RESET) * 2.7 V VDD 3.6 V, IOH = -5 mA * 1.71 V VDD 2.7 V, IOH = -2.5 mA VOH Max. 1, 2 VDD - 0.5 -- V VDD - 0.5 -- V Output high voltage -- High drive pad (except RESET) * 2.7 V VDD 3.6 V, IOH = -20 mA * 1.71 V VDD 2.7 V, IOH = -10 mA IOHT Output high current total for all ports VOL Output low voltage -- Normal drive pad Notes 1, 2 VDD - 0.5 -- V VDD - 0.5 -- V -- 100 mA -- 1 * 2.7 V VDD 3.6 V, IOL = 5 mA -- 0.5 V * 1.71 V VDD 2.7 V, IOL = 2.5 mA -- 0.5 V Table continues on the next page... 8 NXP Semiconductors Kinetis KL02 32 KB Flash, Rev. 5 08/2017 General Table 7. Voltage and current operating behaviors (continued) Symbol VOL Description Min. Max. Unit Notes Output low voltage -- High drive pad 1 * 2.7 V VDD 3.6 V, IOL = 20 mA -- * 1.71 V VDD 2.7 V, IOL = 10 mA 0.5 V -- 0.5 V Output low current total for all ports -- 100 mA -- IIN Input leakage current (per pin) for full temperature range -- 1 A 3 IIN Input leakage current (per pin) at 25 C -- 0.025 A 3 IIN Input leakage current (total all pins) for full temperature range -- 41 A 3 IOZ Hi-Z (off-state) leakage current (per pin) -- 1 A -- RPU Internal pullup resistors 20 50 k 4 IOLT 1. PTA12, PTA13, PTB0 and PTB1 I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. 2. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When configured as a GPIO output, it acts as a pseudo open drain output. 3. Measured at VDD = 3.6 V 4. Measured at VDD supply voltage = VDD min and Vinput = VSS 2.2.4 Power mode transition operating behaviors All specifications except tPOR and VLLSxRUN recovery times in the following table assume this clock configuration: * CPU and system clocks = 48 MHz * Bus and flash clock = 24 MHz * FEI clock mode POR and VLLSxRUN recovery use FEI clock mode at the default CPU and system frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz. Table 8. Power mode transition operating behaviors Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.8 V to execution of the first instruction across the operating temperature range of the chip. Min. Typ. Max. Unit -- -- 300 s -- 95 115 s 1 * VLLS0 RUN Table continues on the next page... Kinetis KL02 32 KB Flash, Rev. 5 08/2017 9 NXP Semiconductors General Table 8. Power mode transition operating behaviors (continued) Symbol Description Min. Typ. Max. Unit -- 93 115 s -- 42 53 s -- 4 4.4 s -- 4 4.4 s * VLLS1 RUN * VLLS3 RUN * VLPS RUN * STOP RUN 1. Normal boot (FTFA_FOPT[LPBOOT]=11). 2.2.5 Power consumption operating behaviors The maximum values stated in the following table represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). Table 9. Power consumption operating behaviors Symbol Temp. Typ. Max Unit Note Analog supply current -- -- See note mA 1 Run mode current in compute operation 48 MHz core / 24 MHz flash / bus clock disabled, code of while(1) loop executing from flash, at 3.0 V -- 3.6 4 mA 2 IDD_RUN Run mode current - 48 MHz core / 24 MHz bus and flash, all peripheral clocks disabled, code executing from flash, at 3.0 V -- 4.3 4.6 mA 2 IDD_RUN Run mode current - 48 MHz core / 24 MHz bus and flash, all peripheral clocks enabled, code executing from flash, at 3.0 V at 25 C 4.8 5 mA 2, 3 at 125 C 5 5.2 mA IDDA IDD_RUNCO Description IDD_WAIT Wait mode current - core disabled / 48 MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled, at 3.0 V -- 2.3 2.6 mA 2 IDD_WAIT Wait mode current - core disabled / 24 MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled, at 3.0 V -- 1.8 2.1 mA 2 Stop mode current with partial stop 2 clocking option - core and system disabled / 10.5 MHz bus, at 3.0 V -- 1.3 1.5 mA 2 IDD_PSTOP2 Table continues on the next page... 10 NXP Semiconductors Kinetis KL02 32 KB Flash, Rev. 5 08/2017 General Table 9. Power consumption operating behaviors (continued) Symbol Description Temp. Typ. Max Unit Note IDD_VLPRCO Very low power run mode current in compute operation - 4 MHz core / 0.8 MHz flash / bus clock disabled, code executing from flash, at 3.0 V -- 145 198 A 4 IDD_VLPR Very low power run mode current - 4 MHz core / 0.8 MHz bus and flash, all peripheral clocks disabled, code executing from flash, at 3.0 V -- 165 217 A 4 IDD_VLPR Very low power run mode current - 4 MHz core / 0.8 MHz bus and flash, all peripheral clocks enabled, code executing from flash, at 3.0 V -- 185 237 A 3, 4 IDD_VLPW Very low power wait mode current - core disabled / 4 MHz system / 0.8 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled, at 3.0 V -- 86 141 A 4 IDD_STOP Stop mode current at 3.0 V at 25 C 230 268 A -- at 50 C 238 301 A at 70 C 259 307 A at 85 C 290 352 A at 105 C 341 437 A at 25 C 2.3 4.28 A at 50 C 4.75 8.29 A at 70 C 10.1 17.63 A at 85 C 20.23 33.55 A at 105 C 40.54 64.75 A at 25 C 1.12 1.33 A at 50 C 1.59 2.12 A at 70 C 2.81 3.57 A at 85 C 5.26 6.45 A at 105 C 10.82 13.59 A at 25 C 0.58 0.69 A at 50 C 0.9 1.04 A at 70 C 1.68 2.02 A at 85 C 3.51 4.05 A at 105 C 7.89 9.42 A at 25 C 0.3 0.4 A at 50 C 0.62 0.75 A at 70 C 1.38 1.71 A at 85 C 3.16 3.71 A at 105 C 7.44 8.98 A IDD_VLPS IDD_VLLS3 IDD_VLLS1 IDD_VLLS0 Very-low-power stop mode current at 3.0 V Very low-leakage stop mode 3 current at 3.0 V Very low-leakage stop mode 1 current at 3.0 V Very low-leakage stop mode 0 current (SMC_STOPCTRL[PORPO] = 0) at 3.0 V -- -- -- -- Table continues on the next page... Kinetis KL02 32 KB Flash, Rev. 5 08/2017 11 NXP Semiconductors General Table 9. Power consumption operating behaviors (continued) Symbol Description IDD_VLLS0 Very low-leakage stop mode 0 current (SMC_STOPCTRL[PORPO] = 1) at 3.0 V Temp. Typ. Max Unit Note at 25 C 0.12 0.23 A 5 at 50 C 0.44 0.58 A at 70 C 1.21 1.55 A at 85 C 3.01 3.57 A at 105 C 7.34 8.89 A 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. MCG configured for FEI mode. 3. Incremental current consumption from peripheral activity is not included. 4. MCG configured for BLPI mode. 5. No brownout. Table 10. Low power mode peripheral adders -- typical value Symbol Description Temperature (C) Unit -40 25 50 70 85 105 IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder. Measured by entering STOP or VLPS mode with 4 MHz IRC enabled. 56 56 56 56 56 56 A IIREFSTEN32KHz 32 kHz internal reference clock (IRC) adder. Measured by entering STOP mode with the 32 kHz IRC enabled. 52 52 52 52 52 52 A IEREFSTEN32KHz External 32 kHz crystal clock adder by means of the OSC0_CR[EREFSTEN and EREFSTEN] bits. Measured by entering all modes with the crystal enabled. VLLS1 440 490 540 560 570 580 nA VLLS3 440 490 540 560 570 580 VLPS 510 560 560 560 610 680 STOP 510 560 560 560 610 680 ICMP CMP peripheral adder measured by placing the device in VLLS1 mode with CMP enabled using the 6-bit DAC and a single external input for compare. Includes 6-bit DAC power consumption. 22 22 22 22 22 22 A IUART UART peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source waiting for RX data at 115200 baud rate. Includes selected clock source power consumption. MCGIRCLK (4 MHz internal reference clock) 66 66 66 66 66 66 A ITPM TPM peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source configured for output compare generating 100 Hz MCGIRCLK (4 MHz internal reference clock) 86 86 86 86 86 86 A Table continues on the next page... 12 NXP Semiconductors Kinetis KL02 32 KB Flash, Rev. 5 08/2017 General Table 10. Low power mode peripheral adders -- typical value (continued) Symbol Description clock signal. No load is placed on the I/O generating the clock signal. Includes selected clock source and I/O switching currents. Temperature (C) OSCERCLK (4 MHz external crystal) Unit -40 25 50 70 85 105 235 256 265 274 280 287 IBG Bandgap adder when BGEN bit is set and device is placed in VLPx, or VLLSx mode. 45 45 45 45 45 45 A IADC ADC peripheral adder combining the measured values at VDD and VDDA by placing the device in STOP or VLPS mode. ADC is configured for low power mode using the internal clock and continuous conversions. 366 366 366 366 366 366 A 2.2.5.1 Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: * * * * MCG in FBE for run mode, and BLPE for VLPR mode No GPIOs toggled Code execution from flash with cache enabled For the ALLOFF curve, all peripheral clocks are disabled except FTFA Kinetis KL02 32 KB Flash, Rev. 5 08/2017 13 NXP Semiconductors General Run Mode Current VS Core Frequency Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = FBE 7.00E-03 6.00E-03 Current Consumption on VDD (A) 5.00E-03 4.00E-03 All Peripheral CLK Gates All Off All On 3.00E-03 2.00E-03 1.00E-03 000.00E+00 '1-1 1 '1-1 2 '1-1 '1-1 '1-1 '1-1 '1-1 '1-2 3 4 6 12 24 48 CLK Ratio Flash-Core Core Freq (MHz) Figure 3. Run mode supply current vs. core frequency 14 NXP Semiconductors Kinetis KL02 32 KB Flash, Rev. 5 08/2017 General VLPR Mode Current VS Core Frequency Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = BLPE 350.00E-06 300.00E-06 Current Consumption on VDD (A) 250.00E-06 200.00E-06 All Peripheral CLK Gates All Off All On 150.00E-06 100.00E-06 50.00E-06 000.00E+00 '1-1 '1-2 1 '1-2 '1-4 2 4 CLK Ratio Flash-Core Core Freq (MHz) Figure 4. VLPR mode current vs. core frequency 2.2.6 EMC radiated emissions operating behaviors Table 11. EMC radiated emissions operating behaviors for 32-pin QFN package Symbol Description Frequency band (MHz) Typ. Unit Notes 1, 2 VRE1 Radiated emissions voltage, band 1 0.15-50 7 dBV VRE2 Radiated emissions voltage, band 2 50-150 6 dBV VRE3 Radiated emissions voltage, band 3 150-500 4 dBV VRE4 Radiated emissions voltage, band 4 500-1000 4 dBV IEC level 0.15-1000 N -- VRE_IEC 2, 3 1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions--TEM Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. Kinetis KL02 32 KB Flash, Rev. 5 08/2017 15 NXP Semiconductors General 2. VDD = 3.3 V, TA = 25 C, fOSC = 32.768 kHz (crystal), fSYS = 48 MHz, fBUS = 24 MHz 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions--TEM Cell and Wideband TEM Cell Method 2.2.7 EMC Radiated Emissions Web Search Procedure boilerplate To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to www.nxp.com. 2. Perform a keyword search for "EMC design" 2.2.8 Capacitance attributes Table 12. Capacitance attributes Symbol CIN Description Input capacitance Min. Max. Unit -- 7 pF Min. Max. Unit 2.3 Switching specifications 2.3.1 Device clock specifications Table 13. Device clock specifications Symbol Description Normal run mode fSYS System and core clock -- 48 MHz fBUS Bus clock -- 24 MHz fFLASH Flash clock -- 24 MHz fLPTMR LPTMR clock -- 24 MHz VLPR and VLPS modes1 fSYS System and core clock -- 4 MHz fBUS Bus clock -- 1 MHz fFLASH Flash clock -- 1 MHz fLPTMR LPTMR clock2 -- 24 MHz fERCLK External reference clock -- 32.768 kHz -- 16 MHz -- 8 MHz fLPTMR_ERCLK LPTMR external reference clock fTPM TPM asynchronous clock Table continues on the next page... 16 NXP Semiconductors Kinetis KL02 32 KB Flash, Rev. 5 08/2017 General Table 13. Device clock specifications (continued) Symbol fUART0 Description UART0 asynchronous clock Min. Max. Unit -- 8 MHz 1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN or from VLPR. 2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin. 2.3.2 General switching specifications These general-purpose specifications apply to all signals configured for GPIO and UART signals. Table 14. General switching specifications Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) -- Synchronous path 1.5 -- Bus clock cycles 1 External RESET and NMI pin interrupt pulse width -- Asynchronous path 100 -- ns 2 GPIO pin interrupt pulse width -- Asynchronous path 16 -- ns 2 Port rise and fall time -- 36 ns 3 1. The greater synchronous and asynchronous timing must be met. 2. This is the shortest pulse that is guaranteed to be recognized. 3. 75 pF load 2.4 Thermal specifications 2.4.1 Thermal operating requirements Table 15. Thermal operating requirements Symbol Description Min. Max. Unit TJ Die junction temperature -40 125 C TA Ambient temperature -40 105 C Notes 1 1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to determine TJ is: TJ = TA + JA x chip power dissipation. Kinetis KL02 32 KB Flash, Rev. 5 08/2017 17 NXP Semiconductors Peripheral operating requirements and behaviors 2.4.2 Thermal attributes Table 16. Thermal attributes Board type Symbol Single-layer (1S) RJA Four-layer (2s2p) Description 16 QFN 24 QFN 32 QFN Unit Notes Thermal resistance, junction to ambient (natural convection) 141 114 101 C/W 1 RJA Thermal resistance, junction to ambient (natural convection) 55 42 35 C/W Single-layer (1S) RJMA Thermal resistance, junction to ambient (200 ft./min. air speed) 120 96 84 C/W Four-layer (2s2p) RJMA Thermal resistance, junction to ambient (200 ft./min. air speed) 49 36 30 C/W -- RJB Thermal resistance, junction to board 27 19 15 C/W 2 -- RJC Thermal resistance, junction to case 20 3.4 3.4 C/W 3 -- JT Thermal characterization parameter, junction to package top outside center (natural convection) 23 15 11 C/W 4 1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions--Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions--Forced Convection (Moving Air). 2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions--Junction-to-Board. 3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions--Natural Convection (Still Air). 3 Peripheral operating requirements and behaviors 3.1 Core modules 3.1.1 SWD electricals Table 17. SWD full voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 1.71 3.6 V SWD_CLK frequency of operation Table continues on the next page... 18 NXP Semiconductors Kinetis KL02 32 KB Flash, Rev. 5 08/2017 Peripheral operating requirements and behaviors Table 17. SWD full voltage range electricals (continued) Symbol Description Min. Max. Unit 0 25 MHz 1/J1 -- ns 20 -- ns * Serial wire debug J2 SWD_CLK cycle period J3 SWD_CLK clock pulse width * Serial wire debug J4 SWD_CLK rise and fall times -- 3 ns J9 SWD_DIO input data setup time to SWD_CLK rise 10 -- ns J10 SWD_DIO input data hold time after SWD_CLK rise 0 -- ns J11 SWD_CLK high to SWD_DIO data valid -- 32 ns J12 SWD_CLK high to SWD_DIO high-Z 5 -- ns J2 J3 J3 SWD_CLK (input) J4 J4 Figure 5. Serial wire clock input timing SWD_CLK J9 SWD_DIO J10 Input data valid J11 SWD_DIO Output data valid J12 SWD_DIO J11 SWD_DIO Output data valid Figure 6. Serial wire data timing Kinetis KL02 32 KB Flash, Rev. 5 08/2017 19 NXP Semiconductors Peripheral operating requirements and behaviors 3.2 System modules There are no specifications necessary for the device's system modules. 3.3 Clock modules 3.3.1 MCG specifications Table 18. MCG specifications Symbol Description Min. Typ. Max. Unit Notes fints_ft Internal reference frequency (slow clock) -- factory trimmed at nominal VDD and 25 C -- 32.768 -- kHz fints_t Internal reference frequency (slow clock) -- user trimmed 31.25 -- 39.0625 kHz -- 0.3 0.6 %fdco 1 fdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature -- using C3[SCTRIM] and C4[SCFTRIM] fdco_t Total deviation of trimmed average DCO output frequency over voltage and temperature -- +0.5/-0.7 3 %fdco 1, 2 fdco_t Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0-70 C -- 0.4 1.5 %fdco 1, 2 Internal reference frequency (fast clock) -- factory trimmed at nominal VDD and 25 C -- 4 -- MHz fintf_ft Frequency deviation of internal reference clock (fast clock) over temperature and voltage -- factory trimmed at nominal VDD and 25 C -- +1/-2 3 %fintf_ft fintf_t Internal reference frequency (fast clock) -- user trimmed at nominal VDD and 25 C 3 -- 5 MHz fintf_ft floc_low Loss of external clock minimum frequency -- RANGE = 00 (3/5) x fints_t -- -- kHz floc_high Loss of external clock minimum frequency -- RANGE = 01, 10, or 11 (16/5) x fints_t -- -- kHz 31.25 -- 39.0625 kHz 20 20.97 25 MHz 40 41.94 48 MHz -- 23.99 -- MHz 2 FLL ffll_ref fdco FLL reference frequency range DCO output frequency range Low range (DRS = 00) 3, 4 640 x ffll_ref Mid range (DRS = 01) 1280 x ffll_ref fdco_t_DMX3 DCO output frequency 2 Low range (DRS = 00) 5, 6 Table continues on the next page... 20 NXP Semiconductors Kinetis KL02 32 KB Flash, Rev. 5 08/2017 Peripheral operating requirements and behaviors Table 18. MCG specifications (continued) Symbol Description Min. Typ. Max. Unit Notes -- 47.97 -- MHz -- 180 -- ps 7 -- -- 1 ms 8 732 x ffll_ref Mid range (DRS = 01) 1464 x ffll_ref Jcyc_fll FLL period jitter * fVCO = 48 MHz tfll_acquire FLL target frequency acquisition time 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 C, fints_ft. 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0. 4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation (fdco_t) over voltage and temperature must be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification is based on standard deviation (RMS) of period or frequency. 8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 3.3.2 Oscillator electrical specifications 3.3.2.1 Oscillator DC electrical specifications Table 19. Oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 -- 3.6 V IDDOSC Supply current -- low-power mode (HGO=0) * 32 kHz IDDOSC 1 -- 500 -- nA Supply current -- high gain mode (HGO=1) * 32 kHz Notes 1 -- 25 -- A Cx EXTAL load capacitance -- -- -- 2, 3 Cy XTAL load capacitance -- -- -- 2, 3 RF Feedback resistor -- low-frequency, low-power mode (HGO=0) -- -- -- M Feedback resistor -- low-frequency, high-gain mode (HGO=1) -- 10 -- M Series resistor -- low-frequency, low-power mode (HGO=0) -- -- -- k RS 2, 4 Table continues on the next page... Kinetis KL02 32 KB Flash, Rev. 5 08/2017 21 NXP Semiconductors Peripheral operating requirements and behaviors Table 19. Oscillator DC electrical specifications (continued) Symbol Vpp5 1. 2. 3. 4. 5. Description Min. Typ. Max. Unit Series resistor -- low-frequency, high-gain mode (HGO=1) -- 200 -- k Peak-to-peak amplitude of oscillation (oscillator mode) -- low-frequency, low-power mode (HGO=0) -- 0.6 -- V Peak-to-peak amplitude of oscillation (oscillator mode) -- low-frequency, high-gain mode (HGO=1) -- VDD -- V Notes VDD=3.3 V, Temperature =25 C See crystal or resonator manufacturer's recommendation Cx,Cy can be provided by using either the integrated capacitors or by using external components. When low power mode is selected, RF is integrated and must not be attached externally. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 3.3.2.2 Symbol fosc_lo tdc_extal tcst Oscillator frequency specifications Table 20. Oscillator frequency specifications Description Min. Typ. Max. Unit Oscillator crystal or resonator frequency -- low frequency mode (MCG_C2[RANGE]=00) 32 -- 40 kHz Input clock duty cycle (external clock mode) 40 50 60 % Crystal startup time -- 32 kHz low-frequency, low-power mode (HGO=0) -- -- ms Crystal startup time -- 32 kHz low-frequency, high-gain mode (HGO=1) -- -- ms Notes 1, 2 1. Proper PC board layout procedures must be followed to achieve specifications. 2. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. 3.4 Memories and memory interfaces 3.4.1 Flash electrical specifications This section describes the electrical characteristics of the flash memory module. 22 NXP Semiconductors Kinetis KL02 32 KB Flash, Rev. 5 08/2017 Peripheral operating requirements and behaviors 3.4.1.1 Flash timing specifications -- program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 21. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit Notes thvpgm4 Longword Program high-voltage time -- 7.5 18 s -- thversscr Sector Erase high-voltage time -- 13 113 ms 1 thversall Erase All high-voltage time -- 52 452 ms 1 1. Maximum time based on expectations at cycling end-of-life. 3.4.1.2 Flash timing specifications -- commands Table 22. Flash command timing specifications Symbol Description Min. Typ. Max. Unit Notes trd1sec1k tpgmchk Read 1s Section execution time (flash sector) -- -- 60 s 1 Program Check execution time -- -- 45 s 1 trdrsrc Read Resource execution time -- -- 30 s 1 tpgm4 Program Longword execution time -- 65 145 s -- tersscr Erase Flash Sector execution time -- 14 114 ms 2 trd1all Read 1s All Blocks execution time -- -- 0.5 ms -- trdonce Read Once execution time -- -- 25 s 1 Program Once execution time -- 65 -- s -- tersall Erase All Blocks execution time -- 61 500 ms 2 tvfykey Verify Backdoor Access Key execution time -- -- 30 s 1 tpgmonce 1. Assumes 25 MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3.4.1.3 Flash high voltage current behaviors Table 23. Flash high voltage current behaviors Symbol Description Min. Typ. Max. Unit IDD_PGM Average current adder during high voltage flash programming operation -- 2.5 6.0 mA IDD_ERS Average current adder during high voltage flash erase operation -- 1.5 4.0 mA Kinetis KL02 32 KB Flash, Rev. 5 08/2017 23 NXP Semiconductors Peripheral operating requirements and behaviors 3.4.1.4 Symbol Reliability specifications Table 24. NVM reliability specifications Description Min. Typ.1 Max. Unit Notes Program Flash tnvmretp10k Data retention after up to 10 K cycles 5 50 -- years -- tnvmretp1k Data retention after up to 1 K cycles 20 100 -- years -- nnvmcycp Cycling endurance 10 K 50 K -- cycles 2 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40 C Tj 125 C. 3.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 3.6 Analog 3.6.1 ADC electrical specifications All ADC channels meet the 12-bit single-ended accuracy specifications. 3.6.1.1 12-bit ADC operating conditions Table 25. 12-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit Notes VDDA Supply voltage Absolute 1.71 -- 3.6 V -- VDDA Supply voltage Delta to VDD (VDD - VDDA) -100 0 +100 mV 2 VSSA Ground voltage Delta to VSS (VSS - VSSA) -100 0 +100 mV 2 VREFH ADC reference voltage high 1.13 VDDA VDDA V 3 VREFL ADC reference voltage low VSSA VSSA VSSA V 3 VADIN Input voltage VREFL -- VREFH V -- CADIN Input capacitance -- 4 5 pF -- RADIN Input series resistance -- 2 5 k -- * 8-bit / 10-bit / 12-bit modes Table continues on the next page... 24 NXP Semiconductors Kinetis KL02 32 KB Flash, Rev. 5 08/2017 Peripheral operating requirements and behaviors Table 25. 12-bit ADC operating conditions (continued) Min. Typ.1 Symbol Description Conditions Max. Unit RAS Analog source resistance (external) 12-bit modes fADCK < 4 MHz -- -- 5 k fADCK ADC conversion clock frequency 12-bit mode 1.0 -- 18.0 MHz Crate ADC conversion rate 12-bit modes Notes 4 5 6 No ADC hardware averaging 20.000 -- 818.330 Ksps Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to VSSA. 4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. 5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT Pad leakage due to input protection ZAS RAS ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN ADC SAR ENGINE VADIN VAS CAS RADIN INPUT PIN INPUT PIN RADIN RADIN INPUT PIN CADIN Figure 7. ADC input impedance equivalency diagram Kinetis KL02 32 KB Flash, Rev. 5 08/2017 25 NXP Semiconductors Peripheral operating requirements and behaviors 3.6.1.2 12-bit ADC electrical characteristics Table 26. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) Symbol Description IDDA_ADC Supply current ADC asynchronous clock source fADACK Conditions1 * ADLPC = 1, ADHSC = 0 * ADLPC = 1, ADHSC = 1 * ADLPC = 0, ADHSC = 0 Min. Typ.2 Max. Unit Notes 0.215 -- 1.7 mA 3 1.2 2.4 3.9 MHz 2.4 4.0 6.1 MHz tADACK = 1/fADACK 3.0 5.2 7.3 MHz 4.4 6.2 9.5 MHz LSB4 5 LSB4 5 LSB4 5 LSB4 VADIN = VDDA5 * ADLPC = 0, ADHSC = 1 Sample Time TUE DNL INL EFS See Reference Manual chapter for sample times Total unadjusted error * 12-bit modes -- 4 6.8 * <12-bit modes -- 1.4 2.1 Differential nonlinearity * 12-bit modes -- 0.7 -1.1 to +1.9 * <12-bit modes -- 0.2 * 12-bit modes -- 1.0 * <12-bit modes -- 0.5 * 12-bit modes -- -4 -5.4 * <12-bit modes -- -1.4 -1.8 * 12-bit modes -- -- 0.5 Integral nonlinearity Full-scale error EQ Quantization error EIL Input leakage error -0.3 to 0.5 -2.7 to +1.9 -0.7 to +0.5 IIn x RAS LSB4 mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) VTEMP25 Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/C 6 Temp sensor voltage 25 C 706 716 726 mV 6 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 26 NXP Semiconductors Kinetis KL02 32 KB Flash, Rev. 5 08/2017 Peripheral operating requirements and behaviors 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. ADC conversion clock < 3 MHz ENOB Typical ADC 12-bit Single Ended ENOB vs ADC Clock 11.9 11.8 11.7 11.6 11.5 11.4 11.3 11.2 11.1 11 10.9 10.8 10.7 10.6 10.5 10.4 10.3 10.2 10.1 10 100Hz, 90% FS Sine Input Hardware Averaging Disabled Averaging of 8 samples Averaging of 32 samples 0 2 4 6 8 10 12 14 16 18 20 22 ADC Clock Frequency (MHz) Figure 8. Typical ENOB vs. ADC_CLK for 12-bit single-ended mode 3.6.2 CMP and 6-bit DAC electrical specifications Table 27. Comparator and 6-bit DAC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 -- 3.6 V IDDHS Supply current, High-speed mode (EN=1, PMODE=1) -- -- 200 A IDDLS Supply current, low-speed mode (EN=1, PMODE=0) -- -- 20 A VAIN Analog input voltage VSS - 0.3 -- VDD V VAIO Analog input offset voltage -- -- 20 mV * CR0[HYSTCTR] = 00 -- 5 -- mV * CR0[HYSTCTR] = 01 -- 10 -- mV * CR0[HYSTCTR] = 10 -- 20 -- mV * CR0[HYSTCTR] = 11 -- 30 -- mV VH Analog comparator hysteresis1 VCMPOh Output high VDD - 0.5 -- -- V VCMPOl Output low -- -- 0.5 V Table continues on the next page... Kinetis KL02 32 KB Flash, Rev. 5 08/2017 27 NXP Semiconductors Peripheral operating requirements and behaviors Table 27. Comparator and 6-bit DAC electrical specifications (continued) Symbol Description Min. Typ. Max. Unit tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 -- -- 40 s 6-bit DAC current adder (enabled) -- 7 -- A IDAC6b INL 6-bit DAC integral non-linearity -0.5 -- 0.5 LSB3 DNL 6-bit DAC differential non-linearity -0.3 -- 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 0.08 0.07 CMP Hystereris (V) 0.06 HYSTCTR Setting 0.05 00 0.04 01 10 11 0.03 0.02 0.01 0 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vin level (V) Figure 9. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) 28 NXP Semiconductors Kinetis KL02 32 KB Flash, Rev. 5 08/2017 Peripheral operating requirements and behaviors 0.18 0.16 0.14 CMP Hysteresis (V) 0.12 HYSTCTR Setting 0.1 00 01 10 11 0.08 0.06 0.04 0.02 0 0.1 0.4 0.7 1 1.3 1.6 1.9 Vin level (V) 2.2 2.5 2.8 3.1 Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) 3.7 Timers See General switching specifications. 3.8 Communication interfaces 3.8.1 SPI switching specifications The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes. See the SPI chapter of the chip's Reference Manual for information about the modified transfer formats used for communicating with slower peripheral devices. All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins. Kinetis KL02 32 KB Flash, Rev. 5 08/2017 29 NXP Semiconductors Peripheral operating requirements and behaviors Table 28. SPI master mode timing on slew rate disabled pads Num. Symbol 1 fop 2 tSPSCK 3 tLead 4 tLag 5 tWSPSCK 6 tSU 7 Min. Max. Unit Note fperiph/2048 fperiph/2 Hz 1 2 x tperiph 2048 x tperiph ns 2 Enable lead time 1/2 -- tSPSCK -- Enable lag time 1/2 -- tSPSCK -- tperiph - 30 1024 x tperiph ns -- Data setup time (inputs) 20 -- ns -- tHI Data hold time (inputs) 0 -- ns -- 8 tv Data valid (after SPSCK edge) -- 12 ns -- 9 tHO Data hold time (outputs) 0 -- ns -- 10 tRI Rise time input -- tperiph - 25 ns -- tFI Fall time input tRO Rise time output -- 25 ns -- tFO Fall time output 11 Description Frequency of operation SPSCK period Clock (SPSCK) high or low time 1. For SPI0, fperiph is the bus clock (fBUS). 2. tperiph = 1/fperiph Table 29. SPI master mode timing on slew rate enabled pads Num. Symbol Description 1 fop 2 tSPSCK 3 tLead Enable lead time 4 tLag Enable lag time 5 tWSPSCK 6 tSU 7 Frequency of operation SPSCK period Min. Max. Unit Note fperiph/2048 fperiph/2 Hz 1 2 x tperiph 2048 x tperiph ns 2 1/2 -- tSPSCK -- 1/2 -- tSPSCK -- tperiph - 30 1024 x tperiph ns -- Data setup time (inputs) 96 -- ns -- tHI Data hold time (inputs) 0 -- ns -- 8 tv Data valid (after SPSCK edge) -- 52 ns -- 9 tHO Data hold time (outputs) 0 -- ns -- 10 tRI Rise time input -- tperiph - 25 ns -- tFI Fall time input tRO Rise time output -- 36 ns -- tFO Fall time output 11 Clock (SPSCK) high or low time 1. For SPI0, fperiph is the bus clock (fBUS). 2. tperiph = 1/fperiph 30 NXP Semiconductors Kinetis KL02 32 KB Flash, Rev. 5 08/2017 Peripheral operating requirements and behaviors SS1 (OUTPUT) 3 2 SPSCK (CPOL=0) (OUTPUT) 10 11 10 11 4 5 5 SPSCK (CPOL=1) (OUTPUT) 6 MISO (INPUT) 7 MSB IN2 BIT 6 . . . 1 LSB IN 8 MOSI (OUTPUT) MSB OUT2 9 BIT 6 . . . 1 LSB OUT 1. If configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 11. SPI master mode timing (CPHA = 0) SS1 (OUTPUT) 2 3 SPSCK (CPOL=0) (OUTPUT) 5 SPSCK (CPOL=1) (OUTPUT) 5 6 MISO (INPUT) 11 10 11 4 7 MSB IN2 BIT 6 . . . 1 LSB IN 9 8 MOSI (OUTPUT) 10 PORT DATA MASTER MSB OUT2 BIT 6 . . . 1 MASTER LSB OUT PORT DATA 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 12. SPI master mode timing (CPHA = 1) Table 30. SPI slave mode timing on slew rate disabled pads Num. Symbol 1 fop 2 tSPSCK 3 tLead Description Min. Max. Unit Note 0 fperiph/4 Hz 1 4 x tperiph -- ns 2 1 -- tperiph -- Frequency of operation SPSCK period Enable lead time Table continues on the next page... Kinetis KL02 32 KB Flash, Rev. 5 08/2017 31 NXP Semiconductors Peripheral operating requirements and behaviors Table 30. SPI slave mode timing on slew rate disabled pads (continued) Num. Symbol 4 tLag 5 tWSPSCK 6 tSU Data setup time (inputs) 7 tHI Data hold time (inputs) 8 ta Slave access time 9 tdis Slave MISO disable time 10 tv 11 12 13 1. 2. 3. 4. Description Min. Max. Unit Note 1 -- tperiph -- tperiph - 30 -- ns -- 3 -- ns -- 7 -- ns -- 23 tperiph ns 3 23 tperiph ns 4 Data valid (after SPSCK edge) -- 25.7 ns -- tHO Data hold time (outputs) 0 -- ns -- tRI Rise time input -- tperiph - 25 ns -- tFI Fall time input tRO Rise time output -- 25 ns -- tFO Fall time output Enable lag time Clock (SPSCK) high or low time For SPI0, fperiph is the bus clock (fBUS). tperiph = 1/fperiph Time to data active from high-impedance state Hold time to high-impedance state Table 31. SPI slave mode timing on slew rate enabled pads Num. Symbol 1 fop 2 tSPSCK 3 tLead 4 tLag 5 tWSPSCK 6 tSU 7 tHI 8 Min. Max. Unit Note 0 fperiph/4 Hz 1 4 x tperiph -- ns 2 Enable lead time 1 -- tperiph -- Enable lag time 1 -- tperiph -- tperiph - 30 -- ns -- Data setup time (inputs) 2 -- ns -- Data hold time (inputs) 7 -- ns -- ta Slave access time -- tperiph ns 3 9 tdis Slave MISO disable time -- tperiph ns 4 10 tv Data valid (after SPSCK edge) -- 122 ns -- 11 tHO Data hold time (outputs) 0 -- ns -- 12 tRI Rise time input -- tperiph - 25 ns -- tFI Fall time input tRO Rise time output -- 36 ns -- tFO Fall time output 13 1. 2. 3. 4. Description Frequency of operation SPSCK period Clock (SPSCK) high or low time For SPI0, fperiph is the bus clock (fBUS). tperiph = 1/fperiph Time to data active from high-impedance state Hold time to high-impedance state 32 NXP Semiconductors Kinetis KL02 32 KB Flash, Rev. 5 08/2017 Peripheral operating requirements and behaviors SS (INPUT) 2 12 13 12 13 4 SPSCK (CPOL=0) (INPUT) 5 3 SPSCK (CPOL=1) (INPUT) 5 9 8 see note MISO (OUTPUT) SLAVE MSB 6 MOSI (INPUT) 10 11 11 BIT 6 . . . 1 SLAVE LSB OUT SEE NOTE 7 MSB IN BIT 6 . . . 1 LSB IN NOTE: Not defined Figure 13. SPI slave mode timing (CPHA = 0) SS (INPUT) 4 2 3 SPSCK (CPOL=0) (INPUT) 5 SPSCK (CPOL=1) (INPUT) 5 see note 8 MOSI (INPUT) SLAVE 13 12 13 11 10 MISO (OUTPUT) 12 MSB OUT 6 9 BIT 6 . . . 1 SLAVE LSB OUT BIT 6 . . . 1 LSB IN 7 MSB IN NOTE: Not defined Figure 14. SPI slave mode timing (CPHA = 1) Kinetis KL02 32 KB Flash, Rev. 5 08/2017 33 NXP Semiconductors Peripheral operating requirements and behaviors 3.8.2 Inter-Integrated Circuit Interface (I2C) timing Table 32. I2C timing Characteristic Symbol Standard Mode Fast Mode Minimum Maximum Minimum Maximum Unit SCL Clock Frequency fSCL 0 1001 0 4002 kHz Hold time (repeated) START condition. After this period, the first clock pulse is generated. tHD; STA 4 -- 0.6 -- s LOW period of the SCL clock tLOW 4.7 -- 1.25 -- s HIGH period of the SCL clock tHIGH 4 -- 0.6 -- s Set-up time for a repeated START condition tSU; STA 4.7 -- 0.6 -- s Data hold time for I2C bus devices tHD; DAT 03 3.454 05 0.93 s tSU; DAT 2506 -- 1004, 7 Data set-up time Rise time of SDA and SCL signals tr Fall time of SDA and SCL signals tf -- 1000 -- ns 8 300 ns 7 20 +0.1Cb -- 300 20 +0.1Cb 300 ns Set-up time for STOP condition tSU; STO 4 -- 0.6 -- s Bus free time between STOP and START condition tBUF 4.7 -- 1.3 -- s Pulse width of spikes that must be suppressed by the input filter tSP N/A N/A 0 50 ns 1. The PTB3 and PTB4 pins can support only the Standard mode. 2. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can be achieved only when using the normal drive pins and VDD 2.7 V. 3. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 4. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal. 5. Input signal Slew = 10 ns and Output Load = 50 pF 6. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty. 7. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; 2 DAT = 1000 + 250 = 1250 ns (according to the Standard mode I C bus specification) before the SCL line is released. 8. Cb = total capacitance of the one bus line in pF. Table 33. I 2C 1Mbit/s timing Characteristic Symbol Minimum Maximum Unit MHz SCL Clock Frequency fSCL 0 11 Hold time (repeated) START condition. After this period, the first clock pulse is generated. tHD; STA 0.26 -- s LOW period of the SCL clock tLOW 0.5 -- s HIGH period of the SCL clock tHIGH 0.26 -- s Set-up time for a repeated START condition tSU; STA 0.26 -- s Data hold time for I2C bus devices tHD; DAT 0 -- s Table continues on the next page... 34 NXP Semiconductors Kinetis KL02 32 KB Flash, Rev. 5 08/2017 Dimensions Table 33. I 2C 1Mbit/s timing (continued) Characteristic Symbol Minimum Maximum Unit Data set-up time tSU; DAT 50 -- ns Rise time of SDA and SCL signals tr 20 +0.1Cb 120 ns Fall time of SDA and SCL signals tf 20 +0.1Cb 2 120 ns Set-up time for STOP condition tSU; STO 0.26 -- s Bus free time between STOP and START condition tBUF 0.5 -- s Pulse width of spikes that must be suppressed by the input filter tSP 0 50 ns 1. The maximum SCL clock frequency of 1 Mbit/s can support 200 pF bus loading when using the normal drive pins and VDD 2.7 V. 2. Cb = total capacitance of the one bus line in pF. SDA tf tSU; DAT tr tLOW tf tHD; STA tSP tr tBUF SCL S HD; STA tHD; DAT tHIGH tSU; STA SR tSU; STO P S Figure 15. Timing definition for devices on the I2C bus 3.8.3 UART See General switching specifications. 4 Dimensions 4.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to nxp.com and perform a keyword search for the drawing's document number: Kinetis KL02 32 KB Flash, Rev. 5 08/2017 35 NXP Semiconductors Pinout If you want the drawing for this package Then use this document number 16-pin QFN 98ASA00525D 24-pin QFN 98ASA00474D 32-pin QFN 98ASA00473D 5 Pinout 5.1 KL02 signal multiplexing and pin assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. NOTE PTB3 and PTB4 are true open drain pins. To use these pins as outputs, you must use an external pullup resistor to make them output correct values when using I2C, GPIO, and UART0. 32 QFN 24 QFN 16 QFN Pin Name 1 1 -- PTB6/ IRQ_2/ LPTMR0_ALT3 DISABLED PTB6/ IRQ_2/ LPTMR0_ALT3 TPM1_CH1 2 2 -- PTB7/ IRQ_3 DISABLED PTB7/ IRQ_3 TPM1_CH0 3 3 1 VDD VDD VDD 4 3 1 VREFH VREFH VREFH 5 4 2 VREFL VREFL VREFL 6 4 2 VSS VSS VSS 7 5 3 PTA3 EXTAL0 EXTAL0 PTA3 I2C0_SCL I2C1_SDA 8 6 4 PTA4 XTAL0 XTAL0 PTA4 I2C0_SDA I2C1_SCL 9 7 5 PTA5 DISABLED PTA5 TPM0_CH1 SPI0_SS_b 10 8 6 PTA6 DISABLED PTA6 TPM0_CH0 SPI0_MISO 11 -- -- PTB8 ADC0_SE11 ADC0_SE11 PTB8 12 -- -- PTB9 ADC0_SE10 ADC0_SE10 PTB9 13 9 -- PTB10 ADC0_SE9 ADC0_SE9 PTB10 TPM0_CH1 14 10 -- PTB11 ADC0_SE8 ADC0_SE8 PTB11 TPM0_CH0 15 11 7 PTA7/ IRQ_4 ADC0_SE7 ADC0_SE7 PTA7/ IRQ_4 SPI0_MISO 36 NXP Semiconductors Default ALT0 ALT1 ALT2 ALT3 TPM_CLKIN1 SPI0_MOSI Kinetis KL02 32 KB Flash, Rev. 5 08/2017 Pinout 32 QFN 24 QFN 16 QFN Pin Name Default ALT0 ALT1 ALT2 ALT3 16 12 8 PTB0/ IRQ_5 ADC0_SE6 ADC0_SE6 PTB0/ IRQ_5 EXTRG_IN SPI0_SCK 17 13 9 PTB1/ IRQ_6 ADC0_SE5/ CMP0_IN3 ADC0_SE5/ CMP0_IN3 PTB1/ IRQ_6 UART0_TX UART0_RX 18 14 10 PTB2/ IRQ_7 ADC0_SE4 ADC0_SE4 PTB2/ IRQ_7 UART0_RX UART0_TX 19 15 -- PTA8 ADC0_SE3 ADC0_SE3 PTA8 I2C1_SCL 20 16 -- PTA9 ADC0_SE2 ADC0_SE2 PTA9 I2C1_SDA 21 -- -- PTA10/ IRQ_8 DISABLED PTA10/ IRQ_8 22 -- -- PTA11/ IRQ_9 DISABLED PTA11/ IRQ_9 23 17 11 PTB3/ IRQ_10 DISABLED PTB3/ IRQ_10 I2C0_SCL UART0_TX 24 18 12 PTB4/ IRQ_11 DISABLED PTB4/ IRQ_11 I2C0_SDA UART0_RX 25 19 13 PTB5/ IRQ_12 NMI_b ADC0_SE1/ CMP0_IN1 PTB5/ IRQ_12 TPM1_CH1 NMI_b 26 20 -- PTA12/ IRQ_13/ LPTMR0_ALT2 ADC0_SE0/ CMP0_IN0 ADC0_SE0/ CMP0_IN0 PTA12/ IRQ_13/ LPTMR0_ALT2 TPM1_CH0 TPM_CLKIN0 27 -- -- PTA13 DISABLED PTA13 28 -- -- PTB12 DISABLED PTB12 29 21 -- PTB13 ADC0_SE13 ADC0_SE13 PTB13 TPM1_CH1 30 22 14 PTA0/ IRQ_0 SWD_CLK ADC0_SE12/ CMP0_IN2 PTA0/ IRQ_0 TPM1_CH0 SWD_CLK 31 23 15 PTA1/ IRQ_1/ LPTMR0_ALT1 RESET_b PTA1/ IRQ_1/ LPTMR0_ALT1 TPM_CLKIN0 RESET_b 32 24 16 PTA2 SWD_DIO PTA2 CMP0_OUT SWD_DIO 5.2 KL02 pinouts The following figures show the pinout diagrams for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see KL02 signal multiplexing and pin assignments. Kinetis KL02 32 KB Flash, Rev. 5 08/2017 37 NXP Semiconductors PTA2 PTA1/IRQ_1/LPTMR0_ALT1 PTA0/IRQ_0 PTB13 PTB12 PTA13 PTA12/IRQ_13/LPTMR0_ALT2 PTB5/IRQ_12 32 31 30 29 28 27 26 25 Pinout 21 PTA10/IRQ_8 VREFL 5 20 PTA9 VSS 6 19 PTA8 PTA3 7 18 PTB2/IRQ_7 PTA4 8 17 PTB1/IRQ_6 PTA6 PTA5 16 4 PTB0/IRQ_5 VREFH 15 PTA11/IRQ_9 PTA7/IRQ_4 22 14 3 PTB11 VDD 13 PTB3/IRQ_10 PTB10 23 12 2 PTB9 PTB7/IRQ_3 11 PTB4/IRQ_11 PTB8 24 10 1 9 PTB6/IRQ_2/LPTMR0_ALT3 Figure 16. KL02 32-pin QFN pinout diagram 38 NXP Semiconductors Kinetis KL02 32 KB Flash, Rev. 5 08/2017 PTA2 PTA1/IRQ_1/LPTMR0_ALT1 PTA0/IRQ_0 PTB13 PTA12/IRQ_13/LPTMR0_ALT2 PTB5/IRQ_12 24 23 22 21 20 19 Pinout 3 16 PTA9 VREFL VSS 4 15 PTA8 PTA3 5 14 PTB2/IRQ_7 PTA4 6 13 PTB1/IRQ_6 PTB10 PTA6 PTA5 12 VDD VREFH PTB0/IRQ_5 PTB3/IRQ_10 11 17 PTA7/IRQ_4 2 10 PTB7/IRQ_3 PTB11 PTB4/IRQ_11 9 18 8 1 7 PTB6/IRQ_2/LPTMR0_ALT3 Figure 17. KL02 24-pin QFN pinout diagram Kinetis KL02 32 KB Flash, Rev. 5 08/2017 39 NXP Semiconductors PTA2 PTA1/IRQ_1/LPTMR0_ALT1 PTA0/IRQ_0 PTB5/IRQ_12 16 15 14 13 Ordering parts PTA3 3 10 PTB2/IRQ_7 PTA4 4 9 PTB1/IRQ_6 8 PTB3/IRQ_10 PTB0/IRQ_5 11 7 2 PTA7/IRQ_4 VREFL VSS 6 PTB4/IRQ_11 PTA6 12 5 1 PTA5 VDD VREFH Figure 18. KL02 16-pin QFN pinout diagram 6 Ordering parts 6.1 Determining valid orderable parts Valid orderable part numbers are provided on the Web. To determine the orderable part numbers for this device, go to nxp.com and perform a part number search for the following device numbers: PKL02 and MKL02 7 Part identification 7.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 40 NXP Semiconductors Kinetis KL02 32 KB Flash, Rev. 5 08/2017 Part identification 7.2 Format Part numbers for this device have the following format: Q KL## A FFF R T PP CC N 7.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Table 34. Part number fields descriptions Field Description Values Q Qualification status * M = Fully qualified, general market flow * P = Prequalification KL## Kinetis family * KL02 A Key attribute * Z = Cortex-M0+ FFF Program flash memory size * 8 = 8 KB * 16 = 16 KB * 32 = 32 KB R Silicon revision * (Blank) = Main * A = Revision after main T Temperature range (C) * V = -40 to 105 PP Package identifier * FG = 16 QFN (3 mm x 3 mm) * FK = 24 QFN (4 mm x 4 mm) * FM = 32 QFN (5 mm x 5 mm) CC Maximum CPU frequency (MHz) * 4 = 48 MHz N Packaging type * R = Tape and reel * (Blank) = Trays 7.4 Example This is an example part number: MKL02Z8VFG4 Kinetis KL02 32 KB Flash, Rev. 5 08/2017 41 NXP Semiconductors Small package marking 8 Small package marking In order to save space, small package devices use special marking on the chip. Q FS FF (TP) Table 35. Small package marking Field Description Values Q Qualification status * M=M * P=P FS Kinetis family and CPU frequency * (0)2T = KL02, 48 MHz of CPU FF Program flash memory size * 3 = 8 KB * 4 = 16 KB * 5 = 32 KB TP Temperature range (C) and package * V = -40 to 105, 24 or 32 QFN * blank = -40 to 105, 16 QFN For example: M2T4 = MKL02Z16VFG4 M02T4V = MKL02Z16VFK4 9 Terminology and guidelines 9.1 Definition: Operating requirement An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 9.1.1 Example This is an example of an operating requirement: Symbol VDD 42 NXP Semiconductors Description 1.0 V core supply voltage Min. 0.9 Max. 1.1 Unit V Kinetis KL02 32 KB Flash, Rev. 5 08/2017 Terminology and guidelines 9.2 Definition: Operating behavior Unless otherwise specified, an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 9.2.1 Example This is an example of an operating behavior: Symbol IWP Description Min. Digital I/O weak pullup/ 10 pulldown current Max. 130 Unit A 9.3 Definition: Attribute An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 9.3.1 Example This is an example of an attribute: Symbol CIN_D Description Input capacitance: digital pins Min. -- Max. 7 Unit pF 9.4 Definition: Rating A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: * Operating ratings apply during operation of the chip. * Handling ratings apply when the chip is not powered. Kinetis KL02 32 KB Flash, Rev. 5 08/2017 43 NXP Semiconductors Terminology and guidelines 9.4.1 Example This is an example of an operating rating: Symbol VDD Description 1.0 V core supply voltage Min. -0.3 Max. 1.2 Unit V 9.5 Result of exceeding a rating Failures in time (ppm) 40 30 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 20 10 0 Operating rating Measured characteristic 44 NXP Semiconductors Kinetis KL02 32 KB Flash, Rev. 5 08/2017 Terminology and guidelines 9.6 Relationship between ratings and operating requirements .) ) ) ing rat e Op g tin in. (m ra in. t (m ax t (m n me rat e Op ing ire qu re ing rat e Op .) en rem re i qu rat e Op ing g tin ra ax (m Fatal range Degraded operating range Normal operating range Degraded operating range Fatal range Expected permanent failure - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Correct operation - No permanent failure - Possible decreased life - Possible incorrect operation Expected permanent failure - Operating (power on) g lin nd Ha n.) mi g( in rat g( ng li nd Ha in rat .) x ma Fatal range Handling range Fatal range Expected permanent failure No permanent failure Expected permanent failure - Handling (power off) 9.7 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: * Never exceed any of the chip's ratings. * During normal operation, don't exceed any of the chip's operating requirements. * If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 9.8 Definition: Typical value A typical value is a specified value for a technical characteristic that: * Lies within the range of values specified by the operating behavior * Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. Kinetis KL02 32 KB Flash, Rev. 5 08/2017 45 NXP Semiconductors Terminology and guidelines 9.8.1 Example 1 This is an example of an operating behavior that includes a typical value: Symbol Description IWP Digital I/O weak pullup/pulldown current Min. 10 Typ. Max. 70 130 Unit A 9.8.2 Example 2 This is an example of a chart that shows typical values for various voltage and temperature conditions: 5000 4500 4000 TJ IDD_STOP (A) 3500 150 C 3000 105 C 2500 25 C 2000 -40 C 1500 1000 500 0 0.90 0.95 1.00 1.05 1.10 VDD (V) 9.9 Typical value conditions Typical values assume you meet the following conditions (or other conditions as specified): 46 NXP Semiconductors Kinetis KL02 32 KB Flash, Rev. 5 08/2017 Revision history Table 36. Typical value conditions Symbol Description Value Unit TA Ambient temperature 25 C VDD 3.3 V supply voltage 3.3 V 10 Revision history The following table provides a revision history for this document. Table 37. Revision history Rev. No. Date Substantial Changes 2 05/2013 Public release. 2.1 07/2013 Removed the specification on OSCERCLK (4 MHz external crystal) because KL02 does not support it. 3 3/2014 * * * * * * * * * Updated the front page and restructured the chapters Added a note to the ILAT in the ESD handling ratings Updated table title in the Voltage and current operating ratings Updated Voltage and current operating requirements Updated footnote to the VOH in the Voltage and current operating behaviors Updated Power mode transition operating behaviors Updated Capacitance attributes Updated the Device clock specifications Added Inter-Integrated Circuit Interface (I2C) timing 4 08/2014 * Updated related source and added block diagram in the front page * Updated Power consumption operating behaviors * Updated tSU and tv in Table 28, tSU, tdis, tv in Table 30 * Updated the note in KL02 signal multiplexing and pin assignments 5 08/2017 * Added a note in the Thermal operating requirements * Added I2C 1 Mbit/s timing table and a footnote to the fSCL of the I2C timing table in the Inter-Integrated Circuit Interface (I2C) timing. Kinetis KL02 32 KB Flash, Rev. 5 08/2017 47 NXP Semiconductors How to Reach Us: Home Page: nxp.com Web Support: nxp.com/support Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by customers technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/SalesTermsandConditions. . NXP, the NXP logo, Freescale, Freescale logo, Energy Efficient Solutions logo, and Kinetis are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. (c) 2012-2017 NXP B.V. Document Number KL02P32M48SF0 Revision 5 08/2017