1. General description
The HEF4027B is a edge-tri ggered dua l JK flip-flop which fe atures inde pendent set-dire ct
(SD), clear-direct (CD), clock (CP) input s and outputs (Q, Q). Dat a is accepted when CP is
LOW, and transferre d to the ou tp u t on th e po sitiv e- goi n g edge of th e cl oc k. Th e active
HIGH asynchronous clear-direct (CD) and set-direct (SD) inputs are independent and
override the J, K, and CP inputs. The outputs are buffered for best system performance.
Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to V SS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Applications
Registers
Counters
Control circuits
4. Ordering information
HEF4027B
Dual JK flip-flop
Rev. 9 — 18 November 2011 Product data sheet
Table 1. Ordering information
Tamb from
40
C to +85
C.
Type number Package
Name Description Version
HEF4027BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
HEF4027BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
HEF4027B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 9 — 18 November 2011 2 of 14
NXP Semiconductors HEF4027B
Dual JK flip-f lo p
5. Functional diagram
Fig 1. Functional di agram
001aae593
9
10
13
11
12
7
6
31
2
15
14
5
4
1SD
1CD
1J 1Q
1CP
1K 1Q
2SD
2CD
2J 2Q
FF 2
FF 1
2CP
2K 2Q
Fig 2. Logic diagram of one flip-flop
001aae595
J
K
C
Q
CD
SD
CP
C
CC
C
C
C
C
C
C
Q
HEF4027B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 9 — 18 November 2011 3 of 14
NXP Semiconductors HEF4027B
Dual JK flip-f lo p
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional description
Fig 3. Pin configuratio n
HEF4027B
2Q VDD
2Q 1Q
2CP 1Q
2CD 1CP
2K 1CD
2J 1K
2SD 1J
VSS 1SD
001aae594
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Table 2. Pin description
Symbol Pin Description
VSS 8 ground supply voltage
1SD, 2SD 9, 7 asynchronous set-direct input (active HIGH)
1J, 2J 10, 6 synchronous input
1K, 2K 11, 5 synchronous input
1CD, 2CD 12, 4 asynchronous clear-direct input (active HIGH)
1CP, 2CP 13, 3 clock input (LOW-to-HIGH edge-trigg ered)
1Q, 2Q 14, 2 complement output
1Q, 2Q 15, 1 true output
VDD 16 supply voltage
Table 3. Function table[1]
Inputs Outputs
nSD nCD nCP nJ nK nQ nQ
HLXXXHL
LHXXXLH
HHXXXHH
HEF4027B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 9 — 18 November 2011 4 of 14
NXP Semiconductors HEF4027B
Dual JK flip-f lo p
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.; = positive-going transition.
8. Limiting values
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
9. Recommended operating conditions
LLL L no change no change
LLHLHL
LLLHLH
LLHHnQ
nQ
Table 3. Function table[1] …continued
Inputs Outputs
nSD nCD nCP nJ nK nQ nQ
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 0.5 +18 V
IIK input clamping current VI<0.5 V or VI>V
DD + 0.5 V - 10 mA
VIinput voltage 0.5 VDD + 0.5 V
IOK output clamping curre nt VO<0.5 V or VO>V
DD + 0.5 V - 10 mA
II/O input/output current - 10 mA
IDD supply current - 50 mA
Tstg storage temperature 65 +150 C
Tamb ambient temperature in free air 40 +85 C
Ptot total power dissipation Tamb 40 C to +85 C
DIP16 package [1] - 750 mW
SO16 package [2] - 500 mW
P power dissipation per output - 100 mW
Table 5. Recommended operating con ditions
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 3 15 V
VIinput voltage 0 VDD V
Tamb ambient temperature in free air 40 +85 C
t/V input transition rise and fall rate VDD = 5 V - 3.75 s/V
VDD = 10 V - 0.5 s/V
VDD = 15 V - 0.08 s/V
HEF4027B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 9 — 18 November 2011 5 of 14
NXP Semiconductors HEF4027B
Dual JK flip-f lo p
10. Static characteristics
Table 6. Static characteristics
VSS = 0 V; VI = VSS or VDD; unless oth erwise specified.
Symbol Parameter Conditions VDD Tamb = 40 C Tamb = 25 C Tamb = 85 CUnit
Min Max Min Max Min Max
VIH HIGH-level input voltage IO < 1 A 5 V 3.5 - 3.5 - 3.5 - V
10 V 7.0 - 7.0 - 7.0 - V
15 V 11.0 - 11.0 - 11.0 - V
VIL LOW-level input voltage IO < 1 A5 V-1.5-1.5-1.5V
10 V - 3.0 - 3.0 - 3.0 V
15 V - 4.0 - 4.0 - 4.0 V
VOH HIGH-level output voltage IO < 1 A 5 V 4.95 - 4.95 - 4.95 - V
10 V 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - V
VOL LOW-level output voltage IO < 1 A 5 V - 0.05 - 0.05 - 0.05 V
10 V - 0.05 - 0.05 - 0 .05 V
15 V - 0.05 - 0.05 - 0 .05 V
IOH HIGH-level output current VO = 2.5 V 5 V - 1.7 - 1.4 - 1.1 mA
VO = 4.6 V 5 V - 0.52 - 0.44 - 0.36 mA
VO = 9.5 V 10 V - 1.3 - 1.1 - 0.9 mA
VO = 13.5 V 15 V - 3.6 - 3.0 - 2.4 mA
IOL LOW-level output current VO = 0.4 V 5 V 0 .52 - 0.44 - 0.36 - mA
VO = 0.5 V 10 V 1.3 - 1.1 - 0 .9 - mA
VO = 1.5 V 15 V 3.6 - 3.0 - 2 .4 - mA
IIinput leakage current 15 V - 0.3 - 0.3 - 1.0 A
IDD supply current IO = 0 A 5 V - 4 .0 - 4.0 - 30 A
10 V - 8.0 - 8.0 - 60 A
15 V - 16.0 - 16.0 - 120 A
CIinput capacitance - - - - 7.5 - - pF
HEF4027B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 9 — 18 November 2011 6 of 14
NXP Semiconductors HEF4027B
Dual JK flip-f lo p
11. Dynamic characteristics
Table 7. Dynamic characteristics
VSS = 0 V; Tamb = 25
C; for test circuit see Figure 7; unless otherwise specifi ed.
Symbol Parameter Conditions VDD Extrapolation formula[1] Min Typ Max Unit
tPHL HIGH to LOW
propagation delay CP Q, Q;
see Figure 4 5 V 78 ns + (0.55 ns/pF)CL- 105 210 ns
10 V 29 ns + (0.23 ns/pF)CL- 4080ns
15 V 22 ns + (0.16 ns/pF)CL- 3060ns
CD Q;
see Figure 4 5 V 93 ns + (0.55 ns/pF)CL- 120 240 ns
10 V 33 ns + (0.23 ns/pF)CL- 4590ns
15 V 27 ns + (0.16 ns/pF)CL- 3570ns
SD Q;
see Figure 4 5 V 113 ns + (0.55 ns/pF ) C L- 140 280 ns
10 V 44 ns + (0.23 ns/pF)CL-55110ns
15 V 32 ns + (0.16 ns/pF)CL- 4080ns
tPLH LOW to HIGH
propagation delay CP Q, Q;
see Figure 4 5 V 58 ns + (0.55 ns/pF)CL- 85 170 ns
10 V 27 ns + (0.23 ns/pF)CL- 3570ns
15 V 22 ns + (0.16 ns/pF)CL- 3060ns
CD Q;
see Figure 4 5 V 48 ns + (0.55 ns/pF)CL- 75 150 ns
10 V 24 ns + (0.23 ns/pF)CL- 3570ns
15 V 17 ns + (0.16 ns/pF)CL- 2550ns
SD Q;
see Figure 4 5 V 43 ns + (0.55 ns/pF)CL- 70 140 ns
10 V 19 ns + (0.23 ns/pF)CL- 3060ns
15 V 17 ns + (0.16 ns/pF)CL- 2550ns
tttransition time see Figure 4 5 V [2] 10 ns + (1.00 ns/pF)CL- 60 120 ns
10 V 9 ns + (0.42 ns/pF)CL- 3060ns
15 V 6 ns + (0.28 ns/pF)CL- 2040ns
tsu set-up time J, K CP;
see Figure 5 5 V 5025- ns
10 V 3010- ns
15 V 20 5 - ns
thhold time J, K CP;
see Figure 5 5 V 25 0 - ns
10 V 20 0 - ns
15 V 15 5 - ns
tWpulse width CP LOW;
minimum width
see Figure 5
5 V 8040- ns
10 V 3015- ns
15 V 2412- ns
SD, CD HIGH;
minimum width
see Figure 6
5 V 9045- ns
10 V 4020- ns
15 V 3015- ns
trec recovery time SD, CD inputs;
see Figure 6 5 V +20 15 - ns
10 V +15 10 - ns
15 V +10 5- ns
HEF4027B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 9 — 18 November 2011 7 of 14
NXP Semiconductors HEF4027B
Dual JK flip-f lo p
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
[2] tt is the same as tTLH and tTHL.
12. Waveforms
fmax maximum
frequency CP input;
J = K = HIGH;
see Figure 5
5 V 4 8 - MHz
10 V 12 25 - MHz
15 V 15 30 - MHz
Table 7. Dynamic characteristics …continu ed
VSS = 0 V; Tamb = 25
C; for test circuit see Figure 7; unless otherwise specifi ed.
Symbol Parameter Conditions VDD Extrapolation formula[1] Min Typ Max Unit
Table 8. Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf
20 ns; Tamb = 25
C.
Symbol Parameter VDD Typical formula for PD (W) Where:
PDdynamic power
dissipation 5 V PD = 900 fi + (fo CL) VDD2fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VDD = supply voltage in V;
(fo CL) = sum of the outputs.
10 V P D = 4500 fi + (fo CL) VDD2
15 V P D = 13200 fi + (fo CL) VDD2
VOH and VOL are typical output voltages levels that occur with the output load.
Measurement points are given in Table 9.
Fig 4. Waveforms showing rise, fall and transition times an d propagation delays
Measurement points are given in Table 9.
Fig 5. Waveforms showing set-up and hold times and minimum clock pulse width
001aah863
SD, CD or CP
INPUT
V
I
0 V
V
OH
V
OL
Q or Q
OUTPUT V
M
V
M
t
PLH
t
PHL
90 %
90 %
10 %
10 %
t
r
t
TLH
t
THL
t
f
001aae596
CP INPUT
J,K INPUT
t
W
V
M
V
M
1/f
max
t
su
t
h
HEF4027B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 9 — 18 November 2011 8 of 14
NXP Semiconductors HEF4027B
Dual JK flip-f lo p
VOH and VOL are typical output voltages levels that occur with the output load.
Measurement points are given in Table 9.
Fig 6. Waveforms showing pulse widths and recovery times
001aae597
SD INPUT
VI
0 V
VI
0 V
VI
0 V
VOH
VOL
CD INPUT
CP INPUT
tW
tW
VM
VM
VM
Q OUTPUT
trec trec
Table 9. Measurement points
Supply voltage Input Output
VDD VMVM
5 V to 15 V 0.5VDD 0.5VDD
Test data is given in Table 10.
Definitions for test circuit:
DUT = Device Under Test.
CL= load capacitance including jig and probe capacitance.
RT= termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 7. Tes t circuit
VDD
VIVO
001aag182
DUT
CL
RT
G
Table 10. Test data
Supply voltage Input Load
VDD VItr, tfCL
5 V to 15 V VSS or VDD 20 ns 50 pF
HEF4027B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 9 — 18 November 2011 9 of 14
NXP Semiconductors HEF4027B
Dual JK flip-f lo p
13. Package outline
Fig 8. Package outline SOT38-4 (DIP16)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT38-4 95-01-14
03-02-13
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
b2
e
D
A2
Z
16
1
9
8
E
pin 1 index
b
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
UNIT A
max. 12 b1(1) (1) (1)
b2cD E e M Z
H
L
mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
min. A
max. bmax.
w
ME
e1
1.73
1.30 0.53
0.38 0.36
0.23 19.50
18.55 6.48
6.20 3.60
3.05 0.2542.54 7.62 8.25
7.80 10.0
8.3 0.764.2 0.51 3.2
inches 0.068
0.051 0.021
0.015 0.014
0.009
1.25
0.85
0.049
0.033 0.77
0.73 0.26
0.24 0.14
0.12 0.010.1 0.3 0.32
0.31 0.39
0.33 0.030.17 0.02 0.13
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
HEF4027B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 9 — 18 November 2011 10 of 14
NXP Semiconductors HEF4027B
Dual JK flip-f lo p
Fig 9. Package outline SOT109-1 (SO16)
HEF4027B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 9 — 18 November 2011 11 of 14
NXP Semiconductors HEF4027B
Dual JK flip-f lo p
14. Revision history
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
HEF4027B v.9 20111118 Product data sheet - HEF4027B v.8
Modifications: Legal pages updated.
Changes in “General description” and “Features and benefits”.
HEF4027B v.8 20111010 Product data sheet - HEF4027B v.7
HEF4027B v.7 200 91125 Product data sheet - HEF4027B v.6
HEF4027B v.6 200 90624 Product data sheet - HEF4027B v.5
HEF4027B v.5 200 81110 Product data sheet - HEF4027B v.4
HEF4027B v.4 200 80703 Product specification - HEF4027B_CNV v.3
HEF4027B_CNV v.3 19950101 Product specification - HEF4027B_CNV v.2
HEF4027B_CNV v.2 19950101 Product specification - -
HEF4027B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 9 — 18 November 2011 12 of 14
NXP Semiconductors HEF4027B
Dual JK flip-f lo p
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat ionThe information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur fo r any reason
whatsoever, NXP Semico nductors’ aggregate and cumulative liabil ity towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suit able for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applic ations and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulatio ns. Export might require a prior
authorization from competent authorities.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specificati on for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
HEF4027B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 9 — 18 November 2011 13 of 14
NXP Semiconductors HEF4027B
Dual JK flip-f lo p
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It i s neither qua lified nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipmen t or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or f ailed product claims result ing from customer design an d
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors HEF4027B
Dual JK flip-f lo p
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of rele ase: 18 Novem ber 2011
Document iden tifier: HE F 4027B
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 3
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
9 Recommended operating conditions. . . . . . . . 4
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
16 Contact information. . . . . . . . . . . . . . . . . . . . . 13
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14