PS ANALOG Complete 16-Channel, 12-Bit DEVICES Data Acquisition Systems AD363/AD364 FEATURES FUNCTIONAL BLOCK DIAGRAMS AD363 waren 16-Channei Date Acquisition Input Stage with: Digitally Controtied Channel Selection/Mode Control 16 Single-Ended or 8 Differential Channels 28 kHz Throughput Rate Guaranteed No Missing Codes Over Temperature ADs6 16-Channel Data Acquisition Input Stage with: Dighally Controlled Channel Selection/Mode Control 16 Single-Ended or 8 Differential Channels 20 kHz Throughput Rate H Guaranteed No Missing Codes Over Temperature a couse, owas Three-State Buffered Digital Output Leite j SAEr crwerm comer seat PRODUCT DESCRIPTIONS The AD363 and AD364 are complete 16-channel data acquisi- tion systems which condition and subsequently convert an ana- log voltage into digiral form. Each system consists of two devices, an analog input stage (AIS) and an analog-to-digital converter (ADC). The AIS includes a two 8-channe! multiplex- ers, a channel address register, a unity gain instrumentation am- plifier, and a sample-hold amplifier. The multiplexers may be connected to the instrumentation amplifier in either an 8- channel differential or 16-channel single ended configuration. A bw unique feature of these products is an internal user controlled switch which connects the multiplexers in either single-ended or differential mode. This allows a single device to perform in i- ther mode with hard-wire programming and permits interfacing a mixture of single-ended and differential signals by dynamically switching the input mode conqol. The AD363 and AD364 differ in ADC performance. Each ADC is a complete 12-bit successive approximation converter includ- ing an internal clock and a precision reference. Active laser trimming results in maximum linearity errors of +0.012% with conversion times of 25 us (AD363) or 32 ps (AD364). The hy- brid AD363-ADC has five user selectable input ranges (+2.5, +5.0, 10.0, 0 to +5, and 0 to +10 volts) and includes a high impedance buffer amplifier. The AD364-ADC is a monolithic converter with 3-state output buffer circuitry for direct interface to an 8-, 12-, or 16-bit processor bus and three user selected input ranges (+5, +10, and @ to +10 volts). Both products are specified for operation over both the commer- cial (0C to +70C) and military (55C to + 125C) temperature ranges. The AD363 and AD364 are available with environmen- tal screening. Please contact the factory or nearest sales office for details. e~ pravewarennewee 4 my pm ORT my REV. A information furnished by Analog Devices is believed to be accureie and sbie. However, no reeponsibitity is sssu: by Analog Devices for its use; nor for any infringements of patents of other rights of third parties One Technology Way. P.0. Box 9106, Norwood, MA 02082-9106, U.5.A. which may result from its use. No license is granted by implication or = T#k: 617/329-4700 Fax: 617/328-6703 = Twx: 710/394-6677 otherwise under any petent or patent rights of Analog Devices. Telex: 924491 Cable: ANALOG NORWOODMASSAD363/AD364 SPECIFICATIONS (typical @ +25C, +15 V and +5 V unless otherwise noted) Parameter ADIORK AD363RS ANALOG INPUTS Number of Inputs 16 Single-Ended or 8 Differential (Electronically Selectable) * Input Voltage Ranges Bipolar 22.5 V, 25.0 V, 210.0V * Unipolar Oto +8 V.0t0 +10 V * Input (Biss) Current, per Channel +50 nA max * Taput Impedance ON Channel 10 , 100 pF * OFF Channel 10" 0, 10 pF * Input Fault Current (Power OFF or ON) 20 mA, max, Invemally Limited * Differential Mode 70 dB min (80 dB) typ) @ | kHz, 20 V p-p * Mox Crocstatk (Interchannel, Any OFF Channel to Any ON Channel) ~80 dB max (-90 dB typ) @ 1 kHz, 20 V p-p * RESOLUTION 12 Bits * ACCURACY Gein Exror' +0,05% FSR (Adjustable to Zero) * Unipolar Offeet Error 10 mV (Adjustable to Zero) * Bipoler Offeet Error 20 mV (Adjustable to Zero) * Linearity Exror 27 LSB mx * Differential Linearity Error +1 LSB max (+1/2 LSB typ) * Relative Accuracy +0.025% FSR * Noise Error I mV p-p, 0.1 Hz to 1 MHz * TEMPERATURE COEFFICIENTS Gain 230 ppm/C max (+10 ppm typ) 225 ppavC max (15 ppevC typ) Offecx, +10 V Range 15 ppmC max (+5 ppm/C typ) +8 ppm/"C max (+5 ppenC typ) Differential Linearity No Missing Codes Over Temperature Range * SIGNAL DYNAMICS Conversion Time 25 ws max (22 ps typ) * Throughput Rate, Full Rated Accuracy 25 kHz min (30 kHz typ) * Sample-and-Hold Aperture Delay 200 as max (150 ns typ) * Aperture Uncertainty 500 pa max (100 ps typ) * Acquisition Time To 20.01% of Final Value 18 ps max (10 ps typ) * For Full-Scale Step Feedthrough 70 dB max (-0 dB typ) @ | kHz * Droop Rate 2 mV/ms max (1 mVims typ) DIGITAL INPUT SIGNALS Convert Command (to ADC Section, Pia 21) Positive Pulse, 200 ns min Width. Leading Edge Input Channel Select (10 Analog Input Section, Pins 28-31) Channel Select Latch (to Analog (aput Section, Pin 32) Semple-Hold Command (to Analog Input Section Pin 13 Normally Connected to ADC Status, Pin 20) Short Cycle (te ADC Section Pin 14) (to Analog Input Section, Pin 1) (*O to 1") Resets Register, Trailing Edge (1 to 0) Starts Conversion 1 TTL Load 4Bit Binary Channel Address 1 LS TTL Load 1" Latch Transparent 0 Latehed 4 LS TTL Loads 9 Semple Mode 1 Hold Mode 2 LS TTL Loads Connect to +5 V for 12-Bits Resolution Connect to Ourpur Bit n + 1 for a Bin Resolution 1 TTL Load 0 Single Ended Mode 1 Differential Mode (+4.6 V min) 3 TTL Loeds se eeAD363/AD364 Pasameter ADS63RK AD363RS DIGITAL OUTPUT SIGNALS (All Codes Positive True) Peralle! Date Unipolar Code Binary * Bipolar Code Offset Binary/Twos Complement * Output Drive 2 TTL Loads * Serial Data (NRZ Format) Unipoler Code Binary a Bipolar Code Offset Binary * Outpat Drive 2 TTL Loads . Seamus (Status) Logic 1 (0) During Conversion * Ourput Drive 2 TTL Loads * Internal Clock Ourput Drive 2 TTL Loads * Frequency S00 kHz * INTERNAL REFERENCE VOLTAGE +10.00 V, +10 mV & Max. External Current timA * Voltage Temperature Coefficient 20 ppm/C max * t POWER REQUIREMENTS Supply Voltages/Currents +15 V, 25% @ +45 mA max (+38 mA Cyp) * -15 V, 25% @ 45 mA max (38 mA typ) * +5 V, 5% @ +136 mA max (+113 mA typ) * E Total Power Dissipation 2 Watts max (1.7 Watts typ) * : TEMPERATURE RANGE Specificauon PC to +70 55C to +125C Storage SSC to + 150C 55C to + 150C PACKAGE OPTIONS Anslog input Section (DH-32E) AD363RKD AD363RSD AD Section (DH-32C) AD363RKD AD363RSD NOTES With $0 1, 1% fixed resistor in place of Gain Adjust pot. *Coaversion time of ADC Section. 5One TTL Load is defined as 1, = =1,6 mA max @ Vy, = 04 V, Tug = 40 pA max @ Voy = 2.4 V. One LS TTL Load is defined as In. = 0.36 mA max @ Vu. 7 0.4 V, dng 7 20 pA max @ Vay > 2.7 Vz *Specifications same as ADI63RK. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS (ALL MODELS) +V, Digital Supply .. 0.00.02 ee eee eee eee +5.5V +V, Analog Supply ...- 2.0. s eer eer eee eres +16V V, Analog Supply .....6 ce eee eee eee 1... t16V Vin Signal 0... eee tree ee eeee =V, Analog Supply Vin Digital . 00.062 e ee eee 0 to +V, Digital Supply AGND to DGND .. 212-2 ec ee eee +lVAD363/AD364 AD363 PIN FUNCTION DESCRIPTION ANALOG INPUT SECTION ANALOG-TO-DIGITAL CONVERTER SECTION Pin Pin Number {| Function _| Number | Functioa _ i Single-End/Differencial Mode Select 1 Data Bit 12 (Least Significant Bit) Out 0: Single-Ended Mode 2 Data Bit 11 Out |": Differential Mode (+4.0 V min) 3 Data Bit 10 Out 2 Digital Ground 4 Dats Bit 9 Our 3 Positive Digital Power Supply, +5 V 5 Data Bix 8 Out 4 High Analog Input, Channel 7 6 Data Bit 7 Out 5 High Analog Input, Channel 6 7 Data Bit 6 Out 6 High Analog Input, Channel 5 8 Data Bit 5 Out 7 High Analog Input, Channel 4 9 Data Bit 4 Our 8 High Analog Input, Channel 3 10 Data Bit 3 Out 9 High Analog Input, Channel 2 iW Data Bit 2 Out 10 High Analog Input, Channel 1 12 Dara Bit 1 (Most Significant Bit) Out ul High Anslog Input, Channel 0 13 Data Bit T (MSB) Our 12 No Connect 14 Short Cycle Control ~ 13 Sample-Hold Command Connect to +5 V for 12 Bits i. =0": Sample Mode Connect to Bit (an + 1) Out for n Bits be 1: Hold Mode 5 Digital Ground Normally Connected to ADC Pin 20 16 Positive Digital Power Supply, +5 V 14 Offset Adjust 7 Status Out 15 Offset Adjust 0; Conversion in Progress 16 Analog Output (Parallel Data Not Valid) Normally Connected to ADC 1": Conversion Complete Analog In (Parallel Data Valid) 7 Ansiog Ground 18 +10 V Reference Out 18 High (Low) Analog Input, Channel 5 (7) 19 Clock Out (Runs During Conversion) 19 High (Low) Analog Input, Channel 14 (6) 20 Status Out 20 Negative Analog Power Supply, 15 V 0: Conversion Complete 21 Positive Analog Power Supply, +15 V (Parallel Data Valid) 22 High (Low) Analog Input, Channel 13 (5) 1: Conversion in Progress 23 High (Low) Analog Input, Channel 12 (4) (Parallel Data Not Valid) 24 High (Low) Ansiog Input, Channel 11 (3) 21 Convert Start In 25 High (Low) Analog Input, Channel 10 (2) Reset Logic _ 26 High (Low) Analog Input, Channel 9 (1) Start Convert ~ & 27 High (Low) Anslog Input, Channel 8 () 22 Comparator In 28 Input Channel Select, Address Bit AE 23 Bipolar Offser 2 Input Channel Select, Address Bit AO Open for Unipolar Inputs I) Input Channel Select, Address Bit Al Consect to ADC Pin 22 for 31 Input Channel Select, Address Bit A2 Bipolar Inputs 32 Input Channel Select Latch 24 10 V Span R In Oo: Latched 28 20 V Span R In 1": Latch Transparent 6 Analog Ground 27 Gain Adjust 28 Positive Analog Power Supply, +15 V 2 Buffer Out (for External Use) Et Buffer In (for External Use) 31 Negative Analog Power Supply, 15 V 32 Serial Data Out Each Bit Valid on Trailing (~W) Edge Clock Out, ADC Pin 19SPECIFICATIONS ics: o +25, 215 vd +5 Vues otrvice ned AD363/AD364 Parameter AD364RJ AD4RK AD364RS AD3RT Units ANALOG INPUTS Number of Inpuss 16 Single-Ended or 8 Differential (Electronically Selectable) Input Voltage Range Tain 20 Trae 210 * * * v laput (Bias) Current per Channei +50 * * nA Input Impedance ON Channel 10%100 . * * DpF OFF Channe! 10'%10 * * * QipF Input Fault Current 20 * * * mA max (ower ON or OFF) (oternally Common-Mode Rejection Limited) Differential Mode 1 kHz 20 V p-p 70 min (80 typ) * * aB Muz Crosstalk (Any OFF CHANNEL to Any ON Channel) 1 kHz OV pp & max (-90 typ) * * * dB Offeer, Channel to Channel 25 * . * mV max ACCURACY Gain Error 03 * . % of FSR Unipolas Offset Error +10 28 . wn mY Bipolar Offset Error 250 20 * * mV Linearity Exror 0.024 0.012 * i % of PSR max Tie 10 Trae 0.024 0.012 * * % of FSR max Differential Linearity Error 0.024 0.012 * % of FSR max Tein 2 Tras 0.024 0.012 * % of FSR max Noise Error I mV p-p 0.1 Hz to | MHz * * * TEMPERATURE COEFFICIENTS Gain 4 31 * an ppa"C Offect (+10 V Range) 12 7 * * ppm/C Opersting Temperature Range OC w +70C * SSC to +125C | *t* ppmC SIGNAL DYNAMICS Conversion Time 32 max (25 typ) * * ws Throughput Rate, Full Accuracy 20 min (25 typ) * , * kHz Semple-Haid Aperture Delay 200 max (150 typ) * * * ns Aperture Uncertainty 500 max (100 typ) * * ps idon Time To.0.01% of Final Value For Full-Scale Step 18 max (10 typ) s t ps Feedthrough at 1 kHz ~70 max (-80 typ) * * * dB Droop Rate 2 max (1 typ) s * mV/ms DIGITAL INPUT SIGNALS Analg Input Section Taput Channel Select 4 Bit Binary Address * * LLS TTL Load . * . Channel Select Latch Y" Latch Transparent * . ~~ Lateched * x. * 4 LS TTL Loads * * * Single-Ended/Differcntial 0 Single Ended * * . Mode Select ]* Differential (+4 V min) * * * 3 TTL Loads * * * Sample-end-Hold Command 9 Sample Mode * * * 1" Hold Mode * * * 1 TTL Load * * * ADC Section 4.5) Data Bit 9 ]": Latch Transparcat 26 Data Bit 10 27 Data Bit 11 28 Srarus OutVe amadee wT: Al$ Functional Block Diagram DESIGN Concept Figures | and 2 show general DAS application using the AD363 and AD364, respectively. By dividing the data acquisition task into two sections, several important advantages are realized. Performance of each design is optimized for its specific function. Production yields are in- creased thus decreasing costs. Furthermore, the standard config- uration packages plug into standard sockets and are easier to handle than larger packages with higher pin counts. = ae =" Figure 1. ADS63 DAS acrowen (9004, 08%) e aDae4 2, 3 ww aOLO8 NPT AS L fro Foi sehen wan L 7 em oF | onnoa I oee-out r4 a on v 3 es. F NAA a Faw om mate aus =n ia ye ty |S Lael eae, : eases Latones j CONTRO. 2 a | conn. ieee im ae of C8 THE AG Ar AtAD, CHNIOE one Lom J laten - BODERSLECT emect Figure 2. AD364 DAS System Timing Figure 3 is a general timing diagram for the circuits shown in Figures i and 2 operating at the maximum conversion rate. ADORED WAT BE CHANGED ADDRESS LATOM COMVERT cOSAAND STATUS (CAMPLE HOLT GATED CLOCE Figure 3. AD363 Timing Diagram The normal sequence of events is as follows: 1. The appropriate Channel Select Address is latched into the addrezs register. Time is allowed for the multiplexers to settle. 2. A Conver: Start command is issued to the ADC which, in response, indicates that it is busy by placing a Logic 1 on its Status line. 3. The ADC Status controls the sample-and-hold. When the ADC is busy, the sample-and-hold is the Hold mode. 4, The ADC goes into its conversion routine. Since the sample- and-hold is holding the proper analog value, the address may be updated during conversion. Thus multiplexer settling time can coincide with conversion and need not affect throughput rate. 5. The ADC indicates completion of its conversion by returning Status to Logic 0. The sample-and-hold returns to the Sample mode. 6. If the input signal has changed full scale (different channels may be widely varying data) the sample-and-hold will typi- cally require 10 microseconds toacquire the next input to sufficient accuracy for 12-bit conversion. After allowing a suitable interval for sample-and-hold to stabilize at its new value, another Coavert Start command may be issued to the ADC. AD363-ADC OPERATION Figure 4 shows a detailed timing diagram for the AD363-ADC. Serial deta changes on rising edges of the internal clock and is guaranteed to be stable on falling edges. AD364-ADC OPERATION There are two sets of control pins on the AD364-ADC: the gen- eral control inputs (CE, CS, and R/C) and the internal register controls inputs (12/8 and Ag). The general control pins function similarly to those on most A/D converters, performing device timing, addressing, cycle initiation, and read enable functions. The internal register contro! inputs, which are not found on most A/D converters, select output data format and conversion cycle length.AD363/AD364 3m, om Giant = an en >| all #4 earea unex e & hh w & & Me he te = tn stares j " t (HOETERNAATE PARALLEL DATA VALID a wrt + = aC L " SL * s { or wn \ - a a aL n i G2 | | 86] 26] 98] 8? a Figure 4, AD363-ADC Timing Diagram (Binary Code 110101011001) The two major control functions, convert start and read enable, are controlled by CE, CS, and R/C. Although all three inputs must be in the correct state to perform the function (for convert start, CE = 1, CS = 0, RE = 0; for read enable, CE = 1, CS = 0, RC = 1), the sequence does not matter. For large sys- tems, typically microprocessor controlled, standard operation for convert start would be ro first set RC = 0 (from R/W line); ad- dress the chip with CS = 0, chen apply a positive start pulse to CE. A read would be done similarly but with R/T = |. Ao (byte select) and 12/8 (data format) inputs work together to control the output data and conversion cycle. In almost ail situa- tions 12/8 is hard-wired high (to Vioeic) oF low (to Digital Common). If it is wired high, all 12 data lines will be enabled when the read function is called by the general contro! inputs. For an 8-bit bus interface, 12/8 will be wired low. In this mode, only the 8 upper bits or the 4 lower bits can be enabled at once, as addressed by Ap. For these applications, the 4 LSBs (Pins 16-19) should be hard-wired to the 4 MSB (Pins 24-27). Thus, during a read, when Ao is low, the upper & bits are enabled and present dave on Pins 20 through 27. When A, goes high, the upper 8 data bits are disabled, the 4 LSBs then present data to Pins 24 to 27, and the 4 middle bits are overridden so that zeros are presented to Pins 20 through 23. The Ag input performs an additional function of controlling conversion length. If Ap is held low prior to cycle initiation, s full 12-bit, 25 ws cycle will result; if Ap is held high prior to cycle initiation, a shortened 8-bit, 16 us cycle will result. The Ag line must be set prior to cycle initiation and held in the de- sired position at least until STS goes high. Thus, for micro- REV. A ~9- processor interface applications, the Ao line must be properly controlled during both the convert start and read functions. STANDARD FULL CONTROL INTERFACE The timing for the standard full control interface is shown in Figure 5. In this opersting mode, CS is used as the address in- put which selects the particular device, R/C selects between the read data and start conversion functions, and CE is used to time WRSHID FEF PULA CONTRO, APRLICAT ION eRervent Haet Tee Figure 6. AD364-ADC Timing Diagram The left side of the figure shows the conversion start control. CS and RE are brought low (their sequence does not matter), then the start pulse is applied to CE. The timing diagram shows a time delay for TS and RVC prior to the start pulse at CE. If less time than this is allowed, the conversion will still be started, but an appropriately longer pulse will be needed at CE. However, if the hold times for CS and R/C after the rising edge of the start pulse at CE are not followed, the conversion may not be initiated. The Ag line determines the conversion cycle length and must be selected prior to conversion initiation. If Ao is low, a 12-bit cy- cle results; if Ag is high, an 8-bit short cycle results. Minimum setup and hold times are shown. The status line goes high to indicate conversion in progress. The analog input signal is al- lowed to vary until the STS goes high. It rust then be held steady until STS again goes low at the end of conversion. The data read function operates in a similar fashion except that RI is now held high. The data is stored in the output register and can be recalled at will until a new conversion cycle is com- manded. In addition, if the converter is arranged in the 8-bit data mode, the Ap line now functions as the byte select address, with setup and hold times as shown. With A, low, Pins 20 to 27 (DB4-1]) come out of three-state and present data. With Ao high, Pins 16-19 (DBO-3) come out of three-state with data and Pins 20-23 present sctive trailing zeros. In the 8-bit mode, Pins 16-19 will be hard-wired directly to Pin 24-27 for direct two byte loading onto an 8-bit bus. There are two delay times for the data lines after CE is brought low: tp is the delay until the outputs are fully invwo the high impedance state. STANDALONE OPERATION For simpler control functions, the AD364-ADC can be con- trolled with just R/C. In this case, CE is wired high, CS low, 12/8 high, and Ag low. There are two ways of cycling the deviceAD363/AD364 TIMING SPECIFICATIONS FULL CONTROL MODE tpsc | 400 ns max top | 200 ns max thec | 300 ns min typ | 25 ns min tgec | 300 ns min tssx_ | 150 ns min tysc | 200 ns min tsxx, | 0 min tence 250 ns min tear 150 ns min tanc 200 as min tase 50 os on tuac | 300 ns min tag {| 50 ns min &w 15-35 ps (12-Bit) | tg =| 150 ns max 10-24 js (8-Bit) | tay | 20 ns min 10-18 ys tsa | O min with this simple hookup. If a negative pulse is used to initiate conversion as in Figure 6, the converter will automatically bring the 12 data lines our of three-state at the end of conversion. The data will remain valid on the output lines until another pulse is applied. If the conversion is initiated by s high pulse 9% shown in Figure 7, the data lines are held in three-state at the end of conversion until RE is brought high. The next conversion cycle is initiated when RT goes low; the data froma the previous cycle will remain valid for the time typ ,- An alternative to the above is to toggle RUE as needed to initiate a new cycle on read data. Data will appear when R/C is brought high, a new cycle is initiated when RC goes low. TRANG FOR STAND -ALONE OPERATIONS GHORT LOW PULSE: OUTPUTS COME ON AFTER CONVERSION nv Figure 6. SHORT 18GH PULSE: OUTPUTS SYNCHRONIZED TO RISING EDGE G1.12 Figure 7. TIMING SPECIFICATIONSFULL CONTROL MODE tua. 250 ns min tos 600 us max tupr 25 ns max tus 300 ns min 1000 ns max lan | 300 n8 min tppr 250 ns max APPLICATIONS Single-Eaded/Differeatial Mode Control The AIS features an internal analog switch that configures the Analog Input Section in either a 16-channel single-ended or 8-channel differential mode. This switch is controlled by a non- TTL logic input applied to Pin 1 of the Analog Input Scction: 0: Single-Ended (16 Channels) 1: Differential (8 Channels) (+4.0 V min) When in the differential mode, a differential source may be ap- plied between corresponding High and Low anslog input channels. : It is possible to mix SE and DIFF inputs by using the mode control to command the appropriate mode. In this case, four microseconds must be allowed for the output of the Analog In- put Section to settle to within +0.01% of its final value, but if the mode is switched concurrent with changing the channel ad- dress, no significant additional delay is introduced. The effect of this delay may be eliminated by changing modes while a conver- sion is in progress (with the sample-and-hold in the Hold mode). When SE and DIFF signals are being processed concur- rently, the DIFF signals must be applied between corresponding High and Low analog input channels. Another application of this feature is the capability of measuring 16 sources individu- ally and/or measuring differences between pairs of those sources. Input Chanee! Addressing Table 1 is the truth table for input channel addressing in both the single-ended and differential modes. The 16-singie-ended channels may be addressed by applying the corresponding digi- tal number to the four Input Channel Select address bits, AE, AO, Al, A2 (Pins 28-31). In the differential mode, the eight channels are addressed by applying the appropriate digital code to AO, Al, and A2; AE must be enabled with a Logic 1. In- ternal logic monitors the status of the SE/DIFF Mode input and addresses the multiplexers singularly or in pairs as required. ADDRESS ON CHANNEL (Pin Number) Differential AE A2 Al AO | Singie-Ended Hi Lo 0 0 09 90 0 (1) None 0 6 0 1 1 (10) None 0 oOo 7 94 z2 9% None o Oo 1 1 3. (8) None 0 1 oO 0 4% None 0 1 0 1 5 6) None 0 1 1 6 6 (5) None 0 1 1 1 7 (4 None 1 o oO 0 8 (27) Oh 6) 1 o 0 1 9 (26) 110) 1(26) t 0 1 #@ WO (25) 2 (9) 225) 1 o 1 i HW (24) 3 (8) 3:24 1 1 09 0 12 (23) 4 (7) = $(23) 1 1 0 1 13 (22) 5 (6) $(22) i I 1 @ 4 19) 6 (5) 6 (19) l 1 1 l 5 (18) 7 (4) 718) Table |. input Channel Addressing Truth TableAD363/AD364 When the channel address is changed, six microseconds must be allowed for the Analog Input Section to settle to within 0.01% of its final ourput (inchuding settling times of all elements in the signal path). The effect of this delay may be eliminated by per- forming the address change while a conversion is in progress (with the sample-and-hold in the hold mode). All unused in- puts must be grounded. Input Chanae! Address Latch The AIS is equipped with a latch for the Input Channel Select address bits. If the Latch Control pin (Pin 32) is at Logic 1, input channel select address information is passed through to the multiplexers. A Logic 0 freezes the input channel address present at the inputs at the 1-t0-0" transition level-triggered. This feature is useful when input channel address information is provided from an address, data or control bus that may be re- quired to service many devices. The ability to latch an address is helpful whenever the user has no control of when address infor- mation may change. Sample-and-Hold Mode Controi The Sample-and-Hold Mode Control input (Pin 13) is normally connected to the Status output (Pin 20) from an analog-to-digital converter. When a conversion is initiated by applying a Convert Start command to the ADC, Status goes to Logic 1, putting the sample-and-hold in to the Hold mode. This freezes the information vo be digitized for the period of conversion. When the conversion is complete, Status returns to Logic 0 and the sample-and-hold returns to the Sample mode. Eighteen microseconds must be allowed for the sample-and-hold to ac- auire (catch up to) the analog input to within +0.01% of the final value before new Convert Start command is issued. The purpose of a sample-and-hold is to stop fast changing input signals long enough to be converted. In this application, it also allows the user to change channels and/or SE/DIFF mode while a conversion is in progress thus eliminating the effects of multiplexer, analog switch and differential amplifier settling times. If maximum throughput rate is required for slowly changing signals, the Sample-and-Hold Mode Control may be wired to ground (Logic 0) rather than to ADC Status thus leaving the sample-and-hold in a continuous sample mode. Analog laput Section Offset Adjust Circuit Although the offset voltage of the AIS may be adjusted, that adjustment is normally performed at the ADC. In some special applications, however, it may be helpful to adjust the offset of the Analog Input Section. An example of such a case would be if the input signals were small (<10 mV) relative to the AIS voltage offset and if a gain stage was to be inserted between the AIS and the ADC. To adjust the offset of the AIS, the circuit shown in Figure 8 is recommended. , v ANALOG Put section ourmur aunt A MOLD 4 BLaaa_le/t2t - s00kr2 , OPPSET VOLTAQE MUST TO Ve ANALOG (018) Figure 8 AIS Offset Voltage Adjustment Under normal conditions, all calibration is performed at the ADC Section.. Gaia Adjust, AD363-ADC: Gain may be adjusted by connect- ing a 100. Q potentiometer between +10 V Reference Output and Gain Adjust Input (ADC Pins 18 and 27). A multi-rurn, low temperature coefficient potentiometer, such as a 20-turn cermet device, is recommended. This potentiometer may be re- placed with a 50 , 0.1% resistor to obtain an absolute gain cali- bration of 0.05% without trimming. Offset Adjust, AD363-ADC: The simpiecst offset adjust circuit requires a 20-turn, 20 k{} cermet potentiometer and a 3.9 MN. resistor as shown in Figure 9a. This arrangement has an adjust- ment range of +8 LSBs, and will contribute a maximum of 2.3 ppm/C offset drift with a carbon composition fixed resistor (TC = -1200 ppm/C). Drift contributions from the offset ad- just circuit can be reduced well below this level using metal-film resistors and the circuit of Figure 9b. Gain Adjust, AD364-ADC: Gain may be adjusted by connect- ing a 100 2 potentiometer between the Reference Output and. Reference Input (ADC Pins 8 and 10). A multi-turn, low tem- perature coefficient potentiometer, such as a 20T cermer device, is recommended. A fixed 50 1, 1% resistor should be connected between Pins 8 and 10 if no gain trim is required. +15V Figure $b. Offset Adjust, AD364-ADC: Offset adjust circuits for unipolar and bipolar operation are shown in Figures 10a and 10b. In each case the potentiometer should be a multi-turn, Jow temperature coefficient device, such as 20-turn cermet. Lowest offset drift in unipolar operation will be realized when the fixed resistors are low-TC (100 ppm/*C) metal-film types.AD363/AD364 If no offact adjustment is desired, Pin 12 should be connected to Pin 9 (unipolar mode) or to Pin 8 through a 50 1 1% resistor (bipolar mode). Figure 10b. Bipolar Gain & Offset Input Scaling: Connections for the various ADC input ranges are given in Tables IT and Ill. Buffer: An uncommitted unity-gain buffer is available in the AD363-ADC. This buffer has a 2 ps settling time to 0.01% for a 20 V step, Its input should be grounded if the buffer is not used. 12 Connect Connect Analog Connect | Bipolar Range Input To Pin: | Span Pin: | Pin 23 Ta: Ow +SV 24 25 to 22 01 +10V 24 - ~2.5 V to +2.5 V | 24 25 to 22 SVwo+SV 24 - 22 ~10Vt0 +10V | 25 - Table it. AD364-ADC Pin Connections Connect Analog Connect Range Input To Pia: | Pin 12 To: Oto +10 V 13 GND* -5VwotsV 3 Pin 8** -10V to +10V 14 Pin 8** *Refer to Figure 10a for gain and offset adjustments. **Refer to Figure 10b for gain and offset adjusrments. Table ill. AD364-ADC Pin Connections Other Considerations Grounding: Analog and digital signal grounds should be kept separate where possible to prevent digital signals from flowing in the analog ground circuit and inducing spurious analog signal noise, Analog Ground (Pin 17) and Digital Ground (Pin 2) are not connected internally; these pins must be connected exter- nally for the system to operate properly. Preferably, this connec- tion is made at only one point, as close to the AIS, as possible. The case is connected internally to Digital Ground to pravide good electrostatic shielding. If the grounds are not tied common on the same card with the AIS they should be connected with back-to-back general purpose diodes as shown in Figure 11. This will protect the AIS from possible damage caused by volt- ages in excess of =1 volt berween the ground systems which could occur if the key grounding card should be removed from the overall system. The device will operate properly with as much as +200 mV between grounds, however this difference will be reflected direcily as an input offset voltage. an adc AGND 86 DGND | aawo wed TO CARO 7 iy CONNECTOR SQUIVALENT Figure 11. Ground-Fault Protection Diodes Power Supply Bypassing: The +15 V and +5 V power leads should be capacitively bypassed to Analog Ground and Digital Ground respectively for optimum device performance. 1 pF tan- talum types are recommended; these capacitors should be lo- cated close to the system. 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