1
Data sheet acquired from Harris Semiconductor
SCHS055C
Features
• High-Voltage Types (20V Rating)
• CD4070B - Quad Exclusive-OR Gate
• CD4077B - Quad Exclusive-NOR Gate
• Medium Speed Operation
-t
PHL, tPLH = 65ns (Typ) at VDD = 10V, CL = 50pF
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full
Package Temperature Range
- 100nA at 18V and 25oC
• Noise Margin (Over Full Package Temperature Range)
- 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Standard No. 13B,
“Standard Specifications for Description of ‘B’ Series
CMOS Devices
Applications
• Logical Comparators
• Adders/Subtractors
• Parity Generators and Checkers
Description
The Harris CD4070B contains four independent Exclusive-
OR gates. The Harris CD4077B contains four independent
Exclusive-NOR gates.
The CD4070B and CD4077B provide the system designer
with a means for direct implementation of the Exclusive-OR
and Exclusive-NOR functions, respectively.
Pinouts
Ordering Information
PART NUMBER TEMP. RANGE
(oC) PACKAGE
CD4070BE -55 to 125 14 Ld PDIP
CD4070BF -55 to 125 14 Ld CERDIP
CD4070BM -55 to 125 14 Ld SOIC
CD4070BNSR -55 to 125 14 Ld SOP
CD4070BPWR -55 to 125 14 Ld TSSOP
CD4077BE -55 to 125 14 Ld PDIP
CD4077BF -55 to 125 14 Ld CERDIP
CD4077BM -55 to 125 14 Ld SOIC
CD4077BM96 -55 to 125 14 Ld SOIC
CD4077BNSR -55 to 125 14 Ld SOP
CD4077BPWR -55 to 125 14 Ld TSSOP
CD4070B
(PDIP, CERDIP, SOIC, SOP, TSSOP)
TOP VIEW
CD4077B
(PDIP, CERDIP, SOIC, SOP, TSSOP)
TOP VIEW
A
B
J = A ⊕ B
K = C ⊕ D
C
D
VSS
VDD
H
G
M = G ⊕ H
L = E ⊕ F
F
E
1
2
3
4
5
6
7
14
13
12
11
10
9
8
A
B
J = A ⊕ B
K = C ⊕ D
C
D
VSS
VDD
H
G
M = G ⊕ H
L = E ⊕ F
F
E
1
2
3
4
5
6
7
14
13
12
11
10
9
8
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2002, Texas Instruments Incorporated
CD4070B,
CD4077B
CMOS Quad Exclusive-OR
and Exclusive-NOR Gate
File Number 910.1
[ /Title
(CD40
70B,
CD407
7B)
/
Sub-
j
ect
(CMO
SQuad
Exclu-
sive-
OR
and
Exclu-
sive-
NOR
Gate)
/
Autho
r ()
/
Key-
words
(Har-
ris
Semi-
con-
ductor,
CD400
0,
metal
gate,
CMOS
, pdip,
cerdip,
mil,
January 1998 - Revised July 2002
2
Functional Diagrams
CD4070B CD4077B
A
B
C
D
E
F
G
H
1
2
5
6
8
9
12
13
3
4
10
11
J = A ⊕ B
K = C⊕ D
M = G ⊕H
L = E ⊕ F
VSS = 7
VDD = 14
J
K
L
M
A
B
C
D
E
F
G
H
1
2
5
6
8
9
12
13
3
4
10
11
J=A
⊕ B
K = C ⊕ D
M = G ⊕ H
L=E
⊕ F
J
K
L
M
FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070B
(1 OF 4 IDENTICAL GATES)
CD4070B TRUTH TABLE (1 OF 4 GATES)
ABJ
000
101
011
110
NOTE:
1 = High Level
0 = Low Level
J = A ⊕B
VDD
VSS
VSS
VDD
VDD
VSS
VSS
VDD
p
n
p
n
p
np
p
n
p
n
J
3(4,10,11)
B†
2(5,9,12)
A†
1(6,8,13)
†INPUTS PROTECTED
BY CMOS PROTECTION
NETWORK
FIGURE 2. SCHEMATIC DIAGRAM FOR CD4077B
(1 OF 4 IDENTICAL GATES)
CD4077B TRUTH TABLE (1 OF 4 GATES)
ABJ
001
100
010
111
NOTE:
1 = High Level
0 = Low Level
J = A ⊕B
VDD
VSS
VSS
VDD
VDD
VSS
VSS
VDD
p
n
p
n
p
n
p
n
p
n
J
3(4,10,11)
B†
2(5,9,12)
A†
1(6,8,13)
†INPUTS PROTECTED
BY CMOS PROTECTION
NETWORK
n
CD4070B, CD4077B
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage Range (VDD) . . . . . . . . . . . . . . . . . -0.5V to 20V
Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5V to VDD 0.5V
DC Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 10mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . . . . 3V to 18V
Package Thermal Impedance, θJA (see Note 1):
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80oC/W
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86oC/W
SOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76oC/W
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113oC/W
Maximum Junction Temperature (Hermetic Package or Die) . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
CONDITIONS
LIMITS AT INDICATED TEMPERATURES (oC)
UNITS-55 -40 85 125
25
VO
(V) VIN
(V) VDD
(V) MIN TYP MAX
Quiescent Device Current
IDD Max - 0, 5 5 0.25 0.25 7.5 7.5 - 0.01 0.25 µA
- 0, 10 10 0.5 0.5 15 15 - 0.01 0.5 µA
- 0, 15 15 1 1 30 30 - 0.01 1 µA
- 0, 20 20 5 5 150 150 - 0.02 5 µA
Output Low (Sink) Current
IOL Min 0.4 0, 5 5 0.64 0.61 0.42 0.36 0.51 1 - mA
0.5 0, 10 10 1.6 1.5 1.1 0.9 1.3 2.6 - mA
1.5 0, 15 15 4.2 4 2.8 2.4 3.4 6.8 - mA
Output High (Source) Current
IOH Min 4.6 0, 5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mA
2.5 0, 5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 - mA
9.5 0, 10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 - mA
13.5 0, 15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 - mA
Output Voltage: Low Level,
VOL Max - 0, 5 5 0.05 0.05 0.05 0.05 - 0 0.05 V
- 0, 10 10 0.05 0.05 0.05 0.05 - 0 0.05 V
- 0, 15 15 0.05 0.05 0.05 0.05 - 0 0.05 V
Output Voltage: High Level,
VOH Min - 0, 5 5 4.95 4.95 4.95 4.95 4.95 5 - V
- 0, 10 10 9.95 9.95 9.95 9.95 9.95 10 - V
- 0, 15 15 14.95 14.95 14.95 14.95 14.95 15 - V
Input Low Voltage,
VIL Max 0.5, 4.5 - 5 1.5 1.5 1.5 1.5 - - 1.5 V
1, 9-103333--3V
1.5, 13.5 - 15 4444--4V
Input High Voltage,
VIH Min 0.5, 4.5 - 5 3.5 3.5 3.5 3.5 3.5 - - V
1, 9-1077777--V
1.5, 13.5 - 15 11 11 11 11 11 - - V
Input Current, IIN Max - 0, 18 18 ±0.1 ±0.1 ±1±1-±10-5 ±0.1 µA
CD4070B, CD4077B
4
AC Electrical Specifications TA = 25oC, Input tr, tf = 20ns, CL = 50pF, RL = 200kΩ
PARAMETER SYMBOL
TEST CONDITIONS LIMITS ON ALL TYPES
UNITSVDD (V) TYP MAX
Propagation Delay Time tPHL, tPLH 5 140 280 ns
10 65 130 ns
15 50 100 ns
Transition Time tTHL, tTLH 5 100 200 ns
10 50 100 ns
15 40 80 ns
Input Capacitance CIN Any Input 5 7.5 pF
Typical Performance Curves
FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
TA = 25oC
GATE TO SOURCE VOLTAGE (VGS) = 15V
10V
5V
30
25
20
15
10
5
00 5 10 15
IOL, OUTPUT LOW (SINK) CURRENT (mA)
VDS, DRAIN TO SOURCE VOLTAGE (V)
TA = 25oC
GATE TO SOURCE VOLTAGE (VGS) = 15V
10V
5V
15
12.5
10
7.5
5
2.5
00 5 10 15
IOL, OUTPUT LOW (SINK) CURRENT (mA)
VDS, DRAIN TO SOURCE VOLTAGE (V)
TA = 25oC
GATE TO SOURCE VOLTAGE (VGS) = -5V
-10V
-15V
-5
-10
-15
-20
-25
-30
0
0-5-10-15
IOH, OUTPUT HIGH (SOURCE) CURRENT (mA)
VDS, DRAIN TO SOURCE VOLTAGE (V)
TA = 25oC
GATE TO SOURCE VOLTAGE (VGS) = -5V
-10V
-15V -15
-10
-5
0
0-5-10-15
IOH, OUTPUT HIGH (SINK) CURRENT (mA)
VDS, DRAIN TO SOURCE VOLTAGE (V)
CD4070B, CD4077B
5
FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE
FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF SUPPLY VOLTAGE FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION AS A
FUNCTION OF INPUT FREQUENCY
Typical Performance Curves (Continued)
TA = 25oC
SUPPLY VOLTAGE (VDD) = 5V
10V
15V
200
150
100
50
00204060
tTHL, tTLH, TRANSITION TIME (ns)
CL, LOAD CAPACITANCE (pF)
80 100 110
TA = 25oC
SUPPLY VOLTAGE (VDD) = 5V
10V
15V
300
200
100
00204060
tPHL, tPLH, PROPAGATION DELAY TIME (ns)
CL, LOAD CAPACITANCE (pF)
80 100
TA = 25oC
300
200
100
00 5 10 15
tPHL, tPLH, PROPAGATION DELAY TIME (ns)
VDD, SUPPLY VOLTAGE (V)
20
LOAD CAPACITANCE CL = 50pF
TA = 25oC
SUPPLY VOLTAGE (V
DD
) = 15V
5V
103
102
10
1
10-1
10-1 110
102
PD, POWER DISSIPATION (µW)
fI, INPUT FREQUENCY (kHz) 103104
104
105
10V
CL = 50pF
CL = 15pF
10V
CD4070B, CD4077B
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