Device Engineering Incorporated 385 East Alamo Drive Chandler, AZ 85225 Phone: (480) 303-0822 Fax: (480) 303-0824 E-mail: admin@deiaz.com DEI1198 8CH GND/OPEN PARALLEL OUTPUT DISCRETE INTERFACE IC FEATURES Eight discrete inputs o Senses GND/OPEN discrete signals. o Meets input threshold and hysteresis requirements specified per AirBus ABD0100H specification. Thresholds: 4.5V/10.5V, Hysteresis: 3V o ~1mA DIN source/sink current to prevent dry relay contacts. o Internal isolation diode. o Uses an external 3K resistor on the inputs to implement lightning transient immunity of 1600V and higher. i.e.: DO160E, Section 22, Levels 4 and 5. o Inputs protected from Lightning Induced Transients per DO160, Section 22, Cat A3 and B3 plus waveform 5A to 500V. Parallel I/O interface o TTL/CMOS compatible inputs and Tristate outputs o CLK & /OE control inputs and outputs Logic Supply Voltage (VCC): 3.3V +/-5% Analog Supply Voltage (VDD): 12.0V to 16.5V 24 Lead TSSOP package Pin compatible with DEI1166/67 PIN ASSIGNMENTS Figure 1 DEI1198 Pin Assignment (24 Lead TSSOP) (c)2013 Device Engineering Inc. 1 of 10 DS-MW-01198-01 Rev. B 9/9/2013 FUNCTIONAL DESCRIPTION DEI1198 is an eight-channel parallel discrete-to-digital interface IC implemented in an HV DIMOS technology. It senses eight GND/OPEN discrete signals of the type commonly found in avionic systems and converts them to logic data. The discrete data is read from the device via a parallel tri-state bus. The discrete input circuits are designed to achieve a high level of lightning transient immunity. The application design requires a series 3K resistor on each discrete input to achieve DO160 Level 3 and WF5A 500V immunity. Higher immunity levels can be achieved (i.e. Level 5) with the addition of a TVS between the resistor and the input pin. Table 1 Pin Description PINS 1-8 9-10 11 NAME DIN[1:8] NC CLK 12 /OE 13 14 19 22 15-18,20-21,23-24 VDD GND VCC GND DO[1:8] DESCRIPTION Discrete Inputs. Eight GND/OPEN discrete input signals. Not Connected. Latch Clock Logic Input A low level on this input enables transparent mode. A high level on this input enables latch mode. Output Enable Logic Input. Low input when /CS is low will enable the tri-state outputs Analog Supply Voltage. 12V to 16.5V Logic/Signal Ground Logic Supply Voltage. 3.3V+/-5% Logic Ground Logic Outputs. Eight tri-state data outputs DIN[1:8] Discrete AFE The Discrete Input Analog Front End circuit function is represented in Figure 3. Each DINn signal is conditioned by the resistor / diode network and presented to a comparator with hysteresis. The external 3K resistor is part of the front end circuitry for achieving threshold and hysteresis requirements while protecting the chip from Lightning Induced Transients. Some notable features are: The DIN source/sink current is ~ 1mA. This current will prevent a "dry" relay contact. The input threshold voltage and hysteresis: o Low-to-high threshold voltage: 10.5V > Vth > 9V o High-to-low threshold voltage: 4.5V < Vth < 6V o Hysteresis: Vhys > 3V Input noise immunity is maximized with a combination of voltage hysteresis and use of a slow input voltage comparator The inputs can withstand continuous input voltages of 49V minimum. The isolation diode breakdown voltage is greater than 45V. The 10K input resistance (consists of a 7K On-Chip resistor and a 3K Off-Chip resistor) is designed to limit diode breakdown current to safe levels during transient events. Table 2 Truth Table CLK /OE DIN[1:8] LATCH[1:8] DO[1:8] 1 1 1 X Output = HiZ, Latch = Hold mode Latch[1:8] <= DIN [1:8] 0 X 0 Hold 0 1 Hold DIN[1:8] 0 1 HiZ X 1 0 0 X Open Ground X X Ground Open Description Latch[1:8] X 0 1 Output = Latched data Latch = Transparent mode Output = Live data Legend: X = don't care input or undefined output HiZ = Hi Impedance (c)2013 Device Engineering Inc. 2 of 10 DS-MW-01198-01 Rev. B 9/9/2013 Figure 2 Function Block Diagram (two channels shown) Figure 33 Analog Front End Detail (c)2013 Device Engineering Inc. 3 of 10 DS-MW-01198-01 Rev. B 9/9/2013 LIGHTNING PROTECTION DINn inputs are designed to survive lightning induced transients as defined by RTCA DO160, Section 22, Cat A3 and B3, Waveforms 3, 4, and 5A. They can withstand Level 3 stress (and WF5A up to 500V) with the external 3 K series resistor for current limiting. Protection for higher stress levels can be achieved (for example: the 3200V of WF3 Level 5) with the addition of transient voltage suppressor (TVS) devices at the DINn pins. First select the TVS clamp voltage < 450V (the intrinsic 1198 device capability). A convenient value would be 48V, which reduces the TVS capacitance to the lowest practicable level. The 3K series resistor limits the TVS surge current, thus allowing small low power TVS devices. For additional technical information on TVS selection, please refer to DEI's 'Transient Voltage Suppressor' Application Note on www.deiaz.com. V V/I Peak 25% to 75% of Largest Peak T1 = 6.4us T2 = 70us 50% t 0 50% F = 1MHZ and 10MHZ 0 Figure 4 Voltage/Current Waveform 3 t T1 T2 Figure 5: Voltage/Current Waveform 4 V/I Peak T1=40us T2=120us Waveform Source Impedance characteristics: Waveform 3 Voc/Isc = 600V / 24A => 25 Waveform 4 Voc/Isc = 300 V / 60 A => 5 Waveform 5A Voc / Isc = 300V / 300A => 1 Waveform 5A Voc / Isc = 500V / 500A => 1 50% 0 T1 T2 t Figure 6 Voltage/Current Waveform 5A (c)2013 Device Engineering Inc. 4 of 10 DS-MW-01198-01 Rev. B 9/9/2013 ELECTRICAL DESCRIPTION Table 3 Absolute Maximum Ratings MIN MAX UNITS VCC Supply Voltage PARAMETER -0.3 +5.0 V VDD Supply Voltage -0.3 18 V -55 +85 C -55 +150 C -10 -600 -300 -500 +49 +600 +300 +500 80 VCC + 1.5 VCC + 0.5 V V V V V V V 0.8 W 145 C 2000 1000 235 V Operating Temperature Plastic Package Storage Temperature Plastic Package Input Voltage (3)(4) DIN[1:8] Continuous DO160, Waveform 3, Level 3 DO160, Waveform 4 and 5, Level 3 DO160, Waveform 4 and 5 DO160, Abnormal Surge Voltage, 100ms Logic Inputs DOUT Power Dissipation @ 85 C, steady state -1.5 -0.5 24L TSSOP Junction Temperature: Tjmax, Plastic Packages ESD per JEDEC A114 Human Body Model Logic and Supply pins DIN pins Peak Body Temperature (10 sec duration) C Notes: 1. Stresses above absolute maximum ratings may cause permanent damage to the device. 2. Voltages referenced to Ground 3. Stress applied to external 3 K series resistor in series with DINn pin. 4. Discrete input voltage amplitude tolerance for WF3, 4 and 5 are +20%/-0% Table 4 Recommended Operating Conditions PARAMETER Supply Voltage Logic Inputs and Outputs Discrete Inputs Operating Temperature Plastic (c)2013 Device Engineering Inc. SYMBOL CONDITIONS VCC VDD DIN[1:8] 3.3V5% 12.0V to 16.5V 0 to VCC 0 to 49V Ta -55 to +85 C 5 of 10 DS-MW-01198-01 Rev. B 9/9/2013 Table 5 DC Electrical Characteristics SYMBOL PARAMETER CONDITIONS (1)(2) LIMITS MIN NOM UNIT MAX Logic Inputs/Outputs V1IH V1IL VIhst VOH HI level input voltage LO level input voltage Input hysteresis voltage, SCLK input HI level output voltage VOL LO level output voltage IIN IOZ Input leakage 3-state leakage current V2IH VTLH RIH IIH V2IL VTHL RIL HI level input voltage Input Threshold Voltage, Low to High HI level DIN-to-GND resistance HI level input current LO level input voltage Input Threshold Voltage, High to Low LO level DIN-to-GND resistance IIL VIhst LO level input current Input hysteresis voltage ICC Max quiescent logic supply current Max quiescent analog supply current IDD Notes: 1. 2. 3. 4. VCC = 3.3V 2.0 50 V V mV VCC - 0.1 V 2.4 V 0.8 (3) I_DOUT = -20uA I_DOUT = -4mA, VCC = 3V I_DOUT = 20uA I_DOUT = 4mA, VCC = 3V VIN = VCC or GND Output in Hi Impedance state. DOUT = VIHmin, VILmax Discrete Inputs (4) Resistor from DIN to GND to guarantee HI input condition. DIN = 28V, VDD = 15V DIN = 49V, VDD = 15V -10 -10 0.1 0.4 10 10 V V uA uA 10.5 9.0 49 10.5 V V 240 2 4.5 6.0 uA mA V V 50K 1 1 -4.0 4.5 Resistor from DIN to GND to guarantee LO input condition. DIN = 0V, VDD = 15V Power Supply VIN(logic) = VCC or GND DIN[1:8]= open VIN(logic) = VCC or GND DIN[1:8]= Open DIN[1:8]= GND, All configured as Ground/Open 500 -0.8 3 -1.3 -1.8 mA V 1.8 3 mA 15 24 22 33 mA Ta = -55 to +85 C. VDD = 12.0 to 16.5V, VCC = 3.3V+/-5% unless otherwise noted Current flowing into device is `+'. Current flowing out of device is `-`. Voltages are referenced to Ground Guaranteed by design. Not production tested With 3K , 2% resistor in series with DIN input pin (c)2013 Device Engineering Inc. 6 of 10 DS-MW-01198-01 Rev. B 9/9/2013 Table 6 AC Electrical Characteristics SYMBOL PARAMETER CONDITIONS (1,2) UNIT LIMITS Min Max tHL Propagation delay, CLK = /OE=0 tLH DIN to to DO. (3) tHZ Output disable delay, /OE to DO HI-Z from tLZ DO Low or High (4)(5) tZH Output Enable delay, /OE to DO HI-Z from DO tZL Low or High (4)(5) tSU DIN setup time, DIN to CLK (6) 550 tH DIN hold time, DIN to CLK (6) Cin Logic input pin Capacitance. (7) Cout DOUT pin capacitance, output in HI-Z state. (7) Notes: 1. DOUT loaded with 50pF to GND. 2. Ta = -55 to +85C. VDD = 12V, VCC = 3V. VIL = 0V, VIH = VCC unless otherwise noted. 3. Timing measured from DO = 1.5V to VDIN = 9V(Rising Edge)/4.5V (Falling Edge). See Figure 7. 4. DOUT loaded with 1K to GND for Hi output, 1K Ohms to VCC for Low output. 5. 6. 7. 8. 550 ns 50 ns 50 ns 10 10 15 ns ns pf pf Timing measured from /OE=1.5V to DO=200mV. See Figure 7. Timing measured from CLK = 1.5V to VDIN = 9V(Rising Edge)/4.5V (Falling Edge). See Figure 7. Not production tested. Guaranteed by design. AC characteristics are sample tested on lot basis. TIMING DIAGRAMS 3.0 DIN 9 1.5 CLK 4.5 0 tHL tLH tSU HI HI DO tH 9 1.5 DIN 4.5 0 3.0 3.0 1.5 OE 0 1.5 1.5 OE 0 tZH HIGH Z tZL tHZ tLZ HIGH Z DO HI DO 1.3 LO 0.2 1.3 0.2 HIGH Z HIGH Z Figure 7 Switching Waveforms (c)2013 Device Engineering Inc. 7 of 10 DS-MW-01198-01 Rev. B 9/9/2013 APPLICATION INFORMATION Discrete Input Filtering The DEI1198 Analog Front End provides a moderate level of noise immunity via a combination of hysteresis and limited bandwidth. The Hysteresis is 3V minimum and the comparator bandwidth is approximately 10MHz. Many applications provide additional noise immunity by means of debounce/filtering in software or in digital circuitry (i.e. FPGA). Common input debounce techniques are readily found with a web search of the term "software debounce" and range from simple detectors of two or more sequential stable readings to FIR filters emulating RC time constants. Input Current Characteristics The DIN Input Current vs. Voltage characteristics are shown in Figure 8. Figure 8 Input IV Characteristics (VDD=15V) (c)2013 Device Engineering Inc. 8 of 10 DS-MW-01198-01 Rev. B 9/9/2013 Package Power Dissipation The DEI1198 power dissipation varies with operating conditions. Figure 9 shows the device package power dissipation for various operating conditions. This includes the contributions from Supply currents and DIN Input currents. The curves are as follows: Table 7 Legend for Power Dissipation Curves SUPPLY VOLTAGE, TEMPERATURE, IC VARIATION CURVE ID GND/OPEN-Nom 3.3V, 12V / 27C / typical IC parameters GND/OPEN-Wst 3.3V, 16.5V / 85C / Worst case IC parameters 800 Power Dissipation (mW) 700 600 500 GND/OPN-Nom GND/OPN-Wst 400 300 200 100 0 0 1 2 3 4 5 6 7 8 Number CH Active Number of Active Channels Figure 9 DEI1198 Power Dissipation vs Active Channels ORDERING INFORMATION Part Number DEI1198-TES-G Marking DEI1198-TES Package 24 TSSOP Temperature -55 / +85 C DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or guarantee regarding suitability of its products for any particular purpose. (c)2013 Device Engineering Inc. 9 of 10 DS-MW-01198-01 Rev. B 9/9/2013 PACKAGE DESCRIPTION - 24L TSSOP Moisture Sensitivity: ja: jc: Lead Finish: Materials: JEDEC Ref: MSL Level 1 / 260 C ~84 C/W ~16 C/W NiPdAu plated RoHS compliant MO-153-AD The PCB design and layout is a significant factor in determining thermal resistance ( ja) of the IC package. Use maximum trace width on all power and signal connections at the IC. These traces serve as heat spreaders which improve heat flow from the IC leads. Figure 10 24 Lead TSSOP Outline (c)2013 Device Engineering Inc. 10 of 10 DS-MW-01198-01 Rev. B 9/9/2013