TOSHIBA TC55257DPL/DFL/DFTL/DTRL-55L,-70L,-85L TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 32,768-WORD BY 8-BIT STATIC RAM DESCRIPTION The TC55257DPL/DFL/DFTL/DTRL is a 262,144-bit static random access memory (SRAM) organized as 32,768 words by 8 bits. Fabricated using Toshibas CMOS Silicon gate process technology, this device operates from a single 5 V + 10% power supply. Advanced circuit technology provides both high speed and low power at an operating current of 5mA/MHz (typ) and a minimum cycle time of 55 ns. It is automatically placed in low- power mode at 0.3 A standby current (typ) when chip enable (CE) is asserted high. There are two control inputs. CE is used to select the device and for data retention control, and output enable (OE) provides fast memory access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. The TC55257DPL/DFL/DFTL/DTRL is available in a standard plastic 28-pin dual-in-line package (DIP), plastic 28-pin small-outline package (SOP) and normal and reverse pinout plastic 28-pin thin-small-outline package (TSOP). FEATURES @ Low-power dissipation @ Access Times (maximum): Operating: 27.5 mW/MHz (typical) @ Standby current of 2 A (maximum) at TCS5257DPLUDFLIDFTU/DTRL Ta = 25C -55L -70L -85L @ Single power supply voltage of 5 V + 10% Access Time 55 ns 70 ns 85 ns @ Power down features using CE. CE Access Time 55 ns 70 ns 85 ns @ Data retention supply voltage of 2 to 5.5 V OE 30 35 45 @ Direct TTL compatibility for all inputs ang 2% Access Time - - - outputs Packages: DIP28-P-600-2.54(DPL) (Weight: 4.42 g typ) SOP28-P-450-1.27(DFL) (Weight: 0.79 g typ) TSOP I 28-P-0.55(DFTL) (Weight: 0.22 g typ) TSOP I 28-P-0.55A (DTRL) (Weight: 0.22 typ) PIN ASSIGNMENT (TOP VIEW) 28 PIN DIP & SOP o 28 PIN TSOP (Normal pinout) (Reverse pinout) TT aiali 28 1 Vop mT MONA ai2Q2 27 1] Raw 4 1 1 14 a7 U3 26H ai3 a6 La 25 Las as U5 24a [ag aalle 23 Hai a3 U7 22 lor a2Us 21 [1 aio aillg 20 ce ao 10 19 Ll vos vor 11 18 [1 vo7 vo2 [12 17 [1 vos vo3 013 16 [1 vos env Lia 15 [1 vo04 hs 28 28 15 Tm TM PIN NAMES AO te Al4 | Address Inputs PINNO. J}1/2/3/4]5]6]7 |8 ]9 |] 10] 11] 12] 13] 14 RAV Read/Write Control PIN NAME]OE|Aq;| Ag | Ag | A13 [RAV Vpp] Aia|Ai2| Az | Ag | As | Aa | Ag OE Output Enable PIN NO. [15/16/17] 18] 19 | 20] 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 ce Chip Enable PIN NAME] A; | A; | Ag [1/01] 1/02/1/03|GND]1/04|/05|06|1/07/1/08| CE [A 01 to 1/08 | Data Input/Output jij 10 Vop Power (+ 5V) GND Ground 961001EBA1 @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. @ The products described in this document are subject to foreign exchange and foreign trade control laws. @ The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 1998-08-05 1/11TOSHIBA TC55257DPL/DFL/DFTL/DTRL-55L,-70L,-85L BLOCK DIAGRAM Ee ao Vv AS wn n op AG now n ~o GND A7 ce | foe ws MEMORY CELL nN aL) |oa ARRAY Alt =! si 512 x 64x 8 we a (262144) Al3 S S SENSE AMP COLUMN ADDRESS DECODER COLUMN ADDRESS REGISTER DATA CONTROL os GENERATOR CLOCK AO A1 A2 A3 A4A10 OPERATION MODE MODE CE 01 to /O8 Read Dout Write Din Outputs Disabled H H High-Z Stand x x High-Z Note: x = don'tcare. H = logic high. L = logic low. ABSOLUTE MAXIMUM RATINGS SYMBOL RATING VALUE UNIT Vop Power Supply Voltage - 0.3 to 7.0 Vv Vin Input Voltage - 0.3* to 7.0 Vv Vio Input/Output Voltage 0.5* to Vpp + 0.5 Vv Pp Power Dissipation 1.0/0.6 ** Ww Tsolder Soldering Temperature (10s) 260 C Tstrg Storage Temperature - 55 to 150 C Topr Operating Temperature 0 to 70 C * 3.0V when measured at a pulse width of 50 ns ** SOP 1998-08-05 2/11TOSHIBA TC55257DPL/DFL/DFTL/DTRL-55L,-70L,-85L DC RECOMMENDED OPERATING CONDITIONS (Ta = 0 to 70C) SYMBOL PARAMETER MIN TYP MAX UNIT Vop Power Supply Voltage 4.5 5.0 5.5 Vin Input High Voltage 2.2 - Vop + 0.3 Vv VIL Input Low Voltage 0.3* - 0.8 VbH Data Retention Supply Voltage 2.0 - 5.5 * 3.0 V when measured at a pulse width of 50 ns DC CHARACTERISTICS (Ta = 0 to 70C, Vpp = 5V + 10%) SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT lit Input Leakage Current Vin = OV to Vop - - + 1.0 PA lou Output High Current Vou = 2.4V - 1.0 - - mA lot Output Low Current VoL = 0.4V 4.0 - - mA CE = Viy or RW = Vi, or OE = Viy _ _ + ILo Output Leakage Current Vout = 0V to Vpp + 1.0 PA CE = ViL teyele = 11S - 10 - Ippe1 RAW = Vin, lout = OMA = mA Other Inputs = Viy/ViL teycle = min - - 70 Operating Current CE=0.2V teycle = 1 ps _ 5 _ Ippo2 RW = Vpp - 0.2 V, lout = OMA mA Other Inputs = Vpp - 0.2.V/0.2V |teyecle = min - - 60 Ipps1 CE = Viq - - 3 mA Standby Current CE =Vpp - 0.2V Ta = 0 to 70C - - 20 Ipps2 =? BA Vpp = 2.0 to 5.5V Ta = 25C - 0.3 2 CAPACITANCE (Ta = 25C, f = 1 MHz) SYMBOL PARAMETER TEST CONDITION MAX UNIT Cin Input Capacitance Vin = GND 10 pF Cout Output Capacitance Vout = GND 10 pF Note: This parameter is periodically sampled and is not 100% tested. 1998-08-05 3/11TOSHIBA TC55257DPL/DFL/DFTL/DTRL-55L,-70L,-85L AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = 0 to 70C, Vpp = 5V + 10%) READ CYCLE 755257DPL/DFL/DFTL/DTRL SYMBOL PARAMETER -55L -70L -85L UNIT MIN MAX MIN MAX MIN MAX tre Read Cycle Time 55 - 70 - 85 - tacc Address Access Time - 55 - 70 - 85 tco Chip Enable Access Time - 55 - 70 - 85 tor Output Enable Access Time - 30 - 35 - 45 tcoe Chip Enable Low to Output Active 10 - 10 - 10 - ns toceE Output Enable Low to Output Active 5 - 5 - 5 - top Chip Enable High to Output High-Z - 20 - 25 - 30 topo Output Enable High to Output High-Z - 20 - 25 - 30 tou Output Data Hold Time 10 - 10 - 10 - WRITE CYCLE TC55257DPL/DFL/DFTL/DTRL SYMBOL PARAMETER -55L -70L -85L UNIT MIN MAX MIN MAX MIN MAX twe Write Cycle Time 55 - 70 - 85 - twp Write Pulse Width 45 - 50 - 60 - tow Chip Enable to End of Write 50 - 60 - 65 - tas Address Setup Time 0 - 0 - 0 - twr Write Recovery Time 0 - 0 - 0 - ns topw RAW Low to Output High-Z - 20 - 25 - 30 toew RAW High to Output Active 5 - 5 - 5 - tos Data Setup Time 25 - 30 - 40 - toy Data Hold Time 0 - 0 - 0 - AC TEST CONDITIONS Output load: 30 pF + one TTL gate (-55L) 100 pF + one TTL gate (-70L, -85L) Input pulse level: 0.6 V, 2.4 V Timing measurements: 1.5 V Reference level: 1.5 V tr, te: 5 ns 1998-08-05 4/11TOSHIBA TC55257DPL/DFL/DFTL/DTRL-55L,-70L,-85L TIMING DIAGRAMS tre ADDRESS Dout VALID DATA OUT INDETERMINATE WRITE CYCLE 1 (R/W CONTROLLED) Gee Note 4) twe ADDRESS RAV CE Dout tou Din Note 5) VALID DATA IN 1998-08-05 5/11TOSHIBA TC55257DPL/DFL/DFTL/DTRL-55L,-70L,-85L WRITE CYCLE 2 (GE CONTROLLED) (ee Note 4) R/W CE Dout toy Din VALID DATA IN Note: (1) R/W remains HIGH for the read cycle. (2) If CE goes LOW coincident with or after R/W goes LOW, the outputs will remain at high impedance. (3) If CE goes HIGH coincident with or before R/W goes HIGH, the outputs will remain at high impedance. (4) If OE is HIGH during the write cycle, the outputs will remain at high impedance. (5) Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. 1998-08-05 6/11TOSHIBA TC55257DPL/DFL/DFTL/DTRL-55L,-70L,-85L DATA RETENTION CHARACTERISTICS (Ta = 0 to 70C) SYMBOL PARAMETER MIN TYP MAX UNIT VbuH Data Retention Supply Voltage 2.0 - 5.5 Vv VpH =3.0V - - 10* Ipps2 Standby Current LA VoH=5.5V - - 20 Chip Deselect to Data Retention tepr . 0 - - Mode Time ns tr Recovery Time tRC (See Note) - * 2 pA(max) at Ta = 0 to 40C Note: Read cycle time. CE CONTROLLED DATA RETENTION MODE Vpp DATA RETENTION MODE (See Note) (See Note) Viq TTT A _ Vpp - 0.2V tepr GND Note: When CE is operating at the Vyq level (2.2 V), the standby current is given by Ippsi during the transition of Vpp from 4.5 to 2.4 V. 1998-08-05 7/11TOSHIBA TC55257DPL/DFL/DFTL/DTRL-55L,-70L,-85L PACKAGE DIMENSIONS (DIP28-P-600-2.54) Units in mm fa 28 15 Y Cod od) od) od od od Od dd od dd oO N st +! N o wn vf = +8, aq CIreroerocrcey cy Cy er CI CI Cy CIC Co ao 4 14 =f 37.5 MAX 37.040.2 3.5403 1.99 Typ Weight: 4.42 g (typ) 1998-08-05 8/11TOSHIBA TC55257DPL/DFL/DFTL/DTRL-55L,-70L,-85L PACKAGE DIMENSIONS (SOP28-P-450-1.27) Units in mm DOOOgUndeonogt- 4 ) PT ee L 0.995TYP 0.43+0.1 (510.250 8.840.2 11.8+0.3 (450mil) 1.27 7 19.0MAX , 18.520.2 ; WN x | aS 8 al $9 a in oy 70.1] ~ 40.1 0.1"6:05 Weight: 0.79 g (typ) 1998-08-05 9/11TOSHIBA TC55257DPL/DFL/DFTL/DTRL-55L,-70L,-85L PACKAGE DIMENSIONS (TSOP I 28-P-0.55) 14 : | 11.8+0.2 | 18 > - - in ; 13.440.2 ; iS " S ft \ . IN Ay Weight: 0.22 g (typ) Units in mm coy 8.2MAX 7.9+0.1 HHH 1.040.1 |_0-140.05 1998-08-05 10/11TOSHIBA TC55257DPL/DFL/DFTL/DTRL-55L,-70L,-85L PACKAGE DIMENSIONS (TSOP I 28-P-0.55A) Units in mm 0.08 HHA BABB ORO 8.2MAX 7.940.1 15 | | 14 1.0+0.1 | || 0.1+0.05 7 0.375TYP 4 9.15 9.08 0.50.1 Weight: 0.22 g (typ) 1998-08-05 11/11