and 5.0 V VCC are not required f or write or erase operations . The devices can also be reprogrammed in standard

EPROM pr ogrammers.

write enable (WE) , and output enable (OE) controls.

The de vice supports pin and command set compatible with JEDEC standard E2PROMs . Commands are written

to the command register using standard microprocessor write timings. Register contents ser ve as input to an

internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch

addresses and data needed for the programming and erase operations. Reading data out of the devices is similar

to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The device is programmed by executing the program command sequence. This will invoke the Embedded

Program Algorithm which is an internal algorithm that automatically times the program pulse widths and v erifies

and regulated voltages are provided for the program and erase operations. A low VCC detector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,

by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been

completed, the device internally returns to the read mode.

Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest

levels of quality, reliability, and cost effectiveness. The MBM29SL800TE/BE memories electrically erase the

addresses. Once the VID is taken aw ay from the RESET pin, all the pre viously protected sectors will be protected

again. See “Temporary Sector Unprotection Timing Diagram” in ■TIMING DIAGRAM and “Temporar y Sector

Unprotection Algorithm” in ■FLOW CHART.

Any operation in the process of being executed will be ter minated and the internal state machine will be reset

to the read mode 20 µs after the RESET pin is driven low. Fur ther more, once the RESET pin goes high, the

command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only

while the Sector Erase operation is in progress. Moreover both Reset commands are functionally equivalent,

to DQ8 bits are ignored.

In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read mode, the Reset operation

is initiated by writing the Reset command sequence into the command register. The de vice remains enabled f or

reads until the command register contents are altered.

The device will automatically power-up in the reset state. In this case, a command sequence is not required to

read data.

ology. The operation is initiated by writing the Autoselect command sequence into the command register.

logical “1” at device output DQ0 for a protected sector. The programming verification should be perform margin

internally generated program pulses and verify the programmed cell margin.

typical command strings and bus operations.

controls or timings during these operations.

erase command, the sector erase operation will begin.

Multiple sectors may be erased concurrently by writing the six bus cycle operations on “MBM29SL800TE/BE

controls or timings during these operations.

operation.

writing the Erase Suspend or Erase Resume command.

of 20 µs to suspend the erase operation. When the devices have entered the erase-suspended mode, the

data in this mode is the same as reading from the standard read mode except that the data must be read from

(DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address

while DQ6 can be read from any address.

chip has resumed erasing.

During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program

Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD) . (Refer to the

“Embedded ProgramTM Algorithm for Fast Mode” in ■FLOW CHART Extended algorithm.)

In addition to nor mal sector protection, the MBM29SL800TE/BE has Extended Sector Protection as extended

function. This function enable to protect sector by forcing VID on RESET pin and write a commnad sequence.

Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The only RESET

The MBM29SL800TE/BE also feature the “Toggle Bit I” as a method to indicate to the host system that the

write pulse sequence. The Toggle Bit I is active during the sector time out.

the command has been accepted, the system software should check the status of DQ3 prior to and following

have been accepted.

Furthermore, DQ2 can also be used to determine which sector is being erased. When the de vice is in the er ase

mode, DQ2 toggles if this bit is read from an erasing sector.

Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row

to determine whether a toggle bit is toggling. Typically a system would note and store the v alue of the toggle bit

after the first read. After the second read, the system would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has completed the progr am or er ase oper ation. The system can

How ev er, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system

mining the status as described in the previous par agraph. Alternatively, it may choose to perform other system

tasks. In this case, the system m ust start at the begining of the algorithm when it returns to determine the status

busy condition during the RESET pulse. Refer to “RY/BY Timing Diagram during Program/Erase Operation

Timing Diagram” and “RESET, RY/BY Timing Diagram” in ■TIMING DIAGRAM for a detailed timing diagram.

The RY/BY pin is pulled high in standby mode.

Since this is an open-drain output, the pull-up resistor needs to be connected to VCC; multiples of devices may

this pin is driven high, the de vices operate in the W ord (16-bit) mode . The data is read and programmed at DQ15

the memory contents only occurs after successful completion of specific multi-bus cycle command sequences.

The devices also incor porate several features to prevent inadvertent write cycles resulting form VCC power-up

Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a wr ite cycle CE and WE

must be a logical zero while OE is a logical one.

VSS to −2.0 V f or periods of up to 20 ns. Maximum DC v oltage on input or I/O pins is VCC + 0.5 V. During v oltage

transitions, input or I/O pins may overshoot to V CC + 2.0 V for periods of up to 20 ns.

(VIN - VCC) does not e xceed +9.0 V. Maximum DC input v oltage on A9, OE and RESET pins is +11.5 V which may