ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM 16Mb SYNCBURSTTM SRAM MT58L1MY18D, MT58V1MV18D, MT58L512Y32D, MT58V512V32D, MT58L512Y36D, MT58V512V36D 3.3V VDD, 3.3V or 2.5V I/O; 2.5V VDD, 2.5V I/O, Pipelined, Double-Cycle Deselect FEATURES 100-Pin TQFP1 * Fast clock and OE# access times * Single +3.3V 0.165Vor 2.5V 0.125V power supply (VDD) * Separate +3.3V or 2.5V isolated output buffer supply (VDDQ) * SNOOZE MODE for reduced-power standby * Common data inputs and data outputs * Individual BYTE WRITE control and GLOBAL WRITE * Three chip enables for simple depth expansion and address pipelining * Clock-controlled and registered addresses, data I/Os and control signals * Internally self-timed WRITE cycle * Burst control (interleaved or linear burst) * Automatic power-down * 100-pin TQFP package * 165-pin FBGA package * Low capacitive bus loading * x18, x32, and x36 versions available OPTIONS 165-Pin FBGA (Preliminary Package Data) TQFP MARKING* * Timing (Access/Cycle/MHz) 3.5ns/6ns/166 MHz 4.0ns/7.5ns/133 MHz 5ns/10ns/100 MHz * Configurations 3.3V VDD, 3.3V or 2.5V I/O 1 Meg x 18 512K x 32 512K x 36 2.5V VDD, 2.5V I/O 1 Meg x 18 512K x 32 512K x 36 -6 -7.5 -10 NOTE: 1. JEDEC-standard MS-026 BHA (LQFP). GENERAL DESCRIPTION MT58L1MY18D MT58L512Y32D MT58L512Y36D The Micron(R) SyncBurstTM SRAM family employs highspeed, low-power CMOS designs that are fabricated using an advanced CMOS process. Micron's 16Mb SyncBurst SRAMs integrate a 1 Meg x 18, 512K x 32, or 512K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE#), two additional chip enables for easy depth expansion (CE2, CE2#), burst control inputs (ADSC#, ADSP#, ADV#), byte write enables (BWx#) and global write (GW#). Note that CE2# is not available on the T Version. Asynchronous inputs include the output enable (OE#), clock (CLK) and snooze enable (ZZ). There is also MT58V1MV18D MT58V512V32D MT58V512V36D * Packages 100-pin TQFP (3-chip enable) 165-pin FBGA T F * Operating Temperature Range Commercial (0C to +70C) None *See page 34 for FBGA package marking guide. Part Number Example: MT58L1MY18DT-7.5 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM FUNCTIONAL BLOCK DIAGRAM 1 MEG x 18 20 SA0, SA1, SAs 18 20 ADDRESS REGISTER 2 MODE SA0-SA1 SA1' BINARY Q1 COUNTER AND LOGIC CLR Q0 ADV# CLK 20 SA0' ADSC# ADSP# BYTE "b" WRITE REGISTER BWb# BYTE "a" WRITE DRIVER 9 BYTE "a" WRITE REGISTER BWa# BYTE "b" WRITE DRIVER 9 9 1 Meg x 9 x 2 MEMORY ARRAY SENSE AMPS 18 OUTPUT BUFFERS OUTPUT 18 REGISTERS 18 DQs DQPa DQPb 18 E 9 BWE# GW# INPUT REGISTERS 18 ENABLE REGISTER CE# CE2 CE2# PIPELINED ENABLE 2 OE# FUNCTIONAL BLOCK DIAGRAM 512K x 32/36 19 SA0, SA1, SAs ADDRESS REGISTER 17 19 19 SA0-SA1 MODE SA1' Q1 BINARY COUNTER SA0' CLR Q0 ADV# CLK ADSC# ADSP# BWd# BYTE "d" WRITE REGISTER 9 BYTE "d" WRITE DRIVER 9 BWc# BYTE "c" WRITE REGISTER 9 BYTE "c" WRITE DRIVER 9 BWb# BWa# BWE# GW# CE# CE2 CE2# OE# 512K x 9 x 4 (x36) BYTE "b" WRITE REGISTER 9 BYTE "b" WRITE DRIVER 9 BYTE "a" WRITE REGISTER 9 BYTE "a" WRITE DRIVER 9 ENABLE REGISTER 512K x 8 x 4 (x32) 36 SENSE AMPS 36 OUTPUT REGISTERS 36 MEMORY ARRAY 36 PIPELINED ENABLE OUTPUT BUFFERS E 36 DQs DQPa DQPb DQPc DQPd INPUT REGISTERS 4 NOTE: Functional block diagrams illustrate simplified device operation. See truth table, pin descriptions and timing diagrams for detailed information. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM GENERAL DESCRIPTION (continued) controls DQds and DQPd. GW# LOW causes all bytes to be written. Parity bits are only available on the x18 and x36 versions. This device incorporates an additional pipelined enable register which delays turning off the output buffer an additional cycle when a deselect is executed. This feature allows depth expansion without penalizing system performance. Micron's 16Mb SyncBurst SRAMs operate from a +3.3V or +2.5V power supply, and all inputs and outputs are TTL-compatible. Users can implement either a 3.3V or 2.5V I/O for the +3.3V VDD or a 2.5V I/O for the +2.5V VDD. The device is ideally suited for Pentium(R) and PowerPC pipelined systems and systems that benefit from a very wide, high-speed data bus. The device is also ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-wide applications. Please refer to the Micron Web site (www.micronsemi.com/en/products/sram/) for the latest data sheet. a burst mode input (MODE) that selects between interleaved and linear burst modes. The data-out (Q), enabled by OE#, is also asynchronous. WRITE cycles can be from one to two bytes wide (x18) or from one to four bytes wide (x32/x36), as controlled by the write control inputs. Burst operation can be initiated with either address status processor (ADSP#) or address status controller (ADSC#) inputs. Subsequent burst addresses can be internally generated as controlled by the burst advance input (ADV#). Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During WRITE cycles on the x18 device, BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb. During WRITE cycles on the x32 and x36 devices, BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb; BWc# controls DQcs and DQPc; BWd# TQFP PIN ASSIGNMENT TABLE PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 x18 NC NC NC x32/x36 NC/DQPc1 DQc DQc VDDQ VSS NC DQc NC DQc DQb DQc DQb DQc VSS VDDQ DQb DQc DQb DQc NC VDD NC VSS DQb DQd DQb DQd VDDQ VSS DQb DQd DQb DQd DQPb DQd NC DQd PIN # 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 x18 x32/x36 VSS VDDQ NC DQd NC DQd NC NC/DQPd1 MODE (LBO#) SA SA SA SA SA1 SA0 DNU DNU VSS VDD SA SA SA SA SA SA SA SA SA PIN # 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 x18 NC NC NC x32/x36 NC/DQPa1 DQa DQa VDDQ VSS NC DQa NC DQa DQa DQa VSS VDDQ DQa DQa ZZ VDD NC VSS DQa DQb DQa DQb VDDQ VSS DQa DQb DQa DQb DQPa DQb NC DQb PIN # 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 x18 x32/x36 VSS VDDQ NC DQb NC DQb SA NC/DQPb1 SA SA ADV# ADSP# ADSC# OE# (G#) BWE# GW# CLK VSS VDD CE2# BWa# BWb# NC BWc# NC BWd# CE2 CE# SA SA NOTE: 1. No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM SA NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC PIN ASSIGNMENT (TOP VIEW) 100-PIN TQFP SA SA ADV# ADSP# ADSC# OE# (G#) BWE# GW# CLK VSS VDD CE2# BWa# BWb# NC NC CE2 CE# SA SA 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SA SA ADV# ADSP# ADSC# OE# (G#) BWE# GW# CLK VSS VDD CE2# BWa# BWb# BWc# BWd# CE2 CE# SA SA 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NC/DQPb1 DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa NC/DQPa1 NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC x18 SA SA SA SA SA SA SA SA SA VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE (LBO#) NC/DQPc1 DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd NC/DQPd1 x32/x36 SA SA SA SA SA SA SA SA SA VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE (LBO#) NOTE: 1. No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM TQFP PIN DESCRIPTIONS x18 x32/x36 37 37 36 36 32-35, 42-50, 32-35, 42-50, 80-82, 99, 81, 82, 99, 100 100 SYMBOL TYPE DESCRIPTION SA0 SA1 SA Input Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. 93 94 - - 93 94 95 96 BWa# BWb# BWc# BWd# Input Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. For the x18 version, BWa# controls DQa pins and DQPa; BWb# controls DQb pins and DQPb. For the x32 and x36 versions, BWa# controls DQa pins and DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins and DQPc; BWd# controls DQd pins and DQPd. Parity is only available on the x18 and x36 versions. 87 87 BWE# Input Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. 88 88 GW# Input Global Write: This active LOW input allows a full 18-, 32-, or 36-bit WRITE to occur independent of the BWE# and BWx# lines and must meet the setup and hold times around the rising edge of CLK. 89 89 CLK Input Clock: This signal registers the address, data, chip enable, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. 98 98 CE# Input Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the internal use of ADSP#. CE# is sampled only when a new external address is loaded. 92 92 CE2# Input Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded. 64 64 ZZ Input Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored. This pin has an internal pull-down and can be floating. 97 97 CE2 Input Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded. 86 86 OE# (G#) Input Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. G# is the JEDEC-standard term for OE#. 83 83 ADV# Input Synchronous Address Advance: This active LOW input is used to advance the internal burst counter, controlling burst access after the external address is loaded. A HIGH on this pin effectively causes wait states to be generated (no address advance). To ensure use of correct address during a WRITE cycle, ADV# must be HIGH at the rising edge of the first clock after an ADSP# cycle is initiated. (continued on next page) 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM TQFP PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL TYPE DESCRIPTION 84 84 ADSP# Input Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ is performed using the new address, independent of the byte write enables and ADSC#, but dependent upon CE#, CE2, and CE2#. ADSP# is ignored if CE# is HIGH. Powerdown state is entered if CE2 is LOW or CE2# is HIGH. 85 85 ADSC# Input Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ or WRITE is performed using the new address if CE# is LOW. ADSC# is also used to place the chip into power-down state when CE# is HIGH. 31 31 MODE (LBO#) Input Mode: This input selects the burst sequence. A LOW on this pin selects "linear burst." NC or HIGH on this pin selects "interleaved burst." Do not alter input state while device is operating. LBO# is the JEDEC-standard term for MODE. (a) 58, 59, (a) 52, 53, 62, 63, 68, 69, 56-59, 62, 63 72, 73 (b) 8, 9, 12, (b) 68, 69 13, 18, 19, 22, 72-75, 78, 79 23 (c) 2, 3, 6-9, 12, 13 (d) 18, 19, 22-25, 28, 29 DQa DQb Input/ SRAM Data I/Os: For the x18 version, Byte "a" is associated with Output DQa pins; Byte "b" is associated with DQb pins. For the x32 and x36 versions, Byte "a" is associated with DQa pins; Byte "b" is associated with DQb pins; Byte "c" is associated with DQc pins; Byte "d" is associated with DQd pins. Input data must meet setup and hold times around the rising edge of CLK. DQc DQd 74 24 - - 51 80 1 30 NC/DQPa NC/DQPb NC/DQPc NC/DQPd 15, 41, 65, 91 15, 41, 65, 91 VDD 4, 11, 20, 27, 4, 11, 20, 27, 54, 61, 70, 77 54, 61, 70, 77 VDDQ 5, 10, 17, 21, 5, 10, 17, 21, 26, 40, 55, 60, 26, 40, 55, 60, 67, 71, 76, 90 67, 71, 76, 90 VSS NC/ I/O No Connect/Parity Data I/Os: On the x32 version, these pins are No Connect (NC). On the x18 version, Byte "a" parity is DQPa; Byte "b" parity is DQPb. On the x36 version, Byte "a" parity is DQPa; Byte "b" parity is DQPb; Byte "c" parity is DQPc; Byte "d" parity is DQPd. Supply Power Supply: See DC Electrical Characteristics and Operating Conditions for range. Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range. Supply Ground: GND. 38, 39 38, 39 DNU - Do Not Use: These signals may either be unconnected or wired to GND to improve package heat dissipation. 1-3, 6, 7, 14 16, 25, 28-30, 51-53, 56, 57, 66, 75, 78, 79, 95, 96 14, 16, 66 NC - No Connect: These signals are not internally connected and may be connected to ground to improve package heat dissipation. NA NA NF - No Function: These pins are internally connected to the die and have the capacitance of an input pin. It is allowable to leave these pins unconnected or driven by signals. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM PIN LAYOUT (TOP VIEW) 165-PIN FBGA x18 x32/x36 10 11 BWE# ADSC# ADV# SA SA GW# OE# (G#) ADSP# SA NC VSS VSS VDDQ NC DQPa VSS VSS VDD VDDQ NC DQa VSS VSS VSS VDD VDDQ NC DQa VDD VSS VSS VSS VDD VDDQ NC DQa VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa VSS NC VDD VSS VSS VSS VDD NC NC ZZ DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQPb NC VDDQ VSS NC SA VSS VSS VDDQ NC NC NC NC SA SA DNU SA1 DNU SA SA SA SA MODE (LBO#) NC SA SA DNU SA0 DNU SA SA SA SA 1 2 3 4 5 6 NC SA CE# BWb# NC CE2# NC SA CE2 NC BWa# CLK NC NC VDDQ VSS VSS VSS NC DQb VDDQ VDD VSS NC DQb VDDQ VDD NC DQb VDDQ NC DQb VDD 7 8 9 A A B VSS VSS VDD VDDQ DQb DQb VSS VSS VSS VDD VDDQ DQb DQb VDD VSS VSS VSS VDD VDDQ DQb DQb VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb VSS NC VDD VSS VSS VSS VDD NC NC ZZ DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa NC/DQPd NC VDDQ VSS NC SA VSS VSS VDDQ NC NC/DQPa NC NC SA SA DNU SA1 DNU SA SA SA SA MODE (LBO#) NC SA SA DNU SA0 DNU SA SA SA SA CE2 BWd# BWa# CLK NC/DQPc NC VDDQ VSS VSS VSS DQc DQc VDDQ VDD VSS DQc DQc VDDQ VDD DQc DQc VDDQ DQc DQc VDD B C D E F G H J K L M N P R NC/DQPb SA M N P NC NC A L M N VDDQ CE2# K L M VSS BWc# BWb# J K L VSS CE# 9 H J K NC SA 8 G H J SA NC 7 F G H GW# OE# (G#) ADSP# 6 E F G NC 5 D E F SA 4 C D E BWE# ADSC# ADV# 3 B C D 11 2 A B C 10 1 N P R P R R TOP VIEW TOP VIEW *No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM FBGA PIN DESCRIPTIONS x18 x32/x36 6R 6R 6P 6P 2A, 2B, 3P, 2A, 2B, 3P, 3R, 4P, 4R, 6N, 3R, 4P, 4R, 6N, 8P, 8R, 9P, 9R, 8P, 8R, 9P, 10A, 10B, 10P, 9R, 10A, 10B, 10R, 11A, 11P, 10P, 10R, 11P, 11R 11R SYMBOL TYPE SA0 SA1 SA Input Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. DESCRIPTION 5B 4A - - 5B 5A 4A 4B BWa# BWb# BWc# BWd# Input Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. For the x18 version, BWa# controls DQa's and DQPa; BWb# controls DQb's and DQPb. For the x32 and x36 versions, BWa# controls DQa's and DQPa; BWb# controls DQb's and DQPb; BWc# controls DQc's and DQPc; BWd# controls DQd's and DQPd. Parity is only available on the x18 and x36 versions. 7A 7A BWE# Input Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. 7B 7B GW# Input Global Write: This active LOW input allows a full 18-, 32- or 36-bit WRITE to occur independent of the BWE# and BWx# lines and must meet the setup and hold times around the rising edge of CLK. 6B 6B CLK Input Clock: This signal registers the address, data, chip enable, byte write enables, and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. 3A 3A CE# Input Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the internal use of ADSP#. CE# is sampled only when a new external address is loaded. 6A 6A CE2# Input Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded. 11H 11H ZZ Input Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored. 3B 3B CE2 Input Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded. 8B 8B OE#(G#) Input Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. (continued on next page) 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM FBGA PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL TYPE DESCRIPTION 9A 9A ADV# Input Synchronous Address Advance: This active LOW input is used to advance the internal burst counter, controlling burst access after the external address is loaded. A HIGH on ADV# effectively causes wait states to be generated (no address advance). To ensure use of correct address during a WRITE cycle, ADV# must be HIGH at the rising edge of the first clock after an ADSP# cycle is initiated. 9B 9B ADSP# Input Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ is performed using the new address, independent of the byte write enables and ADSC#, but dependent upon CE#, CE2, and CE2#. ADSP# is ignored if CE# is HIGH. Powerdown state is entered if CE2 is LOW or CE2# is HIGH. 8A 8A ADSC# Input Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ or WRITE is performed using the new address if CE# is LOW. ADSC# is also used to place the chip into power-down state when CE# is HIGH. 1R 1R MODE (LB0#) Input Mode: This input selects the burst sequence. A LOW on this input selects "linear burst." NC or HIGH on this input selects "interleaved burst." Do not alter input state while device is operating. (a) 10J, 10K, (a) 10J, 10K, 10L, 10M, 11D, 10L, 10M, 11J, 11E, 11F, 11G 11K, 11L, 11M (b) 1J, 1K, (b) 10D, 10E, 1L, 1M, 2D, 10F, 10G, 11D, 2E, 2F, 2G 11E, 11F, 11G (c) 1D, 1E, 1F, 1G, 2D, 2E, 2F, 2G (d) 1J, 1K, 1L, 1M, 2J, 2K, 2L, 2M 11C 1N - - 11N 11C 1C 1N 1H, 4D, 4E, 4F, 1H, 4D, 4E, 4F, 4G, 4H, 4J, 4G, 4H, 4J, 4K, 4L, 4M, 4K, 4L, 4M, 8D, 8E, 8F, 8D, 8E, 8F, 8G, 8H, 8J, 8G, 8H, 8J, 8K, 8L, 8M 8K, 8L, 8M DQa DQb Input/ SRAM Data I/Os: For the x18 version, Byte "a" is associated DQas; Output Byte "b" is associated with DQbs. For the x32 and x36 versions, Byte "a" is associated with DQas; Byte "b" is associated with DQbs; Byte "c" is associated with DQcs; Byte "d" is associated with DQds. Input data must meet setup and hold times around the rising edge of CLK. DQc DQd NC/DQPa NC/DQPb NC/DQPc NC/DQPd VDD NC/ I/O No Connect/Parity Data I/Os: On the x32 version, these are No Connect (NC). On the x18 version, Byte "a" parity is DQPa; Byte "b" parity is DQPb. On the x36 version, Byte "a" parity is DQPa; Byte "b" parity is DQPb; Byte "c" parity is DQPc; Byte "d" parity is DQPd. Supply Power Supply: See DC Electrical Characteristics and Operating Conditions for range. (continued on next page) 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM FBGA PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL 3C, 3D, 3E, 3F, 3G, 3J, 3K, 3L, 3M, 3N, 9C, 9D, 9E, 9F, 9G, 9J, 9K, 9L, 9M, 9N 3C, 3D, 3E, 3F, 3G, 3J, 3K, 3L, 3M, 3N, 9C, 9D, 9E, 9F, 9G, 9J, 9K, 9L, 9M, 9N VDDQ TYPE DESCRIPTION Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range. 2H, 4C, 4N, 5C, 2H, 4C, 4N, 5C, 5D, 5E 5F, 5D, 5E 5F, 5G, 5H, 5J, 5G, 5H, 5J, 5K, 5L, 5M, 5K, 5L, 5M, 6C, 6D, 6E, 6F, 6C, 6D, 6E, 6F, 6G, 6H, 6J, 6G, 6H, 6J, 6K, 6L, 6M, 6K, 6L, 6M, 7C, 7D, 7E, 7C, 7D, 7E, 7F, 7G, 7H, 7F, 7G, 7H, 7J, 7K, 7L, 7J, 7K, 7L, 7M, 7N, 8C, 8N 7M, 7N, 8C, 8N VSS 5P, 5R, 7P, 7R 5P, 5R, 7P, 7R DNU - Do Not Use: These signals may either be unconnected or wired to GND to improve package heat dissipation. 1A, 1B, 1C, 1A, 1B, 1P, 1D, 1E, 1F, 2C, 2N, 2P, 1G, 1P, 2C, 2R, 3H, 5N, 2J, 2K, 2L, 9H, 10C, 10H, 2M, 2N, 2P, 10N, 11A, 11B 2R, 3H, 4B, 5A, 5N, 9H, 10C, 10D, 10E, 10F, 10G, 10H, 10N, 11B, 11J, 11K, 11L, 11M, 11N NC - No Connect: These signals are not internally connected and may be connected to ground to improve package heat dissipation. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 Supply Ground: GND. 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 X...X01 X...X00 X...X11 X...X10 X...X10 X...X11 X...X00 X...X01 X...X11 X...X10 X...X01 X...X00 LINEAR BURST ADDRESS TABLE (MODE = LOW) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 X...X01 X...X10 X...X11 X...X00 X...X10 X...X11 X...X00 X...X01 X...X11 X...X00 X...X01 X...X10 PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x18) FUNCTION GW# BWE# BWa# BWb# READ H H X X READ H L H H WRITE Byte "a" H L L H WRITE Byte "b" H L H L WRITE All Bytes H L L L WRITE All Bytes L X X X PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x32/x36) FUNCTION GW# BWE# BWa# BWb# BWc# BWd# READ H H X X X X READ H L H H H H WRITE Byte "a" H L L H H H WRITE All Bytes H L L L L L WRITE All Bytes L X X X X X NOTE: Using BWE# and BWa# through BWd#, any one or more bytes may be written. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM TRUTH TABLE (Notes 1-8) OPERATION DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down ADDRESS USED None None None None DESELECT Cycle, Power-Down SNOOZE MODE, Power-Down READ Cycle, Begin Burst READ Cycle, Begin Burst None None External External L X L L H X L L X X H H L H L L H X L L L X X X X X X X X X X X WRITE Cycle, Begin Burst READ Cycle, Begin Burst External External L L L L H H L L H H L L X X READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst External Next Next L X X L X X H X X L L L H H H L H H READ Cycle, Continue Burst READ Cycle, Continue Burst Next Next H H X X X X L L X X WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst Next Next Current X H X X X X X X X L L L READ Cycle, Suspend Burst READ Cycle, Suspend Burst Current Current X H X X X X READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst Current Current Current H X H X X X X X X CE# CE2# CE2 H X X L X L L H X L X L ZZ L L L L ADSP# ADSC# ADV# WRITE# OE# X L X X X L X X X X L X X X X H L X X X CLK L-H L-H L-H L-H DQ High-Z High-Z High-Z High-Z X X L H L-H X L-H L-H High-Z High-Z Q High-Z L H X L L-H L-H D Q X L L H H H H L H L-H L-H L-H High-Z Q High-Z H H L L H H L H L-H L-H Q High-Z H X H H H H L L H L L H X X L L-H L-H L-H D D Q L L H X H H H H H H H L L-H L-H High-Z Q L L L X H X H H H H H H H L L H X X L-H L-H L-H High-Z D D NOTE: 1. X means "Don't Care." # means active LOW. H means logic HIGH. L means logic LOW. 2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc# or BWd#) and BWE# are LOW or GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH. 3. BWa# enables WRITEs to DQa's and DQPa. BWb# enables WRITEs to DQb's and DQPb. BWc# enables WRITEs to DQc's and DQPc. BWd# enables WRITEs to DQd's and DQPd. DQPa and DQPb are only available on the x18 and x36 versions. DQPc and DQPd are only available on the x36 version. 4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held HIGH throughout the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM 3.3V VDD, ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Maximum junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. See Micron Technical Note TN-05-14 for more information. Voltage on VDD Supply Relative to VSS ................................ -0.5V to +4.6V Voltage on VDDQ Supply Relative to VSS ................................ -0.5V to +4.6V VIN (DQx) .................................... -0.5V to VDDQ + 0.5V VIN (inputs) ................................... -0.5V to VDD + 0.5V Storage Temperature (TQFP) .............. -55C to +150C Storage Temperature (FBGA) .............. -55C to +125C Junction Temperature** ................................... +150C Short Circuit Output Current ............................ 100mA 2.5V VDD, ABSOLUTE MAXIMUM RATINGS* Voltage on VDD Supply Relative to VSS ................................ -0.3V to +3.6V Voltage on VDDQ Supply Relative to VSS ................................ -0.3V to +3.6V VIN (DQx) .................................... -0.3V to VDDQ + 0.3V VIN (inputs) ................................... -0.3V to VDD + 0.3V Storage Temperature (TQFP) .............. -55C to +150C Storage Temperature (FBGA) .............. -55C to +125C Junction Temperature** ................................... +150C Short Circuit Output Current ............................ 100mA 3.3V VDD, 3.3V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (0C TA +70C; VDD = +3.3V 0.165V; VDDQ = +3.3V 0.165V unless otherwise noted) DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage CONDITIONS 0V VIN VDD Output(s) disabled, 0V VIN VDD IOH = -4.0mA IOL = 8.0mA Isolated Output Buffer Supply SYMBOL VIH MIN 2.0 MAX VDD + 0.3 UNITS V NOTES 1, 2 VIL ILI ILO -0.3 -1.0 -1.0 0.8 1.0 1.0 V A A 1, 2 3 VOH VOL VDD 2.4 - 3.135 - 0.4 3.465 V V V 1, 4 1, 4 1 VDDQ 3.135 3.465 V 1, 5 NOTE: 1. All voltages referenced to VSS (GND). 2. For 3.3V VDD: Overshoot: VIH +4.6V for t tKC/2 for I 20mA Undershoot: VIL -0.7V for t tKC/2 for I 20mA Power-up: VIH +3.6V and VDD 3.135V for t 200ms For 2.5V VDD: Overshoot: VIH +3.6V for t tKC/2 for I 20mA Undershoot: VIL -0.5V for t tKC/2 for I 20mA Power-up: VIH +2.65V and VDD 2.375V for t 200ms 3. MODE has an internal pull-up, and input leakage = 10A. 4. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the stated DC values. AC I/O curves are available upon request. 5. VDDQ should never exceed VDD. VDD and VDDQ can be connected together. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM 3.3V VDD, 2.5V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (0C TA +70C; VDD = +3.3V 0.165V; VDDQ = +2.5V 0.125V unless otherwise noted) DESCRIPTION Input High (Logic 1) Voltage CONDITIONS SYMBOL MIN MAX UNITS NOTES Data bus (DQx) Inputs VIHQ VIH 1.7 1.7 VDDQ + 0.3 VDD + 0.3 V V 1, 2 1, 2 Input Low (Logic 0) Voltage VIL -0.3 0.7 V 1, 2 0V VIN VDD ILI -1.0 1.0 A 3 Output(s) disabled, 0V VIN VDDQ (DQx) ILO -1.0 1.0 A Output High Voltage IOH = -2.0mA IOH = -1.0mA VOH VOH 1.7 2.0 - - V V 1, 4 1, 4 Output Low Voltage IOL = 2.0mA IOL = 1.0mA VOL VOL - - 0.7 0.4 V V 1, 4 1, 4 VDD 3.135 3.6 V 1 VDDQ 2.375 2.625 V 1 Input Leakage Current Output Leakage Current Supply Voltage Isolated Output Buffer Supply 2.5V VDD, 2.5V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (0C TA +70C; VDD = +2.5V 0.125V; VDDQ = +2.5V 0.125V unless otherwise noted) DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES Data bus (DQx) Inputs VIHQ VIH 1.7 1.7 VDDQ + 0.3 VDD + 0.3 V V 1, 2 1, 2 VIL -0.3 0.7 V 1, 2 0V VIN VDD ILI -1.0 1.0 A 3 Output(s) disabled, 0V VIN VDDQ (DQx) ILO -1.0 1.0 A Output High Voltage IOH = -2.0mA IOH = -1.0mA VOH VOH 1.7 2.0 - - V V 1, 4 1, 4 Output Low Voltage IOL = 2.0mA IOL = 1.0mA VOL VOL - - 0.7 0.4 V V 1, 4 1, 4 VDD 2.375 2.625 V 1 VDDQ 2.375 2.625 V 1 Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Supply Voltage Isolated Output Buffer Supply NOTE: 1. All voltages referenced to VSS (GND). 2. For 3.3V VDD: Overshoot: VIH +4.6V for t tKC/2 for I 20mA Undershoot: VIL -0.7V for t tKC/2 for I 20mA Power-up: VIH +3.6V and VDD 3.135V for t 200ms For 2.5V VDD: Overshoot: VIH +3.6V for t tKC/2 for I 20mA Undershoot: VIL -0.5V for t tKC/2 for I 20mA Power-up: VIH +2.65V and VDD 2.375V for t 200ms 3. MODE has an internal pull-up, and input leakage = 10A. 4. The load used for VOH, VOL testing is shown in Figure 4 for 2.5V I/O. AC load current is higher than the shown DC values. AC I/O curves are available upon request. 5. This parameter is sampled. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM TQFP CAPACITANCE DESCRIPTION Control Input Capacitance CONDITIONS SYMBOL TYP MAX UNITS NOTES TA = 25C; f = 1 MHz; CI 3 4 pF 1 VDD = 3.3V CO 4 5 pF 1 Address Capacitance CA 3 3.5 pF 1 Clock Capacitance CCK 3 3.5 pF 1 Input/Output Capacitance (DQ) FBGA CAPACITANCE DESCRIPTION CONDITIONS Address/Control Input Capacitance Output Capacitance (Q) TA = 25C; f = 1 MHz Clock Capacitance SYMBOL TYP MAX UNITS NOTES CI 2.5 3.5 pF 1 CO 4 5 pF 1 CCK 2.5 3.5 pF 1 TQFP THERMAL RESISTANCE DESCRIPTION Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Top of Case) CONDITIONS SYMBOL TYP Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. JA 46 UNITS NOTES C/W 1 JC 2.8 C/W 1 FBGA THERMAL RESISTANCE DESCRIPTION Junction to Ambient (Airflow of 1m/s) Junction to Case (Top) CONDITIONS SYMBOL TYP Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. qJA 40 C/W 1 qJC 9 C/W 1 qJB 17 C/W 1 Junction to Pins (Bottom) UNITS NOTES NOTE: 1. This parameter is sampled. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM IDD OPERATING CONDITIONS AND MAXIMUM LIMITS (Note 1, unless otherwise noted)(0C TA +70C) MAX DESCRIPTION CONDITIONS SYMBOL TYP -6 -7.5 -10 Power Supply Current: Operating Device selected; All inputs VIL or VIH; Cycle time tKC (MIN); VDD = MAX; Outputs open IDD 225 475 425 325 mA 2, 3, 4 Power Supply Current: Idle Device selected; VDD = MAX; ADSC#, ADSP#, GW#, BWx#, ADV# VIH; All inputs VSS + 0.2 or VDD - 0.2; Cycle time tKC (MIN) Device deselected; VDD = MAX; All inputs VSS + 0.2 or VDD - 0.2; All inputs static; CLK frequency = 0 IDD1 55 110 100 85 mA 2, 3, 4 ISB2 0.4 10 10 10 mA 3, 4 ISB3 8 25 25 25 mA 3, 4 ISB4 55 110 90 85 mA 3, 4 CMOS Standby TTL Standby Clock Running Device deselected; VDD = MAX; All inputs VIL or VIH; All inputs static; CLK frequency = 0 Device deselected; VDD = MAX; ADSC#, ADSP#, GW#, BWx#, ADV# VIH; All inputs VSS + 0.2 or VDD - 0.2; Cycle time tKC (MIN) UNITS NOTES NOTE: 1. If VDD = +3.3V, then VDDQ = +3.3V or +2.5V. If VDD = +2.5V, then VDDQ = +2.5V. Voltage tolerances: +3.3V 0.165 or +2.5V 0.125V for all values of VDD and VDDQ. 2. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and greater output loading. 3. "Device deselected" means device is in power-down mode as defined in the truth table. "Device selected" means device is active (not in power-down mode). 4. Typical values are measured at 3.3V, 25C, and 10ns cycle time. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM AC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (Notes 1, 10 unless otherwise noted) (0C TA +70C) -6 DESCRIPTION Clock Clock cycle time Clock frequency Clock HIGH time Clock LOW time Output Times Clock to output valid Clock to output invalid Clock to output in Low-Z Clock to output in High-Z OE# to output valid OE# to output in Low-Z OE# to output in High-Z Setup Times Address Address status (ADSC#, ADSP#) Address advance (ADV#) Write signals (BWa#-BWd#, BWE#, GW#) Data-in Chip enables (CE#, CE2#, CE2) Hold Times Address Address status (ADSC#, ADSP#) Address advance (ADV#) Write signals (BWa#-BWd#, BWE#, GW#) Data-in Chip enables (CE#, CE2#, CE2) SYMBOL MIN tKC 6.0 fKF tKH tKL tKQLZ 3.5 0 tAS tADSS tAAS tWS tDS tCES tAH tADSH tAAH tWH tDH tCEH 100 3.0 3.0 4.0 5.0 1.5 0 4.2 4.2 0 3.5 MAX 10 1.5 0 3.5 3.5 tOEHZ -10 MIN 133 2.5 2.5 1.5 0 tOEQ -7.5 MAX 7.5 2.3 2.3 tKQHZ tOELZ MIN 166 tKQ tKQX MAX 5.0 5.0 0 4.2 4.5 UNITS NOTES ns MHz ns ns 2 2 ns ns ns ns ns ns ns 3 3, 4, 5, 6 3, 4, 5, 6 7 3, 4, 5, 6 3, 4, 5, 6 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.0 2.0 2.0 2.0 ns ns ns ns 8, 9 8, 9 8, 9 8, 9 1.5 1.5 1.5 1.5 2.0 2.0 ns ns 8, 9 8, 9 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns 8, 9 8, 9 8, 9 8, 9 0.5 0.5 0.5 0.5 0.5 0.5 ns ns 8, 9 8, 9 NOTE: 1. Test conditions as specified with the output loading shown in Figure 1 for +3.3V I/O (VDDQ = +3.3V 0.165V) and Figure 3 for 2.5V I/O (VDDQ = +2.5V 0.125V) unless otherwise noted. 2. Measured as HIGH above VIH and LOW below VIL. 3. This parameter is measured with the output loading shown in Figure 2. 4. This parameter is sampled. 5. Transition is measured 500mV from steady state voltage. 6. Refer to Technical Note TN-58-09, "Synchronous SRAM Bus Contention Design Considerations," for a more thorough discussion on these parameters. 7. OE# is a "Don't Care" when a byte write enable is sampled LOW. 8. A WRITE cycle is defined by at least one byte write enable LOW and ADSP# HIGH for the required setup and hold times. A READ cycle is defined by all byte write enables HIGH and ADSC# or ADV# LOW or ADSP# LOW for the required setup and hold times. 9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when either ADSP# or ADSC# is LOW and chip enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP# or ADSC# is LOW to remain enabled. 10. If VDD = +3.3V, then VDDQ = +3.3V or +2.5V. If VDD = +2.5V, then VDDQ = +2.5V. Voltage tolerances: +3.3V 0.165 or +2.5V 0.125V for all values of VDD and VDDQ. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM 3.3V I/O Output Load Equivalents 3.3V VDD, 3.3V I/O AC TEST CONDITIONS Input pulse levels ................... VIH = (VDD/2.2) + 1.5V Q .................... VIL = (VDD/2.2) - 1.5V Z O= 50 Input rise and fall times ...................................... 1ns 50 Input timing reference levels ....................... VDD/2.2 VT = 1.5V Output reference levels ............................. VDDQ/2.2 Figure 1 Output load .............................. See Figures 1 and 2 +3.3V 3.3V VDD, 2.5V I/O AC TEST CONDITIONS 317 Input pulse levels ............... VIH = (VDD/2.64) + 1.25V Q ................ VIL = (VDD/2.64) - 1.25V 5pF 351 Input rise and fall times ...................................... 1ns Input timing reference levels ..................... VDD/2.64 Output reference levels ................................ VDDQ/2 Figure 2 Output load .............................. See Figures 3 and 4 2.5V VDD, 2.5V I/O AC TEST CONDITIONS 2.5V I/O Output Load Equivalents Input pulse levels .................... VIH = (VDD/2) + 1.25V Q ..................... VIL = (VDD/2) - 1.25V Z O= 50 Input rise and fall times ...................................... 1ns 50 Input timing reference levels .......................... VDD/2 VT = 1.25V Output reference levels ................................ VDDQ/2 Output load .............................. See Figures 3 and 4 Figure 3 +3.3V LOAD DERATING CURVES 317 Micron 1 Meg x 18, 512K x 32 and 512K x 36 SyncBurst SRAM timing is dependent upon the capacitive loading on the outputs. Consult the factory for copies of I/O current versus voltage curves. Q 351 5pF Figure 4 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM SNOOZE MODE ZZ is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When ZZ becomes a logic HIGH, ISB2Z is guaranteed after the setup time tZZ is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed. SNOOZE MODE is a low-current, "power-down" mode in which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time ZZ is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become gated inputs and are ignored. SNOOZE MODE ELECTRICAL CHARACTERISTICS DESCRIPTION Current during SNOOZE MODE CONDITIONS SYMBOL ZZ VIH ZZ active to input ignored MAX UNITS ISB2Z 10 mA tZZ 2(tKC) ns 1 ns 1 2(tKC) ns 1 ns 1 ZZ inactive to input sampled tRZZ ZZ active to snooze current tZZI tRZZI ZZ inactive to exit snooze current MIN 2(tKC) 0 NOTES NOTE: 1. This parameter is sampled. SNOOZE MODE WAVEFORM CLK t ZZ ZZ I t RZZ t ZZI SUPPLY I ISB2Z t ALL INPUTS (except ZZ) RZZI DESELECT or READ Only Outputs (Q) High-Z DON'T CARE 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM READ TIMING3 tKC CLK tKL tKH tADSS tADSH ADSP# tADSS tADSH ADSC# tAS tAH A1 ADDRESS A2 tWS A3 Burst continued with new base address. tWH GW#, BWE#, BWa#-BWd# tCES Deselect (NOTE 4) cycle. tCEH CE# (NOTE 2) tAAS tAAH ADV# ADV# suspends burst. OE# tOEQ tKQ t OELZ tKQX (NOTE 3) t KQLZ Q t OEHZ Q(A2) Q(A1) High-Z t KQHZ Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A3) t KQ Burst wraps around to its initial state. (NOTE 1) Single READ BURST READ DON'T CARE UNDEFINED READ TIMING PARAMETERS -6 SYM tKC fKF tKH tKL MIN 6.0 tKQLZ 2.3 2.3 tOEHZ 2.5 2.5 1.5 0 UNITS ns MHz SYM ns ns tAAS ns ns ns tCES 5.0 5.0 ns ns tAAH 4.5 ns ns 100 5.0 1.5 1.0 4.2 4.2 0 3.5 -6 MAX 3.0 3.0 1.5 0 0 MIN 10 4.0 3.5 3.5 tOEQ -10 MAX 133 3.5 tKQHZ tOELZ MIN 7.5 166 tKQ tKQX -7.5 MAX 0 4.2 MIN -7.5 MAX MIN -10 MAX MIN MAX UNITS tAS 1.5 1.5 2.0 ns tADSS 1.5 1.5 1.5 1.5 1.5 1.5 2.0 2.0 2.0 ns ns ns 1.5 0.5 1.5 0.5 2.0 0.5 ns ns tWH 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns tCEH 0.5 0.5 0.5 ns tWS tAH tADSH NOTE: 1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2. 2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause Q to be driven until after the following clock rising edge. 4. Outputs are disabled within two clock cycles after deselect. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM WRITE TIMING t KC CLK tKH tKL tADSS tADSH ADSP# ADSC# extends burst. tADSS tADSH tADSS tADSH ADSC# tAS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP# initiates burst. tWS tWH BWE#, BWa#-BWd# (NOTE 5) tWS tWH GW# tCES tCEH CE# (NOTE 2) tAAS tAAH ADV# ADV# suspends burst. (NOTE 4) OE# (NOTE 3) tDS D tDH D(A2) D(A1) High-Z D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) tOEHZ (NOTE 1) Q BURST READ Single WRITE BURST WRITE Extended BURST WRITE DON'T CARE UNDEFINED WRITE TIMING PARAMETERS -6 SYM tKC MIN 6.0 fKF tKH tKL -7.5 MAX MIN 7.5 166 2.3 2.3 tOEHZ -10 MAX MIN 10 133 2.5 2.5 MIN 1.5 100 MHz ns ns tCES 1.5 0.5 1.5 0.5 2.0 0.5 ns ns 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns 0.5 0.5 0.5 0.5 0.5 0.5 ns ns tAS 1.5 1.5 2.0 tADSS 1.5 1.5 1.5 1.5 1.5 1.5 2.0 2.0 2.0 ns ns ns tWS -10 SYM tDS 3.0 3.0 4.2 -7.5 UNITS ns ns ns tAAS 3.5 -6 MAX 4.5 tAH tADSH tAAH tDH tWH tCEH MAX MIN 1.5 MAX MIN 2.0 MAX UNITS ns NOTE: 1. D(A2) refers to input for address A2. D(A2 + 1) refers to input for the next internal burst address following A2. 2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/ output data contention for the time period prior to the byte write enable inputs being sampled. 4. ADV# must be HIGH to permit a WRITE to the loaded address. 5. Full-width WRITE can be initiated by GW# LOW; or by GW# HIGH, BWE# LOW and BWa#-BWb# LOW for x18 device; or GW# HIGH, BWE# LOW and BWa#-BWd# LOW for x32 and x36 devices. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM READ/WRITE TIMING3 tKC CLK tKL tKH tADSS tADSH ADSP# ADSC# tAS A1 ADDRESS tAH A2 BWE#, BWa#-BWd# (NOTE 4) tCES A4 A3 tWS tWH tDS tDH A5 A6 D(A5) D(A6) tCEH CE# (NOTE 2) ADV# OE# tKQ tOELZ D High-Z Q Q(A1) High-Z D(A3) tOEHZ tKQLZ Q(A2) Q(A4) Back-to-Back READs Single WRITE Q(A4+1) Q(A4+2) Q(A4+3) BURST READ Back-to-Back WRITEs (NOTE 5) DON'T CARE UNDEFINED READ/WRITE TIMING PARAMETERS -6 SYM tKC MIN -7.5 MAX 6.0 fKF MIN -10 MAX 7.5 166 MIN 133 2.3 2.5 3.0 tKL 2.3 2.5 3.0 tKQLZ tOELZ 3.5 0 0 tOEHZ tAS 4.0 0 0 3.5 1.5 UNITS 100 ns MHz ns 10 tKH tKQ -6 MAX 1.5 2.0 tADSS tWS tDS MIN -10 MAX MIN MAX UNITS 2.0 2.0 2.0 ns ns ns 1.5 0.5 1.5 0.5 2.0 0.5 ns ns 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns 0.5 0.5 ns 5.0 tADSH 4.5 ns ns ns tDH 0.5 0.5 0.5 ns tCEH 0.5 tWH MIN 1.5 1.5 1.5 tCES tAH -7.5 MAX 1.5 1.5 1.5 ns ns 1.0 0 4.2 SYM NOTE: 1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4. 2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed. 4. GW# is HIGH. 5. Back-to-back READs may be controlled by either ADSP# or ADSC#. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM TEST ACCESS PORT (TAP) IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG) TEST CLOCK (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. The SRAM incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 2.5V I/O logic levels. The SRAM contains a TAP controller, instruction register, boundary scan register, bypass register and ID register. TEST MODE SELECT (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. TEST DATA-IN (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see Figure 5. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Figure 6.) DISABLING THE JTAG FEATURE These pins can be left floating (unconnected), if the JTAG function is not to be implemented. Upon powerup, the device will come up in a reset state which will not interfere with the operation of the device. 1 TEST-LOGIC RESET 0 RUN-TEST/ IDLE 0 1 SELECT DR-SCAN 1 SELECT IR-SCAN 0 1 0 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 1 1 EXIT1-IR 0 1 0 PAUSE-DR 0 PAUSE-IR 1 0 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-DR 1 0 1 EXIT1-DR 0 1 UPDATE-IR 1 0 0 Figure 5 TAP Controller State Diagram NOTE: The 0/1 next to each state represents the value of TMS at the rising edge of TCK. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM TEST DATA-OUT (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. (See Figure 5.) The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Figure 6.) When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the boardlevel serial test data path. BYPASS REGISTER To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. PERFORMING A TAP RESET A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. BOUNDARY SCAN REGISTER The boundary scan register is connected to all the input and bidirectional pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for 9Mb and 18Mb Claymore SRAMs. The x36 configuration has a 68-bit-long register, and the x18 configuration has a 49-bit-long register. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the ShiftDR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the TAP REGISTERS Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. INSTRUCTION REGISTER Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in Figure 5. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. 0 Bypass Register 2 1 0 TDI Selection Circuitry Instruction Register 31 30 29 . . Selection Circuitry TDO . 2 1 0 Identification Register x . . . . . 2 1 0 Boundary Scan Register* TCK TMS TAP CONTROLLER *x = 49 for the x18 configuration, x = 68 for the x36 configuration. Figure 6 TAP Controller Block Diagram 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. register is connected to TDI, and the LSB is connected to TDO. IDENTIFICATION (ID) REGISTER The ID register is loaded with a vendor-specific, 32bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. TAP INSTRUCTION SET OVERVIEW Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals into the SRAM and cannot preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather it performs a capture of the I/O ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1-compliant. When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bi-directional pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold time (tCS plus tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/ PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between TDI and TDO. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. RESERVED These instruction are not implemented but are reserved for future use. Do not use these instructions. TAP TIMING 1 2 Test Clock (TCK) 3 tTHTL tMVTH tTHMX tDVTH tTHDX t TLTH 4 5 6 tTHTH Test Mode Select (TMS) Test Data-In (TDI) tTLOV tTLOX Test Data-Out (TDO) DON'T CARE UNDEFINED TAP AC ELECTRICAL CHARACTERISTICS (Notes 1, 2) (+20C TJ +100C; +2.4V VDD +2.6V) DESCRIPTION Clock Clock cycle time Clock frequency Clock HIGH time Clock LOW time Output Times TCK LOW to TDO unknown TCK LOW to TDO valid TDI valid to TCK HIGH TCK HIGH to TDI invalid Setup Times TMS setup Capture setup Hold Times TMS hold Capture hold SYMBOL MIN tTHTH 100 fTF tTHTL 10 tTLTH 40 40 tTLOX 0 tTHDX tMVTH tCS tTHMX tCH UNITS ns MHz ns ns 10 10 ns ns ns ns 10 10 ns ns 10 10 ns ns tTLOV tDVTH MAX 20 NOTE: 1. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 2. Test conditions are specified using the load in Figure 7. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM TAP AC TEST CONDITIONS 1.25V Input pulse levels ....................................... VSS to 2.5V 50 Input rise and fall times ......................................... 1ns Input timing reference levels ............................. 1.25V TDO Z O= 50 Output reference levels ..................................... 1.25V 20pF Test load termination supply voltage ............... 1.25V Figure 7 TAP AC Output Load Equivalent TAP DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (+20C TJ +110C; +2.4V VDD +2.6V unless otherwise noted) DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES VIH VIL 1.7 -0.3 VDD + 0.3 0.7 V V 1, 2 1, 2 0V VIN VDD Output(s) disabled, 0V VIN VDDQ (DQx) ILI ILO -5.0 -5.0 5.0 5.0 A A Output Low Voltage Output Low Voltage IOLC = 100A IOLT = 2mA VOL1 VOL2 0.2 0.7 V V 1 1 Output High Voltage Output High Voltage IOHC = -100A IOHT = -2mA VOH1 VOH2 V V 1 1 Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current 2.1 1.7 NOTE: 1. All voltages referenced to VSS (GND). 2. Overshoot: VIH (AC) VDD + 1.5V for t tKHKH/2 Undershoot: VIL (AC) -0.5V for t tKHKH/2 Power-up: VIH +2.6V and VDD 2.4V and VDDQ 1.4V for t 200ms During normal operation, VDDQ must not exceed VDD. Control input signals (such as LD#, R/W#, etc.) may not have pulse widths less than tKHKL (MIN) or operate at frequencies exceeding fKF (MAX). 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM IDENTIFICATION REGISTER DEFINITIONS INSTRUCTION FIELD 512K x 18 REVISION NUMBER (31:28) xxxx DESCRIPTION Reserved for version number. DEVICE DEPTH (27:23) 00111 Defines depth of 256K or 512K words. DEVICE WIDTH (22:18) 00011 Defines width of x18 or x36 bits. MICRON DEVICE ID (17:12) xxxxxx Reserved for future use. MICRON JEDEC ID CODE (11:1) 00000101100 ID Register Presence Indicator (0) 1 Allows unique identification of SRAM vendor. Indicates the presence of an ID register. SCAN REGISTER SIZES REGISTER NAME BIT SIZE Instruction 3 Bypass 1 ID 32 Boundary Scan 68 INSTRUCTION CODES INSTRUCTION CODE DESCRIPTION EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM FBGA BOUNDARY SCAN ORDER (x18) FBGA BIT# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 SIGNAL NAME SA SA SA SA SA SA SA DQa DQa DQa DQa ZZ DQa DQa DQa DQa DQPa SA SA SA ADV# ADSP ADSC# OE# (G#) BWE# GW# 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 PIN ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD FBGA BIT# 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 29 SIGNAL NAME CLK SA BWa# BWb# SA CE# SA SA DQb DQb DQb DQb VDD DQb DQb DQb DQb DQPb MODE (LBO#) SA SA SA SA SA1 SA0 PIN ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM FBGA BOUNDARY SCAN ORDER (x32/36) FBGA BIT# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 SIGNAL NAME SA SA SA SA SA SA SA NC/DQPa DQa DQa DQa DQa DQa DQa DQa DQa ZZ DQb DQb DQb DQb DQb DQb DQb DQb NC/DQPb SA SA ADV# ADSP# ADSC# OE# (G#) BWE# GW# CLK 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 PIN ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD FBGA BIT# 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 30 SIGNAL NAME SA BWa# BWb# BWc# BWd# SA CE# SA SA NC/DQPc DQc DQc DQc DQc DQc DQc DQc DQc VDD DQd DQd DQd DQd DQd DQd DQd DQd NC/DQPd MODE (LBO#) SA SA SA SA SA1 SA0 PIN ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM FBGA PART MARKING GUIDE SDK PC Product Family Speed Grade S = SRAM M = SRAM Mechanical sample X = SRAM Engineering sample B = C= D= F = G= H= J = K = Product Type B C D F G H J K = = = = = = = = QDRTM burst of 2 QDR burst of 4 DDR SyncBurstTM, Pipelined, Single-Cycle Deslect SyncBurst, Pipelined, Double-Cycle Deslect SyncBurst, Flow-Through ZBT(R), Pipelined ZBT, Flow-Through 2Mb, 3.3V VDD 2Mb, 2.5V VDD 2Mb, 1.8V VDD 4Mb, 3.3V VDD 4Mb, 2.5V VDD 4Mb, 1.8V VDD 8Mb, 3.3V VDD 8Mb, 2.5V VDD 8Mb, 1.8V VDD 16Mb, 3.3V VDD 16Mb, 2.5V VDD 16Mb, 1.8V VDD Q= R = S = T = V = W= X= Y = Z = L = M= N = P = Q = R = S = T = -8 -8.5 -9 -9.5 -10 -10.5 -11 -12 Width B = x18, 3.3V VDDQ C = x18, 2.5V VDDQ D = x18, 3.3V & 2.5V VDDQ F = x18, HSTL VDDQ G = x32, 3.3V VDDQ H = x32, 2.5V VDDQ J = x32, 3.3V & 2.5V VDDQ K = x32, HSTL VDDQ L = x36, 3.3V VDDQ M = x36, 2.5V VDDQ N = x36, 3.3V & 2.5V VDDQ P = x36, HSTL VDDQ Q = x72, 3.3V VDDQ R = x72, 2.5V VDDQ S = x72, 3.3V & 2.5V VDDQ T = x72, HSTL VDDQ Density B = C= D= F = G= H= J = K = L = M= N= P = -3 -3.3 -4 -4.4 -5 -6 -7 -7.5 32Mb, 3.3V VDD 32Mb, 2.5V VDD 32Mb, 1.8V VDD 64Mb, 3.3V VDD 64Mb, 2.5V VDD 64Mb, 1.8V VDD 128Mb, 3.3V VDD 128Mb, 2.5V VDD 128Mb, 1.8V VDD QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by Micron Technology, Inc., and Motorola Inc. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM 100-PIN PLASTIC TQFP (JEDEC LQFP) PIN #1 ID 22.10 +0.10 -0.15 0.15 +0.03 -0.02 0.32 +0.06 -0.10 0.65 20.10 0.10 DETAIL A 0.62 1.50 0.10 0.10 14.00 0.10 16.00 +0.20 -0.05 0.25 0.10 +0.10 -0.05 GAGE PLANE 1.00 (TYP) 0.60 0.15 1.40 0.05 DETAIL A NOTE: 1. All dimensions in millimeters MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM 165-PIN FBGA 0.85 0.075 0.10 A SEATING PLANE A +.05 O .45 -.10 TYP 10.00 1.00 (TYP) PIN A1 ID 1.20 MAX PIN A1 ID 7.50 0.05 14.00 15.00 0.10 7.00 0.05 1.00 (TYP) MOLD COMPOUND: EPOXY NOVOLAC SUBSTRATE: PLASTIC LAMINATE 6.50 0.05 SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb SOLDER BALL PAD: O .33mm 5.00 0.05 13.00 0.10 NOTE: 1. All dimensions in millimeters MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 SyncBurst is a trademark and Micron is a registered trademark of Micron Technology, Inc. Pentium is a registered trademark of Intel Corporation. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM REVISION HISTORY Changed FBGA capacitance values, Rev. 7/00, ADVANCE ............................................................................... Aug/8/00 CI; TYP 2.5 pF from 4 pF; MAX 3.5 pF from 5 pF CO; TYP 4 pF from 6 pF; MAX 5 pF from 7 pF CCK; TYP 2.5 pF from 5 pF; MAX 3.5 pF from 6 pF Removed Industrial Temperature references, Rev. 7/00, ADVANCE .............................................................. July/24/00 Added 165-pin FBGA package, Rev. 7/00, ADVANCE .................................................................................... Jun/28/00 Added FBGA part marking references Removed 119-pin PBGA and references Added Note: "IT available for -8.5 and -10 speed grades" Change Pin 14 to NC from VDD, Rev. 4/00, ADVANCE .................................................................................. Apr/13/00 Added note: ZZ has internal pull-down Updated Boundary Scan Order, Rev. 3/00, ADVANCE ..................................................................................... Apr/6/00 Added ADVANCE status, Rev. 1/00, ADVANCE .............................................................................................. Jan/18/00 MT58L1MY18D, Rev. 11/99, ADVANCE ........................................................................................................ Nov/11/99 Added BGA JTAG functionality 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 - Rev 7/00 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.