MNEATACYST CAT27C210/CAT27C2101 1 Megabit HIGH SPEED CMOS EPROM FEATURES m Fast Read Access Times: 150/170/200/250ns (Commercial) -170/200/250ns (Industrial) Single 5V SupplyRead Mode Low Power CMOS Dissipation: ~Active: 50 mA (Commercial) 60 mA (Industrial) -Standby: 100 pA m@ High Speed Programming: 100 p.s/word m CMOS and TTL Compatible /O @ 12.5V Programming Level mg JEDEC Standard Pinouts: 40 pin DIP and CERDIP -44 pin PLCC gw Electronic Signature DESCRIPTION The CAT27C210/CAT27C210! is a high speed low power 64K x 16 bits UV erasable and electronically re- programmable EPROM ideally suited for high speed applications. Any word can be accessed in less than 150ns making this device compatible with high perfor- mance microprocessor systems by eliminating the need for speed-robbing wait states. The Quick-Pulse programming algorithm reduces the time required to program the chip and ensures more re- liable programming. The CAT27C210/CAT27C2101 is used in applications where fast turnaround and pattern experimentation are important requirements. The CAT27C210/CAT27C2101 is manufactured using Catalysts advanced CMOS floating gate technology. The device is available in JEDEC approved 40 pin DIP and CERDIP and 44 pin PLCC packages. The transpar- ent lid on the 40 pin CERDIP allows the user the option of UV erasing the bit pattern in the device, thus allowing a new pattern to be written in. BLOCK DIAGRAM + X-BUFFERS 65,536 x 16 BIT _ LATCHES ARRAY ]_~s AND DECODER -Voc Ag-A15 ADDRESS I INPUTS ~< VpP > Y-BUFFERS LATCHES OUTPUT BUFFERS . +} AND DECODER READ/WRITE CKT vss CE +| VOg-V045 OE ! CONTROLLOGIC PGM + 5131 FHD Foe Note: (1) Quick-Pulse is a trademark of Intel Corporation. TO 5131 1992 by Catalyst Semiconductor, Inc. 9-13 Characteristics subject to change without noticeCAT27C210/CAT27C210! PIN CONFIGURATION DIP and CERDIP Package Vpp C1 400) Voc cE Cf 2 39 [7 PGM VO;, (3 38 [J NC VO14 4 37 FO Ais VOy3 0] 5 36 [J Aig VOyo 6 35 7 Aq3 Wy, 7 34 Ayo VOi19o 8 33 FF) Aqy Og CJ 9 32 FI Ayo Og CY 10 31 Ag Vss G11 30 FI Vss W712 aa DA Og C13 28D Az VOg 14 = 27 Dg W040] 15 26D As Oz [] 16 25 [7 Aq VOo CY 17 2477 Ag VO, (] 18 23 [J Ao Wp Cli9 2D A, OE 20 21 PA PLCC Package PIN FUNCTIONS Ao~A15 Addresses VOo-W/O1s Data Inputs/Outputs CE Chip Enable OE Output Enable PGM Write Enable NC No Connect Vpp Program Supply Voltage Voc 5V Supply Vss Ground at Ww esswie Sho fz DONO Aon v.27 65 43 2 1 44434241 493514 Ads O14 8 387) Ayo VOi;9 9 37 Ay /Qg [10 36 1 Ajo VOg CT 11 357 Ag Vss C12 341] Vss nc (13 331 NC VO7 C14 32 [7] Ag VOg C15 3117) Az Os C16 30 [7] Ag VvO4g C17 2977 As 18 19 20 21 22 23 24 25 26 27 28 UVOUUUUUUUOOUT ESCEBLLILLZ 5131 FHD Fot 9-14ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias .................... 55C to +125C Storage Temperature ........c eee -65C to +150C Voltage on Any Pin with Respect to Ground) ..0........ ~2.0V to Voc +2.0V Voltage on Pin Ag with Respect to Ground) 00.00. ~2.0V to +13.5V Vep with Respect to Ground during ProgranvErase ......... 2.0V to +14.0V Vcc with Respect to Ground .......0000000.. 2.0V to +7.0V Package Power Dissipation Capability (Ta = 25C) occ 1.0W Lead Soldering Temperature (10 secs) ... Output Short-Circuit Current oc RELIABILITY CHARACTERISTICS CAT27C210/CAT27C2101 *COMMENT Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specifica- tion is not implied. Exposure to any absolute maximum rating for extended periods may affect device perfor- mance and reliability. Symbol Parameter Min. Max. Units Test Method Vzap) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ITH @)5) Latch-Up 100 mA JEDEC Standard 17 CAPACITANCE Ta = 25C, f = 1.0 MHz, Vcc =5V Symbol Test Max. Units Conditions Cin) Input Capacitance 6 pF Vin = OV Cour) Output Pin Capacitance 10 pF Vout = OV CVppl) Vep Supply Capacitance 25 pF Vpp = OV Note: (2) This parameter is tested initially and after a design or process change. (3) The minimum DC input voltage is -0.5. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is Voc + 0.5V, which may overshoot to Vcc + 2.0V for periods of less than 20 ns. (4) Output shorted for no more than one second. No more than one output shorted ata time. (5) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to Vcc + 1V.CAT27C210/CAT27C2101 D.C. OPERATING CHARACTERISTICS, Read Operation CAT27C210 Ta = 0C to +70C, Voc = +5V +10%, unless otherwise specified. CAT27C2101 Ta = 40C to +85C, Veco = +5V +10%, unless otherwise specified. Limits Symbol Parameter Min. Typ. Max. | Units Test Conditions icc) Vcc Operating Current Com. 60 CE = Vit, f = 5MHz (TTL) Ind. 70 mA All /Os Open iccc | Vcc Operating Current Com. 50 CE = Vic, f = 5MHz (CMOS) Ind. 60 mA All /Os Open Isp1 Vcc Standby Current Com. 1 CE =Vit (TTL) Ind. 1 mA Ispe Vcc Standby Current Com. 100 CE=Vit (CMOS) Ind. 100 pA let Input Leakage Current 1 pA Vin = 5.5V lLo Output Leakage Current 1 pA Vout = 5.5V Ipp1 Vpp Leakage Current 1 pA Vpp =5.5V Vin Input High Level TTL 2.0 Vec +0.5 Vv Viv Input Low Level TTL -0.5 0.8 Vv Vou Output Voltage High Level 2.4 Vv loH = -1.0 mA Vou Output Voltage Low Level 0.40 Vv lo. = 4.0 mA Vic Input Low Level CMOS 0.5 0.30 Vv Vinc Input High Level CMOS Vec-05 Vcc +0.5 Vv Note: (6) The maximum current value is with outputs I/O9 to 1/01. unloaded.CAT27C210/CAT27C2101 A.C. CHARACTERISTICS, Read Operation CAT27C210 Ta = 0C to +70C, Voc = +5V +10%, unless otherwise specified. CAT27C2101 Ta = 40C to +85C, Voc = +5V +10%, unless otherwise specified. 27C210-17 270210-20 27C210-25 27C210-15 27C2101-17 27C2101-20 27C210I-25 Symbol Parameter Min Max. | Min. | Max. | Min. | Max.| Min. | Max. | Unit tacc Address Access Time 150 170 200 250 ns tce CE to Output Delay 150 170 200 250 ns toe OE to Output Delay 60 70 80 100 ns ton(X7) | Output Hoid A, OE, CE 0 0 a) ns tor) | OE High to High-Z Output 0 35 0 40 0 50 0 60 ns Figure 1. A.C. Testing Input/Output Waveform() 24V SOV INPUT PULSE LEVELS REFERENCE POINTS 0.45V 0.8V 5131 FHD Fo2 Figure 2. A.C. Testing Load Circuit (example) 1.3V 1N914 3.3K DEVICE UNDER OUT TEST cL= 100 pF IT C_ INCLUDES JIG CAPACITANCE 5129 FHD Fos Note: (2) This parameter is tested initially and after a design or process change. (7) Output floating (High-Z) is defined as the state where the extemal data line is no longer driven by the output buffer. (8) Input rise and fall times (10% to 90%) <10ns.CAT27C210/CAT27C2101 D.C. CHARACTERISTICS, Programming Operation CAT27C210 Ta = 25C +5C CAT27C2101 Ta = 25C +5C Limits Symbol Parameter Min. Typ. Max. Units Test Conditions Supply Voltage 6.0 6.25 6.5 Vv Veco (Quick Pulse Algorithm) Supply Voltage 5.75 6.0 6.25 Vv (Intelligent Algorithm) Programming Voltage 12.5 12.75 13.0 Vv VppX19) | (Quick Pulse Algorithm) Programming Voltage 12.0 12.5 13.0 Vv (Intelligent Algorithm) iccp) Vcc Supply Current 45 mA CE =Vir Program and Verify Ipp) Vpp Supply Current 40 mA CE =Vit Program Operation lu Input Leakage Current 10 pA Vin = 5.25V ILo Output Leakage Current 10 pA Vout = .25V Vit Input Low-Level TTL -0.50 0.80 Vv Vite Input Low-Level CMOS -0.50 0.30 Vv Vin Input High-Level TTL 2.0 Veco + 0.5 Vv Vic Input High-Level CMOS Vcc 0.50 Vec + 0.5 Vv Voi Output Low Voltage (Verify) 0.40 Vv lo. =2.4mA Vou Output High Voltage (Verify) 2.4 Vv lon = 400 pA Vi(6)(9) Ag Signature Mode Voltage 11.5 12.5 V Note: (6) The maximum current value is with outputs !/Og to 1/015 unloaded. (9) Vcc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. (10) When programming, a 0.1 uF capacitor is required across Vpp and GND to suppress spurious voltage transients which can damage the device.A.C, CHARACTERISTICS, Programming Operation CAT27C210 Ta = 25C +5C CAT27C210I Ta = 25C +5C CAT27C210/CAT27C2101 Limits Symbol Parameter Min. Typ. Max. Unit Test Conditions tas Address Setup Time 2 ps toes OE Setup Time 2 us tos Data Setup Time 2 ys taH Address Hold Time 0 ys tox Data Hold Time 2 ps tvps() Vpp Setup Time 2 Ls tvcs) Vcc Setup Time 2 ys tpw CE Program Pulse Width 95 100 105 bs (Quick Pulse Algorithm) tpw CE Program Pulse Width 0.95 1.0 1.05 ms (Intelligent Algorithm) topw CE Overprogram Pulse Width 2.85 78.5 ms (Intelligent Algorithm) torp@) | OE High to Output High-Z 0 130 ns toe Data Valid from OE 150 ns Note: (2) This parameter is tested initially and after a design or process change. {7) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer. (9) Vcc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.CAT27C210/CAT27C2101 FUNCTION TABLE Pins Mode CE OE Vpp PGM Ao Ag 0 Read Vit VIL Vec xX Xx xX Dout Output Disable Vit Vin Vec Xx X X High-Z Standby Vi xX Vec x xX Xx High-Z Program Vit Vin Vpp Vit xX x Din Program Verify Vit VIL Vpp Vin xX X Dout Program Inhibit Vin X Vpp X xX X High-Z Signature MFG. Vit Vit Voc Xx VIL VH 0031H Signature Device Vit Vit Vcc Xx Vin Vu 0007H NOTES ON THE FUNCTION TABLE Logic Levels: Supply Voltage: Read: Output Disable: Standby: Program: Program Verify: Program Inhibit: Signature MFG: Signature Device: Vin = TTL Logic 1 level Vit = TTL Logic 0 level X =Logic Do not care, Vin or ViL Vpp = Programming/High-Voltage Voc = Read/Low-Voltage Vu = 12.0V +0.5V Read Mode: The content of the addressed memory word is placed on the I/O pins I/Oo to I/O15. Device is selected (active mode), programming is disabled and I/Opo to /Q15 output buffers are tristated (PMOS and NMOS drivers turned-off). Device is deselected, low power dissipation. Word Programming Mode: Logic zeros in the bit pattern driving the I/Oo to 1/O15 data input buffers are written into the respective memory cells of the addressed word. Following a programming cycle, to verify the cell contents of the memory word being programmed (not recommended as a normal read operation). CE set to logic one prevents programming and deselects the device. Signature mode with all other addresses at Vi_, code of IC manufacturer (Catalyst) output on I/O pins l/Oo to 1/045. Signature mode with all other addresses at ViL, code of IC type output on I/O pins I/Opo to I/O15.CAT27C210/CAT27C2101 DEVICE OPERATION Read Operation and Standby Modes Memory access for reading an address location is con- trolled by CE and OE. Chip enable CE is used indepen- dently of all other input signals as the primary device selection. In the logic zero state (TTL level Vit), CE powers up all inputs and enables internal circuitry. Inthe logic one state (CMOS level Vic) CE places the device in standby mode, all DC paths to ground are shut-off, and the power dissipation is reduced to a minimum. A logic one on Output Enable OE disables the output buffers and places the output pads in a high impedance state. Assuming that the address lines Ao to Ais have been stable for a time equal to tacc toe, the output data is available after a delay of toe from the falling edge of OE. Signature Mode The Signature Mode allows one to identify the |C manu- facturer and the device type. This mode is entered as a regular Read Mode by driving the CE and OE inputs low, and additionally driving the Ag pin to high-voltage (Vx) with all other address lines at Vic. Driving Aoto Vi with all other addresses at Vi, gives the the binary code of the IC manufacturer on outputs |/Oo to /O4s. CATALYST Code: 0000 0000 0011 0001 (0031H) Driving Aoto Vin with all other addresses at ViL, gives the the binary code of the device type on outputs I/Op9 to /O15. 27C210/27C210I Code: 0000 0000 0000 0111 (0007H) Figure 3. Read Operation Timing Vi ADDRESS Vit VIH Vit VIH VIL HIGH-Z OUTPUT ADDRESSES VALID OH VALID OUTPUT 5129 FHD F04 9-21CAT27C210/CAT27C2101 Programming Mode As shipped, all the bits of the CAT27C210/CAT27C2101 are in the logic 1 state. The device is programmed by selectively writing logic O"s into the desired bit locations. To enter the programming mode, Vcc and Vpp must be adjusted to their programming levels, CE pulled to Vit, and a program write pulse applied to the PGM pin. After the program write pulse, the programmed data may then be verified by enabling the outputs (OE = Vi, CE = Vit, and PGM = Vin), then comparing the written data to the read data. This device is compatible with Intelligent (2) and the Quick-Pulse Programming algorithms. The flow charts for both the algorithms are given in Figures 5 and 6. Figure 4. Programming Operation Timing VIH ADDRESS VIL tas DATA HIGH-Z DATA INPUT tos tDH VPP Vpp Voc 6.25/6V(11) Vcc 5V VI cE VIL ViH PGM Vit ViH OE VIL Note: PROGRAM ADDRESS VERIFY $131 FHD FOS. (11) Vec = 6.25V +0.25V for Quick Pulse algorithm; 6.0V +0.25V for Intelligent Programming algorithm. (12) Intelligent is a trademark of Intel Corporation. 9-22U.V. ERASURE OPERATION FOR CERDIP EPROMS Direct exposure to fluorescent lamps such as those used in room light fixtures, can erase the CAT27C210/ CAT27C210i EPROM in less than three years. When exposed to direct sun light the EPROM can be erased in less than a week. The recommended erasure procedure is to expose the CAT27C210/CAT27C2101 EPROM to a standard ultra- violet light with a wavelength of 2537 Angstroms. The integrated dose for proper erasure is 15 Wsec/cm?2. The CAT27C210/CAT27C2101 erasure time with this dosage is approximately 15 to 60 minutes using an ultraviolet lamp with a 1200 pW/cm? power rating. The EPROM should be placed within 1 inch of the lamp tubes. The maximum integrated dose a CAT27C210/ CAT27C210| EPROM can be exposed to is 7258 Wsec/ cm? (one week at 1200 uW/cm?). Exposure of the device tohigher U.V. doses may cause permanent damage and loss of functionality. Figure 5. Quick Pulse Algorithm ADDR = FIRST LOCATION Voc = 6.25V Vpp = 12.75V PROGRAM 100 ps PULSE INCREMENT X VERIFY WORD PASS LAST ADDRESS? YES Voc = Vpp =5,0V YES INCREMENT ADDRESS COMPARE ALL WORDS TO ORIGINAL DATA DEVICE FAILED DEVICE PASSED $131 FHD Fo7 Figure 6. Intelligent Programming Algorithm PROGRAM 1ms PULSE INCREMENT X L VERIFY WORD PASS PROGRAM 1 PULSE OF 3X ms DURATION INCREMENT ADDRESS LAST ADDRESS? YES Voc = Vpp =5.0V COMPARE ALL WORDS TO ORIGINAL DATA FAIL DEVICE FAILED DEVICE PASSED $131 FHD Foe 9-23