515ABA98M0000AAG - Silicon Labs

VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO)

100 kHZ TO 250 MHZ

Features

Applications

Description

The Si515 VCXO utilizes Silicon Laboratories' advanced PLL technology to

provide any frequency from 100 kHz to 250 MHz. Unlike a traditional VCXO where

a different crystal is required for each output frequency, the Si515 uses one fixed

crystal and Silicon Labs’ proprietary synthesizer to generate any frequency across

this range. This IC-based approach allows the crystal resonator to provide

enhanced reliability, improved mechanical robustness, and excellent stability. In

addition, this solution provides superior control voltage linearity and supply noise

rejection, improving PLL stability and simplifying low jitter PLL design in noisy

environments. The Si515 is factory-configurable for a wide variety of user

specifications, including frequency, supply voltage, output format, tuning slope and

stability. Specific configurations are factory-programmed at time of shipment,

eliminating long lead times and non-recurring engineering charges associated with

custom frequency oscillators.

Functional Block Diagram

Supports any frequency from

100 kHz to 250 MHz

Low-jitter operation

Short lead times: <2 weeks

AT-cut fundamental mode crystal

ensures high reliability/low aging

High power supply noise rejection

1% control voltage linearity

Available CMOS, LVPECL, LVDS,

and HCSL outputs

Optional integrated 1:2 CMOS

fanout buffer

3.3 and 2.5 V supply options

Industry-standard 3.2 x 5.0 mm

and 5 x 7 mm package/pinouts

Pb-free/RoHS-compliant

Selectable Kv (60, 90, 120,

150 ppm/V)

SONET/SDH/OTN

PON

Low Jitter PLLs

xDSL

Broadcast video

Telec o m

Switches/routers

FPGA/ASIC clock generation

VDD

Any-Frequency

0.1 to 250 MHz

Clock Synthesis

Fixed

Frequency

Oscillator

CLK+

CLK–

GND

Vc ADC

Power Supply Filtering

Ordering Information:

See page 14.

Pin Assignments:

See page 12.

Si5602

VDD

CLK–

CLK+

GND

LVPECL/LVDS/HCSL/

Dual CMOS VCXO

VDD

CLK

GND

CMOS VC XO

Si515

2 Rev. 1.0

Si515

Rev. 1.0 3

TABLE OF CONTENTS

Section Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

2.1. Dual CMOS Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

4. Package Outline Diagram: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

5. PCB Land Pattern: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

6. Package Outline Diagram: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

7. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

8. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

8.1. Si515 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

8.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Si515

4 Rev. 1.0

1. Electrical Specifications

Table 1. Recommended Operating Conditions

VDD = 2.5 or 3.3 V ±10%, TA = –40 to +85 oC

Parameter Symbol Test Condition Min Typ Max Unit

Supply Voltage

VDD

3.3 V option 2.97 3.3 3.63 V

2.5 V option 2.25 2.5 2.75 V

Supply Current

IDD

CMOS, 100 MHz,

single-ended

—2429mA

LVDS

(output enabled)

—2226mA

LVPECL

(output enabled)

—4246mA

HCSL

(output enabled)

—4447mA

Tristate

(output disabled)

——22mA

OE “1” Setting VIH See Note 0.80 x VDD ——V

OE “0” Setting VIL See Note — — 0.20 x VDD V

OE Internal Pull-Up/

Pull-Down Resistor*

RI—45—k

Operating Temperature TA–40 — 85 oC

*Note: Active high and active low polarity OE options available. Active high uses internal pull-up. Active low uses internal pull-

down. See ordering information on page 13.

Si515

Rev. 1.0 5

Table 2. Vc Control Voltage Input

VDD = 2.5 or 3.3 V ±10%, TA = –40 to +85 oC

Parameter Symbol Test Condition Min Typ Max Unit

Control Voltage Range VC0.1 x VDD VDD/2 0.9 x VDD V

Control Voltage Tuning Slope

(10 to 90% VDD)

Kv Positive slope,

ordering option

60, 90, 120, 150 ppm/V

Kv Variation Kv_var — — ±10 %

Control Voltage Linearity LVC BSL –5 ±1 +5 %

Modulation Bandwidth BW — 10 — kHz

Vc Input Impedance ZVC —100—k

Table 3. Output Clock Frequency Characteristics

VDD = 2.5 or 3.3 V ±10%, TA = –40 to +85 oC

Parameter Symbol Test Condition Min Typ Max Unit

Nominal Frequency FOCMOS, Dual CMOS 0.1 — 212.5 MHz

FOLVDS/LVPECL/HCSL 0.1 — 250 MHz

Temperature Stability STTA = –40 to +85 oC –20 — +20 ppm

Aging A Frequency drift over 10 year life — — ±8.5 ppm

Minimum Absolute Pull Range APR Ordering option ±30, ±50,±80, ±100 ppm

Startup Time TSU Minimum VDD to output fre-

quency (FO) within specification

——10ms

Disable Time TDFO

10 MHz — — 5 µs

FO<10MHz 40 µs

Enable Time TEFO

10 MHz — — 20 µs

FO<10MHz 60 µs

Si515

6 Rev. 1.0

Table 4. Output Clock Levels and Symmetry

VDD = 2.5 or 3.3 V ±10%, TA = –40 to +85 oC

Parameter Symbol Test Condition Min Typ Max Unit

CMOS Output Logic High VOH 0.85 x VDD ——V

CMOS Output Logic Low VOL — — 0.15 x VDD V

CMOS Output Logic High

Drive IOH

3.3 V –8 — — mA

2.5 V –6 — — mA

CMOS Output Logic Low

Drive IOL

3.3 V 8 — — mA

2.5 V 6 — — mA

CMOS Output Rise/Fall Time

(20 to 80% VDD)

TR/TF

0.1 to 125 MHz,

CL = 15 pF —0.81.2ns

0.1 to 212.5 MHz,

CL = no load —0.60.9ns

LVPECL/HCSL Output

Rise/Fall Time

(20 to 80% VDD)

TR/TF——565ps

LVDS Output Rise/Fall Time

(20 to 80% VDD)TR/TF——800ps

LVPECL Output Common

Mode VOC

50  to VDD – 2 V,

single-ended —VDD –

1.4 V —V

LVPECL Output Swing VO

50  to VDD – 2 V,

single-ended 0.55 0.8 0.90 VPPSE

LVDS Output Common Mode VOC

100  line-line,

VDD = 3.3/2.5 V 1.13 1.23 1.33 V

LVDS Output Swing VO

Single-ended 100 

differential termination 0.25 0.38 0.42 VPPSE

HCSL Output Common Mode VOC 50 to ground 0.35 0.38 0.42 V

HCSL Output Swing VOSingle-ended 0.58 0.73 0.85 VPPSE

Duty Cycle DC 48 50 52 %

Si515

Rev. 1.0 7

Table 5. Output Clock Jitter and Phase Noise (LVPECL)

VDD = 2.5 or 3.3 V ±10%, TA= –40 to +85 oC; Output Format = LVPECL

Parameter Symbol Test Condition Min Typ Max Unit

Period Jitter (RMS) JPRMS 10 k samples1——1.3 ps

Period Jitter (PK-PK) JPPKPK 10 k samples1——11 ps

Phase Jitter (RMS)

φJ

12 kHz to 20 MHz2 (brickwall) — 0.9 1.3 ps

1.875 MHz to 20 MHz2 (brickwall) — 0.25 0.5 ps

Phase Noise, 155.52 MHz

φN

100 Hz offset — –71 — dBc/Hz

1 kHz offset — –93 — dBc/Hz

10 kHz offset — –113 — dBc/Hz

100 kHz offset — –124 — dBc/Hz

1 MHz offset — –136 — dBc/Hz

Additive RMS Jitter Due to

External Power Supply

Noise3JPSRR

100 kHz sinusoidal noise — 4.0 — ps

200 kHz sinusoidal noise — 3.5 — ps

500 kHz sinusoidal noise — 3.5 — ps

1 MHz sinusoidal noise — 3.5 — ps

Spurious Performance SPR FO=156.25MHz,

Offset > 10 kHz —–75— dBc

Notes:

1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,

212.5, 250 MHz.

2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5, 250 MHz.

3. 156.25 MHz. Increase in jitter on output clock due to spurs introduced by sinewave noise added to VDD (100 mVPP).

Si515

8 Rev. 1.0

Table 6. Output Clock Jitter and Phase Noise (LVDS)

VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA= –40 to +85 oC; Output Format = LVDS

Parameter Symbol Test Condition Min Typ Max Unit

Period Jitter

(RMS)

JPRMS 10k samples1 ——2.1ps

Period Jitter

(Pk-Pk)

JPPKPK 10k samples1 ——18ps

Phase Jitter

(RMS)

φJ 1.875 MHz to 20 MHz integration

bandwidth2 (brickwall)

—0.250.55ps

12 kHz to 20 MHz integration band-

width2 (brickwall)

—0.81.1ps

Phase Noise,

156.25 MHz

φN100Hz—–72—dBc/Hz

1kHz — –93 — dBc/Hz

10 kHz — –114 — dBc/Hz

100 kHz — –123 — dBc/Hz

1 MHz — –136 — dBc/Hz

Spurious SPR LVPECL output, 156.25 MHz,

offset>10 kHz

—–75—dBc

Notes:

1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,

212.5, 250 MHz.

2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.

Si515

Rev. 1.0 9

Table 7. Output Clock Jitter and Phase Noise (HCSL)

VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = HCSL

Parameter Symbol Test Condition Min Typ Max Unit

Period Jitter

(RMS)

JPRMS 10k samples*——1.2ps

Period Jitter

(Pk-Pk)

JPPKPK 10k samples*——11ps

Phase Jitter

(RMS)

φJ 1.875 MHz to 20 MHz integration

bandwidth*(brickwall)

—0.250.30ps

12 kHz to 20 MHz integration band-

width* (brickwall)

—0.81.0ps

Phase Noise,

156.25 MHz

φN100Hz—–75—dBc/Hz

1kHz — –98 — dBc/Hz

10 kHz — –117 — dBc/Hz

100 kHz — –127 — dBc/Hz

1 MHz — –136 — dBc/Hz

Spurious SPR LVPECL output, 156.25 MHz,

offset>10 kHz

—–75—dBc

*Note: Applies to an output frequency of 100 MHz.

Si515

10 Rev. 1.0

Table 8. Output Clock Jitter and Phase Noise (CMOS, Dual CMOS)

VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = CMOS, Dual CMOS

Parameter Symbol Test Condition Min Typ Max Unit

Phase Jitter

(RMS)

φJ 1.875 MHz to 20 MHz integration

bandwidth2 (brickwall)

—0.250.35ps

12 kHz to 20 MHz integration band-

width2 (brickwall)

—0.81.1ps

Phase Noise,

156.25 MHz

φN100Hz—–71—dBc/Hz

1kHz — –93 — dBc/Hz

10 kHz — –113 — dBc/Hz

100 kHz — –123 — dBc/Hz

1 MHz — –136 — dBc/Hz

Spurious SPR LVPECL output, 156.25 MHz,

offset>10 kHz

—–75—dBc

Notes:

1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,

212.5 MHz.

2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 MHz.

Table 9. Environmental Compliance and Package Information

Parameter Conditions/Test Method

Mechanical Shock MIL-STD-883, Method 2002

Mechanical Vibration MIL-STD-883, Method 2007

Solderability MIL-STD-883, Method 2003

Gross and Fine Leak MIL-STD-883, Method 1014

Resistance to Solder Heat MIL-STD-883, Method 2036

Moisture Sensitivity Level MSL 1

Contact Pads Gold over Nickel

Si515

Rev. 1.0 11

Table 10. Thermal Characteristics

Parameter Symbol Test Condition Value Unit

Thermal Resistance Junction to Ambient JA Still air 110 °C/W

Table 11. Absolute Maximum Ratings1

Parameter Symbol Rating Unit

Maximum Operating Temperature TAMAX 85 oC

Storage Temperature TS–55 to +125 oC

Supply Voltage VDD –0.5 to +3.8 V

Input Voltage (any input pin) VI–0.5 to VDD + 0.3 V

ESD Sensitivity (HBM, per JESD22-A114) HBM 2 kV

Soldering Temperature (Pb-free profile)2TPEAK 260 oC

Soldering Temperature Time at TPEAK (Pb-free profile)2TP 20–40 sec

Notes:

1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation or

specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended

periods may affect device reliability.

2. The device is compliant with JEDEC J-STD-020.

Si515

12 Rev. 1.0

2. Pin Descriptions

Table 12. Si515 Pin Descriptions (CMOS)

Pin Name CMOS Function

1 VCControl Voltage Input.

2OE Output Enable. Internal pull-up for OE active high. Pull-

down for OE active low. See ordering information.

3GND Electrical and Case Ground.

4CLK Clock Output.

5NC No connect. Make no external connection to this pin.

6 VDD Power Supply Voltage.

Table 13. Si515 Pin Descriptions (LVPECL/LVDS/HCSL/Dual CMOS)

Pin Name LVPECL/LVDS/HCSL/Dual CMOS Function

1 VCControl Voltage Input.

2OE Output Enable. Internal pull-up for OE active high. Pull-

down for OE active low. See ordering information.

3GND Electrical and Case Ground.

4CLK+ Clock Output.

5CLK– Complementary Clock Output.

6 VDD Power Supply Voltage.

VDD

CLK–

CLK+

GND

LVPECL/LVDS/HCSL/

Dual CMOS VCX

VDD

CLK

GND

CMO S VCXO

Si515

Rev. 1.0 13

2.1. Dual CMOS Buffer

Dual CMOS output format ordering options support either complementary or in-phase output signals. This feature

enables replacement of multiple VCXOs with a single Si515 device.

Figure 1. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase Outputs

Complementary

Outputs

In-Phase

Outputs

Si515

14 Rev. 1.0

3. Ordering Information

The Si515 supports a variety of options including frequency, stability, tuning slope, output format, and VDD. Specific

device configurations are programmed into the Si515 at time of shipment. Configurations are specified using the

Part Number Configuration chart shown below. Silicon Labs provides a web browser-based part number

configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this tool. The

Si515 VCXO series is supplied in industry-standard, RoHS compliant, lead-free, 3.2 x 5.0 mm and 5 x 7 mm

packages. Tape and reel packaging is an ordering option.

Figure 2. Part Number Convention

Example ordering part number: 515BBB212M500BAGR.

The series prefix, 515, indicates the device is a single frequency VCXO.

The 1st option code B specifies the output format is LVDS and powered from a 3.3 V supply. The stability and APR

code B indicates a temperature stability of ±20 ppm with a tuning slope of ±120 ppm/V. The 3rd option code B

specifies the OE pin is active low.

The frequency code is 212M500. Per this convention, and as indicated by the part number lookup utility at

www.silabs.com/VCXOpartnumber, the output frequency is 212.5 MHz. The package code B refers to the

3.2 x 5 mm footprint with six pins. The last A refers to the product revision, G indicates the temperature range (–40

to +85 °C), and R specifies the device ships in tape and reel format.

Note: CMOS and Dual CMOS maximum frequency is 212.5 MHz.

Series Output Format Package

515

Single Frequency VCXO

LVPECL, LVDS, HCSL,

CMOS, Dual CMOS 6-pin

A = Revision: A

G = Temp Range: -40°C to 85°C

R = Tape & Reel; Blank = Trays.

515

XXXMXXX

Option Code:

Output Format

VDD Output Format

A 3.3V LVPECL

AGR

515

XXXMXXX

B3.3V LVDS

C3.3V CMOS

D 3.3V HCSL

E 2.5V LVPECL

AGR

Package Option

Dimensions

5x7mm

F2.5V LVDS

G2.5V CMOS

H 2.5V HCSL

M 3.3V Dual CMOS (In-phase)

Option Code:

Output Enable

OE Polarity

OE Active High

Option Code: Stability & APR

B 3.2 x 5 mm

N 3.3V Dual CMOS (Complementary)

P 2.5V Dual CMOS (In-phase)

Q 2.5V Dual CMOS (Complementary)

Frequency Code

Active

High

B OE Active Low

Option

Code:

Stability

APR

Frequency

Code

Frequency Description

Mxxxxxx fOUT < 1 MHz

xMxxxxx 1 MHz  fOUT < 10 MHz

10 MH 

100 MH

Temp

Stability Kv Minimum APR

3.3 V 2.5 V

A ±20ppm ±150ppm/V ±100ppm ±80ppm

xxxx



OUT <

100

xxxMxxx 100 MHz  fOUT < 250 MHz

xxxxxx Code if frequency requires >6 digit resolution

B ±20ppm ±120ppm/V ±80ppm ±50ppm

C ±20ppm ±90ppm/V ±50ppm ±30ppm

D ±20ppm ±60ppm/V ±30ppm Not Supported

Si515

Rev. 1.0 15

4. Package Outline Diagram: 5 x 7 mm, 6-pin

Figure 3 illustrates the package details for the Si515. Table 14 lists the values for the dimensions shown in the

illustration.

Figure 3. Si515 Outline Diagram

Table 14. Package Diagram Dimensions (mm)

Dimension Min Nom Max

A 1.50 1.65 1.80

b 1.30 1.40 1.50

c 0.50 0.60 0.70

D 5.00 BSC.

D1 4.30 4.40 4.50

e 2.54 BSC.

E 7.00 BSC.

E1 6.10 6.20 6.30

H 0.55 0.65 0.75

L 1.17 1.27 1.37

L1 0.05 0.10 0.15

p 1.80 — 2.60

R 0.7 REF.

aaa 0.15

bbb 0.15

ccc 0.10

ddd 0.10

eee 0.05

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.



Si515

16 Rev. 1.0

5. PCB Land Pattern: 5 x 7 mm, 6-pin

Figure 4 illustrates the 5 x 7 mm PCB land pattern for the Si515. Table 15 lists the values for the dimensions shown

in the illustration.

Figure 4. Si515 PCB Land Pattern

Table 15. PCB Land Pattern Dimensions (mm)

Dimension (mm)

C1 4.20

E5.08

X1 1.55

Y1 1.95

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.

3. This Land Pattern Design is based on the IPC-7351 guidelines.

4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition

(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.

Solder Mask Design

5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder

mask and the metal pad is to be 60 µm minimum, all the way around the pad.

Stencil Design

6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used

to assure good solder paste release.

7. The stencil thickness should be 0.125 mm (5 mils).

8. The ratio of stencil aperture to land pad size should be 1:1.

Card Assembly

9. A No-Clean, Type-3 solder paste is recommended.

10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for

Small Body Components.

Si515

Rev. 1.0 17

6. Package Outline Diagram: 3.2 x 5.0 mm, 6-pin

Figure 5 illustrates the package details for the 3.2 x 5 mm Si510/511. Table 16 lists the values for the dimensions

shown in the illustration.

Figure 5. Si510/511 Outline Diagram

Table 16. Package Diagram Dimensions (mm)

Dimension Min Nom Max

A1.061.171.28

b0.540.640.74

c0.350.450.55

D 3.20 BSC

D1 2.55 2.60 2.65

e 1.27 BSC

E 5.00 BSC

E1 4.35 4.40 4.45

H0.450.550.65

L0.901.001.10

L1 0.05 0.10 0.15

p1.171.271.37

R0.32 REF

aaa 0.15

bbb 0.15

ccc 0.10

ddd 0.10

eee 0.05

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.



Si515

18 Rev. 1.0

7. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin

Figure 6 illustrates the recommended 3.2 x 5 mm PCB land pattern for the Si515. Table 17 lists the values for the

dimensions shown in the illustration.

Figure 6. Si515 PCB Land Pattern

Table 17. PCB Land Pattern Dimensions (mm)

Dimension (mm)

C1 2.60

E1.27

X1 0.80

Y1 1.70

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.

3. This Land Pattern Design is based on the IPC-7351 guidelines.

4. All dimensions shown are at Maximum Material Condition (MMC). Least Material

Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.

Solder Mask Design

5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the

solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.

Sten cil Desig n

6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be

used to assure good solder paste release.

7. The stencil thickness should be 0.125 mm (5 mils).

8. The ratio of stencil aperture to land pad size should be 1:1.

Card Assembly

9. A No-Clean, Type-3 solder paste is recommended.

10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification

for Small Body Components.



Si515

Rev. 1.0 19

8. Top Marking

Use the part number configuration utility located at: www.silabs.com/VCXOPartNumber to cross-reference the

mark code to a specific device configuration.

8.1. Si515 Top Marking

8.2. Top Marking Explanation

Mark Method: Laser

Line 1 Marking: 5 = Si515

CCCCC = Mark Code

5CCCCC

Line 2 Marking: TTTTTT = Assembly Manufacturing Code TTTTTT

Line 3 Marking: Pin 1 indicator. Circle with 0.5 mm diameter;

left-justified

YY = Year.

WW = Work week.

Characters correspond to the year and

work week of package assembly.

YYWW

5CCCCC

TTTTTTYYWW

Si515

20 Rev. 1.0

DOCUMENT CHANGE LIST

Revision 0.9 to Revision 1.0

Updated Table 1 on page 4.

Updates to supply current typical and maximum values

for CMOS, LVDS, LVPECL and HCSL.

CMOS frequency test condition corrected to 100 MHz.

Updates to OE VIH minimum and VIL maximum values.

Updated Table 3 on page 5.

Dual CMOS nominal frequency maximum added.

Disable time maximum values updated.

Enable time parameter added.

Updated Table 4 on page 6.

CMOS output rise / fall time typical and maximum

values updated.

LVPECL/HCSL output rise / fall time maximum value

updated.

LVPECL output swing maximum value updated.

LVDS output common mode typical and maximum

values updated.

HCSL output swing maximum value updated.

Duty cycle minimum and maximum values tightened to

48/52%.

Updated Table 5 on page 7.

Phase jitter test condition, typical and maximum value

updated.

Phase noise typical values updated.

Additive RMS jitter due to external power supply noise

typical values updated.

Added Tables 6, 7, 8 for LVDS, HCSL, CMOS and

Dual CMOS operations.

Added note to Figure 2 clarifying CMOS and Dual

CMOS maximum frequency.

Updated Figure 5 outline diagram to correct pinout.

Updated “8. Top Marking” section and moved to

page 19.

Si515

Rev. 1.0 21

NOTES:

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515BCA27M0000BAG 515CCA27M0000BAG 515CCA25M0000AAG 515CAA144M800AAG 515CAA000256AAG

515CDA000256AAG 515CBA80M0000AAG 515CBA80M0000BAG 515ABA98M0000AAG 515CBA144M800AAG

515CBA169M475AAG 515CAA25M0000AAG 515CDB117M675AAG 515CDB125M675AAG 515CDB144M975AAG

515CDB58M8375AAG 515CDB62M8375AAG 515CAB5M00000BAG 515CCB13M0000BAG 515BCA148M500AAG

515CBB000327AAG 515CBB144M795AAG 515NBA20M0000BAG 515BAA125M000BAG 515BCA144M795AAG

515CAB4M09600BAG 515CAA125M000AAG 515CAA40M0000AAG 515BCA176M500AAG 515BCA105M000AAG

515NCA49M1520BAG 515ACA10M7000AAG 515AAA7M10000AAG 515CCAM524288AAG 515CAA24M5760AAG

515CDA43M1000AAG 515CDA22M5792AAG 515CDA24M5760AAG 515CAA70M6560AAG 515ACB4M00000AAG

515ACB10M0000AAG 515BCA135M000BAG 515CBA3M64000AAG 515BCA236M500AAG 515BCA169M406AAG

515ACAM100000AAG 515CBBM100000AAG 515CDBM100000AAG 515CCB1M95840AAG 515CCA56M3200AAG

515CAB98M0000AAG 515BAA000123BAG 515BAA000108BAG