© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1001_C0G_200C_SMD • 7/29/2016 1
One world. One KEMET
Overview
KEMET’s High Temperature surface mount C0G Multilayer
Ceramic Capacitors (MLCCs) are constructed of a robust
and proprietary C0G/NP0 base metal electrode (BME)
dielectric system that offers industry-leading performance
at extreme temperatures up to 200°C. These devices are
specically designed to withstand the demands of harsh
industrial environments such as down-hole oil exploration
and automotive/avionics engine compartment circuitry.
KEMET’s High Temperature C0G capacitors are temperature
compensating and are well suited for resonant circuit
applications or those where Q and stability of capacitance
characteristics are required. They exhibit no change in
capacitance with respect to time and voltage and boast a
negligible change in capacitance with reference to ambient
temperature. Capacitance change is limited to ±30ppm/ºC
from −55°C to +200°C. In addition, these capacitors exhibit
high insulation resistance with low dissipation factor at
elevated temperatures up to 200°C. They also exhibit low ESR
at high frequencies and offer greater volumetric efciency
over competitive high temperature precious metal electrode
(PME) and BME ceramic capacitor devices.
These devices are Lead (Pb)-Free, RoHS and REACH
compliant without the need of any exemptions.
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
High Temperature 200°C, C0G Dielectric, 10 – 200 VDC
(Industrial Grade)
Ordering Information
C1210 H124 J 5 G A C TU
Ceramic Case Size
(L" x W")
Specication/
Series
Capacitance
Code (pF)
Capacitance
Tolerance1Voltage Dielectric Failure Rate/
Design Termination Finish2Packaging/
Grade (C-Spec)
0402
0603
0805
1206
1210
1812
2220
H = High
Temperature
(200°C)
Two signicant digits +
number of zeros.
Use 9 for 1.0 – 9.9 pF
Use 8 for 0.5 – 0.99 pF
e.g., 2.2 pF = 229
e.g., 0.5 pF = 508
B = ±0.10 pF
C = ±0.25 pF
D = ±0.5 pF
F = ±1%
G = ±2%
J = ±5%
K = ±10%
M = ±20%
8 = 10 V
4 = 16 V
3 = 25 V
5 = 50 V
1 = 100 V
2 = 200 V
G = C0G A = N/A C = 100% Matte Sn
L = SnPb (5% Pb minimum)
E = Gold (Au) 1.97 – 11.8 µin
F = Gold (Au) 30 – 50 µin
G = Gold (Au) 100 µin
minimum
See
“Packaging
C-Spec
Ordering
Options
Table”
below
1 Additional capacitance tolerance offerings may be available. Contact KEMET for details.
2 Additional termination nish options may be available. Contact KEMET for details.
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© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1001_C0G_200C_SMD • 7/29/2016 2
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)
Benets
• −55°C to +200°C operating temperature range
• Lead (Pb)-free, RoHS and REACH compliant
• EIA 0402, 0603, 0805, 1206, 1210, 1812, and 2220
case sizes
• DC voltage ratings of 10 V, 16 V, 25 V, 50 V, 100 V,
and 200 V
• Capacitance offerings ranging from 0.5 pF up to 470 nF
• Available capacitance tolerances of ±0.10 pF, ±0.25 pF,
±0.5 pF, ±1%, ±2%, ±5%, ±10% or ±20%
• No piezoelectric noise
• Extremely low ESR and ESL
• High thermal stability
• High ripple current capability
• Preferred capacitance solution at line frequencies and into
the MHz range
• No capacitance change with respect to applied rated DC
voltage
• Negligible capacitance change with respect to temperature
from −55°C to +200°C
• No capacitance decay with time
• Non-polar device, minimizing installation concerns
• 100% pure matte tin-plated termination nish allowing for
excellent solderability
• Gold (Au), Tin/Lead (Sn/Pb) and 100% pure matte Tin (Sn)
termination nishes available
Applications
Typical applications include critical timing, tuning, circuits requiring low loss, circuits with pulse, high current, decoupling,
bypass, ltering, transient voltage suppression, blocking and energy storage for use in extreme environments such as down-
hole exploration, aerospace engine compartments and geophysical probes.
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1001_C0G_200C_SMD • 7/29/2016 3
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)
Packaging C-Spec Ordering Options Table
Termination Finish Options Packaging Type/Options Packaging
Ordering Code (C-Spec)
Standard Packaging – Unmarked3
C = 100% Matte Sn
L = SnPb (5% Pb min.)
F = Gold (Au) 30 – 50 µin
G = Gold (Au) 100 µin minimum
Bulk Bag
Blank
1
Wafe Tray
2
7292
7" Tape & Reel
TU
13" Reel
7411 (EIA 0603 and smaller case sizes)
7210 (EIA 0805 and larger case sizes)
7” Tape & Reel/2 mm pitch
4
7081
7" Tape & Reel – 50 pieces
T050
7" Tape & Reel – 100 pieces
T100
7" Tape & Reel – 250 pieces
T250
7" Tape & Reel – 500 pieces
T500
7" Tape & Reel – 1,000 pieces
T1K0
Moisture Sensitive Packaging5 – Unmarked3
E = Gold (Au) 1.97 – 11.8 µin
F = Gold (Au) 30 – 50 µin
G = Gold (Au) 100 µin minimum
Wafe Tray
2
7282
7" Tape & Reel
7130
7" Tape & Reel – 50 pieces
Contact KEMET6
7" Tape & Reel – 100 pieces
7" Tape & Reel – 250 pieces
7" Tape & Reel – 500 pieces
7" Tape & Reel – 1,000 pieces
1 Default packaging is “Bulk Bag”. An ordering code C-Spec is not required for “Bulk Bag” packaging.
1 “Bulk Bag” packaging option is not available for Gold (Au) termination nish options and case sizes larger than 2225 (5664 Metric).
2 “Wafe Tray” packaging option is not available for case sizes larger than 2225 (5664 Metric).
3 The terms “Marked” and “Unmarked” pertain to laser marking option of components. All packaging options labeled as “Unmarked” will contain
capacitors that have not been laser marked. The option to laser mark is not available on these devices.
3 Reeling quantities are dependent upon chip size and thickness dimension. When ordering using the “T1K0” packaging option, 1812 through 2225 case
size devices with chip thickness of ≥ 1.9 mm (nominal) may be shipped on multiple 7” reels or a single 13” reel. Additional reeling or packaging options
may be available. Contact KEMET for details.
4 The 2 mm pitch option allows for double the packaging quantity of capacitors on a given reel size. This option is limited to EIA 0603 (1608 metric) case
size devices. For more information regarding 2 mm pitch option see “Tape & Reel Packaging Information”.
5 Moisture sensitive packaging is required for Gold (Au) termination option “E” (1.97 – 11.8 µin)
6 Additional reeling or packaging options may be available. Contact KEMET for details.
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1001_C0G_200C_SMD • 7/29/2016 4
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)
Dimensions – Millimeters (Inches)
L
B
W
S
T
EIA Size
Code
Metric Size
Code
L
Length
W
Width
T
Thickness
B
Bandwidth
S
Separation
Minimum
Mounting
Technique
0402 1005
1.00 (0.040)
±0.05 (0.002)
0.50 (0.020)
±0.05 (0.002)
See Table 2 for
Thickness
0.30 (0.012)
±0.10 (0.004)
0.30 (0.012)
Solder Reow
Only
0603 1608
1.60 (0.063)
±0.15 (0.006)
0.80 (0.032)
±0.15 (0.006)
0.35 (0.014)
±0.15 (0.006) 0.70 (0.028)
Solder Wave or
Solder Reow
0805 2012
2.00 (0.079)
±0.20 (0.008)
1.25 (0.049)
±0.20 (0.008)
0.50 (0.02)
±0.25 (0.010)
0.75 (0.030)
1206 3216
3.20 (0.126)
±0.20 (0.008)
1.60 (0.063)
±0.20 (0.008)
0.50 (0.02)
±0.25 (0.010)
N/A
1210 3225
3.20 (0.126)
±0.20 (0.008)
2.50 (0.098)
±0.20 (0.008)
0.50 (0.02)
±0.25 (0.010)
Solder Reow
Only
1812 4532
4.50 (0.177)
±0.30 (0.012)
3.20 (0.126)
±0.30 (0.012)
0.60 (0.024)
±0.35 (0.014)
2220 5650
5.70 (0.224)
±0.40 (0.016)
5.00 (0.197)
±0.40 (0.016)
0.60 (0.024)
±0.35 (0.014)
Qualication/Certication
High temperature (200ºC) Industrial grade products meet or exceed the requirements outlined in Table 4, Performance &
Reliability. Qualication packages are available for review and download on our website at www.kemet.com/hightemp
Environmental Compliance
Lead (Pb)-free, RoHS, and REACH compliant without exemptions (excluding SnPb termination nish option).
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1001_C0G_200C_SMD • 7/29/2016 5
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)
Electrical Parameters/Characteristics
Item Parameters/Characteristics
Operating Temperature Range −55°C to +200°C
Capacitance Change with Reference to
+25°C and 0 VDC Applied (TCC) ±30 ppm/ºC (up to 200ºC)
Aging Rate (Maximum % Capacitance Loss/Decade Hour) 0%
1Dielectric Withstanding Voltage (DWV)
250% of rated voltage
(5±1 seconds and charge/discharge not exceeding 50 mA)
2Dissipation Factor (DF) Maximum Limit at 25ºC 0.1%
3Insulation Resistance (IR) Minimum Limit at 25°C 1,000 megohm microfarads or 100 GΩ
(Rated voltage applied for 120±5 seconds at 25°C)
1 DWV is the voltage a capacitor can withstand (survive) for a short period of time. It exceeds the nominal and continuous working voltage of the
capacitor.
2 Capacitance and dissipation factor (DF) measured under the following conditions:
1 MHz ±100 kHz and 1.0 ±0.2 Vrms if capacitance ≤ 1,000 pF
1 kHz ±50 Hz and 1.0 ±0.2 Vrms if capacitance > 1,000 pF
3 To obtain IR limit, divide MΩ-µF value by the capacitance and compare to GΩ limit. Select the lower of the two limits.
Note: When measuring capacitance it is important to ensure the set voltage level is held constant. The HP4284 & Agilent E4980 have a feature known as
Automatic Level Control (ALC). The ALC feature should be switched to “ON.”
Post Environmental Limits
High Temperature Life, Biased Humidity, Moisture Resistance
Dielectric Rated DC
Voltage
Capacitance
Value
Dissipation Factor
(Maximum %)
Capacitance
Shift
Insulation
Resistance
C0G All All 0.5
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1001_C0G_200C_SMD • 7/29/2016 6
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)
Electrical Characteristics
IR vs. Temperature with 25 V DC Bias (Rated Voltage)
Capacitance vs. Temperature with 25 V DC Bias
(Rated Voltage)
BME vs. PME/IR vs. Temperature with 25 V DC Bias
(Rated Voltage)
DF vs. Temperature without DC Bias.
C1210H104J1GAC - Life Test IR Distribution (Lognormal)
Delta Cap vs. Temperature (Typical)
0
50
100
150
200
−60
−40
−20
0
20
40
60
80
100
120
140
160
180
200
Capacitance (nF)
Temperature (°C)
200ºC C0G 100nF no DC
200ºC C0G 100nF 25V DC
−1.00
−0.50
0.00
0.50
1.00
−60
−40
−20
0
20
40
60
80
100
120
140
160
180
200
DF (%)
Temperature (°C)
200ºC C0G MLCC 100nF
−20
−15
−10
−5
0
5
10
15
20
−60
−40
−20
0
20
40
60
80
100
120
140
160
180
200
Delta Cap (%)
Temperature (ºC)
0 Vr
100% Vr
100.010.01.00.1
99
95
90
80
70
60
50
40
30
20
10
5
1
25°C IR (GOhms)
Percent %
0 hrs
2000 hrs
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
−60
−40
−20
0
20
40
60
80
100
120
140
160
180
200
IR (MOhms)
Temperature (°C)
PME C0G MLCC 1206/10nF
BME C0G MLCC 1206/10nF
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
−60
−40
−20
0
20
40
60
80
100
120
140
160
180
200
IR (MOhms)
Temperature (°C)
200ºC C0G MLCC 100nF
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1001_C0G_200C_SMD • 7/29/2016 7
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)
Table 1A – Capacitance Range/Selection Waterfall (0402 – 1206 Case Sizes)
Capacitance Cap
Code
Case Size / Series C0402H C0603H C0805H C1206H
Voltage Code 8 4 3 5 1 8 4 3 5 1 2 8 4 3 5 1 2 8 4 3 5 1 2
Rated Voltage (VDC)
10
16
25
50
100
10
16
25
50
100
200
10
16
25
50
100
200
10
16
25
50
100
200
Capacitance Tolerance
Product Availability and Chip Thickness Codes
See Table 2 for Chip Thickness Dimensions
0.5 & 0.75 pF 508 & 758 B C D BB BB BB BB CF CF CF CF CF CF DN DN DN DN DN DN
1.0 - 9.0 pF* 109 - 919* B C D BB BB BB BB CF CF CF CF CF CF DN DN DN DN DN DN EB EB EB EB EB EB
10 - 91 pF* 100 - 910* F G J K M BB BB BB BB CF CF CF CF CF CF DN DN DN DN DN DN EB EB EB EB EB EB
100 - 180 pF* 101 - 181* F G J K M BB BB BB BB BB CF CF CF CF CF CF DN DN DN DN DN DN EB EB EB EB EB EB
200 - 430 pF* 201 - 431* F G J K M BB BB BB BB BB CF CF CF CF CF DN DN DN DN DN DN EB EB EB EB EB EB
470 pF 471 F G J K M BB BB BB BB BB CF CF CF CF CF DN DN DN DN DN DP EB EB EB EB EB EB
510 pF 511 F G J K M BB BB BB BB BB CF CF CF CF CF DN DN DN DN DN DN EB EB EB EB EB EB
560 pF 561 F G J K M BB BB BB BB BB CF CF CF CF CF DN DN DN DN DN DN EB EB EB EB EB EB
620 pF 621 F G J K M BB BB BB BB BB CF CF CF CF CF DN DN DN DN DN DN EB EB EB EB EB EB
680 pF 681 F G J K M BB BB BB BB BB CF CF CF CF CF DN DN DN DN DN DN EB EB EB EB EB EB
750 pF 751 F G J K M BB BB BB BB BB CF CF CF CF CF DN DN DN DN DN DN EB EB EB EB EB EB
820 pF 821 F G J K M BB BB BB BB BB CF CF CF CF CF DN DN DN DN DN DN EB EB EB EB EB EB
910 pF 911 F G J K M BB BB BB BB BB CF CF CF CF CF DN DN DN DN DP DP EB EB EB EB EB EB
1,000 pF 102 F G J K M BB BB BB BB BB CF CF CF CF CF DN DN DN DN DP DP EB EB EB EB EB EE
1,100 pF 112 FG J K M BB BB BB BB CF CF CF CF CF DN DN DN DN DN EB EB EB EB EB EB
1,200 pF 122 F G J K M BB BB BB BB CF CF CF CF CF DN DN DN DN DN EB EB EB EB EB EB
1,300 pF 132 F G J K M BB BB BB BB CF CF CF CF CF DP DP DP DP DP EB EB EB EB EC EC
1,500 pF 152 F G J K M BB BB BB BB CF CF CF CF CF DP DP DP DP DP EB EB EB EB ED EC
1,600 pF 162 F G J K M CF CF CF CF CF DP DP DP DP DP EB EB EB EB ED ED
1,800 pF 182 F G J K M CF CF CF CF CF DP DP DP DP DP EB EB EB EB ED ED
2,000 pF 202 F G J K M CF CF CF CF CF DN DN DN DN DN EB EB EB EB ED ED
2,200 pF 222 F G J K M CF CF CF CF CF DN DN DN DN DN EB EB EB EB EE EE
2,400 pF 242 F G J K M CF CF CF CF CF DN DN DN DN DN EB EB EB EB EC EC
2,700 pF 272 F G J K M CF CF CF CF CF DN DN DN DN DN EB EB EB EB EC EC
3,000 pF 302 F G J K M CF CF CF CF CF DP DP DP DP DN EC EC EC EC EC
3,300 pF 332 F G J K M CF CF CF CF CF DP DP DP DP DN EC EC EC EC EE
3,600 pF 362 F G J K M CF CF CF CF CF DP DP DP DP DN EC EC EC EC EE
3,900 pF 392 F G J K M CF CF CF CF CF DE DE DE DE DN EC EC EC EC EF
4,300 pF 432 F G J K M CF CF CF CF CF DE DE DE DE DN EC EC EC EC EC
4,700 pF 472 F G J K M CF CF CF CF CF DE DE DE DE DN EC EC EC EC EC
5,100 pF 512 F G J K M CF CF CF CF DE DE DE DE DN ED ED ED ED ED
5,600 pF 562 F G J K M CF CF CF CF DN DN DN DN DN ED ED ED ED ED
6,200 pF 622 F G J K M CF CF CF CF DN DN DN DN DN EB EB EB EB EB
6,800 pF 682 F G J K M CF CF CF CF DN DN DN DN DN EB EB EB EB EB
7,500 pF 752 F G J K M CF CF CF DN DN DN DN DN EB EB EB EB EB
8,200 pF 822 F G J K M CF CF CF DN DN DN DN DN EC EC EC EC EB
9,100 pF 912 F G J K M CF CF CF DN DN DN DN DN EC EC EC EC EB
10,000 pF 103 F G J K M CF CF CF DN DN DN DN DP ED ED ED ED EB
12,000 pF 123 F G J K M DN DN DN DN DE EB EB EB EB EB
15,000 pF 153 F G J K M DN DN DN DP DG EB EB EB EB EB
18,000 pF 183 F G J K M DN DN DN DP EB EB EB EB EB
22,000 pF 223 F G J K M DP DP DP DF EB EB EB EB EC
27,000 pF 273 F G J K M DF DF DF EB EB EB EB EE
33,000 pF 333 F G J K M DG DG DG EB EB EB EB EE
39,000 pF 393 F G J K M DG DG DG EC EC EC EE EH
47,000 pF 473 F G J K M DG DG DG EC EC EC EE EH
56,000 pF 563 F G J K M ED ED ED EF
68,000 pF 683 F G J K M EF EF EF EH
82,000 pF 823 F G J K M EH EH EH EH
0.10 µF 104 F G J K M EH EH EH
Capacitance Cap Code
Rated Voltage (VDC)
10
16
25
50
100
10
16
25
50
100
200
10
16
25
50
100
200
10
16
25
50
100
200
Voltage Code 8 4 3 5 1 8 4 3 5 1 2 8 4 3 5 1 2 8 4 3 5 1 2
Case Size / Series C0402H C0603H C0805H C1206H
*Capacitance range Includes E24 decade values only. (i.e., 10, 11, 12, 13, 15, 16, 18, 20, 22, 24, 27, 30, 33, 36, 39, 43, 47, 51, 56, 62, 68, 75, 82, and 91)
KEMET reserves the right to substitute product with an improved temperature characteristic, tighter capacitance tolerance and/or higher voltage
capability within the same form factor (conguration and dimensions).
These products are protected under US Patents 7,172,985 and 7,670,981, other patents pending, and any foreign counterparts.
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1001_C0G_200C_SMD • 7/29/2016 8
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)
Table 1B – Capacitance Range/Selection Waterfall (1210 – 2220 Case Sizes)
*Capacitance range Includes E24 decade values only. (i.e., 10, 11, 12, 13, 15, 16, 18, 20, 22, 24, 27, 30, 33, 36, 39, 43, 47, 51, 56, 62, 68, 75, 82, and 91)
KEMET reserves the right to substitute product with an improved temperature characteristic, tighter capacitance tolerance and/or higher voltage
capability within the same form factor (conguration and dimensions).
These products are protected under US Patents 7,172,985 and 7,670,981, other patents pending, and any foreign counterparts.
Capacitance Cap
Code
Case Size / Series C1210H C1812H C2220H
Voltage Code 8 4 3 5 1 2 8 4 3 5 1 2 8 4 3 5 1 2
Rated Voltage (VDC)
10
16
25
50
100
200
10
16
25
50
100
200
10
16
25
50
100
200
Capacitance Tolerance
Product Availability and Chip Thickness Codes
See Table 2 for Chip Thickness Dimensions
0.5 & 0.75 pF 508 & 758 B C D
1.0 - 9.1 pF* 109 - 919* B C D FB FB FB FB FB FB
10 - 91 pF* 100 - 910* F G J K M FB FB FB FB FB FB
100 - 910 pF* 101 - 911* F G J K M FB FB FB FB FB FB
1,000 pF 102 F G J K M FB FB FB FB FB FB
1,100 pF 112 F G J K M FB FB FB FB FB FB
1,200 pF 122 F G J K M FB FB FB FB FB FB
1,300 pF 132 F G J K M FB FB FB FB FB FC
1,500 pF 152 F G J K M FB FB FB FB FB FE
1,600 pF 162 F G J K M FB FB FB FB FB FE
1,800 pF 182 F G J K M FB FB FB FB FB FE
2,000 pF 202 F G J K M FB FB FB FB FC FE
2,200 pF 222 F G J K M FB FB FB FB FC FG
2,400 pF 242 F G J K M FB FB FB FB FC FC
2,700 pF 272 F G J K M FB FB FB FB FC FC
3,000 pF 302 F G J K M FB FB FB FB FC FF
3,300 pF 332 F G J K M FB FB FB FB FF FF
3,600 pF 362 F G J K M FB FB FB FB FF FF
3,900 pF 392 F G J K M FB FB FB FB FF FF
4,300 pF 432 F G J K M FB FB FB FB FF FF
4,700 pF 472 F G J K M FF FF FF FF FG FG
5,100 pF 512 F G J K M FB FB FB FB FG FG
5,600 pF 562 F G J K M FB FB FB FB FG FG
6,200 pF 622 F G J K M FB FB FB FB FG
6,800 pF 682 F G J K M FB FB FB FB FG
7,500 pF 752 F G J K M FC FC FC FC FC
8,200 pF 822 F G J K M FC FC FC FC FC
9,100 pF 912 F G J K M FE FE FE FE FE
10,000 pF 103 F G J K M FF FF FF FF FF
12,000 pF 123 F G J K M FG FG FG FG FB
15,000 pF 153 F G J K M FG FG FG FG FB GB GB GB GB GB
18,000 pF 183 F G J K M FB FB FB FB FB GB GB GB GB GB
22,000 pF 223 F G J K M FB FB FB FB FB GB GB GB GB GB
27,000 pF 273 F G J K M FB FB FB FB FB GB GB GB GB GB
33,000 pF 333 F G J K M FB FB FB FB FB GB GB GB GB GB
39,000 pF 393 F G J K M FB FB FB FB FE GB GB GB GB GB
47,000 pF 473 F G J K M FB FB FB FB FE GB GB GB GB GB
56,000 pF 563 F G J K M FB FB FB FB FF GB GB GB GB GB
68,000 pF 683 F G J K M FB FB FB FC FG GB GB GB GB GB
82,000 pF 823 F G J K M FC FC FC FF FH GB GB GB GB GB
0.10 µF 104 F G J K M FE FE FE FG FM GB GB GB GB GD
0.12 µF 124 F G J K M FG FG FG FH GB GB GB GB GH
0.15 µF 154 F G J K M FH FH FH FM GD GD GD GD GN
0.18 µF 184 F G J K M GH GH GH GH
0.22 µF 224 F G J K M GK GK GK GK
0.47 µF 474 F G J K M JJ JJ JJ JJ
Capacitance Cap Code
Rated Voltage (VDC)
10
16
25
50
100
200
10
16
25
50
100
200
10
16
25
50
100
200
Voltage Code 8 4 3 5 1 2 8 4 3 5 1 2 8 4 3 5 1 2
Case Size / Series C1210H C1812H C2220H
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1001_C0G_200C_SMD • 7/29/2016 9
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)
Table 2A – Chip Thickness/Tape & Reel Packaging Quantities
Thickness
Code
Case
Size1
Thickness ±
Range (mm)
Paper Quantity1Plastic Quantity
7" Reel 13" Reel 7" Reel 13" Reel
BB
0402
0.50±0.05
10,000
50,000
0
0
CF
0603
0.80±0.07
4,000
15,000
0
0
DN
0805
0.78±0.10
4,000
15,000
0
0
DP
0805
0.90±0.10
4,000
15,000
0
0
DE
0805
1.00±0.10
0
0
2,500
10,000
DF
0805
1.10±0.10
0
0
2,500
10,000
DG
0805
1.25±0.15
0
0
2,500
10,000
EB
1206
0.78±0.10
4,000
10,000
4,000
10,000
EC
1206
0.90±0.10
0
0
4,000
10,000
ED
1206
1.00±0.10
0
0
2,500
10,000
EE
1206
1.10±0.10
0
0
2,500
10,000
EF
1206
1.20±0.15
0
0
2,500
10,000
EH
1206
1.60±0.20
0
0
2,000
8,000
FB
1210
0.78±0.10
0
0
4,000
10,000
FC
1210
0.90±0.10
0
0
4,000
10,000
FE
1210
1.00±0.10
0
0
2,500
10,000
FF
1210
1.10±0.10
0
0
2,500
10,000
FG
1210
1.25±0.15
0
0
2,500
10,000
FH
1210
1.55±0.15
0
0
2,000
8,000
FM
1210
1.70±0.20
0
0
2,000
8,000
GB
1812
1.00±0.10
0
0
1,000
4,000
GD
1812
1.25±0.15
0
0
1,000
4,000
GH
1812
1.40±0.15
0
0
1,000
4,000
GK
1812
1.60±0.20
0
0
1,000
4,000
GN
1812
1.70±0.20
0
0
1,000
4,000
JJ
2220
2.20±0.15
0
0
500
2,000
Thickness
Code
Case
Size1
Thickness ±
Range (mm)
7" Reel 13" Reel 7" Reel 13" Reel
Paper Quantity1Plastic Quantity
Package quantity based on nished chip thickness specications.
1 If ordering using the 2mm Tape and Reel pitch option, the packaging quantity outlined in the table above will be doubled. This option is limited to EIA
0603 (1608 metric) case size devices. For more information regarding 2mm pitch option see “Tape & Reel Packaging Information”.
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1001_C0G_200C_SMD • 7/29/2016 10
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)
Table 2B – Bulk Packaging Quantities
Packaging Type
Loose Packaging Secure Packaging
Bulk Bag (default)
2” x 2” Wafe Pack/
Tray
3
Packaging C-Spec1N/A27282/7292
Case Size
Chip Thickness
(mm)
Packaging Quantities (pieces/unit packaging)
EIA (in) Metric (mm) Minimum Maximum Minimum Maximum
0402
1005
All
1
50,000
1
368
0603
1608
368
0805
2012
100
1206
3216
≤ 1.25 (nominal)
126
1206
3216
> 1.25 (nominal)
50
1210
3225
All
80
1808
4520
20,000
50
1812
4532
42
1825
4564
20
2220
5650
20
2225
5664
20
1 The "Packaging C-Spec" is a 4-digit code which identies the packaging type. When ordering, the proper code must be included in the 15th through
18th character positions of the ordering code. See "Ordering Information" section of this document for further details. Product ordered without a
packaging C-Spec will default to our standard "Bulk Bag" packaging.
2 A packaging C-Spec (see note 1 above) is not required For "Bulk Bag" packaging (excluding Anti-Static Bulk Bag). The 15th through 18th character
positions of the ordering code should be left blank. All product ordered without a packaging C-Spec will default to our standard "Bulk Bag" packaging.
3 Also commonly referred to as “Chip Carrier” or “Molded Tray”. All tray packaging options offer static protection.
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1001_C0G_200C_SMD • 7/29/2016 11
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)
Table 3 – Chip Capacitor Land Pattern Design Recommendations per IPC–7351
EIA
Size
Code
Metric
Size
Code
Density Level A:
Maximum (Most)
Land Protrusion (mm)
Density Level B:
Median (Nominal)
Land Protrusion (mm)
Density Level C:
Minimum (Least)
Land Protrusion (mm)
C Y X V1 V2 C Y X V1 V2 C Y X V1 V2
0402 1005 0.50 0.72 0.72 2.20 1.20 0.45 0.62 0.62 1.90 1.00 0.40 0.52 0.52 1.60 0.80
0603 1608 0.90 1.15 1.10 4.00 2.10 0.80 0.95 1.00 3.10 1.50 0.60 0.75 0.90 2.40 1.20
0805 2012 1.00 1.35 1.55 4.40 2.60 0.90 1.15 1.45 3.50 2.00 0.75 0.95 1.35 2.80 1.70
1206 3216 1.60 1.35 1.90 5.60 2.90 1.50 1.15 1.80 4.70 2.30 1.40 0.95 1.70 4.00 2.00
1210 3225 1.60 1.35 2.80 5.65 3.80 1.50 1.15 2.70 4.70 3.20 1.40 0.95 2.60 4.00 2.90
121013225 1.50 1.60 2.90 5.60 3.90 1.40 1.40 2.80 4.70 3.30 1.30 1.20 2.70 4.00 3.00
1812 4532 2.15 1.60 3.60 6.90 4.60 2.05 1.40 3.50 6.00 4.00 1.95 1.20 3.40 5.30 3.70
2220 5650 2.75 1.70 5.50 8.20 6.50 2.65 1.50 5.40 7.30 5.90 2.55 1.30 5.30 6.60 5.60
1 Only for capacitance values ≥ 22 µF
Density Level A: For low-density product applications. Recommended for wave solder applications and provides a wider process window for reow
solder processes. KEMET only recommends wave soldering of EIA 0603, 0805 and 1206 case sizes.
Density Level B: For products with a moderate level of component density. Provides a robust solder attachment condition for reow solder processes.
Density Level C: For high component density product applications. Before adapting the minimum land pattern variations the user should perform
qualication testing based on the conditions outlined in IPC Standard 7351 (IPC–7351).
Image below based on Density Level B for an EIA 1210 case size.
Y
C C
X X
V1
V2
Grid Placement Courtyard
Y
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1001_C0G_200C_SMD • 7/29/2016 12
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)
Soldering Process
Recommended Soldering Technique:
• Solder wave or solder reow for EIA case sizes 0603, 0805 and 1206
• All other EIA case sizes are limited to solder reow only
Recommended Reow Soldering Prole:
KEMET’s families of surface mount multilayer ceramic capacitors (SMD MLCCs) are compatible with wave (single or dual),
convection, IR or vapor phase reow techniques. Preheating of these components is recommended to avoid extreme thermal
stress. KEMET’s recommended prole conditions for convection and IR reow reect the prole conditions of the IPC/
J-STD-020 standard for moisture sensitivity testing. These devices can safely withstand a maximum of three reow passes
at these conditions.
Prole Feature Termination Finish
SnPb 100% Matte Sn
Preheat/Soak
Temperature Minimum (TSmin)
100°C
150°C
Temperature Maximum (T
Smax
)150°C 200°C
Time (tS) from TSmin to TSmax
60 – 120 seconds
60 – 120 seconds
Ramp-Up Rate (TL to TP)
3°C/second
maximum
3°C/second
maximum
Liquidous Temperature (T
L
)183°C 217°C
Time Above Liquidous (t
L
) 60 – 150 seconds 60 – 150 seconds
Peak Temperature (T
P
)235°C 260°C
Time Within 5°C of Maximum
Peak Temperature (t
P
)
20 seconds
maximum
30 seconds
maximum
Ramp-Down Rate (TP to TL)
6°C/second
maximum
6°C/second
maximum
Time 25°C to Peak
Temperature
6 minutes
maximum
8 minutes
maximum
Note 1: All temperatures refer to the center of the package, measured on the
capacitor body surface that is facing up during assembly reow.
Time
Temperature
Tsmin
25
Tsmax
TL
TPMaximum Ramp Up Rate = 3ºC/sec
Maximum Ramp Down Rate = 6ºC/sec
tP
tL
ts
25ºC to Peak
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1001_C0G_200C_SMD • 7/29/2016 13
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)
Table 4 – Performance & Reliability: Test Methods and Conditions
Product Qualication Test Plan
Reliability/Environmental Tests per MIL–STD–202//JESD22
High Temperature Life 200°C rated voltage 1,000 hours
Load Humidity 85°C/85%RH rated voltage 1,000 hours
Low Voltage Humidity 85°C/85%RH, 1.5 V, 1,000 hours
Temperature Cycling −55°C to +200°C, 50 Cycles
Thermal Shock −55°C to +150°C, 20 seconds transfer, 15 minute dwell, 300 cycles
Moisture Resistance Cycled Temp/RH 0 V, 10 cycles at 24 hours each
Physical, Mechanical & Process Tests per MIL–STD 202/JIS–C–6429
Resistance to Solvents Include Aqueous wash chemical, OKEM Clean or equivalent
Mechanical Shock and Vibration Method 213: Figure 1, Condition F Method 204: 5 gs for 20 minutes 12 cycles
Resistance to Soldering Heat Condition B, no per-heat of samples, Single Wave Solder
Terminal Strength Force of 1.8 kg for 60 seconds
Board Flex Appendix 2, Note: 3.0 mm (minimum)
Storage and Handling
Ceramic chip capacitors should be stored in normal working environments. While the chips themselves are quite robust in
other environments, solderability will be degraded by exposure to high temperatures, high humidity, corrosive atmospheres,
and long term storage. In addition, packaging materials will be degraded by high temperature–reels may soften or warp
and tape peel force may increase. KEMET recommends that maximum storage temperature not exceed 40°C and maximum
storage humidity not exceed 70% relative humidity. In addition, temperature uctuations should be minimized to avoid
condensation on the parts and atmospheres should be free of chlorine and sulfur bearing compounds. For optimized
solderability chip stock should be used promptly, preferably within the time frame outlined in the table below:
Termination Finish Termination Finish Ordering Code1Storage Life
100% Matte Tin (Sn) C 1.5 years upon receipt
SnPb (5% Pb min.) L 1.5 years upon receipt
Gold (Au) 1.97 – 11.8 µin2E 6 months upon receipt2
Gold (Au) 30 – 50 µin F 1.5 years upon receipt
Gold (Au) 100 µin min. G 1.5 years upon receipt
1 The fourteenth (14th) character position of the KEMET part number is assigned to identify and/or dene the termination nish.
For more information, see “Ordering Information” section of this document.
2 Gold plating option “E” devices should remain in its factory sealed moisture sensitive packaging during storage. If the factory sealed packaging is
disturbed please store any remaining packaged components in a dry box container to prevent oxidation of the termination nish.
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1001_C0G_200C_SMD • 7/29/2016 14
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)
Construction
Dielectric
Material (CaZrO3)
Detailed Cross Section
Barrier Layer
(Ni)
Inner Electrodes
(Ni)
Barrier Layer
(Ni)
Inner Electrodes
(Ni)
Dielectric Material
(CaZrO3)
Termination Finish:
C = 100% Matte Sn
L = SnPb - 5% Pb min
E = Gold (Au) 1.97 - 11.8 µin
F = Gold (Au) 30 - 50 µin
G = Gold (Au) 100 µin min
Termination Finish
(See options at left)
End Termination/
External Electrode
(Cu)
End Termination/
External Electrode
(Cu)
Capacitor Marking (Optional):
Laser marking option is not available on:
• C0G, Ultra Stable X8R and Y5V dielectric devices
• EIA 0402 case size devices
• EIA 0603 case size devices with Flexible Termination option.
• KPS Commercial and Automotive grade stacked devices.
These capacitors are supplied unmarked only.
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Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)
Tape & Reel Packaging Information
KEMET offers multilayer ceramic chip capacitors packaged in 8, 12 and 16 mm tape on 7" and 13" reels in accordance with
EIA Standard 481. This packaging system is compatible with all tape-fed automatic pick and place systems. See Table 2 for
details on reeling quantities for commercial chips.
8 mm, 12 mm
or 16 mm Carrier Tape
178 mm (7.00")
or
330 mm (13.00")
Anti-Static Reel
Embossed Plastic* or
Punched Paper Carrier.
Embossment or Punched Cavity
Anti-Static Cover Tape
(.10 mm (.004") Maximum Thickness)
Chip and KPS Orientation in Pocket
(except 1825 Commercial, and 1825 and 2225 Military)
*EIA 01005, 0201, 0402 and 0603 case sizes available on punched paper carrier only.
KEMET
®
Bar Code Label
Sprocket Holes
Table 5 – Carrier Tape Con guration, Embossed Plastic & Punched Paper (mm)
EIA Case Size
Tape
Size
(W)*
Embossed Plastic Punched Paper
7" Reel 13" Reel 7" Reel 13" Reel
Pitch (P
1
)* Pitch (P
1
)*
01005 – 0402 8 2 2
0603 82/4 2/4
0805 84444
1206 – 1210 84444
1805 – 1808 12 4 4
≥ 1812 12 8 8
KPS 1210 12 8 8
KPS 1812 & 2220 16 12 12
Array 0508 & 0612 844
*Refer to Figures 1 & 2 for W and P1 carrier tape reference locations.
*Refer to Tables 6 & 7 for tolerance speci cations.
New 2 mm Pitch Reel Options*
Packaging
Ordering Code
(C-Spec)
Packaging Type/Options
C-3190
Automotive grade 7" reel unmarked
C-3191
Automotive grade 13" reel unmarked
C-7081
Commercial grade 7" reel unmarked
C-7082
Commercial grade 13" reel unmarked
* 2 mm pitch reel only available for 0603 EIA case size.
2 mm pitch reel for 0805 EIA case size under development.
Bene ts of Changing from 4 mm to 2 mm Pitching Spacing
• Lower placement costs
• Double the parts on each reel results in fewer reel
changes and increased ef ciency
• Fewer reels result in lower packaging, shipping and
storage costs, reducing waste
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1001_C0G_200C_SMD • 7/29/2016 16
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)
Figure 1 – Embossed (Plastic) Carrier Tape Dimensions
Po
T
F
W
Center Lines of Cavity
Ao
Bo
User Direction of Unreeling
Cover Tape
Ko
B
1
is for tape feeder reference only,
including draft concentric about B
o
.
T
2
ØD
1
ØDo
B
1
S
1
T
1
E
1
E
2
P
1
P
2
Embossment
For cavity size,
see Note 1 Table 4
[10 pitches cumulative
tolerance on tape ± 0.2 mm]
Table 6 – Embossed (Plastic) Carrier Tape Dimensions
Metric will govern
Constant Dimensions — Millimeters (Inches)
Tape Size D0
D
1
Minimum
Note 1
E1P0P2
R Reference
Note 2
S
1
Minimum
Note 3
T
Maximum
T
1
Maximum
8 mm
1.5+0.10 −0.0
(0.059+0.004 −0.0)
1.0
(0.039)
1.75±0.10
(0.069±0.004) 4.0±0.10
(0.157±0.004) 2.0±0.05
(0.079±0.002)
25.0
(0.984)
0.600
(0.024) 0.600
(0.024) 0.100
(0.004)
12 mm 1.5
(0.059) 30
(1.181)
16 mm
Variable Dimensions — Millimeters (Inches)
Tape Size Pitch
B
1
Maximum
Note 4
E
2
Minimum
F P1
T
2
Maximum
W
Maximum
A0,B0 & K0
8 mm Single (4 mm)
4.35
(0.171)
6.25
(0.246)
3.5±0.05
(0.138±0.002)
4.0±0.10
(0.157±0.004)
2.5
(0.098)
8.3
(0.327)
Note 512 mm
Single (4 mm) &
Double (8 mm)
8.2
(0.323)
10.25
(0.404)
5.5±0.05
(0.217±0.002)
8.0±0.10
(0.315±0.004)
4.6
(0.181)
12.3
(0.484)
16 mm Triple (12 mm)
12.1
(0.476)
14.25
(0.561)
7.5±0.05
(0.138±0.002)
12.0±0.10
(0.157±0.004)
4.6
(0.181)
16.3
(0.642)
1. The embossment hole location shall be measured from the sprocket hole controlling the location of the embossment. Dimensions of embossment
location and hole location shall be applied independent of each other.
2. The tape with or without components shall pass around R without damage (see Figure 6).
3. If S1 < 1.0 mm, there may not be enough area for cover tape to be properly applied (see EIA Standard 481 paragraph 4.3 section b).
4. B1 dimension is a reference dimension for tape feeder clearance only.
5. The cavity de ned by A0, B0 and K0 shall surround the component with suf cient clearance that:
(a) the component does not protrude above the top surface of the carrier tape.
(b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed.
(c) rotation of the component is limited to 20° maximum for 8 and 12 mm tapes and 10° maximum for 16 mm tapes (see Figure 3).
(d) lateral movement of the component is restricted to 0.5 mm maximum for 8 and 12 mm wide tape and to 1.0 mm maximum for 16 mm tape
(See Figure 4).
(e) for KPS Series product, A0 and B0 are measured on a plane 0.3 mm above the bottom of the pocket.
(f) see Addendum in EIA Standard 481 for standards relating to more precise taping requirements.
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1001_C0G_200C_SMD • 7/29/2016 17
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)
Figure 2 – Punched (Paper) Carrier Tape Dimensions
User Direction of Unreeling
Top Cover Tape
T
Center Lines of Cavity
P1
ØDo Po E1
F
E2W
G
A0
B0
Cavity Size,
See
Note 1, Table 7
Bottom Cover Tape
T1
T1
Bottom Cover Tape
[10 pitches cumulative
tolerance on tape ± 0.2 mm]
Table 7 – Punched (Paper) Carrier Tape Dimensions
Metric will govern
Constant Dimensions — Millimeters (Inches)
Tape Size D0E1P0P2T1 Maximum G Minimum
R Reference
Note 2
8 mm 1.5 +0.10 -0.0
(0.059 +0.004 -0.0) 1.75 ±0.10
(0.069 ±0.004) 4.0 ±0.10
(0.157 ±0.004) 2.0 ±0.05
(0.079 ±0.002)
0.10
(0.004)
Maximum
0.75
(0.030) 25
(0.984)
Variable Dimensions — Millimeters (Inches)
Tape Size Pitch E2 Minimum F P1 T Maximum W Maximum A0 B0
8 mm Half (2 mm) 6.25
(0.246) 3.5 ±0.05
(0.138 ±0.002)
2.0 ±0.05
(0.079 ±0.002)
1.1
(0.098)
8.3
(0.327)
Note 1
8 mm Single (4 mm)
4.0 ±0.10
(0.157 ±0.004)
8.3
(0.327)
1. The cavity de ned by A0, B0 and T shall surround the component with suf cient clearance that:
a) the component does not protrude beyond either surface of the carrier tape.
b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed.
c) rotation of the component is limited to 20° maximum (see Figure 3).
d) lateral movement of the component is restricted to 0.5 mm maximum (see Figure 4).
e) see Addendum in EIA Standard 481 for standards relating to more precise taping requirements.
2. The tape with or without components shall pass around R without damage (see Figure 6).
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1001_C0G_200C_SMD • 7/29/2016 18
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)
Packaging Information Performance Notes
1. Cover Tape Break Force: 1.0 Kg minimum.
2. Cover Tape Peel Strength: The total peel strength of the cover tape from the carrier tape shall be:
Tape Width Peel Strength
8 mm 0.1 to 1.0 Newton (10 to 100 gf)
12 and 16 mm 0.1 to 1.3 Newton (10 to 130 gf)
The direction of the pull shall be opposite the direction of the carrier tape travel. The pull angle of the carrier tape shall be
165° to 180° from the plane of the carrier tape. During peeling, the carrier and/or cover tape shall be pulled at a velocity of
300 ±10 mm/minute.
3. Labeling: Bar code labeling (standard or custom) shall be on the side of the reel opposite the sprocket holes. Refer to EIA
Standards 556 and 624.
Figure 3 – Maximum Component Rotation
Ao
Bo
°
T
°
s
Maximum Component Rotation
Top View
Maximum Component Rotation
Side View
Tape Maximum
Width (mm) Rotation (°
T)
8,12 20
16 – 200 10 Tape Maximum
Width (mm) Rotation ( °
S)
8,12 20
16 – 56 10
72 – 200 5
Typical Pocket Centerline
Typical Component Centerline
Figure 4 – Maximum Lateral Movement
0.5 mm maximum
0.5 mm maximum
8 mm & 12 mm Tape
1.0 mm maximum
1.0 mm maximum
16 mm Tape
Figure 5 – Bending Radius
RR
Bending
Radius
Embossed
Carrier
Punched
Carrier
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1001_C0G_200C_SMD • 7/29/2016 19
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)
Figure 6 – Reel Dimensions
AD(See Note)
Full Radius,
See Note
B(see Note)
Access Hole at
Slot Location
(Ø 40 mm minimum)
If present,
tape slot in core
for tape start:
2.5 mm minimum width x
10.0 mm minimum depth
W3 (Includes
flange distortion
at outer edge)
W2 (Measured at hub)
W1 (Measured at hub)
C
(Arbor hole
diameter)
Note: Drive spokes optional; if used, dimensions B and D shall apply.
N
Table 8 – Reel Dimensions
Metric will govern
Constant Dimensions — Millimeters (Inches)
Tape Size A B Minimum CD Minimum
8 mm 178 ±0.20
(7.008 ±0.008)
or
330 ±0.20
(13.000 ±0.008)
1.5
(0.059) 13.0 +0.5/-0.2
(0.521 +0.02/-0.008) 20.2
(0.795)
12 mm
16 mm
Variable Dimensions — Millimeters (Inches)
Tape Size N Minimum W1 W2 Maximum W3
8 mm
50
(1.969)
8.4 +1.5/-0.0
(0.331 +0.059/-0.0)
14.4
(0.567)
Shall accommodate tape
width without interference
12 mm
12.4 +2.0/-0.0
(0.488 +0.078/-0.0)
18.4
(0.724)
16 mm
16.4 +2.0/-0.0
(0.646 +0.078/-0.0)
22.4
(0.882)
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1001_C0G_200C_SMD • 7/29/2016 20
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)
Figure 7 – Tape Leader & Trailer Dimensions
Trailer
160 mm Minimum
Carrier Tape
END START
Round Sprocket Holes
Elongated Sprocket Holes
(32 mm tape and wider)
Top Cover Tape
Top Cover Tape
Punched Carrier
8 mm & 12 mm only
Embossed Carrier
Components
100 mm
Minimum Leader
400 mm Minimum
Figure 8 – Maximum Camber
Carrier Tape
Round Sprocket Holes
1 mm Maximum, either direction
Straight Edge
250 mm
Elongated sprocket holes
(32 mm & wider tapes)
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1001_C0G_200C_SMD • 7/29/2016 21
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)
Waf e Tray Packaging Information – 2" x 2" w/ Static Protection
Figure 9 – Waf e Tray Dimensions – Inches (Millimeters)
90°
A
0.10 (2.54) X 45°
1.800 ±0.004 SQ
(45.720 ±0.102 SQ)
1.812 ±0.004 SQ
(46.025 ±0.102 SQ)
2.000 ±0.004 SQ
(50.800 ±0.102 SQ)
STANDARD RIB MATRIX
X
M2
M M3
M1
Y
X
Z
0.086
(2.184)
0.156 +0.002/-0.003
(3.962 +0.051/-0.076)
0.004
(0.102)
0.098
(2.489)
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1001_C0G_200C_SMD • 7/29/2016 22
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)
Table 9A – Waf e Tray Dimensions – Inches
Case Size
2" x 2" Waf e Tray Dimensions – Inches
Packaging Quantity
(pcs/unit
packaging)
M
M1
M2
M3
X
Y
Z
A°
MATRIX
EIA (in)
Metric (mm)
±0.003
±0.003
±0.002
±0.002
±0.002
±0.002
±0.003
± 1/2°
(X x Y)
0402
1005
0.175
0.153
0.077
0.110
0.073
0.042
0.041
7
16 X 23
368
0504
1210
0.235
0.226
0.172
0.170
0.080
0.090
0.055
5
10 X 10
100
0603
1608
0.175
0.153
0.077
0.110
0.073
0.042
0.041
7
16 X 23
368
0805
2012
0.232
0.186
0.181
0.171
0.062
0.092
0.036
10
10 X 10
100
1005
2512
0.230
0.240
0.190
0.140
0.060
0.110
0.075
5
12 X 9
108
12061,2
3216
0.194
0.228
0.193
0.124
0.067
0.130
0.065
5
14 X 9
126
12061,3
3216
0.250
0.250
0.375
0.167
0.100
0.200
0.070
5
10 X 5
50
1210
3225
0.217
0.244
0.215
0.174
0.110
0.145
0.080
5
10 X 8
80
1808
4520
0.271
0.285
0.286
0.243
0.150
0.200
0.075
5
7 X 6
42
1812
4532
0.271
0.285
0.286
0.243
0.150
0.200
0.075
5
7 X 6
42
1825
4564
0.318
0.362
0.424
0.34
0.24
0.32
0.032
5
5 X 4
20
2220
5650
0.318
0.362
0.424
0.34
0.24
0.32
0.032
5
5 X 4
20
2225
5664
0.318
0.362
0.424
0.34
0.24
0.32
0.032
5
5 X 4
20
1 Packaging of 1206 (3216 metric) case size capacitors is dependent upon the nominal chip thickness of the device. See "Capacitance Range/Selection
Waterfall" and "Chip Thickness/Tape & Reel Packaging Quantities" to identify the nominal chip thickness of the capacitor.
2 Assigned to 1206 (3216 metric) case size capacitors with nominal thickness of ≤ 1.25mm (0.049 inches).
3 Assigned to 1206 (3216 metric) case size capacitors with nominal thickness of > 1.25mm (0.049 inches).
Table 9B – Waf e Tray Dimensions – Millimeters
Case Size
2" x 2" Waf e Tray Dimensions – Millimeters
Packaging Quantity
(pcs/unit
packaging)
M
M1
M2
M3
X
Y
Z
A°
MATRIX
EIA (in)
Metric (mm)
±0.08
±0.08
±0.05
±0.05
±0.05
±0.05
±0.08
± 1/2°
(X x Y)
0402
1005
4.45
3.89
1.96
2.79
1.85
1.07
1.04
7
16 X 23
368
0504
1210
5.97
5.74
4.37
4.32
2.03
2.29
1.40
5
10 X 10
100
0603
1608
4.45
3.89
1.96
2.79
1.85
1.07
1.04
7
16 X 23
368
0805
2012
5.89
4.72
4.60
4.34
1.57
2.34
0.91
10
10 X 10
100
1005
2512
5.84
6.10
4.83
3.56
1.52
2.79
1.91
5
12 X 9
108
12061,2
3216
4.93
5.79
4.90
3.15
1.70
3.30
1.65
5
14 X 9
126
12061,3
3216
6.35
6.35
9.53
4.24
2.54
5.08
1.78
5
10 X 5
50
1210
3225
5.51
6.20
5.46
4.42
2.79
3.68
2.03
5
10 X 8
80
1808
4520
6.88
7.24
7.26
6.17
3.81
5.08
1.91
5
7 X 6
42
1812
4532
6.88
7.24
7.26
6.17
3.81
5.08
1.91
5
7 X 6
42
1825
4564
8.08
9.19
10.77
8.64
6.10
8.13
0.81
5
5 X 4
20
2220
5650
8.08
9.19
10.77
8.64
6.10
8.13
0.81
5
5 X 4
20
2225
5664
8.08
9.19
10.77
8.64
6.10
8.13
0.81
5
5 X 4
20
1 Packaging of 1206 (3216 metric) case size capacitors is dependent upon the nominal chip thickness of the device. See "Capacitance Range/Selection
Waterfall" and "Chip Thickness/Tape & Reel Packaging Quantities" to identify the nominal chip thickness of the capacitor.
2 Assigned to 1206 (3216 metric) case size capacitors with nominal thickness of ≤ 1.25mm (0.049 inches).
3 Assigned to 1206 (3216 metric) case size capacitors with nominal thickness of > 1.25mm (0.049 inches).
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1001_C0G_200C_SMD • 7/29/2016 23
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)
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Disclaimer
All product speci cations, statements, information and data (collectively, the “Information”) in this datasheet are subject to change. The customer is responsible for
checking and verifying the extent to which the Information contained in this publication is applicable to an order at the time the order is placed.
All Information given herein is believed to be accurate and reliable, but it is presented without guarantee, warranty, or responsibility of any kind, expressed or implied.
Statements of suitability for certain applications are based on KEMET Electronics Corporation’s (“KEMET”) knowledge of typical operating conditions for such
applications, but are not intended to constitute – and KEMET speci cally disclaims – any warranty concerning suitability for a speci c customer application or use.
The Information is intended for use only by customers who have the requisite experience and capability to determine the correct products for their application. Any
technical advice inferred from this Information or otherwise provided by KEMET with reference to the use of KEMET’s products is given gratis, and KEMET assumes no
obligation or liability for the advice given or results obtained.
Although KEMET designs and manufactures its products to the most stringent quality and safety standards, given the current state of the art, isolated component
failures may still occur. Accordingly, customer applications which require a high degree of reliability or safety should employ suitable designs or other safeguards
(such as installation of protective circuitry or redundancies) in order to ensure that the failure of an electrical component does not result in a risk of personal injury or
property damage.
Although all product–related warnings, cautions and notes must be observed, the customer should not assume that all safety measures are indicted or that other
measures may not be required.
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