MC74VHC244 Octal Bus Buffer The MC74VHC244 is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology. The MC74VHC244 is a noninverting 3-state buffer, and has two active-low output enables. This device is designed to be used with 3-state memory address drivers, etc. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems to 3 V systems. * High Speed: tPD = 3.9 ns (Typ) at VCC = 5 V * Low Power Dissipation: ICC = 4 mA (Max) at TA = 25C * High Noise Immunity: VNIH = VNIL = 28% VCC * Power Down Protection Provided on Inputs * Balanced Propagation Delays * Designed for 2 V to 5.5 V Operating Range * Low Noise: VOLP = 0.9 V (Max) * Pin and Function Compatible with Other Standard Logic Families * Latchup Performance Exceeds 300 mA * ESD Performance: Human Body Model > 2000 V Machine Model > 200 V * Chip Complexity: 136 FETs * These Devices are Pb-Free and are RoHS Compliant A1 A2 A3 A4 DATA INPUTS B1 B2 B3 B4 OUTPUT ENABLES 2 18 4 16 6 14 8 12 11 9 13 7 15 5 17 3 MARKING DIAGRAMS 20 20 1 SOIC-20 DW SUFFIX CASE 751D VHC244 AWLYYWWG 1 20 20 1 VHC 244 ALYWG G TSSOP-20 DT SUFFIX CASE 948E 1 20 1 20 SOEIAJ-20 M SUFFIX CASE 967 1 VHC244 AWLYWWG VHC244 = Specific Device Code A = Assembly Location WL, L = Wafer Lot Y = Year WW, W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location) YA1 YA2 YA3 PIN ASSIGNMENT YA4 YB1 http://onsemi.com NONINVERTING OUTPUTS YB2 YB3 YB4 1 OEA 19 OEB OEA 1 20 VCC A1 2 19 OEB YB4 3 18 YA1 A2 4 17 B4 YB3 5 16 YA2 A3 6 15 B3 YB2 7 14 YA3 A4 8 13 B2 YB1 9 12 YA4 GND 10 11 B1 Figure 1. Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the Ordering Information Table on page 2 of this data sheet. (c) Semiconductor Components Industries, LLC, 2011 May, 2011 - Rev. 8 1 Publication Order Number: MC74VHC244/D MC74VHC244 FUNCTION TABLE INPUTS OUTPUTS OEA, OEB A, B YA, YB L L L L H H H X Z ORDERING INFORMATION Device Shipping Package MC74VHC244DW - OBSOLETE* SOIC-20 WB 38 Units/Rail MC74VHC244DWR2G SOIC-20 WB (Pb-Free) 1000/Tape & Reel MC74VHC244DTG TSSOP-20 (Pb-Free) 75 Units/Rail MC74VHC244DTR2G TSSOP-20 (Pb-Free) 2500/Tape & Reel MC74VHC244M - OBSOLETE* SOIC EIAJ-20 (Pb-Free) 1600 Units/Box MC74VHC244MELG SOIC EIAJ-20 (Pb-Free) 2000/Tape & Reel *This device is obsolete, information available for reference. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MAXIMUM RATINGS (Note 1) Symbol Parameter Value Unit VCC Positive DC Supply Voltage -0.5 to +7.0 V VIN Digital Input Voltage -0.5 to +7.0 V VOUT DC Output Voltage -0.5 to VCC +0.5 V IIK Input Diode Current -20 mA IOK Output Diode Current $20 mA IOUT DC Output Current, per Pin $25 mA ICC DC Supply Current, VCC and GND Pins $75 mA PD Power Dissipation in Still Air 500 450 mW TSTG Storage Temperature Range -65 to +150 C VESD ESD Withstand Voltage Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) >2000 >200 >2000 V ILATCHUP Latchup Performance Above VCC and Below GND at 125C (Note 5) $300 mA qJA Thermal Resistance, Junction-to-Ambient 96 128 C/W SOIC TSSOP SOIC TSSOP Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2. Tested to EIA/JESD22-A114-A 3. Tested to EIA/JESD22-A115-A 4. Tested to JESD22-C101-A 5. Tested to EIA/JESD78 http://onsemi.com 2 MC74VHC244 RECOMMENDED OPERATING CONDITIONS Symbol Characteristics Min Max Unit 2.0 5.5 V DC Input Voltage 0 5.5 V VOUT DC Output Voltage 0 VCC V TA Operating Temperature Range, all Package Types -55 125 C tr, tf Input Rise or Fall Time 0 100 20 ns/V VCC DC Supply Voltage VIN VCC = 3.3 V + 0.3 V VCC = 5.0 V + 0.5 V 90 419,300 47.9 100 178,700 20.4 110 79,600 9.4 120 37,000 4.2 130 17,800 2.0 140 8,900 1.0 TJ = 80 C 117.8 TJ = 90 C 1,032,200 TJ = 100 C 80 FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 110 C Time, Years TJ = 120 C Time, Hours TJ = 130 C Junction Temperature C NORMALIZED FAILURE RATE DEVICE JUNCTION TEMPERATURE VERSUS TIME TO 0.1% BOND FAILURES 1 1 10 100 1000 TIME, YEARS Figure 2. Failure Rate vs. Time Junction Temperature DC CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol VIH VIL VOH Parameter Condition Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Maximum High-Level Output Voltage VIN = VIH or VIL IOH = -50 mA VIN = VIH or VIL IOH = -4 mA IOH = -8 mA VOL Maximum Low-Level Output Voltage VIN = VIH or VIL IOL = 50 mA VIN = VIH or VIL IOH = 4 mA IOH = 8 mA (V) TA = 25C Min Typ TA 85C Max Min Max -55C TA 125C Min 2.0 1.5 1.5 1.5 1.5 3.0 to 5.5 VCCX 0.7 VCCX 0.7 VCCX 0.7 VCCX 0.7 Max V 2.0 0.5 0.5 0.5 3.0 to 5.5 VCCX 0.3 VCCX 0.3 VCCX 0.3 2.0 3.0 4.5 1.9 2.9 4.4 3.0 4.5 2.58 3.94 2.0 3.0 4.5 2.0 3.0 4.5 0.0 0.0 0.0 1.9 2.9 4.4 1.9 2.9 4.4 2.48 3.8 2.34 3.66 Unit V V 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 0.36 0.36 0.44 0.44 0.52 0.52 V IIN Input Leakage Current VIN = 5.5 V or GND 0 to 5.5 0.1 1.0 1.0 mA IOZ Maximum 3-State Leakage Current VIN = VIH or VIL 5.5 0.25 2.5 2.5 mA Maximum Quiescent Supply Current (per package) VIN = VCC or GND 5.5 4.0 40.0 40.0 mA ICC VOUT = VCC or GND http://onsemi.com 3 MC74VHC244 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIII IIIII II IIIIIIIIIIII IIIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIII IIIII IIIII II IIIIIIIII IIIIII IIIII IIII IIIIIIII IIIIIIIII II III III III III III III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIII IIIIIIIII II III III III III III III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIIIIIII II IIIIIIIII II III III III III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns) TA = 25C Symbol tPLH, tPHL tPZL, tPZH tPLZ, tPHZ tOSLH, tOSHL Parameter Min Test Conditions -55C 3 TA 3 125C TA 3 85C Typ Max Min Max Min Max Unit ns Maximum Propagation Delay, A to YA or B to YB VCC = 3.3 0.3 V CL = 15 pF CL = 50 pF 5.8 8.3 8.4 11.9 1.0 1.0 10.0 13.5 1.0 1.0 11.0 14.5 VCC = 5.0 0.5 V CL = 15 pF CL = 50 pF 3.9 5.4 5.5 7.5 1.0 1.0 6.5 8.5 1.0 1.0 7.5 9.5 Output Enable Time OEA to YA or OEB to YB VCC = 3.3 0.3 V RL = 1 kW CL = 15 pF CL = 50 pF 6.6 9.1 10.6 14.1 1.0 1.0 12.5 16.0 1.0 1.0 13.5 17.0 VCC = 5.0 0.5 V RL = 1 kW CL = 15 pF CL = 50 pF 4.7 6.2 7.3 9.3 1.0 1.0 8.5 10.5 1.0 1.0 9.5 11.5 Output Disable Time OEA to YA or OEB to YB VCC = 3.3 0.3 V RL = 1 kW CL = 50 pF 10.3 14.0 1.0 16.0 1.0 17.0 VCC = 5.0 0.5 V RL = 1 kW CL = 50 pF 6.7 9.2 1.0 10.5 1.0 11.5 Output to Output Skew VCC = 3.3 0.3 V (Note 6) CL = 50 pF 1.5 1.5 1.5 VCC = 5.0 0.5 V (Note 6) CL = 50 pF 1.0 1.0 1.5 10 10 10 Cin Maximum Input Capacitance 4 Cout Maximum Three-State Output Capacitance (Output in High-Impedance State) 6 ns ns ns pF pF Typical @ 25C, VCC = 5.0V CPD 19 Power Dissipation Capacitance (Note 7) pF 6. Parameter guaranteed by design. tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|. 7. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per bit). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V) TA = 25C Symbol Typ Parameter Max Unit VOLP Quiet Output Maximum Dynamic VOL 0.6 0.9 V VOLV Quiet Output Minimum Dynamic VOL -0.6 -0.9 V VIHD Minimum High Level Dynamic Input Voltage 3.5 V VILD Maximum Low Level Dynamic Input Voltage 1.5 V http://onsemi.com 4 MC74VHC244 SWITCHING WAVEFORMS VCC VCC A or B OEA or OEB 50% 50% GND GND tPLH YA or YB tPZL tPHL tPZH VOL +0.3V tPHZ VOH -0.3V 50% VCC YA or YB Figure 3. Switching Waveform HIGH IMPEDANCE 50% VCC YA or YB 50% VCC tPLZ HIGH IMPEDANCE Figure 4. Switching Waveform TEST CIRCUITS TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST OUTPUT DEVICE UNDER TEST CL* 1 kW CL* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 5. Test Circuit Figure 6. Test Circuit INPUT Figure 7. Input Equivalent Circuit http://onsemi.com 5 MC74VHC244 PACKAGE DIMENSIONS SOIC-20 WB DW SUFFIX CASE 751D-05 ISSUE G A 20 q X 45 _ E h 1 10 20X B B 0.25 M T A S B S A L H M 10X 0.25 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 18X e A1 SEATING PLANE C T http://onsemi.com 6 DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ MC74VHC244 PACKAGE DIMENSIONS TSSOP-20 CASE 948E-02 ISSUE C 20X 0.15 (0.006) T U 2X L K REF 0.10 (0.004) S L/2 20 M T U S V K K1 IIII IIII IIII S J J1 11 B -U- PIN 1 IDENT SECTION N-N 0.25 (0.010) N 1 10 M 0.15 (0.006) T U S A -V- N F DETAIL E C G D H DETAIL E 0.100 (0.004) -T- SEATING NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 6.40 6.60 0.252 0.260 B 4.30 4.50 0.169 0.177 ----C 1.20 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC -W- H 0.27 0.37 0.011 0.015 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_ PLANE SOLDERING FOOTPRINT 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS http://onsemi.com 7 MC74VHC244 PACKAGE DIMENSIONS SOEIAJ-20 CASE 967-01 ISSUE A 20 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 11 Q1 E HE 1 M_ L 10 DETAIL P Z D e VIEW P A A1 b 0.13 (0.005) c M 0.10 (0.004) DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.15 0.25 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --0.81 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.006 0.010 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.032 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 http://onsemi.com 8 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC74VHC244/D