Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LM7372 SNOS926F - MAY 1999 - REVISED SEPTEMBER 2014 LM7372 High Speed, High Output Current, Dual Operational Amplifier 1 Features 3 Description The LM7372 is a high speed dual voltage feedback amplifier with the slewing characteristic of current feedback amplifiers. However, it can be used in all traditional voltage feedback amplifier configurations. -80 dBc Highest Harmonic Distortion @1 MHz, 2VPP Very High Slew Rate: 3000 V/s Wide Gain Bandwidth Product: 120 MHz -3 dB Frequency @ AV = +2: 200 MHz Low Supply Current: 13 mA (both amplifiers) High Open Loop Gain: 85 dB High Output Current: 150 mA Differential Gain and Phase: 0.01%, 0.02 * 1 * * * * * * * The LM7372 is stable for gains as low as +2 or -1. It provides a very high slew rate at 3000 V/s and a wide gain bandwidth product of 120 MHz, while consuming only 6.5 mA/per amplifier of supply current. It is ideal for video and high speed signal processing applications such as xDSL and pulse amplifiers. With 150 mA output current, the LM7372 can be used for video distribution, as a transformer driver or as a laser diode driver. 2 Applications * * * * * * HDSL and ADSL Drivers Multimedia Broadcast Systems Professional Video Cameras CATV/Fiber Optics Signal Processing Pulse Amplifiers and Peak Detectors HDTV Amplifiers Operation on 15 V power supplies allows for large signal swings and provides greater dynamic range and signal-to-noise ratio. The LM7372 offers high SFDR and low THD, ideal for ADC/DAC systems. In addition, the LM7372 is specified for 5 V operation for portable applications. The LM7372 is built on TI's Advance VIPTM III (Vertically integrated PNP) complementary bipolar process. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LM7372 DDA (8) 4.90 mm x 3.91 mm LM7372 D (16) 9.90 mm x 3.91 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Harmonic Distortion vs Frequency Single Supply Application (16-Pin SOIC) -50 VCC 5 + VIN VCC 4 14 C6 0.1uF + 1/2 LM7372 - 3 R9 50 R3 5.1k R1 10.2k C7 20uF 1:1 R5 2k R6 2k + C3 47uF R7 2k R4 5.1k C2 0.1uF - VIN 100 R2 10.2k 12 11 Twisted Pair Line R8 50 HARMONIC DISTORTION (dBc) VS = 12V + C1 0.1uF AV = 2 VO = 2VP-P -70 HD2 RL = 100 HD3 -90 -110 1/2 LM7372 + 13 6 100k 1M 10M FREQUENCY (Hz) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM7372 SNOS926F - MAY 1999 - REVISED SEPTEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 4 4 4 4 5 6 6 7 8 Absolute Maximum Ratings ...................................... Handling Ratings....................................................... Recommended Operating Conditions (1) ................... Thermal Information .................................................. 15V DC Electrical Characteristics .......................... 15V AC Electrical Characteristics .......................... 5V DC Electrical Characteristics ............................ 5V AC Electrical Characteristics ............................ Typical Performance Characteristics ........................ 7 Detailed Description ............................................ 12 8 Application and Implementation ........................ 13 7.1 Functional Block Diagram ....................................... 12 8.1 Application Information............................................ 13 8.2 Typical Application .................................................. 13 8.3 Application Details................................................... 14 9 Power Supply Recommendations...................... 20 10 Layout................................................................... 21 10.1 Layout Guidelines ................................................. 21 11 Device and Documentation Support ................. 21 11.1 Trademarks ........................................................... 21 11.2 Electrostatic Discharge Caution ............................ 21 11.3 Glossary ................................................................ 21 12 Mechanical, Packaging, and Orderable Information ........................................................... 21 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (March 2013) to Revision F Page * Changed data sheet structure and organization. Added, updated, or renamed the following sections: Device Information Table, Pin Configuration and Functions, Application and Implementation; Device and Documentation Support; Mechanical, Packaging, and Ordering Information.................................................................................................. 1 * Changed "Junction Temperature Range" to "Operating Temperature Range" ...................................................................... 4 * Deleted TJ = 25C for Electrical Characteristics tables .......................................................................................................... 5 Changes from Revision D (March 2013) to Revision E * 2 Page Changed layout of National Data Sheet to TI format ........................................................................................................... 21 Submit Documentation Feedback Copyright (c) 1999-2014, Texas Instruments Incorporated Product Folder Links: LM7372 LM7372 www.ti.com SNOS926F - MAY 1999 - REVISED SEPTEMBER 2014 5 Pin Configuration and Functions NOTE For SO PowerPAD package the exposed pad should be tied either to V- or left electrically floating. Die attach material is conductive and is internally tied to V-. * Heatsink Pins. (1) Package DDA 8-Pin SO PowerPAD Top View 1 Package D 16-Pin SOIC Top View + 8 * V OUT A 16 1 NC 2 * 15 NC A - 2 + OUT A 3 7 OUT B -IN A 14 V+ A - + 13 OUT B -IN A 4 +IN A 3 + 12 -IN B +IN A 5 6 -IN B B B V- 6 - + NC 7 4 - V 5 - 11 +IN B 10 NC +IN B * 9 8 * Pin Functions PIN NAME NUMBER I/O DESCRIPTION DDA D * -- 1,8,9,16 -- -IN A 2 4 I ChA Inverting Input +IN A 3 5 I ChA Non-inverting Input -IN B 6 12 I ChB Inverting Input +IN B 5 11 I ChB Non-inverting Input NC -- 2, 7, 10, 15 -- No Connection OUT A 1 3 O Output A OUT B 7 13 O Output B Heatsink Pin - V 4 6 I Negative Supply V+ 8 14 I Positive Supply (1) The maximum power dissipation is a function of T(JMAX), RJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (T(JMAX) - TA)/RJA. All numbers apply for packages soldered directly into a PC board. The value for RJA is 106C/W for the 16-Pin SOIC package. With a total area of 4sq. in of 1oz CU connected to pins 1,6,8,9 & 16, RJA for the 16-Pin SOIC is decreased to 70C/W. 8-Pin SO PowerPAD package RJA is with 2 in2 heatsink (top and bottom layer each) and 1 oz. copper (see Table 2 and Application and Implementation ) Submit Documentation Feedback Copyright (c) 1999-2014, Texas Instruments Incorporated Product Folder Links: LM7372 3 LM7372 SNOS926F - MAY 1999 - REVISED SEPTEMBER 2014 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) (2) (3) over operating free-air temperature range (unless otherwise noted) PARAMETER MIN MAX UNIT 36 V 10 V Suppy Voltage (V+-V-) Differential Input Voltage (VS = 15V) Output Short Circuit to Ground (2) Continuous Infrared or Convection Reflow (20 sec.) Soldering Information Wave Soldering Lead Temperature (10 sec.) Input Voltage Maximum Junction Temperature (4) (1) (2) (3) (4) 235 C 260 C V- to V+ V 150 C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150C. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. The maximum power dissipation is a function of T(JMAX), RJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (T(JMAX) - TA)/RJA. All numbers apply for packages soldered directly into a PC board. The value for RJA is 106C/W for the 16-Pin SOIC package. With a total area of 4sq. in of 1oz CU connected to pins 1,6,8,9 & 16, RJA for the 16-Pin SOIC is decreased to 70C/W. 8-Pin SO PowerPAD package RJA is with 2 in2 heatsink (top and bottom layer each) and 1 oz. copper (see Table 2 and Application and Implementation ) 6.2 Handling Ratings MIN Tstg V(ESD) (1) (2) (3) -65 Storage temperature range Electrostatic discharge (1) MAX UNIT 150 C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (2) 1500 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (3) 200 V For testing purposes, ESD was applied using human body model, 1.5k in series with 100pF. Machine model, 0 in series with 200pF. JEDEC document JEP155 states that 1500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 200-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions (1) over operating free-air temperature range (unless otherwise noted) Supply Voltage Operating Temperature Range (1) MIN MAX 9 36 UNIT V -40 85 C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. 6.4 Thermal Information THERMAL METRIC (1) RJA (1) (2) 4 Junction-to-ambient thermal resistance DDA 8 PINS 106 D (2) 16 PINS (2) 47 UNIT C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The maximum power dissipation is a function of T(JMAX), RJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (T(JMAX) - TA)/RJA. All numbers apply for packages soldered directly into a PC board. The value for RJA is 106C/W for the 16-Pin SOIC package. With a total area of 4sq. in of 1oz CU connected to pins 1,6,8,9 & 16, RJA for the 16-Pin SOIC is decreased to 70C/W. 8-Pin SO PowerPAD package RJA is with 2 in2 heatsink (top and bottom layer each) and 1 oz. copper (see Table 2 and Application and Implementation ) Submit Documentation Feedback Copyright (c) 1999-2014, Texas Instruments Incorporated Product Folder Links: LM7372 LM7372 www.ti.com 6.5 SNOS926F - MAY 1999 - REVISED SEPTEMBER 2014 15V DC Electrical Characteristics Unless otherwise specified, all limits ensured for VCM = 0V and RL = 1k. Boldface apply at the temperature extremes. PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) 2.0 8.0 10.0 VOS Input Offset Voltage TC VOS Input Offset Voltage Average Drift IB Input Bias Current IOS Input Offset Current RIN Input Resistance RO Open Loop Output Resistance CMRR Common Mode Rejection Ratio VCM = 10V 75 70 93 PSRR Power Supply Rejection Ratio VS = 15V to 5V 75 70 90 VCM Input Common-Mode Voltage Range CMRR > 60dB AV VO Large Signal Voltage Gain (3) Output Swing 12 IS (1) (2) (3) V/C 2.7 10 12 A 0.1 4.0 6.0 A 40 M Differential Mode 3.3 M 15 75 70 85 RL = 100 70 66 81 13 12.7 13.4 -13 -12.7 -13.3 11.8 11.4 12.4 -11.2 -10.8 -11.9 RL = 1k dB dB 13 RL = 1k IOUT = 150mA Output Short Circuit Current mV Common Mode IOUT = - 150mA ISC UNIT V dB dB V V V V Sourcing 260 mA Sinking 250 mA Supply Current (both Amps) 13 17 19 mA All limits are specified by testing or statistical analysis. Typical values represent the most likely parametic norm. Large signal voltage gain is the total output swing divided by the input signal required to produce that swing. For VS = 15V, VOUT = 10V. For VS = 5V, VOUT = 2V Submit Documentation Feedback Copyright (c) 1999-2014, Texas Instruments Incorporated Product Folder Links: LM7372 5 LM7372 SNOS926F - MAY 1999 - REVISED SEPTEMBER 2014 6.6 www.ti.com 15V AC Electrical Characteristics Unless otherwise specified, all limits ensured for VCM = 0V and RL = 1k. Boldface apply at the temperature extremes. PARAMETER SR Slew Rate TEST CONDITIONS (3) MIN (1) TYP (2) AV = +2, VIN 13VP-P 3000 AV = +2, VIN 10VP-P 2000 Unity Bandwidth Product MAX (1) UNIT V/s 120 MHz 220 MHz AVOL = 6dB 70 deg AV = -1, AO = 5V, RL = 500 50 AV = -2, VIN = 5V, RL = 500 6.0 -3dB Frequency AV = +2 m Phase Margin tS Settling Time (0.1%) tP Propagation Delay AD Differential Gain (4) D Differential Phase (4) hd2 Second Harmonic Distortion FIN = 1MHz, AV = +2 hd3 IMD ns ns 0.01% 0.02 deg VOUT = 2VP-P, RL = 100 -80 dBc VOUT = 16.8VP-P, RL = 100 -73 dBc Third Harmonic Distortion FIN = 1MHz, AV = +2 VOUT = 2VP-P, RL = 100 -91 dBc VOUT = 16.8VP-P, RL = 100 -67 dBc Intermodulation Distortion Fin 1 = 75kHz, Fin 2 = 85kHz VOUT = 16.8VP-P, RL = 100 -87 dBc en Input-Referred Voltage Noise f = 10kHz 14 nV/Hz in Input-Referred Current Noise f = 10kHz 1.5 pA/Hz (1) (2) (3) (4) All limits are specified by testing or statistical analysis. Typical values represent the most likely parametic norm. Slew Rate is the average of the rising and falling slew rates. Differential gain and phase are measured with AV = +2, VIN = 1VPP at 3.58 MHz and output is 150 terminated. 6.7 5V DC Electrical Characteristics Unless otherwise specified, all limits ensured for VCM = 0V and RL = 1k. Boldface apply at the temperature extremes. PARAMETER VOS Input Offset Voltage TC VOS Input Offset Voltage Average Drift IB Input Bias Current IOS Input Offset Current RIN Input Resistance TEST CONDITIONS MIN (1) TYP (2) MAX (1) 2.2 8.0 10.0 12 V/C 10 12 A 0.1 4 6 A Common Mode 40 M Differential Mode 3.3 M 15 Open Loop Output Resistance CMRR Common Mode Rejection Ratio VCM = 2.5V 70 65 90 PSRR Power Supply Rejection Ratio VS = 15V to 5V 75 70 90 VCM Input Common-Mode Voltage Range CMRR > 60dB AV Large Signal Voltage Gain (3) RL = 1k 70 65 78 RL = 100 64 60 72 6 mV 3.3 RO (1) (2) (3) UNIT 3 dB dB V dB dB All limits are specified by testing or statistical analysis. Typical values represent the most likely parametic norm. Large signal voltage gain is the total output swing divided by the input signal required to produce that swing. For VS = 15V, VOUT = 10V. For VS = 5V, VOUT = 2V Submit Documentation Feedback Copyright (c) 1999-2014, Texas Instruments Incorporated Product Folder Links: LM7372 LM7372 www.ti.com SNOS926F - MAY 1999 - REVISED SEPTEMBER 2014 5V DC Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for VCM = 0V and RL = 1k. Boldface apply at the temperature extremes. PARAMETER VO TEST CONDITIONS Output Swing RL = 1k IOUT = - 80mA IOUT = 80mA ISC IS 6.8 Output Short Circuit Current MIN (1) TYP (2) 3.2 3.0 3.4 -3.2 -3.0 -3.4 2.5 2.2 2.8 -2.5 -2.2 -2.7 Sourcing 150 Sinking 150 Supply Current (both Amps) 12.4 MAX (1) UNIT V V V V mA mA 16 18 mA 5V AC Electrical Characteristics Unless otherwise specified, all limits ensured for VCM = 0V and RL = 1k. Boldface apply at the temperature extremes. PARAMETER SR Slew Rate (3) TEST CONDITIONS AV = +2, VIN 3VP-P Unity Bandwidth Product -3dB Frequency AV = +2 MIN (1) TYP (2) MAX (1) UNIT 700 V/s 100 MHz 125 MHz 70 deg m Phase Margin tS Settling Time (0.1%) AV = -1, VO = 1V, RL = 500 70 ns tP Propagation Delay AV = +2, VIN = 1V, RL = 500 7 ns AD Differential Gain (4) D Differential Phase (4) hd2 Second Harmonic Distortion FIN = 1MHz, AV = +2 VOUT = 2VP-P, RL = 100 -84 hd3 Third Harmonic Distortion FIN = 1MHz, AV = +2 VOUT = 2VP-P, RL = 100 -94 en Input-Referred Voltage Noise f = 10kHz 14 nV/Hz in Input-Referred Current Noise f = 10kHz 1.8 pA/Hz (1) (2) (3) (4) 0.02% 0.03 deg dBc dBc All limits are specified by testing or statistical analysis. Typical values represent the most likely parametic norm. Slew Rate is the average of the rising and falling slew rates. Differential gain and phase are measured with AV = +2, VIN = 1VPP at 3.58 MHz and output is 150 terminated. Submit Documentation Feedback Copyright (c) 1999-2014, Texas Instruments Incorporated Product Folder Links: LM7372 7 LM7372 SNOS926F - MAY 1999 - REVISED SEPTEMBER 2014 www.ti.com 6.9 Typical Performance Characteristics -50 -30 VS = 12V AV = 2 HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) VS = 12V VO = 2VP-P -70 HD2 RL = 100 HD3 -90 -110 AV = 2 -50 RL = 100 HD2 -70 -90 -110 1M 100k 10M 1M 100k FREQUENCY (Hz) Figure 2. Harmonic Distortion vs Frequency -30 -30 VS = 12V VS = 12V HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) AV = 8 VO = 2VP-P -50 HD2 RL = 100 -70 HD3 -90 HD3 AV = 8 VO = 16.8VP-P -50 RL = 100 HD2 -70 -90 -110 1M 100k 100M 1M 100k FREQUENCY (Hz) 10M FREQUENCY (Hz) Figure 3. Harmonic Distortion vs Frequency Figure 4. Harmonic Distortion vs Frequency -50 -40 VS = 12V VS = 12V AV = 8 AV = 8 RL = 100 f = 1MHz RL = 100 f = 100kHz -70 DISTORTION (dBc) DISTORTION (dBc) 10M FREQUENCY (Hz) Figure 1. Harmonic Distortion vs Frequency HD2 -90 HD3 -110 -60 HD2 -80 HD3 -100 1 10 20 1 OUTPUT VOLTAGE (VP-P) 10 20 OUTPUT VOLTAGE (VP-P) Figure 5. Harmonic Distortion vs 8 HD3 VO = 16.8VP-P Figure 6. Harmonic Distortion vs Output Level Submit Documentation Feedback Copyright (c) 1999-2014, Texas Instruments Incorporated Product Folder Links: LM7372 LM7372 www.ti.com SNOS926F - MAY 1999 - REVISED SEPTEMBER 2014 Typical Performance Characteristics (continued) -50 VS = 12V VS = 12V AV = 2 AV = 2 RL = 100 f = 100kHZ -80 DISTORTION (dBc) DISTORTION (dBc) -60 HD2 -100 RL = 100 f = 1MHZ -70 HD2 -90 HD3 HD3 -110 -120 1 10 1 20 10 OUTPUT VOLTAGE (VP-P) OUTPUT VOLTAGE (VP-P) Figure 7. Harmonic Distortion vs Output Level Figure 8. Harmonic Distortion vs Output Level -40 -60 VS = 12V VS = 12v AV = 2 AV = 2 VO = 2VP-P f = 100kHz -80 -60 DISTORTION (dBc) DISTORTION (dBc) 20 HD2 -100 VO = 2VP-P f = 1MHz -80 HD2 HD3 -100 HD3 -120 -120 10 100 1000 10 1000 LOAD RESISTANCE (:) LOAD RESISTANCE (:) Figure 9. Harmonic Distortion vs Load Resistance -40 100 Figure 10. Harmonic Distortion vs Load Resistance -40 VS = 12V VS = 12V AV = 8 -80 HD2 -100 VO = 2VP-P f = 100kHz -60 DISTORTION (dBc) DISTORTION (dBc) AV = 8 VO = 2VP-P f = 1MHz -60 -80 HD2 -100 HD3 HD3 -120 -120 10 100 1000 10 LOAD RESISTANCE (:) 100 1000 LOAD RESISTANCE (:) Figure 11. Harmonic Distortion vs Load Resistance Figure 12. Harmonic Distortion vs Load Resistance Submit Documentation Feedback Copyright (c) 1999-2014, Texas Instruments Incorporated Product Folder Links: LM7372 9 LM7372 SNOS926F - MAY 1999 - REVISED SEPTEMBER 2014 www.ti.com Typical Performance Characteristics (continued) 2 2 VS = 12V 1 1 RL = 100 0 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 0 GAIN = +2 -1 -2 GAIN = +8 -3 -4 -1 GAIN = +2 -2 GAIN = +8 -3 -4 -5 -5 -6 -6 VS = 15V RL = 100 1 10 100 1 1000 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 13. Frequency Response Figure 14. Frequency Response 2 VS = 5V VS = 12V RL = 100 AV = 2 OUTPUT VOLTAGE (100mV/div) 1 NORMALIZED GAIN (dB) 0 -1 GAIN = +2 -2 GAIN = +8 -3 -4 RL = 100 -5 -6 1 10 100 1000 TIME (100ns/div) FREQUENCY (MHz) Figure 16. Small Signal Pulse Response Figure 15. Frequency Response 100 AV = 2 90 RL = 100 80 TJA (C/W) OUTPUT VOLTAGE (2V/div) VS = 12V 70 0.5 oz 60 1.0 oz 50 2.0 oz 40 30 20 0 TIME (100ns/div) 1.0 1.5 2.0 2.5 2 COPPER AREA (in ) Figure 17. Large Signal Pulse Response 10 0.5 Figure 18. Thermal Performance of 8ld-SO PowerPAD Submit Documentation Feedback Copyright (c) 1999-2014, Texas Instruments Incorporated Product Folder Links: LM7372 LM7372 www.ti.com SNOS926F - MAY 1999 - REVISED SEPTEMBER 2014 Typical Performance Characteristics (continued) -50 3 VS = 5V VS = 15V 2.5 VO = 2VP-P -70 INPUT BIAS CURRENT (A) HARMONIC DISTORTION (dBc) AV = 2 RL = 100 HD2 -90 HD3 2 1.5 1 0.5 0 -40 -110 100k 1M 10M 25 85 125 TEMPERATURE (C) FREQUENCY (Hz) Figure 20. Input Bias Current (A) vs Temperature Figure 19. Harmonic Distortion vs Frequency 20 VS = 15V OUTPUT VOLTAGE (V) POSITIVE OUTPUT 10 0 NEGATIVE OUTPUT -10 -20 -200 -100 0 100 200 OUTPUT CURRENT (mA) Figure 21. Output Voltage vs Output Current Submit Documentation Feedback Copyright (c) 1999-2014, Texas Instruments Incorporated Product Folder Links: LM7372 11 LM7372 SNOS926F - MAY 1999 - REVISED SEPTEMBER 2014 www.ti.com 7 Detailed Description 7.1 Functional Block Diagram M1 Q1 Q4 RE IN - V - IN + OUTPUT BUFFER + A V Q3 Q2 M2 Figure 22. Simplified Schematic Diagram 12 Submit Documentation Feedback Copyright (c) 1999-2014, Texas Instruments Incorporated Product Folder Links: LM7372 LM7372 www.ti.com SNOS926F - MAY 1999 - REVISED SEPTEMBER 2014 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LM7372 is a high speed dual operational amplifier with a very high slew rate and very low distortion. Like many other op amps, it is used in conventional voltage feedback amplifier applications, and has a class AB output stage in order to deliver high currents to low impedance loads. However, it draws a low quiescent supply current in most situations since the supply current increases when necessary to keep up with large output swing and/or high frequency (see High Frequency/Large Signal Swing Considerations). For most op amps in typical applications, this topology means that internal power dissipation is rarely an issue, even with the trend to smaller surface mount packages. However, TI has designed the LM7372 for applications where there are significant levels of power dissipation, and a way to effectively remove the internal heat generated by this power dissipation is needed in order to maintain the semiconductor junction temperature at acceptable levels. This is particularly important in environments with elevated ambient temperatures. 8.2 Typical Application V+ + 0.1uF 3 + VIN 2 5.1k 0.1uF 8 20uF + 1/2 LM7372 - 1 50 1:1 2k Twisted Pair Line 2k 100 2k 50 6 0.1uF 5 - VIN 1/2 LM7372 + 7 4 5.1k V0.1uF + 20uF Figure 23. Split Supply Application (SO PowerPAD) Submit Documentation Feedback Copyright (c) 1999-2014, Texas Instruments Incorporated Product Folder Links: LM7372 13 LM7372 SNOS926F - MAY 1999 - REVISED SEPTEMBER 2014 www.ti.com Typical Application (continued) VCC + C1 0.1uF 5 + VIN VCC 4 14 C6 0.1uF + 1/2 LM7372 - 3 R9 50 R3 5.1k R1 10.2k C7 20uF 1:1 R5 2k Twisted Pair Line R6 2k + C3 47uF 100 R7 2k R2 10.2k R4 5.1k 12 C2 0.1uF 11 - VIN R8 50 1/2 LM7372 + 13 6 Figure 24. Single Supply Application (16-Pin SOIC) 8.3 Application Details Several factors contribute to power dissipation and consequently higher semiconductor junction temperatures. Understanding these factors is necessary if the LM7372 is to perform to the desired specifications. Since different applications will have different dissipation levels and since there are various possible compromises between the ways these factors will contribute to the total junction temperature, this section will examine the typical application shown in Figure 24 as an example, and offer solutions when encountering excessive junction temperatures. There are two major contributors to the internal power dissipation. The first is the product of the supply voltage and the LM7372 quiescent current when no signal is being delivered to the external load, and the second is the additional power dissipated while delivering power to the external load. For low frequency (<1MHz) applications, the LM7372 supply current specification will suffice to determine the quiescent power dissipation (see High Frequency/Large Signal Swing Considerations for cases where the frequency range exceeds 1MHz and the LM7372 supply current increases). The LM7372 quiescent supply current is given as 6.5 mA per amplifier, so with a 24-V supply, the power dissipation is: PQ = VS x 2Iq -3 = 24 x 2 x (6.5 x 10 ) = 312mW where * (VS = V+ - V-) (1) This is already a high level of internal power dissipation, and in a small surface mount package with a thermal resistance of RJA = 140C/Watt -- a not unreasonable value for an 8-Pin SOIC package -- would result in a junction temperature 140C/W x 0.312W = 43.7C above the ambient temperature. A similar calculation using the worst case maximum supply current specification of 8.5 mA per amplifier at an 85C ambient will yield a power dissipation of 456 mW with a junction temperature of 149C, perilously close to the maximum permitted junction temperature of 150C. The second contributor to high junction temperature is the additional power dissipated internally when power is being delivered to the external load. This cause of temperature rise can be more difficult to calculate, even when the actual operating conditions are known. 14 Submit Documentation Feedback Copyright (c) 1999-2014, Texas Instruments Incorporated Product Folder Links: LM7372 LM7372 www.ti.com SNOS926F - MAY 1999 - REVISED SEPTEMBER 2014 Application Details (continued) For a Class B output stage, one transistor of the output pair will conduct the load current as the output voltage swings positive, with the other transistor drawing no current, and hence dissipating no power. During the other half of the signal swing, this situation is reversed, with the lower transistor sinking the load current and the upper transistor cut off. The current in each transistor will be a half wave rectified version of the total load current. Ideally neither transistor will dissipate power when there is no signal swing, but will dissipate increasing power as the output current increases. However, as the signal voltage across the load increases with load current, the voltage across the output transistor (which is the difference voltage between the supply voltage and the instantaneous voltage across the load) will decrease and a point will be reached where the dissipation in the transistor will begin to decrease again. If the signal is driven into a square wave, ideally the transistor dissipation will fall to zero. Therefore, for each amplifier, with an effective load each of RL and a sine wave source, integration over the half cycle with a supply voltage VS and a load voltage VL yields the average power dissipation of: PD = VSVL/RL - VL2/2RL where * * VS is the supply voltage VL is the peak signal swing across the load RL (2) For the package, the power dissipation will be doubled since there are two amplifiers in the package, each contributing half the swing across the load. The circuit in Single Supply Application, Figure 24, is using the LM7372 as the upstream driver in an ADSL application with Discrete MultiTone modulation. With DMT the upstream signal is spread into 32 adjacent channels each 4 kHz wide. For transmission over POTS, the regular telephone service, this upstream signal from the CPE (Customer Premise Equipment) occupies a frequency band from around 20 kHz up to a maximum frequency of 135 kHz. At first sight, these relatively low transmission frequencies certainly do not seem to require the use of very high speed amplifiers with GBW products in the range of hundreds of megahertz. However, the close spacing of multiple channels places stringent requirements on the linearity of the amplifier, since nonlinearities in the presence of multiple tones will cause harmonic products to be generated that can easily interfere with the higher frequency down stream signals also present on the line. The need to deliver 3rd Harmonic distortion terms lower than -75 dBc is the reason for the LM7372 quiescent current levels. Each amplifier is running over 3mA in the output stage alone in order to minimize crossover distortion. The xDSL signal levels are adjusted to provide a given power level on the line, and in the case of ADSL, this is an average power of 13 dBm. For a line with a characteristic impedance of 100 this is only 20 mW (= 1 mW x 10(13/10)). Because the transformer shown in Figure 24 is part of a transceiver circuit, two back-termination resistors are connected in series with each amplifier output. Therefore the equivalent RL for each amplifier is also 100 , and each amplifier is required to deliver 20 mW to this load. Since VL2/2RL = 20mW then VL = 2V(peak). (3) Using Equation 2 with this value for signal swing and a 24V supply, the internal power dissipation per amplifier is 132.8mW. Adding the quiescent power dissipation to the amplifier dissipation gives the total package internal power dissipation as PD(TOTAL) = 312mW + (2 x 132.8mW) = 578mW (4) This result is actually quite pessimistic because it assumes that the dissipation as a result of load current is simply added to the dissipation as a result of quiescent current. This is not correct, since the AB bias current in the output stage is diverted to load current as the signal swing amplitude increases from zero. In fact with load currents in excess of 3.3 mA, all the bias current is flowing in the load, consequently reducing the quiescent component of power dissipation. Also, it assumes a sine wave signal waveform when the actual waveform is composed of many tones of different phases and amplitudes which may demonstrate lower average power dissipation levels. Submit Documentation Feedback Copyright (c) 1999-2014, Texas Instruments Incorporated Product Folder Links: LM7372 15 LM7372 SNOS926F - MAY 1999 - REVISED SEPTEMBER 2014 www.ti.com Application Details (continued) The average current for a load power of 20 mW is 14.1 mA (= (20mW/100)). Neglecting the AB bias current, this appears as a full-wave rectified current waveform in the supply current with a peak value of 19.9mA. The peak to average ratio for a waveform of this shape is 1.57, so the total average load current is 12.7 mA (= 19.9 mA/1.57). Adding this to the quiescent current, and subtracting the power dissipated in the load (20 mV x 2 = 40 mW) gives the same package power dissipation level calculated above (= (12.7 + 13) mA x 24 V -40 mV = 576 mW). Nevertheless, when the supply current peak swing is measured, it is found to be significantly lower because the AB bias current is contributing to the load current. The supply current has a peak swing of only 14 mA (compared to 19.9 mA) superimposed on the quiescent current, with a total average value of only 21 mA. Therefore, the total package power dissipation in this application is: PD(TOTAL) = (VS x Iavg) - Power in Load = (24 x 21)mW - 40mW = 464mW (5) This level of power dissipation would not take the junction temperature in the 8-Pin SO PowerPAD package over the absolute maximum rating at elevated ambient temperatures (barely), but there is no margin to allow for component tolerances or signal variances. To develop 20 mW in a 100 requires each amplifier to deliver a peak voltage of only 2V, or 4V(P-P). This level of signal swing does not require a high supply voltage but the application uses a 24V supply. This is because the modulation technique uses a large number of tones to transmit the data. While the average power level is held to 20 mW, at any time the phase and amplitude of individual tones will be such as to generate a combined signal with a higher peak value than 2 V. For DMT this crest factor is taken to be around 5.33 so each amplifier has to be able to handle a peak voltage swing of: VLpeak = 1.4 x 5.33 = 7.5 V or 15 V(P-P) (6) If other factors, such as transformer loss or even higher peak to average ratios are allowed for, this means the amplifiers must each swing between 16 to 18 V(P-P). The required signal swing can be reduced by using a step-up transformer to drive the line. For example a 1:2 ratio will reduce the peak swing requirement by half, and this would allow the supply to be reduced by a corresponding amount. This is not recommended for the LM7372 in this particular application for two reasons. First, although the quiescent power contribution to the overall dissipation is reduced by about 150 mW, the internal power dissipation to drive the load remains the same, since the load for each amplifier is now 25 instead of 100 . Secondly, this is a transceiver application where downstream signals are simultaneously appearing at the transformer secondary. The down stream signals appear differentially across the back termination resistors and are now stepped down by the transformer turns ratio with a consequent loss in receiver sensitivity compared to using a 1:1 transformer. Any trade-off to reduce the supply voltage by an increase in turns ratio should bear these factors in mind, as well as the increased signal current levels required with lower impedance loads. At an elevated ambient temperature of 85C and with an average power dissipation of 464mW, a package thermal resistance between 60C/W and 80C/W will be needed to keep the maximum junction temperature in the range 110C to 120C. The SO PowerPAD package would be the package of choice here with ample board copper area to aid in heat dissipation (see Table 2). For most standard surface mount packages (8-Pin SOIC, 14-Pin SOIC, 16-Pin SOIC, and so forth), the only means of heat removal from the die is through the bond wires to external copper connecting to the leads. Usually it will be difficult to reduce the thermal resistance of these packages below 100C/W by these methods and several manufacturers, including Texas Instruments, offer package modifications to enhance the thermal characteristics. 16 Submit Documentation Feedback Copyright (c) 1999-2014, Texas Instruments Incorporated Product Folder Links: LM7372 LM7372 www.ti.com SNOS926F - MAY 1999 - REVISED SEPTEMBER 2014 Application Details (continued) L* H* 16-PIN SURFACE MOUNT Figure 25. Copper Heatsink Patterns The LM7372 is available in the 16-Pin SOIC package. Since only 8 pins are needed for the two operational amplifiers, the remaining pins are used for heat sink purposes. Each of the end pins, 1,8,9 & 16 are internally bonded to the lead frame and form an effective means of transferring heat to external copper. This external copper can be either electrically isolated or be part of the topside ground plane in a single supply application. Figure 25 shows a copper pattern which can be used to dissipate internal heat from the LM7372. Table 1 gives some values of RJA for different values of L and H with 1oz copper. Table 1. 16-Pin SOIC Thermal Resistance with Area of Cu L (in) H (in) RJA (C/W) 1 0.5 83 2 1 70 3 1.5 67 From Table 1 it is apparent that two areas of 1oz copper at each end of the package, each 2 in2 in area (for a total of 2600mm2) will be sufficient to hold the maximum junction temperature under 120C with an 85C ambient temperature. An even better package for removing internally generated heat is a package with an exposed die attach paddle. Improved removal of internal heat can be achieved by directly connecting bond wires to the lead frame inside the package. Since this lead frame supports the die attach paddle, heat is transferred directly from the substrate to the outside copper by these bond wires. The LM7372 is also available in the 8-Pin SO PowerPAD package. For this package the entire lower surface of the paddle is not covered with plastic, which would otherwise act as a thermal barrier to heat transfer. Heat is transferred directly from the die through the paddle rather than through the small diameter bonding wires. Values of RJA in C/W for the SO PowerPAD package with various areas and weights of copper are tabulated in Table 2. Submit Documentation Feedback Copyright (c) 1999-2014, Texas Instruments Incorporated Product Folder Links: LM7372 17 LM7372 SNOS926F - MAY 1999 - REVISED SEPTEMBER 2014 www.ti.com Table 2. Thermal Resistance of SO PowerPAD Package COPPER AREA 0.5 in2 (EACH SIDE) 1.0 in2 (EACH SIDE) 2.0 in2 (EACH SIDE) 0.5 oz 1.0 oz 2.0 oz Top Layer Only 115 91 74 105 79 60 102 72 52 0.5 oz 1.0 oz 2.0 oz Bottom Layer Only 102 92 85 88 75 66 81 65 54 0.5 oz 1.0 oz 2.0 oz Top And Bottom 83 71 63 70 57 48 63 47 37 Table 2 clearly demonstrates the superior thermal qualities of the exposed pad package. For example, using the topside copper only in the same way as shown for the SOIC package (Figure 25), the SO PowerPAD requires half the area of 1 oz copper (2 in2, total or 1300mm2), for a comparable thermal resistance of 72C/Watt. This gives considerably more flexibility in the PCB layout aside from using less copper. The shape of the heat sink shown in Figure 25 is necessary to allow external components to be connected to the package pins. If thermal vias are used beneath the SO PowerPAD to the bottom side ground plane, then a square pattern heat sink can be used and there is no restriction on component placement on the top side of the board. Even better thermal characteristics are obtained with bottom layer heat sinking. A 2 inch square of 0.5oz copper gives the same thermal resistance (81C/W) as a competitive thermally enhanced 8-Pin SOIC package which needs two layers of 2 oz copper, each 4 in2 (for a total of 5000 mm2). With heavier copper, thermal resistances as low as 54C/W are possible with bottom side heat sinking only, substantially improving the long term reliability since the maximum junction temperature is held to less than 110C, even with an ambient temperature of 85C. If both top and bottom copper planes are used, the thermal resistance can be brought to under 40C/W. 8.3.1 High Frequency/Large Signal Swing Considerations The LM7372 employs a unique input stage in order to support large slew rate and high output current capability with large output swings, with a relatively low quiescent current. This input architecture boosts the device supply current when the application demands it. The result is a supply current which increases at high enough frequencies when the output swing is large enough with added power dissipation as a consequence. Figure 26 shows the amount of increase in supply current as a function of frequency for various sinusoidal output swing amplitudes: 1000 10V supply (1 amplifier) 10V supply (2 amplifiers) TJ = 140C 100 30V supply (1 amplifier) 10 30V supply 6V PP PP (2 amplifiers) PP PP 2V 3V PP PP 1V 1 15 V 20 V PP 24 V PP 10 V IS INCREASE (mA) 8-Pin SO PowerPAD qJA = 47C/W TA = 85C 1 10 100 FREQUENCY (MHz) Figure 26. Power Supply Current Increase 18 Submit Documentation Feedback Copyright (c) 1999-2014, Texas Instruments Incorporated Product Folder Links: LM7372 LM7372 www.ti.com SNOS926F - MAY 1999 - REVISED SEPTEMBER 2014 Figure 26 shows that there could be 1 mA or more excess supply current per amplifier with close to full output swing (24 VPP) when frequency is just above 1MHz (or at higher frequencies when the output swing is less). This boost in supply current enables the output to "keep up" with high frequency/large signal output swing, but in turn, increases the total package power dissipation and therefore raises the device junction temperature. As a consequence, it is necessary to pay special attention to the package heatsink design for these demanding applications, especially for ones that run at higher supply voltages. For that reason, Figure 26 has the safe operating limits for the 8-Pin SO PowerPAD package -- for example, "30V supply (2 amplifiers)" horizontal line -superimposed on top of it (with TJ limit of 140C when operated at 85C ambient), so that the designer can readily decide whether or not there is need for additional heat sinking. For example, if the LM7372 is operating similarly to the Figure 24 schematic with a single power supply of 10 V, it is safe to have up to 10 VPP output swing at up to 40 MHz with no additional heat sinking. This is determined by inspecting Figure 24 where the "10 V supply (2 amplifiers)" safe operating limit intercepts the 10 VPP swing graph at around 40 MHz Use the "10 V supply (1 amplifier) safe operating limit in cases where the second amplifier in the LM7372 package does not experience high frequency/high output swing conditions. At any given "IS increase" value (y axis), the product of frequency and output swing remains essentially constant for all output swing plots. This holds true for the lower frequency range before the plots experience a slope increase. Therefore, if the application example just discussed operates up to 60MHz instead, it is possible to calculate the junction-temperature-limited maximum output swing of 6.7 VPP(= 40 MHz x 10VPP/60 MHz) instead. Please note that Figure 26 precludes any additional amplifier power dissipation related to load (this topic is discussed below in detail). This load current, if large enough, will reduce the operating frequency/output swing further. It is important to note that the LM7372 can be destroyed if it is allowed to dissipate enough power that compromises its maximum junction temperature limit of 150C. With the op amp tied to a load, the device power dissipation consists of the quiescent power due to the supply current flow into the device, in addition to power dissipation due to the load current. The load portion of the power itself could include an average value (due to a DC load current) and an AC component. DC load current would flow if there is an output voltage offset, or the output AC average current is non-zero, or if the op amp operates in a single supply application where the output is maintained somewhere in the range of linear operation. Therefore: PD(TOTAL) = PQ + PDC + PAC PQ = |IS * VS| (Op Amp Quiescent Power Dissipation) PDC = |IO * (VR - VO)| (DC Load Power) (7) (8) (9) For PAC, (AC Load Power) see Table 3 where: * IS = Supply Current * VS = Total Supply Voltage (V+ - V-) * IO = Average Load Current * VO = Average Output Voltage * VR = Reference Voltage (V+ for sourcing and V- for sinking current) Table 3 shows the maximum AC component of the load power dissipated by the op amp for standard Sinusoidal, Triangular, and Square Waveforms: Table 3. Normalized Maximum AC Power Dissipated in the Output Stage for Standard Waveforms PAC (W./V2) SINUSOIDAL TRIANGULAR SQUARE 50.7 x 10-3 46.9 x 10-3 62.5 x 10-3 The table entries are normalized to VS2/RL. These entries are computed at the output swing point where the amplifier dissipation is the highest for each waveform type. To figure out the AC load current component of power dissipation, simply multiply the table entry corresponding to the output waveform by the factor VS2/RL. For example, with 5V supplies, a 100- load and triangular output waveform, power dissipation in the output stage is calculated as: PAC = 46.9 x 10-3 x 102/100 = 46.9mW which contributes another 2.2C (= 46.9mW x 47C/W) rise to the LM7372 junction temperature in the 8-Pin SO PowerPAD package. Submit Documentation Feedback Copyright (c) 1999-2014, Texas Instruments Incorporated Product Folder Links: LM7372 19 LM7372 SNOS926F - MAY 1999 - REVISED SEPTEMBER 2014 www.ti.com 9 Power Supply Recommendations The LM7372 is fabricated on a high voltage, high speed process. Using high supply voltages ensures adequate headroom to give low distortion with large signal swings. In Figure 24, a single 24 V supply is used. To maximize the output dynamic range the non-inverting inputs are biased to half supply voltage by the resistive divider R1, R2. The input signals are AC coupled and the coupling capacitors (C1, C2) can be scaled with the bias resistors (R3, R4) to form a high pass filter if unwanted coupling from the POTS signal occurs. Supply decoupling is important at both low and high frequencies. The 10F Tantalum and 0.1F Ceramic capacitors should be connected close to the supply Pin 14. Note that the V- pin (pin 6), and the PCB area associated with the heatsink (Pins 1,8,9 & 16) are at the same potential. Any layout should avoid running input signal leads close to this ground plane, or unwanted coupling of high frequency supply currents may generate distortion products. Although this application shows a single supply, conversion to a split supply is straightforward. The half supply resistive divider network is eliminated and the bias resistors at the non-inverting inputs are returned to ground. For example, see Figure 23 where the pin numbers in Figure 23 are given for SO PowerPAD package, whereas those in Single Supply Application (16-Pin SOIC) are for the SOIC package. With a split supply, note that the ground plane and the heatsink copper must be separate and are at different potentials, with the heatsink (pin 4 of the SO PowerPAD, pins 6,1,8,9 and 16 of the SOIC) now at a negative potential (V-). In either configuration, the area under the input pins should be kept clear of copper (whether ground plane copper or heatsink copper) to avoid parasitic coupling to the inputs. The LM7372 is stable with non inverting closed loop gains as low as +2. Typical of any voltage feedback operational amplifier, as the closed loop gain of the LM7372 is increased, there is a corresponding reduction in the closed loop signal bandwidth. For low distortion performance it is recommended to keep the closed loop bandwidth at least 10X the highest signal frequency. This is because there is less loop gain (the difference between the open loop gain and the closed loop gain) available at higher frequencies to reduce harmonic distortion terms. 20 Submit Documentation Feedback Copyright (c) 1999-2014, Texas Instruments Incorporated Product Folder Links: LM7372 LM7372 www.ti.com SNOS926F - MAY 1999 - REVISED SEPTEMBER 2014 10 Layout 10.1 Layout Guidelines Generally, a good high-frequency layout will keep power supply and ground traces away from the inverting input and output pins. Parasitic capacitance on these nodes to ground will cause frequency response peaking and possible circuit oscillations (see Application Note OA-15, "Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers", SNOA367, for more information). Texas Instruments suggests the following evaluation boards as a guide for high frequency layout and as an aid in device testing and characterization: Table 4. Printed Circuit Board Layout and Evaluation Boards DEVICE PACKAGE LM7372MA 16-Pin SOIC EVALUATION BOARD PN None LM7372MR 8-Pin SO PowerPAD LMH730121 The DAP (die attach paddle) on the 8-Pin SO PowerPAD should be tied to V-. It should not be tied to ground. See the respective Evaluation Board documentation. 11 Device and Documentation Support 11.1 Trademarks VIP is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.3 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 1999-2014, Texas Instruments Incorporated Product Folder Links: LM7372 21 PACKAGE OPTION ADDENDUM www.ti.com 11-Jan-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LM7372IMA NRND SOIC D 16 48 Non-RoHS & Green Call TI Call TI -40 to 85 LM7372IMA LM7372IMA/NOPB ACTIVE SOIC D 16 48 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LM7372IMA LM7372IMAX/NOPB ACTIVE SOIC D 16 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LM7372IMA DDA 8 95 RoHS & Green SN Level-3-260C-168 HR -40 to 85 LM73 72MR SO PowerPAD DDA 8 2500 Non-RoHS & Green Call TI Call TI -40 to 85 LM73 72MR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green SN Level-3-260C-168 HR -40 to 85 LM73 72MR LM7372MR/NOPB LM7372MRX LM7372MRX/NOPB ACTIVE SO PowerPAD NRND (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Jan-2021 (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM7372IMAX/NOPB SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1 LM7372MRX SO Power PAD DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM7372MRX/NOPB SO Power PAD DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM7372IMAX/NOPB SOIC D 16 2500 367.0 367.0 35.0 LM7372MRX SO PowerPAD DDA 8 2500 367.0 367.0 35.0 LM7372MRX/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE DDA0008B PowerPAD TM SOIC - 1.7 mm max height SCALE 2.400 PLASTIC SMALL OUTLINE C 6.2 TYP 5.8 A SEATING PLANE PIN 1 ID AREA 0.1 C 6X 1.27 8 1 2X 3.81 5.0 4.8 NOTE 3 4 5 8X B 4.0 3.8 NOTE 4 0.51 0.31 0.25 1.7 MAX C A B 0.25 TYP 0.10 SEE DETAIL A 5 4 EXPOSED THERMAL PAD 3.4 2.8 0.25 GAGE PLANE 9 8 1 0 -8 0.15 0.00 1.27 0.40 DETAIL A 2.71 2.11 TYPICAL 4214849/A 08/2016 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MS-012. www.ti.com EXAMPLE BOARD LAYOUT DDA0008B PowerPAD TM SOIC - 1.7 mm max height PLASTIC SMALL OUTLINE (2.95) NOTE 9 SOLDER MASK DEFINED PAD (2.71) SOLDER MASK OPENING SEE DETAILS 8X (1.55) 1 8 8X (0.6) 9 SYMM (1.3) TYP (3.4) SOLDER MASK OPENING (4.9) NOTE 9 6X (1.27) 5 4 (R0.05) TYP METAL COVERED BY SOLDER MASK SYMM ( 0.2) TYP VIA (1.3) TYP (5.4) LAND PATTERN EXAMPLE SCALE:10X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS PADS 1-8 4214849/A 08/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004). 9. Size of metal pad may vary due to creepage requirement. 10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com EXAMPLE STENCIL DESIGN DDA0008B PowerPAD TM SOIC - 1.7 mm max height PLASTIC SMALL OUTLINE (2.71) BASED ON 0.125 THICK STENCIL 8X (1.55) (R0.05) TYP 1 8 8X (0.6) (3.4) BASED ON 0.125 THICK STENCIL 9 SYMM 6X (1.27) 5 4 METAL COVERED BY SOLDER MASK SYMM (5.4) SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL THICKNESSES SOLDER PASTE EXAMPLE EXPOSED PAD 100% PRINTED SOLDER COVERAGE BY AREA SCALE:10X STENCIL THICKNESS SOLDER STENCIL OPENING 0.1 0.125 0.150 0.175 3.03 X 3.80 2.71 X 3.40 (SHOWN) 2.47 X 3.10 2.29 X 2.87 4214849/A 08/2016 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. 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