ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
12/10/8-Bit, 1 MSPS, 16/12/8/4-Channel, Single-Ended, MicroPower, Serial Interface ADCs
Check for Samples: ADS7950, ADS7951, ADS7952, ADS7953,ADS7954, ADS7955, ADS7956, ADS7957,ADS7958, ADS7959,
ADS7960, ADS7961
1FEATURES DESCRIPTION
• 1-MHz Sample Rate Serial Devices The ADS79XX is a 12/10/8-bit multichannel
analog-to-digital converter family. The following table
• Product Family of 12/10/8-Bit Resolution shows all twelve devices from this product family.
• Zero Latency The devices include a capacitor based SAR A/D
• 20-MHz Serial Interface converter with inherent sample and hold.
• Analog Supply Range: 2.7 to 5.25V The devices accept a wide analog supply range from
• I/O Supply Range: 1.7 to 5.25V 2.7V to 5.25V. Very low power consumption makes
• Two SW Selectable Unipolar, Input Ranges: 0 these devices suitable for battery-powered and
to 2.5V and 0 to 5V isolated power supply applications.
• Auto and Manual Modes for Channel Selection A wide 1.7V to 5.25V I/O supply range facilitates a
• 12,8,4-Channel Devices can Share 16 Channel glue-less interface with the most commonly used
Device Footprint CMOS digital hosts.
• Two Programmable Alarm Levels per Channel The serial interface is controlled by CS and SCLK for
• Four Individually Configurable GPIOs for easy connection with microprocessors and DSP.
TSSOP package devices. One GPIO for QFN The input signal is sampled with the falling edge of
devices CS. It uses SCLK for conversion, serial data output,
• Typical Power Dissipation: 14.5 mW (+VA = 5V, and reading serial data in. The devices allow auto
+VBD = 3V) at 1 MSPS sequencing of preselected channels or manual
selection of a channel for the next conversion cycle.
• Power-Down Current (1 mA)
• Input Bandwidth (47 MHz at 3dB) There are two software selectable input ranges (0V -
2.5V and 0V - 5V), four individually configurable
• 38-,30-Pin TSSOP and 32-,24-Pin QFN GPIOs ( in case of TSSOP package devices), and
Packages two programmable alarm thresholds per channel.
These features make the devices suitable for most
APPLICATIONS data acquisition applications.
• PLC / IPC The devices offer an attractive power-down feature.
• Battery Powered Systems This is extremely useful for power saving when the
• Medical Instrumentation device is operated at lower conversion speeds.
• Digital Power Supplies The 16/12-channel devices from this family are
• Touch Screen Controllers available in a 38-pin TSSOP and 32 pin QFN
• High-Speed Data Acquisition Systems package and the 4/8-channel devices are available in
• High-Speed Closed-Loop Systems a 30-pin TSSOP and 24 pin QFN packages.
MICROPOWER MULTI-CHANNEL ADS79XX FAMILY
RESOLUTION
NUMBER OF
CHANNELS 12 BIT 10 BIT 8 BIT
16 ADS7953 ADS7957 ADS7961
12 ADS7952 ADS7956 ADS7960
8 ADS7951 ADS7955 ADS7959
4 ADS7950 ADS7954 ADS7958
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2008–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Compare
Alarm
Threshold
ControlLogic
&
Sequencing
SDI
SCLK
CS
SDO
MXO AINP REF
ADC
GPIO BDGND VBD
+VA AGND
Ch0
Ch1
Ch2
Chn*
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ADS79XX BLOCK DIAGRAM
NOTE: n* is number of channels (16,12,8, or 4) depending on the device from the ADS79XX product family.
NOTE: 4 number of GPIO are available in TSSOP package devices only, QFN package devices offer only one GPIO.
2Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
ORDERING INFORMATION - 12-BIT
MAXIMUM MAXIMUM NO MISSING TRANSPORT
PACKAGE
INTEGRAL DIFFERENTIAL CODES AT NUMBER OF PACKAGE TEMPERATURE ORDERING
MODEL MEDIA
LINEARITY LINEARITY RESOLUTION CHANNELS DESIGNATOR RANGE INFORMATION
TYPE QTY
(LSB) (LSB) (BIT)
ADS7953SBDBT Tube, 50
38 pin TSSOP DBT ADS7953SBDBTR Reel, 2000
ADS7953 SB 16 ADS7953SBRHBT Tube, 250
32 pin QFN RHB ADS7953SBRHBR Reel, 3000
ADS7952SBDBT Tube, 50
38 pin TSSOP DBT ADS7952SBDBTR Reel, 2000
ADS7952 SB 12 ADS7952SBRHBT Tube, 250
32 pin QFN RHB ADS7952SBRHBR Reel, 3000
±1 ±1 12 –40°C to 125°C ADS7951SBDBT Tube, 50
30 pin TSSOP DBT ADS7951SBDBTR Reel, 2000
ADS7951 SB 8 ADS7951SBRGET Tube, 250
24 pin QFN RGE ADS7951SBRGER Reel, 3000
ADS7950SBDBT Tube, 50
30 pin TSSOP DBT ADS7950SBDBTR Reel, 2000
ADS7950 SB 4 ADS7950SBRGET Tube, 250
24 pin QFN RGE ADS7950SBRGER Reel, 3000
ADS7953SDBT Tube, 50
38 pin TSSOP DBT ADS7953SDBTR Reel, 2000
ADS7953 S 16 ADS7953SRHBT Tube, 250
32 pin QFN RHB ADS7953SRHBR Reel, 3000
ADS7952SDBT Tube, 50
38 pin TSSOP DBT ADS7952SDBTR Reel, 2000
ADS7952 S 12 ADS7952SRHBT Tube, 250
32 pin QFN RHB ADS7952SRHBR Reel, 3000
±1.5 ±2 11 –40°C to 125°C ADS7951SDBT Tube, 50
30 pin TSSOP DBT ADS7951SDBTR Reel, 2000
ADS7951S 8 ADS7951SRGET Tube, 250
24 pin QFN RGE ADS7951SRGER Reel, 3000
ADS7950SDBT Tube, 50
30 pin TSSOP DBT ADS7950SDBTR Reel, 2000
ADS7950 S 4 ADS7950SRGET Tube, 250
24 pin QFN RGE ADS7950SRGER Reel, 3000
ORDERING INFORMATION - 10-BIT
MAXIMUM MAXIMUM NO MISSING NUMBER TRANSPORT
PACKAGE
INTEGRAL DIFFERENTIAL CODES AT PACKAGE TEMPERATURE ORDERING
MODEL OF MEDIA
LINEARITY LINEARITY RESOLUTION DESIGNATOR RANGE INFORMATION
TYPE
CHANNELS QTY
(LSB) (LSB) (BIT)
ADS7957SDBT Tube, 50
38 pin TSSOP DBT ADS7957SDBTR Reel, 2000
ADS7957 S 16 ADS7957SRHBT Tube, 250
32 pin QFN RHB ADS7957SRHBR Reel, 3000
ADS7956SDBT Tube, 50
38 pin TSSOP DBT ADS7956SDBTR Reel, 2000
ADS7956 S 12 ADS7956SRHBT Tube, 250
32 pin QFN RHB ADS7956SRHBR Reel, 3000
±0.5 ±0.5 10 –40°C to 125°C ADS7955SDBT Tube, 50
30 pin TSSOP DBT ADS7955SDBTR Reel, 2000
ADS7955 S 8 ADS7955SRGET Tube, 250
24 pin QFN RGE ADS7955SRGER Reel, 3000
ADS7954SDBT Tube, 50
30 pin TSSOP DBT ADS7954SDBTR Reel, 2000
ADS7954 S 4 ADS7954SRGET Tube, 250
24 pin QFN RGE ADS7954SRGER Reel, 3000
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
ORDERING INFORMATION - 8-BIT
MAXIMUM MAXIMUM NO MISSING TRANSPORT
PACKAGE
INTEGRAL DIFFERENTIAL CODES AT NUMBER OF PACKAGE TEMPERATURE ORDERING
MODEL MEDIA
LINEARITY LINEARITY RESOLUTION CHANNELS DESIGNATOR RANGE INFORMATION
TYPE QTY
(LSB) (LSB) (BIT)
ADS7961SDBT Tube, 50
38 pin TSSOP DBT ADS7961SDBTR Reel, 2000
ADS7961 S 16 ADS7961SRHBT Tube, 250
32 pin QFN RHB ADS7961SRHBR Reel, 3000
ADS7960SDBT Tube, 50
38 pin TSSOP DBT ADS7960SDBTR Reel, 2000
ADS7960 S 12 ADS7960SRHBT Tube, 250
32 pin QFN RHB ADS7960SRHBR Reel, 3000
±0.3 ±0.3 8 –40°C to 125°C ADS7959SDBT Tube, 50
30 pin TSSOP DBT ADS7959SDBTR Reel, 2000
ADS7959 S 8 ADS7959SRGET Tube, 250
24 pin QFN RGE ADS7959SRGER Reel, 3000
ADS7958SDBT Tube, 50
30 pin TSSOP DBT ADS7958SDBTR Reel, 2000
ADS7958 S 4 ADS7958SRGET Tube, 250
24 pin QFN RGE ADS7958SRGER Reel, 3000
ABSOLUTE MAXIMUM RATINGS(1)
VALUE UNIT
AINP or CHn to AGND –0.3 to +VA +0.3 V
+VA to AGND, +VBD to BDGND –0.3 to +7.0 V
Digital input voltage to BDGND –0.3 to (7.0) V
Digital output to BDGND –0.3 to (+VA + 0.3) V
Operating temperature range –40 to 125 °C
Storage temperature range –65 to 150 °C
Junction temperature (TJMax) 150 °C
Power dissipation (TJMax–TA)/qJA
qJA thermal impedance, DBT Package 100.6 °C/W
qJA thermal impedance, RHB Package 34 °C/W
qJA thermal impedance, RGE Package 38 °C/W
DBT packaged versions of ADS79XX family devices are rated for MSL2 260°C per
the JSTD-020 specifications and the RGE and RHB packaged versions of ADS79XX
family devices are rated for MSL3 260C per JSTD-020 specifications
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
4Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
ELECTRICAL CHARACTERISTICS, ADS7950/51/52/53
+VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA= -40°C to 125°C, fsample = 1 MHz (unless otherwise
noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Range 1 0 Vref
Full-scale input span(1) V
Range 2 while 2Vref ≤+VA 0 2*Vref
–0.20 VREF
Range 1 +0.20
Absolute input range V
–0.20 2*VREF
Range 2 while 2Vref ≤+VA +0.20
Input capacitance 15 rF
Input leakage current TA= 125°C 61 nA
SYSTEM PERFORMANCE
Resolution 12 Bits
ADS795XSB (2) 12
No missing codes Bits
ADS795XS(2) 11
ADS795XSB(2) –1 ±0.5 1
Integral linearity LSB(3)
ADS795XS(2) –1.5 ±0.75 1.5
ADS795XSB(2) –1 ±0.5 1
Differential linearity LSB
ADS795XS(2) –2 ±0.75 1.5
Offset error(4) –3.5 ±1.1 3.5 LSB
Range 1 –2 ±0.2 2
Gain error LSB
Range 2 ±0.2
Total unadjusted error (TUE) ±2 LSB
SAMPLING DYNAMICS
Conversion time 20 MHz sclk 800 nSec
Acquisition time 325 nSec
Maximum throughput rate 20 MHz sclk 1.0 MHz
Aperture delay 5 nsec
Step response 150 nsec
Over voltage recovery 150 nsec
DYNAMIC CHARACTERISTICS
Total harmonic distortion(5) 100 kHz –82 dB
Signal-to-noise ratio 100 kHz, ADS795XSB(2) 70 71.7 dB
100 kHz, ADS795XS(2) 70 71.7
Signal-to-noise + distortion 100 kHz, ADS795XSB(2) 69 71.3 dB
100 kHz, ADS795XS(2) 68 71.3
Spurious free dynamic range 100 kHz 84 dB
Small signal bandwidth At –3 dB 47 MHz
Any off-channel with 100kHz, Full-scale input to
channel being sampled with DC input (isolation –95
crosstalk).
Channel-to-channel crosstalk dB
From previously sampled to channel with 100kHz,
Full-scale input to channel being sampled with DC –85
input (memory crosstalk).
EXTERNAL REFERENCE INPUT
(1) Ideal input span; does not include gain or offset error.
(2) ADS795X, where X indicates 0, 1, 2, or 3
(3) LSB means Least Significant Bit.
(4) Measured relative to an ideal full-scale input
(5) Calculated on the first nine harmonics of the input frequency.
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
ELECTRICAL CHARACTERISTICS, ADS7950/51/52/53 (continued)
+VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA= -40°C to 125°C, fsample = 1 MHz (unless otherwise
noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Vref reference voltage at REFP(6) 2.0 2.5 3.0 V
Reference resistance 100 kΩ
ALARM SETTING
Higher threshold range 0 FFC Hex
Lower threshold range 0 FFC Hex
DIGITAL INPUT/OUTPUT
Logic family CMOS
VIH 0.7*(+VBD)
VIL +VBD = 5 V 0.8
Logic level VIL +VBD = 3 V 0.4 V
VOH At Isource = 200 mA Vdd-0.2
VOL At Isink = 200 mA 0.4
Data format MSB first MSB First
POWER SUPPLY REQUIREMENTS
+VA supply voltage 2.7 3.3 5.25 V
+VBD supply voltage 1.7 3.3 5.25 V
At +VA = 2.7 to 3.6 V and 1MHz throughput 1.8 mA
At +VA = 2.7 to 3.6 V static state 1.05 mA
Supply current (normal mode) At +VA = 4.7 to 5.25 V and 1 MHz throughput 2.3 3 mA
At +VA = 4.7 to 5.25 V static state 1.1 1.5 mA
Power-down state supply current 1 mA
+VBD supply current +VA = 5.25V, fs= 1MHz 1 mA
Power-up time 1 mSec
Invalid conversions after power up or 1 Number
reset s
TEMPERATURE RANGE
Specified performance –40 125 °C
(6) Device is designed to operate over Vref = 2.0 V to 3.0 V. However one can expect lower noise performance at Vref < 2.4 V. This is due to
SNR degradation resulting from lowered signal range.
ELECTRICAL CHARACTERISTICS, ADS7954/55/56/57
+VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA= -40°C to 125°C, fsample = 1 MHz (unless otherwise
noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Range 1 0 Vref
Full-scale input span(1) V
Range 2 while 2Vref ≤+VA 0 2*Vref
VREF
Range 1 –0.20 +0.20
Absolute input range V
2*VREF
Range 2 while 2Vref ≤+VA –0.20 +0.20
Input capacitance 15 rF
Input leakage current TA= 125°C 61 nA
SYSTEM PERFORMANCE
Resolution 10 Bits
No missing codes 10 Bits
(1) Ideal input span; does not include gain or offset error.
6Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
ELECTRICAL CHARACTERISTICS, ADS7954/55/56/57 (continued)
+VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA= -40°C to 125°C, fsample = 1 MHz (unless otherwise
noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Integral linearity –0.5 ±0.2 0.5 LSB(2)
Differential linearity –0.5 ±0.2 0.5 LSB
Offset error(3) –1.5 ±0.5 1.5 LSB
Range 1 –1 ±0.1 1
Gain error LSB
Range 2 ±0.1
SAMPLING DYNAMICS
Conversion time 20 MHz SCLK 800 nSec
Acquisition time 325 nSec
Maximum throughput rate 20 MHz SCLK 1.0 MHz
Aperture delay 5 nsec
Step response 150 nsec
Over voltage recovery 150 nsec
DYNAMIC CHARACTERISTICS
Total harmonic distortion(4) 100 kHz –80 dB
Signal-to-noise ratio 100 kHz 60 dB
Signal-to-noise + distortion 100 kHz 60
Spurious free dynamic range 100 kHz 82 dB
Full power bandwidth At –3 dB 47 MHz
Any off-channel with 100kHz, Full-scale input to –95
channel being sampled with DC input.
Channel-to-channel crosstalk dB
From previously sampled to channel with 100kHz, –85
Full-scale input to channel being sampled with DC
input.
EXTERNAL REFERENCE INPUT
Vref reference voltage at REFP 2.0 2.5 3.0 V
Reference resistance 100 kΩ
ALARM SETTING
Higher threshold range 000 FFC Hex
Lower threshold range 000 FFC Hex
DIGITAL INPUT/OUTPUT
Logic family CMOS
VIH 0.7*(+VBD)
VIL +VBD = 5 V 0.8
Logic level VIL +VBD = 3 V 0.4 V
VOH At Isource = 200 mA Vdd-0.2
VOL At Isink = 200 mA 0.4
Data format MSB first MSB First
POWER SUPPLY REQUIREMENTS
+VA supply voltage 2.7 3.3 5.25 V
+VBD supply voltage 1.7 3.3 5.25 V
At +VA = 2.7 to 3.6 V and 1MHz throughput 1.8 mA
At +VA = 2.7 to 3.6 V static state 1.05 1 mA
Supply current (normal mode) At +VA = 4.7 to 5.25 V and 1 MHz throughput 2.3 3 mA
At +VA = 4.7 to 5.25 V static state 1.1 1.5 mA
(2) LSB means Least Significant Bit.
(3) Measured relative to an ideal full-scale input
(4) Calculated on the first nine harmonics of the input frequency.
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
ELECTRICAL CHARACTERISTICS, ADS7954/55/56/57 (continued)
+VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA= -40°C to 125°C, fsample = 1 MHz (unless otherwise
noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power-down state supply current 1 mA
+VBD supply current +VA = 5.25V, fs= 1MHz 1 mA
Power-up time 1 mSec
Invalid conversions after power up or 1 Numbers
reset
TEMPERATURE RANGE
Specified performance –40 125 °C
ELECTRICAL CHARACTERISTICS, ADS7958/59/60/61
+VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA= -40°C to 125°C, fsample = 1 MHz (unless otherwise
noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Range 1 0 Vref
Full-scale input span(1) V
Range 2 while 2Vref ≤+VA 0 2*Vref
VREF
Range 1 –0.20 +0.20
Absolute input range V
2*VREF
Range 2 while 2Vref ≤+VA –0.20 +0.20
Input capacitance 15 rF
Input leakage current TA= 125°C 61 nA
SYSTEM PERFORMANCE
Resolution 8 Bits
No missing codes 8 Bits
Integral linearity –0.3 ±0.1 0.3 LSB(2)
Differential linearity –0.3 ±0.1 0.3 LSB
Offset error(3) –0.5 ±0.2 0.5 LSB
Range 1 –0.6 ±0.1 0.6
Gain error LSB
Range 2 ±0.1
SAMPLING DYNAMICS
Conversion time 20 MHz SCLK 800 nSec
Acquisition time 325 nSec
Maximum throughput rate 20 MHz SCLK 1.0 MHz
Aperture delay 5 nsec
Step response 150 nsec
Over voltage recovery 150 nsec
DYNAMIC CHARACTERISTICS
Total harmonic distortion(4) 100 kHz –75 dB
Signal-to-noise ratio 100 kHz 49 dB
Signal-to-noise + distortion 100 kHz 49
Spurious free dynamic range 100 kHz –78 dB
Full power bandwidth At –3 dB 47 MHz
(1) Ideal input span; does not include gain or offset error.
(2) LSB means Least Significant Bit.
(3) Measured relative to an ideal full-scale input
(4) Calculated on the first nine harmonics of the input frequency.
8Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
ELECTRICAL CHARACTERISTICS, ADS7958/59/60/61 (continued)
+VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA= -40°C to 125°C, fsample = 1 MHz (unless otherwise
noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Any off-channel with 100kHz, Full-scale input to –95
channel being sampled with DC input.
Channel-to-channel crosstalk dB
From previously sampled to channel with 100kHz,
Full-scale input to channel being sampled with DC –85
input.
ETERNAL REFERENCE INPUT
Vref reference voltage at REFP 2.0 2.5 3.0 V
Reference resistance 100 kΩ
ALARM SETTING
Higher threshold range 000 FF Hex
Lower threshold range 000 FF Hex
DIGITAL INPUT/OUTPUT
Logic family CMOS
VIH 0.7*(+VBD)
VIL +VBD = 5 V 0.8
Logic level VIL +VBD = 3 V 0.4 V
VOH At Isource = 200 mA Vdd-0.2
VOL At Isink = 200 mA 0.4
Data format MSB First
POWER SUPPLY REQUIREMENTS
+VA supply voltage 2.7 3.3 5.25 V
+VBD supply voltage 1.7 3.3 5.25 V
At +VA = 2.7 to 3.6 V and 1MHz throughput 1.8 mA
At +VA = 2.7 to 3.6 V static state 1.05 mA
Supply current (normal mode) At +VA = 4.7 to 5.25 V and 1 MHz throughput 2.3 3 mA
At +VA = 4.7 to 5.25 V static state 1.1 1.5 mA
Power-down state supply current 1 mA
+VBD supply current +VA = 5.25V, fs= 1MHz 1 mA
Power-up time 1 mSec
Invalid conversions after power up or 1 Numbers
reset
TEMPERATURE RANGE
Specified performance –40 125 °C
TIMING REQUIREMENTS (see Figure 45,Figure 46,Figure 47, and Figure 48)
All specifications typical at –40°C to 125°C, +VA = 2.7 V to 5.25 V (unless otherwise specified)
PARAMETER TEST CONDITIONS(1) (2) MIN TYP MAX UNIT
+VBD = 1.8 V 16
tconv Conversion time +VBD = 3 V 16 SCLK
+VBD = 5 V 16
+VBD = 1.8 V 40
Minimum quiet sampling time needed from bus
tq+VBD = 3 V 40 ns
3-state to start of next conversion +VBD = 5 V 40
(1) 1.8V specifications apply from 1.7V to 1.9V, 3V specifications apply from 2.7V to 3.6V, 5V specifications apply from 4.75V to 5.25V.
(2) With 50-pF load
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
TIMING REQUIREMENTS (see Figure 45,Figure 46,Figure 47, and Figure 48) (continued)
All specifications typical at –40°C to 125°C, +VA = 2.7 V to 5.25 V (unless otherwise specified)
PARAMETER TEST CONDITIONS(1) (2) MIN TYP MAX UNIT
+VBD = 1.8 V 38
td1 Delay time, CS low to first data (DO–15) out +VBD = 3 V 27 ns
+VBD = 5 V 17
+VBD = 1.8 V 8
tsu1 Setup time, CS low to first rising edge of SCLK +VBD = 3 V 6 ns
+VBD = 5 V 4
+VBD = 1.8 V 35
td2 Delay time, SCLK falling to SDO next data bit valid +VBD = 3 V 27 ns
+VBD = 5 V 17
+VBD = 1.8 V 7
th1 Hold time, SCLK falling to SDO data bit valid +VBD = 3 V 5 ns
+VBD = 5 V 3
+VBD = 1.8 V 26
td3 Delay time, 16th SCLK falling edge to SDO 3-state +VBD = 3 V 22 ns
+VBD = 5 V 13
+VBD = 1.8 V 2
tsu2 Setup time, SDI valid to rising edge of SCLK +VBD = 3 V 3 ns
+VBD = 5 V 4
+VBD = 1.8 V 12
th2 Hold time, rising edge of SCLK to SDI valid +VBD = 3 V 10 ns
+VBD = 5 V 6
+VBD = 1.8 V 20
tw1 Pulse duration CS high +VBD = 3 V 20 ns
+VBD = 5 V 20
+VBD = 1.8 V 24
td4 Delay time CS high to SDO 3-state +VBD = 3 V 21 ns
+VBD = 5 V 12
+VBD = 1.8 V 20
twh Pulse duration SCLK high +VBD = 3 V 20 ns
+VBD = 5 V 20
+VBD = 1.8 V 20
twl Pulse duration SCLK low +VBD = 3 V 20 ns
+VBD = 5 V 20
+VBD = 1.8 V 20
Frequency SCLK +VBD = 3 V 20 MHz
+VBD = 5 V 20
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Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
1 30
2
3
4
5
6
7
8
9
10
11
12
13
14
15
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ADS7950
ADS7954
ADS7958
GPIO2
GPIO3
REFM
REFP
+VA
AGND
MXO
AINP
AINM
AGND
NC
CH3
NC
CH2
NC
GPIO1
GPIO0
+VBD
BDGND
SDO
SDI
SCLK
CS
AGND
+VA
CH0
NC
CH1
NC
NC
1 30
2
3
4
5
6
7
8
9
10
11
12
13
14
15
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ADS7951
ADS7955
ADS7959
GPIO2
GPIO3
REFM
REFP
+VA
AGND
MXO
AINP
AINM
AGND
CH7
CH6
CH5
CH4
NC
GPIO1
GPIO0
+VBD
BDGND
SDO
SDI
SCLK
CS
AGND
+VA
CH0
CH1
CH2
CH3
NC
1 38
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
ADS7952
ADS7956
ADS7960
GPIO2
GPIO3
REFM
REFP
+VA
AGND
MXO
AINP
AINM
AGND
NC
NC
NC
NC
CH11
CH10
CH9
CH8
AGND
GPIO1
GPIO0
+VBD
BDGND
SDO
SDI
SCLK
CS
AGND
+VA
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AGND
1 38
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
ADS7953
ADS7957
ADS7961
GPIO2
GPIO3
REFM
REFP
+VA
AGND
MXO
AINP
AINM
AGND
CH15
CH14
CH13
CH12
CH11
CH10
CH9
CH8
AGND
GPIO1
GPIO0
+VBD
BDGND
SDO
SDI
SCLK
CS
AGND
+VA
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AGND
1
8
916
32 25
24
17
AGND
AINM
AINP
MXO
CH15
CH12
CH13
CH14
SCLK
+VA
AGND
CS
CH0
CH3
CH2
CH1
CH11
CH10
CH9
CH8
CH7
CH6
CH5
CH4
+VA
REFP
REFM
GPIO
+VBD
BDGND
SDO
SDI
ADS7953/
ADS7957/
ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
DEVICE INFORMATION
PIN CONFIGURATION (TOP VIEW)
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 11
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ADS7959, ADS7960, ADS7961
1
8
916
32 25
24
17
AGND
AINM
AINP
MXO
NC
CH10
CH11
NC
SCLK
+VA
AGND
CS
NC
CH1
CH0
NC
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
+VA
REFP
REFM
GPIO
+VBD
BDGND
SDO
SDI
ADS7952/
ADS7956/
ADS7960
1
7
24
18
+VA
AINP
MXO
AGND
AINM
CH7
SDI
AGND
CS
SCLK
+VA
CH0
CH6
CH5
CH4
CH3
CH2
CH1
REFP
REFM
GPIO
+VBD
BDGND
SDO
ADS7951/
ADS7955/
ADS7959
613
19
12
1
7
24
18
+VA
AINP
MXO
AGND
AINM
NC
SDI
AGND
CS
SCLK
+VA
NC
NC
CH3
CH2
CH1
CH0
NC
REFP
REFM
GPIO
+VBD
BDGND
SDO
ADS7950/
ADS7954/
ADS7958
613
19
12
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
TERMINAL FUNCTIONS - TSSOP PACKAGES
DEVICE NAME
ADS7953 ADS7952 ADS7951 ADS7950
ADS7957 ADS7956 ADS7955 ADS7954 PIN NAME I/O FUNCTION
ADS7961 ADS7960 ADS7959 ADS7958
PIN NO.
REFERENCE
4 4 4 4 REFP I Reference input
3 3 3 3 REFM I Reference ground
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Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
TERMINAL FUNCTIONS - TSSOP PACKAGES (continued)
DEVICE NAME
ADS7953 ADS7952 ADS7951 ADS7950
ADS7957 ADS7956 ADS7955 ADS7954 PIN NAME I/O FUNCTION
ADS7961 ADS7960 ADS7959 ADS7958
PIN NO.
ADC ANALOG INPUT
8 8 8 8 AINP I Signal input to ADC
9 9 9 9 AINM I ADC input ground
MULTIPLEXER
7 7 7 7 MXO O Multiplexer output
28 28 20 20 Ch0 I Analog channels for multiplexer
27 27 19 18 Ch1 I
26 26 18 14 Ch2 I
25 25 17 12 Ch3 I
24 24 14 - Ch4 I
23 23 13 - Ch5 I
22 22 12 - Ch6 I
21 21 11 - Ch7 I
18 18 - - Ch8 I
17 17 - - Ch9 I
16 16 - - Ch10 I
15 15 - - Ch11 I
14 - - - Ch12 I
13 - - - Ch13 I
12 - - - Ch14 I
11 - - - Ch15 I
DIGITAL CONTROL SIGNALS
31 31 23 23 CS I Chip select input
32 32 24 24 SCLK I Serial clock input
33 33 25 25 SDI I Serial data input
34 34 26 26 SDO O Serial data output
GENERAL PURPOSE INPUTS / OUTPUTS: These pins have programmable dual functionality. Refer to Table 8 for functionality
programming
37 37 29 29 GPIO0 I/O General purpose input or output
High alarm or O Active high output indicating high alarm or high/low
High/Low alarm depending on programming
alarm
38 38 30 30 GPIO1 I/O General purpose input or output
Low alarm O Active high output indicating low alarm
1 1 1 1 GPIO2 I/O General purpose input or output
Range I Selects range: High -> Range 2 / Low -> Range 1
2 2 2 2 GPIO3 I/O General purpose input or output
PD I Active low power down input
POWER SUPPLY AND GROUND
5, 29 5, 29 5, 21 5, 21 +VA — Analog power supply
6, 10, 19, 6, 10, 19, 6, 10, 22 6, 10, 22 AGND — Analog ground
20, 30 20, 30
36 36 28 28 +VBD — Digital I/O supply
35 35 27 27 BDGND — Digital ground
NC PINS
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Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
TERMINAL FUNCTIONS - TSSOP PACKAGES (continued)
DEVICE NAME
ADS7953 ADS7952 ADS7951 ADS7950
ADS7957 ADS7956 ADS7955 ADS7954 PIN NAME I/O FUNCTION
ADS7961 ADS7960 ADS7959 ADS7958
PIN NO.
— 11, 12, 13, 15, 16 11, 13, 15, — — Pins internally not connected, do not float these pins
14 16, 17, 19
TERMINAL FUNCTIONS - QFN PACKAGES
DEVICE NAME
ADS7953 ADS7952 ADS7951 ADS7950
ADS7957 ADS7956 ADS7955 ADS7954 PIN NAME I/O FUNCTION
ADS7961 ADS7960 ADS7959 ADS7958
PIN NO.
REFERENCE
31 31 24 24 REFP I Reference input
30 30 23 23 REFM I Reference ground
ADC ANALOG INPUT
3 3 4 4 AINP I Signal input to ADC
4 4 5 5 AINM I ADC input ground
MULTIPLEXER
2 2 3 3 MXO O Multiplexer output
20 18 13 11 Ch0 I Analog-input channels for multiplexer
19 17 12 10 Ch1 I
18 16 11 9 Ch2 I
17 15 10 8 Ch3 I
16 14 9 - Ch4 I
15 13 8 - Ch5 I
14 12 7 - Ch6 I
13 11 6 - Ch7 I
12 10 - - Ch8 I
11 9 - - Ch9 I
10 8 - - Ch10 I
9 7 - - Ch11 I
8 - - - Ch12 I
7 - - - Ch13 I
6 - - - Ch14 I
5 - - - Ch15 I
DIGITAL CONTROL SIGNALS
23 23 16 16 CS I Chip select input
24 24 17 17 SCLK I Serial clock input
25 25 18 18 SDI I Serial data input
26 26 19 19 SDO O Serial data output
GENERAL PURPOSE INPUT / OUTPUT: This pin has programmable dual functionality. Refer to Table 8 for functionality programming
29 29 22 22 GPIO0 I/O General purpose input or output
High alarm or O Active high output indicating high alarm or high/low
High/Low alarm depending on programming
alarm
POWER SUPPLY AND GROUND
21, 32 21, 32 1, 14 1, 14 +VA — Analog power supply
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Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
TERMINAL FUNCTIONS - QFN PACKAGES (continued)
DEVICE NAME
ADS7953 ADS7952 ADS7951 ADS7950
ADS7957 ADS7956 ADS7955 ADS7954 PIN NAME I/O FUNCTION
ADS7961 ADS7960 ADS7959 ADS7958
PIN NO.
1, 22 1, 22 2, 15 2, 15 AGND — Analog ground
28 28 21 21 +VBD — Digital I/O supply
27 27 20 20 BDGND — Digital ground
NC PINS
— 5, 6, 19, — 6, 7, 12, 13 — — Pins internally not connected, do not float these pins
20
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ADS7959, ADS7960, ADS7961
2
2.2
2.4
2.6
2.8
3
3.2
3.4
-40 15 70 125
T -Free-AirTemperature-°C
A
+VA -SupplyCurrent-mA
f =1MSPS,
V =5.5V
S
DD
1
1.5
2
2.5
3
3.5
2.7 3.4 4.1 4.8 5.5
+VA -SupplyVoltage-V
+VA -SupplyCurrent-mA
f =1MSPS,
T =25°C
S
A
0.9
1
1.1
1.2
1.3
1.4
1.5
2.7 3.4 4.1 4.8 5.5
+VA -SupplyCurrent-mA
+VA -SupplyVoltage-V
T =25°C
A
0
0.5
1
1.5
2
2.5
0 100 200 300 400 500
WithPowerdown,
T =25°C
A
5V
2.7V
+VA -SupplyCurrent-mA
f -SampleRate-KSPS
S
0
0.5
1
1.5
2
2.5
0 200 400 600 800 1000
f -SampleRate-KSPS
S
5V
2.7V
NoPowerdown,
T =25°C
A
+VA -SupplyCurrent-mA
1.07
1.075
1.08
1.085
1.09
1.095
1.1
1.105
1.11
1.115
-40 15 70 125
T -Free-AirTemperature-°C
A
+VA -SupplyCurrent-mA
V =5.5V
DD
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
TYPICAL CHARATERISTICS (all ADS79XX Family Devices)
SUPPLY CURRENT STATIC SUPPLY CURRENT SUPPLY CURRENT
vs vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE FREE-AIR TEMPERATURE
Figure 1. Figure 2. Figure 3.
STATIC SUPPLY CURRENT SUPPLY CURRENT SUPPLY CURRENT
vs vs vs
FREE-AIR TEMPERATURE SAMPLE RATE SAMPLE RATE
Figure 4. Figure 5. Figure 6.
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ADS7959, ADS7960, ADS7961
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
2.7 3.2 3.7 4.2 4.7 5.2
DNL -DifferentialNonlinearity-LSBs
DNL max
DNL min
5.5
+VA -SupplyVoltage-V
f =1MSPS,
T =25°C
S
A
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
-40 15 70 125
DNL max
DNL min
T -Free-AirTemperature-°C
A
DNL -DifferentialNonlinearity-LSBs
+VA =5V,
+VBD=5V,
f =1MSPS
S
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
-40 15 70 125
INL max
INL min
+VA =5V,
+VBD=5V,
f =1MSPS
S
INL -IntegralNonlinearity-LSBs
T -Free-AirTemperature-°C
A
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.7 3.4 4.1 4.8 5.5
OffsetError-LSBs
+VA -SupplyVoltage-V
+VBD=1.8V,
f =1MSPS,
T =25°C
S
A
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.5
+VBD-InteraceSupply-V
OffsetError-LSBs
+VA =5.5V,
f =1MSPS,
T =25°C
S
A
5.3
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.5
+VBD-InteraceSupply-V
GainError-LSBs
+VA =5.5V,
f =1MSPS,
T =25°C
S
A
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
2.7 3.4 4.1 4.8 5.5
GainError-LSBs
+VA -SupplyVoltage-V
+VBD=1.8V,
f =1MSPS,
T =25°C
S
A
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
-40 15 70 125
T -Free-AirTemperature-°C
A
OffsetError-LSBs
+VA =5.5V,
+VBD=1.8V,
f =1MSPS
S
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
TYPICAL CHARACTERISTICS (12-Bit Devices Only)
Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves
DIFFERENTIAL NONLINEARITY INTEGRAL NONLINEARITY DIFFERENTIAL NONLINEARITY
vs vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE FREE-AIR TEMPERATURE
Figure 7. Figure 8. Figure 9.
INTEGRAL NONLINEARITY OFFSET ERROR OFFSET ERROR
vs vs vs
FREE-AIR TEMPERATURE SUPPLY VOLTAGE INTERFACE SUPPLY VOLTAGE
Figure 10. Figure 11. Figure 12.
GAIN ERROR GAIN ERROR OFFSET ERROR
vs vs vs
SUPPLY VOLTAGE INTERFACE SUPPLY VOLTAGE FREE-AIR TEMPERATURE
Figure 13. Figure 14. Figure 15.
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
-40 15 70 125
+VA =5.5V,
+VBD=1.8V,
f =1MSPS
S
GainError-LSBs
T -Free-AirTemperature-°C
A
69
69.5
70
70.5
71
71.5
72
2.7 3.4 4.1 4.8 5.5
SNR-Signal-to-NoiseRatio-dB
+VA -SupplyVoltage-V
+VBD=3V,
f =1MSPS,
f =100kHz
T =25°C
S
IN
A
69
69.5
70
70.5
71
71.5
72
2.7 3.4 4.1 4.8 5.5
SINAD-Signal-to-NoiseandDistortion-dB
+VA -SupplyVoltage-V
+VBD=3V,
f =1MSPS,
f =100kHz
T =25°C
S
IN
A
-90
-89
-88
-87
-86
-85
-84
-83
-82
-81
-80
2.7 3.4 4.1 4.8 5.5
THD-TotalHarmonicDistortion-
+VA -SupplyVoltage-V
+VBD=3V,
f =1MSPS,
f =100kHz
T =25°C
S
IN
A
80
81
82
83
84
85
86
87
88
89
90
2.7 3.4 4.1 4.8 5.5
SFDR-SpuriousFreeDynamicRange-dB
+VA -SupplyVoltage-V
+VBD=3V,
f =1MSPS,
f =100kHz
T =25°C
S
IN
A
69
69.5
70
70.5
71
71.5
72
-40 15 70 125
SNR-Signal-to-NoiseRatio-dB
T -Free-AirTemperature-°C
A
+VA =5V
+VBD=3V,
f =1MSPS,
f =100kHz
S
IN
69
69.5
70
70.5
71
71.5
72
-40 15 70 125
SINAD-Signal-to-NoiseandDistortion-dB
T -Free-AirTemperature-°C
A
+VA =5V
+VBD=3V,
f =1MSPS,
f =100kHz
S
IN
-90
-89
-88
-87
-86
-85
-84
-83
-82
-81
-80
-40 15 70 125
THD-TotalHarmonicDistortion-dB
T -Free-AirTemperature-°C
A
+VA =5V
+VBD=3V,
f =1MSPS,
f =100kHz
S
IN
80
81
82
83
84
85
86
87
88
89
90
-40 15 70 125
SFDR-SpuriousFreeDynamicRange-dB
T -Free-AirTemperature-°C
A
+VA =5V
+VBD=3V,
f =1MSPS,
f =100kHz
S
IN
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
TYPICAL CHARACTERISTICS (12-Bit Devices Only) (continued)
Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves
GAIN ERROR SIGNAL-TO-NOISE RATIO SIGNAL-TO-NOISE + DISTORTION
vs vs vs
FREE-AIR TEMPERATURE SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 16. Figure 17. Figure 18.
TOTAL HARMONIC DISTORTION SPURIOUS FREE DYNAMIC RANGE SIGNAL-TO-NOISE RATIO
vs vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE FREE-AIR TEMPERATURE
Figure 19. Figure 20. Figure 21.
SIGNAL-TO-NOISE + DISTORTION TOTAL HARMONIC DISTORTION SPURIOUS FREE DYNAMIC RANGE
vs vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 22. Figure 23. Figure 24.
18 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
69
69.5
70
70.5
71
71.5
72
72.5
73
10 30 50 70 90 110 130 150
f -InputFrequency-KHz
IN
SNR-Signal-to-NoiseRatio-dB
+VA =5V
+VBD=3V,
f =1MSPS,
T =25°C,
MXOShortedto AINP
S
A
69
69.5
70
70.5
71
71.5
72
72.5
73
10 30 50 70 90 110 130 150
f -InputFrequency-KHz
IN
SINAD-Signal-to-NoiseandDistortion-dB
+VA =5V
+VBD=3V,
f =1MSPS,
T =25°C,
MXOShortedto AINP
S
A
-90
-88
-86
-84
-82
-80
-78
-76
-74
-72
-70
10 30 50 70 90 110 130 150
f -InputFrequency-KHz
IN
THD-TotalHarmonicDistortion-dB
+VA =5V
+VBD=3V,
f =1MSPS,
T =25°C,
MXOShortedto AINP
S
A
70
75
80
85
90
95
100
10 30 50 70 90 110 130 150
f -InputFrequency-KHz
IN
SFDR-SpuriousFreeDynamicRange-dB
+VA =5V
+VBD=3V,
f =1MSPS,
T =25°C,
MXOShortedto AINP
S
A
69
69.5
70
70.5
71
71.5
72
20 40 60 80 100
10 W
f -InputFrequency-KHz
IN
SINAD-Signal-to-NoiseandDistortion-dB
100 W
500 W
1000 W
+VA =5V
+VBD=5V,
f =1MSPS,
T =25°C,
BufferBetweenMXOand AINP
S
A
-90
-88
-86
-84
-82
-80
-78
-76
-74
-72
-70
20 40 60 80 100
10 W100 W
500 W
1000 W
THD-TotalHarmonicDistortion-dB
f -InputFrequency-KHz
IN
+VA =5V
+VBD=5V,
f =1MSPS,
T =25°C,
BufferBetweenMXOand AINP
S
A
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
TYPICAL CHARACTERISTICS (12-Bit Devices Only) (continued)
Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves
SIGNAL-TO-NOISE RATIO SIGNAL-TO-NOISE + DISTORTION TOTAL HARMONIC DISTORTION
vs vs vs
INPUT FREQUENCY INPUT FREQUENCY INPUT FREQUENCY
Figure 25. Figure 26. Figure 27.
SIGNAL-TO-NOISE + DISTORTION TOTAL HARMONIC DISTORTION
vs vs
SPURIOUS FREE DYNAMIC RANGE INPUT FREQUENCY INPUT FREQUENCY
vs (Across Different Source Resistance (Across Different Source Resistance
INPUT FREQUENCY Values) Values)
Figure 28. Figure 29. Figure 30.
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ADS7959, ADS7960, ADS7961
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0 5 10 15
ChannelNumber
DNL max
DNL min
DNL -DifferentialNonlinearity-LSBs
+VA =5V,
+VBD=5V,
f =1MSPS
S
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0 5 10 15
ChannelNumber
INL -IntegralNonlinearity-LSBs
INL max
INL min
+VA =5V,
+VBD=5V,
f =1MSPS
S
70
72
74
76
78
80
82
84
86
88
90
20 40 60 80 100
SFDR-SpuriousFreeDynamicRange-dB
f -InputFrequency-KHz
IN
10 W
1000 W
+VA =5V
+VBD=5V,
f =1MSPS,
T =25°C,
BufferBetweenMXOand AINP
S
A
100 W
500 W
70
70.5
71
71.5
72
72.5
73
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
ChannelNumber
SNR-Signal-to-NoiseRatio-dB
+VA =5V,
+VBD=5V,
f =1MSPS
S
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
0 5 10 15 20
E -OffsetError-LSBs
O
ChannelNumber
+VA =5V,
+VBD=5V,
f =1MSPS
S
0
0.05
0.1
0.15
0.2
0.25
0 5 10 15 20
E -GainError-LSBs
G
ChannelNumber
+VA =5V,
+VBD=5V,
f =1MSPS
S
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
TYPICAL CHARACTERISTICS (12-Bit Devices Only) (continued)
Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY
(Across Different Source Resistance DIFFERENTIAL NONLINEARITY INTEGRAL NONLINEARITY VARIATION
Values) VARIATION ACROSS CHANNELS ACROSS CHANNELS
Figure 31. Figure 32. Figure 33.
OFFSET ERROR VARIATION ACROSS GAIN ERROR VARIATION ACROSS SIGNAL-TO-NOISE RATIO VARIATION
CHANNELS CHANNELS ACROSS CHANNELS
Figure 34. Figure 35. Figure 36.
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Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
70
70.5
71
71.5
72
72.5
73
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
ChannelNumber
SINAD-Signal-to-NoiseandDistortion-dB
+VA =5V,
+VBD=5V,
f =1MSPS
S
0
10
20
30
40
50
60
70
80
90
100
-40 -25 -10 5 20 35 50 65 80 95 110 125
AINP -LeakageCurrent-nA
V =1.25V
I
T -Free-AirTemperature-°C
A
V =2.5V
I
V =0V
I
+VA =5V,
+VBD=5V
0
5
10
15
20
25
0.25 0.5 0.75 1 1.25 1.5 1.75 2
TUEMax-LSB
NumberofDevices
0
5
10
15
20
25
-1.75
-1.5
-1.25
-1
-0.75
-0.5
-0.25
0
0.25
0.5
0.75
1
TUEMin-LSB
NumberofDevices
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
TYPICAL CHARACTERISTICS (12-Bit Devices Only) (continued)
Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves
CROSSTALK INPUT LEAKAGE CURRENT
SIGNAL-TO-NOISE + DISTORTION vs vs
VARIATION ACROSS CHANNELS INPUT FREQUENCY FREE-AIR TEMPERATURE
Figure 37. Figure 38. Figure 39.
TOTAL UNADJUSTED ERROR (TUE Max) TOTAL UNADJUSTED ERROR (TUE Min)
Figure 40. Figure 41.
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Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0 1024 2048 3072 4096
Code
DNL -LSBs
DNL
+VA =5V
+VBD=5V,
f =1MSPS,
T =25°C
S
A
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
01024 2048 3072 4096
Code
INL -LSBs
INL
+VA =5V,
+VBD=5V,
f =1MSPS
S
FFT
-160
-140
-120
-100
-80
-60
-40
-20
0
0100000 200000 300000 400000 500000
f-Frequency-Hz
Amplitude-dB
+VA =5V
+VBD=5V,
f =1MSPS,
f =100kHz
Npoints=16384
S
IN
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
TYPICAL CHARACTERISTICS (12-Bit Devices Only)
Figure 42.
Figure 43.
Figure 44.
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ADS7959, ADS7960, ADS7961
1 3 5 7 911 13 1516 35 7 9 11 13 1516
1
12 bitconversionresult
16 biti/pword 16 biti/pword
12 bitconversionresult
Sampling
instance
Muxchanchange
Analogi/
CS
SCLK
SDO
SDI
MUX
Acquisition
Conversion Conversionphase Conversionphase
GPO
GPI
Muxchanchange
Framen Framen+1
Datawritten (thrSDI) inframenDatawritten (thrSDI) inframen-1
GPIstatusislatchedinon CSfalling
edgeandtransferredtoSDOframen
tacq
tcnv
Top
4 bit
Top
4 bit
psettlingafterChanchange
Acquisitionphase
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
DETAILED DESCRIPTION
DEVICE OPERATION
The ADS7950 to ADS7961 are 12/10/8-bit multichannel devices. Figure 45,Figure 46,Figure 47, and Figure 48
show device operation timing. Device operation is controlled with CS, SCLK, and SDI. The device outputs its
data on SDO.
Figure 45. Device Operation Timing Diagram
Each frame begins with the falling edge of CS. With the falling edge of CS, the input signal from the selected
channel is sampled, and the conversion process is initiated. The device outputs data while the conversion is in
progress. The 16-bit data word contains a 4-bit channel address, followed by a 12-bit conversion result in MSB
first format. There is an option to read the GPIO status instead of the channel address. (Refer to Table 1,
Table 2, and Table 5 for more details.)
The device selects a new multiplexer channel on the second SCLK falling edge. The acquisition phase starts on
the fourteenth SCLK rising edge. On the next CS falling edge the acquisition phase will end, and the device
starts a new frame.
The TSSOP packaged device has four General Purpose IO (GPIO) pins, QFN versions have only one GPIO.
These four pins can be individually programmed as GPO or GPI. It is also possible to use them for preassigned
functions, refer to Table 10. GPO data can be written into the device through the SDI line. The device refreshes
the GPO data on the CS falling edge as per the SDI data written in previous frame.
Similarly the device latches GPI status on the CS falling edge and outputs the GPI data on the SDO line (if GPI
read is enabled by writing DI04=1 in the previous frame) in the same frame starting with the CS falling edge.
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
th 2
1 2 3 4 5 6 14 15 16
CS
SCLK
SDO
SDI
DO-
15
DO-
14
DO-
13
DO-
12
DO-11
MSB
DO-10
MSB-1
DO-0
LSB
DO-1
LSB+1
DO-2
LSB+2
DI-15 DI-14 DI-12 DI-11 DI-10 DI-2 DI-1 DI-0
a
tsu 1
td 1td 2th 1
tsu2
td 3
tw 1
tq
1/tthroughput (singleframe)
DI-13
1 2 3 4 5 6 14 15 16
CS\
SCLK
SDO
SDI
DO-
15
DO-
14
DO-
13
DO-
12
DO-11
MSB
DO-10
MSB-1
DO-0
-
DO-1
-
DO-2
LSB
DI-15 DI-14 DI-13 DI-12 DI-11 DI-10 DI-2 DI-1 DI-0
a
tsu1
td1 td2th1
tsu2
th2
td3
tw1
tq
1/t throughput (single frame)
CS
1 2 3 4 5 6 12 13 16
CS\
SCLK
SDO
SDI
DO-
15
DO-
14
DO-
13
DO-
12
DO-11
MSB
DO-10
MSB-1
DO-0
-
DO-3
-
DO-4
LSB
DI-15 DI-14 DI-13 DI-12 DI-11 DI-10 DI-4 DI-3 DI-0
a
tsu1
td1 td2th1
tsu2
th2
td3
tw1
tq
1/t throughput (single frame)
CS
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
Figure 46. Serial Interface Timing Diagram for 12-Bit Devices ( ADS7950/51/52/53)
Figure 47. Serial Interface Timing Diagram for 10-Bit Devices (ADS7954/55/56/57)
Figure 48. Serial Interface Timing Diagram for 8-Bit Devices (ADS7958/59/60/61)
The falling edge of CS clocks out DO-15 (first bit of the four bit channel address), and remaining address bits are
clocked out on every falling edge of SCLK until the third falling edge. The conversion result MSB is clocked out
on the 4th SCLK falling edge and LSB on the 15th/13th/11th falling edge respectively for 12/10/8-bit devices. On
the 16th falling edge of SCLK, SDO goes to the 3-state condition. The conversion ends on the 16th falling edge
of SCLK.
The device reads a sixteen bit word on the SDI pin while it outputs the data on the SDO pin. SDI data is latched
on every rising edge of SCLK starting with the 1st clock as shown in Figure 46,Figure 47, and Figure 48.
CS can be asserted (pulled high) only after 16 clocks have elapsed.
24 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
The device has two (high and low) programmable alarm thresholds per channel. If the input crosses these limits;
the device flags out an alarm on GPIO0/GPIO1 depending on the GPIO program register settings (refer to
Table 10). The alarm is asserted (under the alarm conditions) on the 12th falling edge of SCLK in the same
frame when a data conversion is in progress. The alarm output is reset on the 10th falling edge of SCLK in the
next frame.
The device offers a power-down feature to save power when not in use. There are two ways to powerdown the
device. It can be powered down by writing DI05 = 1 in the mode control register (refer to Table 1,Table 2, and
Table 5); in this case the device powers down on the 16th falling edge of SCLK in the next data frame. Another
way to powerdown the device is through GPIO in the case of the TSSOP packaged devices . GPIO3 can act as
the PD input (refer to Table 10, to assign this functionality to GPIO3). This is an asynchronous and active low
input. The device powers down instantaneously after GPIO3 (PD) = 0. The device will power up again on the CS
falling edge with DI05 = 0 in the mode control register and GPIO3 (PD) = 1.
CHANNEL SEQUENCING MODES
There are three modes for channel sequencing, namely Manual mode,Auto-1 mode,Auto-2 mode. Mode
selection is done by writing into the control register (refer to Table 1,Table 2, and Table 5). A new multiplexer
channel is selected on the second falling edge of SCLK (as shown in Figure 45) in all three modes.
Manual mode: When configured to operate in Manual mode, the next channel to be selected is programmed in
each frame and the device selects the programmed channel in the next frame. On powerup or after reset the
default channel is 'Channel-0' and the device is in Manual mode.
Auto-1 mode: In this mode the device scans pre-programmed channels in ascending order. A new multiplexer
channel is selected every frame on the second falling edge of SCLK. There is a separate ‘program register’ for
pre-programming the channel sequence. Table 3 and Table 4 show Auto-1 ‘program register’ settings.
Once programmed the device retains ‘program register’ settings until the device is powered down, reset, or
reprogrammed. It is allowed to exit and re-enter the Auto-1 mode any number of times without disturbing
‘program register’ settings.
The Auto-1 program register is reset to FFFF/FFF/FF/F hex for the 16/12/8/4 channel devices respectively upon
device powerup or reset; implying the device scans all channels in ascending order.
Auto-2 mode: In this mode the user can configure the program register to select the last channel in the scan
sequence. The device scans all channels from channel 0 up to and including the last channel in ascending order.
The multiplexer channel is selected every frame on the second falling edge of SCLK. There is a separate
‘program register’ for pre-programming of the last channel in the sequence (multiplexer depth). Table 6 lists the
‘Auto-2 prog’ register settings for selection of the last channel in the sequence.
Once programmed the device retains program register settings until the device is powered down, reset, or
reprogrammed. It is allowed to exit and re-enter Auto-2 mode any number of times, without disturbing the
‘program register’ settings.
On powerup or reset the bits D9-D6 of the Auto-2 program register are reset to F/B/7/3 hex for the 16/12/8/4
channel devices respectively; implying the device scans all channels in ascending order.
DEVICE PROGRAMMING AND MODE CONTROL
The following section describes device programming and mode control. These devices feature two types of
registers to configure and operate the devices in different modes. These registers are referred as ‘Configuration
Registers’. There are two types of ‘Configuration Registers’ namely ‘Mode control registers’ and ‘Program
registers’.
Mode Control Register
A ‘Mode control register’ is configured to operate the device in one of three channel sequencing modes, namely
Manual mode, Auto-1 Mode, Auto-2 Mode. It is also used to control user programmable features like range
selection, device power-down control, GPIO read control, and writing output data into the GPIO.
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ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
Program Registers
The 'Program registers’ are used for device configuration settings and are typically programmed once on
powerup or after device reset. There are different program registers such as ‘Auto-1 mode programming’ for
pre-programming the channel sequence, ‘Auto-2 mode programming’ for selection of the last channel in the
sequence, ‘Alarm programming’ for all 16 channels (or 12,8,4 channels depending on the device) and GPIO for
individual pin configuration as GPI or GPO or a pre-assigned function.
DEVICE POWER-UP SEQUENCE
The device power-up sequence is shown in Figure 49. Manual mode is the default power-up channel sequencing
mode and Channel-0 is the first channel by default. As explained previously, these devices offer Program
Registers to configure user programmable features like GPIO, Alarm, and to pre-program the channel sequence
for Auto modes. At ‘powerup or on reset’ these registers are set to the default values listed in Table 1 to
Table 10. It is recommended to program these registers on powerup or after reset. Once configured; the device
is ready to use in any of the three channel sequencing modes namely Manual, Auto-1, and Auto-2.
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ADS7959, ADS7960, ADS7961
Devicepoweruporreset
Deviceoperationinmanualmode,Channel0;
SDOInvalidinfirstframe
CS
Firstframe
CS
CS
CS
CS
Operationinmanualmode
CS
CS CS
Auto1registerprogram(note1)
Auto2registerprogram(note1)
Alarmregisterprogram(note1)
GPIOregisterprogram(note1)
Operationin Auto1mode Operationin Auto2mode
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
(1) The device continues its operation in Manual mode channel 0 through out the programming sequence and outputs
valid conversion results. It is possible to change channel, range, GPIO by inserting extra frames in between two
programming blocks. It is also possible to bypass any programming block if the user does not intent to use that
feature.
(2) It is possible to reprogram the device at any time during operation, regardless of what mode the device is in. During
programming the device continues its operation in whatever mode it is in and outputs valid data.
Figure 49. Device Power-Up Sequence
OPERATING IN MANUAL MODE
The details regarding entering and running in Manual channel sequencing mode are illustrated in Figure 50.
Table 1 lists the Mode Control Register settings for Manual mode in detail. Note that there are no Program
Registers for manual mode.
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ADS7959, ADS7960, ADS7961
Deviceoperationin Auto 1 or
Auto 2 mode
ChangetoManualmode?
* Sample: Samplesandconvertschannelselectedin ‘framen-1’
* Mux : Selectschannelincrementedfrompreviousframeasperautosequencethischannelwillbe
acquiredinthisframeandsampledatstartof ‘framen+1’
* Range: Asprogrammedin ‘framen-1’ . Appliestochannelselectedforacquisitionincurrentframe.
* SDI : Programmingfor ‘framen +1’
DI15..12 = 0001 binary …. Selectsmanualmode
DI11=1 enablesprogrammingof ‘rangeandGPIO’
DI10..7 = binaryaddressofchannel
DI6.. Asperrequiredrangeforchanneltobeselected
DI5=0 .. Nopowerdown
DI4..0… asperGPIOsettings
*SDO : DO15..0 address (orGPIOdata) & conversiondataofchannelselectedin ‘framen -1’
* GPIO :
O/P: latchedon CS fallingedgeasperDI3..0 writteninframen-1’
I/P: Inputstatuslatchedonfallingedgeof CSandtransferredseriallyonSDOinthesame
frame
No
Yes
CS
CS
Continueoperation in manualmode
CS
Frame: n-1
Frame: n
Request
forManual
mode
* Sample: Samplesandconvertschannelselectedin ‘framen’
* Mux : Selectschannelprogrammedin ‘framen’(Manualmode) thischannelwillbeacquiredinthis
frameandsampledatstartof ‘framen+2’
* Range: Asprogrammedin ‘framen’. Appliestochannelselectedforacquisitionincurrentframe.*
SDI : Programmingfor ‘framen+2’
DI15..12 = 0001 binary …. Tocontinueinmanualmode
DI11=1 enablesprogrammingof ‘rangeandGPIO’
DI10..7 = binaryaddressofchannel
DI6.. Asperrequiredrangeforchanneltobeselected
DI5=0 .. Nopowerdown
DI4..0… asperGPIOsettings
*SDO : DO15..0 address (orGPIOdata) & conversiondataofchannelselectedin ‘framen’
* GPIO :
O/P: latchedon CS fallingedgeasperDI3..0 writteninframe ‘n’
I/P: Inputstatuslatchedonfallingedgeof CS andtransferredseriallyonSDOinthesame
frame
CS
Frame:
n+1
Entryinto
Manual
Mode
* Sample: Samplesandconvertschannelselectedin ‘framen+1’
* Mux : Selectschannelprogrammedin ‘framen+1’ (Manualmode), thischannelwillbeacquiredin
thisframeandsampledatstartof ‘framen+3’
* Range: Asprogrammedin ‘framen+1’ . Appliestochannelselectedforacquisitionincurrentframe.*
SDI : Programmingfor ‘framen+3’
DI15..12 = 0001 binary …. Selectsmanualmode
DI11=1 enablesprogrammingof ‘rangeandGPIO’
DI10..7 = binaryaddressofchannel
DI6.. Asperrequiredrangeforchanneltobeselected
DI5=0 .. Nopowerdown
DI4..0… asperGPIOsettings
*SDO : DO15..0 address (orGPIOdata) & conversiondataofchannelselectedin ‘framen+1’
* GPIO :
O/P: latchedon CS fallingedgeasperDI3..0 writteninframen+1’
I/P: Inputstatuslatchedonfallingedgeof CSandtransferredseriallyonSDOinthesame
frame
CS
Frame:
n+2
Operation
inManual
mode
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
Figure 50. Entering and Running in Manual Channel Sequencing Mode
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ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
Table 1. Mode Control Register Settings for Manual Mode
DESCRIPTION
RESET
BITS LOGIC
STATE FUNCTION
STATE
DI15-12 0001 0001 Selects Manual Mode
DI11 0 1 Enables programming of bits DI06-00.
0 Device retains values of DI06-00 from the previous frame.
DI10-07 0000 This four bit data represents the address of the next channel to be selected in the next frame. DI10: MSB and
DI07: LSB. e.g. 0000 represents channel- 0, 0001 represents channel-1 etc.
DI06 0 0 Selects 2.5V i/p range (Range 1)
1 Selects 5V i/p range (Range 2)
DI05 0 0 Device normal operation (no powerdown)
1 Device powers down on 16th SCLK falling edge
DI04 0 SDO outputs current channel address of the channel on DO15..12 followed by 12 bit conversion
0result on DO11..00.
1 GPIO3-GPIO0 data (both input and output) is mapped onto DO15-DO12 in the order shown below.
Lower data bits DO11-DO00 represent 12-bit conversion result of the current channel.
DOI5 DOI4 DOI3 DOI2
GPIO3(1) GPIO2(1) GPIO1(1) GPIO0(1)
DI03-00 0000 GPIO data for the channels configured as output. Device will ignore the data for the channel which is configured
as input. SDI bit and corresponding GPIO information is given below
DI03 DI02 DI01 DI00
GPIO3(2) GPIO2(2) GPIO1(2) GPIO0(2)
(1) GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only.
(2) GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only.
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Device operation in Manual or
Auto-2 mode
Change to Auto -1 mode?
* Sample: Samplesandconvertschannelselectedin ‘framen -1’
* Mux : Selectschannelincrementedfrompreviousframeasper Auto -2 sequence, orchannel
programmedinpreviousframeincaseofmanualmode. Thischannelwillbeacquiredinthisframe
andsampledatstartof ‘framen +1’
* Range: Asprogrammedin ‘framen-1’ . Appliestochannelselectedforacquisitionincurrentframe.
* SDI : Programmingfor ‘framen+1’
DI15..12 = 0010 binary …. Selects Auto-1 mode
DI11=1 enablesprogrammingof ‘rangeandGPIO’
DI10 = x, Deviceautomaticallyresetschanneltolowestnumberin Auto -1 sequence.
DI6.. Asperrequiredrangeforchanneltobeselected
DI5=0 .. Nopowerdown
DI4..0… asperGPIOsettings
*SDO : DO15..0 address (orGPIOdata) & conversiondataofchannelselectedin ‘framen -1’
* GPIO :
O/P: latchedon CS fallingedgeasperDI 3..0 writteninframen-1’
I/P: Inputstatuslatchedonfallingedgeof CS andtransferredseriallyonSDOinthesame
frame
No
Yes
CS
CS
Continue operation in Auto -1 mode
CS
Frame: n-1
Frame: n
Request
for Auto-1
mode
* Sample: Samplesandconvertschannelselectedin ‘framen’
* Mux : Selectslowestchannel# in Auto-1 sequence; thischannelwillbeacquiredinthisframeand
sampledatstartof ‘framen+2’
* Range: Asprogrammedin ‘framen’. Appliestochannelselectedforacquisitionincurrentframe.
* SDI : Programmingfor ‘framen +2’
DI15..12 = 0010 binary …. Tocontinuein Auto -1 mode
DI11=1 enablesprogrammingof ‘rangeandGPIO’
DI10 =0, nottoresetchannelsequence
DI6.. Asperrequiredrangeforchanneltobeselected
DI5=0 .. Nopowerdown
DI4..0…asperGPIOsettings
*SDO : DO15..0 address (orGPIOdata) & conversiondataofchannelselectedin ‘framen’
* GPIO :
O/P: latchedon CS fallingedgeasperDI 3..0 writteninframe ‘n’
I/P: Inputstatuslatchedonfallingedgeof CS andtransferredseriallyonSDOinthesame
frame
CS
Frame:
n+1
Entryinto
Auto-1
Mode
* Sample: Samplesandconvertschannelselectedin ‘framen+1’(ie. Lowestchannel# in Auto-1
sequence)
* Mux : Selectsnexthigherchannelin Auto -1 sequence, thischannelwillbeacquiredinthisframe
andsampledatstartof ‘framen +3’
* Range: Asprogrammedin ‘framen+1’. Appliestochannelselectedforacquisitionincurrentframe.*
SDI : Programmingfor ‘framen+3’
DI15..12 = 0010 binary …. Tocontinuein Auto -1 mode
DI11=1 enablesprogrammingof ‘rangeandGPIO’
DI10 =0 nottoresetchannelsequence
DI6.. Asperrequiredrangeforchanneltobeselected
DI5=0 .. Nopowerdown
DI4..0…asperGPIOsettings
*SDO : DO15..0 address (orGPIOdata) & conversiondataofchannelselectedin ‘framen+1’
* GPIO :
O/P: latchedon CS fallingedgeasperDI3..0 writteninframen+1’
I/P: Inputstatuslatchedonfallingedgeof CS andtransferredseriallyonSDOinthesame
frame
CS
Frame:
n+2
Operation
in Auto-1
mode
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
OPERATING IN AUTO-1 MODE
The details regarding entering and running in Auto-1 channel sequencing mode are illustrated in the flowchart in
Figure 51.Table 2 lists the Mode Control Register settings for Auto-1 mode in detail.
Figure 51. Entering and Running in Auto-1 Channel Sequencing Mode
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ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
Table 2. Mode Control Register Settings for Auto-1 Mode
DESCRIPTION
RESET
BITS LOGIC
STATE FUNCTION
STATE
DI15-12 0001 0010 Selects Auto-1 Mode
DI11 0 1 Enables programming of bits DI10-00.
0 Device retains values of DI10-00 from previous frame.
DI10 0 1 The channel counter is reset to the lowest programmed channel in the Auto-1 Program Register
0 The channel counter increments every conversion (No reset)
DI09-07 000 xxx Do not care
DI06 0 0 Selects 2.5V i/p range (Range 1)
1 Selects 5V i/p range (Range 2)
DI05 0 0 Device normal operation (no powerdown)
1 Device powers down on the 16th SCLK falling edge
DI04 0 SDO outputs current channel address of the channel on DO15..12 followed by 12-bit conversion
0result on DO11..00.
1 GPIO3-GPIO0 data (both input and output) is mapped onto DO15-DO12 in the order shown below.
Lower data bits DO11-DO00 represent 12-bit conversion result of the current channel.
DO15 DO14 DO13 DO12
GPIO3(1) GPIO2(1) GPIO1(1) GPIO0(1)
DI03-00 0000 GPIO data for the channels configured as output. Device will ignore the data for the channel which is configured
as input. SDI bit and corresponding GPIO information is given below
DI03 DI02 DI01 DI00
GPIO3(2) GPIO2(2) GPIO1(2) GPIO0(2)
(1) GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only.
(2) GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only.
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ADS7959, ADS7960, ADS7961
Deviceinanyoperationmode
Yes
No
CS
CS
Entryinto Auto 1
register
programming
sequence
CS
Auto 1 register
programming
Program Auto1register?
SDI:DI15..12=1000
(Deviceenters Auto1programmingsequence)
SDI:DI15..0aspertables4,5
Endof Auto1registerprogramming
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
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The Auto-1 Program Register is programmed (once on powerup or reset) to pre-select the channels for the
Auto-1 sequence. Auto-1 Program Register programming requires two CS frames for complete programming. In
the first CS frame the device enters the Auto-1 register programming sequence and in the second frame it
programs the Auto-1 Program Register. Refer to Table 2,Table 3, and Table 4 for complete details.
NOTE: The device continues its operation in selected mode during programming. SDO is valid, however it is not possible to
change the range or write GPIO data into the device during programming.
Figure 52. Auto-1 Register Programming Flowchart
Table 3. Program Register Settings for Auto-1 Mode
DESCRIPTION
RESET
BITS STATE LOGIC STATE FUNCTION
FRAME 1
DI15-12 NA 1000 Device enters Auto-1 program sequence. Device programming is done in the next frame.
DI11-00 NA Do not care
FRAME 2
DI15-00 All 1s 1 (individual bit) A particular channel is programmed to be selected in the channel scanning sequence. The
channel numbers are mapped one-to-one with respect to the SDI bits; e.g.
DI15 →Ch15, DI14 →Ch14 … DI00 →Ch00
A particular channel is programmed to be skipped in the channel scanning sequence. The
0 (individual bit) channel numbers are mapped one-to-one with respect to the SDI bits; e.g.
DI15 →Ch15, DI14 →Ch14 … DI00 →Ch00
Table 4. Mapping of Channels to SDI Bits for 16,12,8,4 Channel Devices
Device(1) SDI BITS
DI15 DI14 DI13 DI12 DI11 DI10 DI09 DI08 DI07 DI06 DI05 DI04 DI03 DI02 DI01 DI00
16 Chan 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
12 Chan X X X X 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
8 Chan X X X X X X X X 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
4 Chan X X X X X X X X X X X X 1/0 1/0 1/0 1/0
(1) When operating in Auto-1 mode, the device only scans the channels programmed to be selected.
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DeviceoperationinManualor
Auto -1 mode
Changeto Auto-2 mode ?
* Sample: Samples andconverts channel selectedin ‘framen-1’
* Mux : Selects channel incremented fromprevious frameas per Auto-1 sequence, orchannel
programmedinprevious frameincaseofmanualmode.. This channel willbeacquired inthis frame
andsampled atstart of ‘framen +1’
* Range: As programmedin ‘framen-1’. Applies tochannel selectedforacquisitionincurrent frame.
* SDI : Programmingfor ‘framen+1’
DI15..12 = 0011 binary …. Selects Auto-2 mode
DI11=1 enables programmingof ‘rangeandGPIO’
DI10 = x, Deviceautomatically resets tochannel 0.
DI6.. As perrequiredrangeforchannel tobeselected
DI5=0 .. Nopowerdown
DI4..0… as perGPIOsettings
*SDO : DO15..0 address(orGPIOdata) & conversion dataofchannel selectedin ‘framen -1’
* GPIO :
O/P: latched on CS fallingedgeas perDI3..0 writteninframen -1’
I/P: Inputstatus latched onfallingedgeof CS andtransferred serially onSDOinthesame
frame
No
Yes
CS
CS
Continueoperationin Auto-2 mode
CS
Frame: n-1
Frame: n
Request
for Auto-2
mode
* Sample: Samples andconverts channel selectedin ‘framen’
* Mux : Selects channel0 (Auto-2 sequencealways starts withCh -0); this channel willbeacquired
inthis frameandsampled atstart of ‘framen+2’
* Range: As programmedin ‘framen’. Applies tochannel selectedforacquisitionincurrent frame.
* SDI : Programmingfor ‘framen +2’
DI15..12 = 0011 binary …. Tocontinue in Auto-2 mode
DI11=1 enables programmingof ‘rangeandGPIO’
DI10 =0, nottoreset channel sequence
DI6.. As perrequiredrangeforchannel tobeselected
DI5=0 .. Nopowerdown
DI4..0… as perGPIOsettings
*SDO : DO15..0 address(orGPIOdata) & conversion dataofchannel selectedin ‘framen’
* GPIO :
O/P: latched on CS fallingedgeas perDI 3..0 writteninframe ‘n’
I/P: Inputstatus latched onfallingedgeof CS andtransferred serially onSDOinthesame
frame
CS
Frame:
n+1
Entry into
Auto-2
Mode
* Sample: Samples andconverts channel 0
* Mux : Selects next higherchannel in Auto -2 sequence, this channel willbeacquired inthis frame
andsampled atstart of ‘framen+3’
* Range: As programmedin ‘framen+1’. Applies tochannel selectedforacquisitionincurrent frame.*
SDI : Programmingfor ‘framen+3’
DI15..12 = 0011 binary …. Tocontinue in Auto-2 mode
DI11=1 enables programmingof ‘rangeandGPIO’
DI10 =0 nottoreset channel sequence
DI6.. As perrequiredrangeforchannel tobeselected
DI5=0 .. Nopowerdown
DI4..0… as perGPIOsettings
*SDO : DO15..0 address(orGPIOdata) & conversion dataofchannel selectedin ‘framen+1’
* GPIO :
O/P: latched on CS fallingedgeas perDI 3..0 writteninframen+1’
I/P: Inputstatus latched onfallingedgeof CS andtransferred serially onSDOinthesame
frame
CS
Frame:
n+2
Operation
in Auto-2
mode
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
OPERATING IN AUTO-2 MODE
The details regarding entering and running in Auto-2 channel sequencing mode are illustrated in Figure 53.
Table 5 lists the Mode Control Register settings for Auto-2 mode in detail.
Figure 53. Entering and Running in Auto-2 Channel Sequencing Mode
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 33
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
Deviceinanyoperationmode
Yes
No
CS
CS
Auto 2 register
programming
Program Auto2register?
SDI:Di15..12=1001
DI9..6=binaryaddressoflastchannelinthesequence
refertables6
Endof Auto2registerprogramming
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
Table 5. Mode Control Register Settings for Auto-2 Mode
DESCRIPTION
RESET
BITS LOGIC
STATE FUNCTION
STATE
DI15-12 0001 0011 Selects Auto-2 Mode
DI11 0 1 Enables programming of bits DI10-00.
0 Device retains values of DI10-00 from the previous frame.
DI10 0 1 Channel number is reset to Ch-00.
0 Channel counter increments every conversion.(No reset).
DI09-07 000 xxx Do not care
DI06 0 0 Selects 2.5V i/p range (Range 1)
1 Selects 5V i/p range (Range 2)
DI05 0 0 Device normal operation (no powerdown)
1 Device powers down on the 16th SCLK falling edge
DI04 0 SDO outputs the current channel address of the channel on DO15..12 followed by the 12-bit
0conversion result on DO11..00.
1 GPIO3-GPIO0 data (both input and output) is mapped onto DO15-DO12 in the order shown below.
Lower data bits DO11-DO00 represent the 12-bit conversion result of the current channel.
DO15 DO14 DO13 DO12
GPIO3(1) GPIO2(1) GPIO1(1) GPIO0(1)
DI03-00 0000 GPIO data for the channels configured as output. Device ignores data for the channel which is configured as
input. SDI bit and corresponding GPIO information is given below
DI03 DI02 DI01 DI00
GPIO3(1) GPIO2(1) GPIO1(1) GPIO0(1)
(1) GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only.
The Auto-2 Program Register is programmed (once on powerup or reset) to pre-select the last channel (or
sequence depth) in the Auto-2 sequence. Unlike Auto-1 Program Register programming, Auto-2 Program
Register programming requires only 1 CS frame for complete programming. See Figure 54 and Table 6 for
complete details.
NOTE: The device continues its operation in the selected mode during programming. SDO is valid, however it is not possible
to change the range or write GPIO data into the device during programming.
Figure 54. Auto-2 Register Programming Flowchart
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Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
Table 6. Program Register Settings for Auto-2 Mode
DESCRIPTION
RESET
BITS LOGIC
STATE FUNCTION
STATE
DI15-12 NA 1001 Auto-2 program register is selected for programming
DI11-10 NA Do not care
DI09-06 NA aaaa This 4-bit data represents the address of the last channel in the scanning sequence. During device
operation in Auto-2 mode, the channel counter starts at CH-00 and increments every frame until it
equals “aaaa”. The channel counter roles over to CH-00 in the next frame.
DI05-00 NA Do not care
CONTINUED OPERATION IN A SELECTED MODE
Once a device is programmed to operate in one of the modes, the user may want to continue operating in the
same mode. Mode Control Register settings to continue operating in a selected mode are detailed in Table 7.
Table 7. Continued Operation in a Selected Mode
DESCRIPTION
RESET
BITS LOGIC
STATE FUNCTION
STATE
DI15-12 0001 0000 The device continues to operate in the selected mode. In Auto-1 and Auto-2 modes the channel
counter increments normally, whereas in the Manual mode it continues with the last selected
channel. The device ignores data on DI11-DI00 and continues operating as per the previous
settings. This feature is provided so that SDI can be held low when no changes are required in the
Mode Control Register settings.
DI11-00 All '0' Device ignores these bits when DI15-12 is set to 0000 logic state
PROGRAMMING ALARM THRESHOLDS
There are two Alarm Program Registers per channel, one for setting the high alarm threshold and the other for
setting the low alarm threshold. For ease of programming, two alarm programming registers per channel,
corresponding to four consecutive channels, are assembled into one group (a total eight registers). There are
four such groups for 16 channel devices and 3/2/1 such groups for 12/8/4 channel devices respectively. The
grouping of the various channels for each device in the ADS79XX family is listed in Table 8. The details
regarding programming the alarm thresholds are illustrated in the flowchart in Figure 55.Table 9 lists the details
regarding the Alarm Program Register settings.
Table 8. Grouping of Alarm Program Registers
GROUP NO. REGISTERS APPLICABLE FOR DEVICE
0 High and low alarm for channel 0, 1, 2, and 3 ADS7953..50, ADS7957..54, ADS7961..58
1 High and low alarm for channel 4, 5, 6, and 7 ADS7953..51, ADS7957..55, ADS7961..59
2 High and low alarm for channel 8, 9, 10, and 11 ADS7953 and 52, ADS7957 and 56, ADS7961 and 60
3 High and low alarm for channel 12, 13, 14, and 15 ADS7953, ADS7957, ADS7961
Each alarm group requires 9 CS frames for programming their respective alarm thresholds. In the first frame the
device enters the programming sequence and in each subsequent frame it programs one of the registers from
the group. The device offers a feature to program less than eight registers in one programming sequence. The
device exits the alarm threshold programming sequence in the next frame after it encounters the first ‘Exit Alarm
Program’ bit high.
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 35
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
Deviceinanyoperationmode
Programalarmthresholds?
Programanothergroupoffourchannels?
Endofalarmprograming
Yes
Yes
No
No
No Yes
CS
CS
Entryintoalarm
register
programming
sequence
CS
Alarmregister
programming
sequence
SDI:DI15..12=11XX
(xxindicatesgroupoffourchannels;refertable8)
Deviceentersalarmregisterprogrammingsequence
SDI:DI15..0aspertable8(programalarmthresholds)
DI12=1?
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
NOTE: The device continues its operation in selected mode during programming. SDO is valid, however it is not possible to
change the range or write GPIO data into the device during programming.
Figure 55. Alarm Program Register Programming Flowchart
Table 9. Alarm Program Register Settings
DESCRIPTION
BITS RESET STATE LOGIC FUNCTION
STATE
FRAME 1
DI15-12 NA 1100 Device enters ‘alarm programming sequence’ for group 0
1101 Device enters ‘alarm programming sequence’ for group 1
1110 Device enters ‘alarm programming sequence’ for group 2
1111 Device enters ‘alarm programming sequence’ for group 3
Note: DI15-12 = 11bb is the alarm programming request for group bb. Here ‘bb’ represents the alarm programming group number in binary
format.
DI11-14 NA Do not care
FRAME 2 AND ONWARDS
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Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
Table 9. Alarm Program Register Settings (continued)
DESCRIPTION
BITS RESET STATE LOGIC FUNCTION
STATE
DI15-14 NA cc Where “cc” represents the lower two bits of the channel number in binary format. The device
programs the alarm for the channel represented by the binary number “bbcc”. Note that “bb” is
programmed in the first frame.
DI13 NA 1 High alarm register selection
0 Low alarm register selection
DI12 NA 0 Continue alarm programming sequence in next frame
1 Exit Alarm Programming in the next frame. Note: If the alarm programming sequence is not
terminated using this feature then the device will remain in the alarm programming sequence
state and all SDI data will be treated as alarm thresholds.
DI11-10 NA xx Do not care
DI09-00 All ones for high This 10-bit data represents the alarm threshold. The 10-bit alarm threshold is compared with the upper 10-bit
alarm register word of the 12-bit conversion result. The device sets off an alarm when the conversion result is higher (High
and all zeros for Alarm) or lower (Low Alarm) than this number. For 10-bit devices, all 10 bits of the conversion result are
low alarm register compared with the set threshold. For 8-bit devices, all 8 bits of the conversion result are compared with DI09
to DI02 and DI00, 01 are 'do not care'.
PROGRAMMING GPIO REGISTERS
NOTE
GPIO 1 to 3 are available only in TSSOP packaged devices. The QFN device offers
'GPIO 0' only. As a result, all references related to 'GPIO 0' only are valid in the case
of QFN package devices.
The device has four General Purpose Input and Output (GPIO) pins. Each of the four pins can be independently
programmed as General Purpose Output (GPO) or General Purpose Input (GPI). It is also possible to use the
GPIOs for some pre-assigned functions (refer to Table 10 for details). GPO data can be written into the device
through the SDI line. The device refreshes the GPO data on every CS falling edge as per the SDI data written in
the previous frame. Similarly, the device latches GPI status on the CS falling edge and outputs it on SDO (if GPI
is read enabled by writing DI04 = 1 during the previous frame) in the same frame starting on the CS falling edge.
The details regarding programming the GPIO registers are illustrated in the flowchart in Figure 56.Table 10 lists
the details regarding GPIO Register programming settings.
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Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
Deviceinanyoperationmode
ProgramGPIOregister?
EndofGPIOregisterprogramming
Yes
No
CS
CS
GPIOregister
programming
SDI:DI15..12=0100
Refertable9forDI11..00data
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
NOTE: The device continues its operation in selected mode during programming. SDO is valid, however it is not possible to
change the range or write GPIO data into the device during programming.
Figure 56. GPIO Program Register Programming Flowchart
Table 10. GPIO Program Register Settings
DESCRIPTION
RESET
BITS LOGIC
STATE FUNCTION
STATE
DI15-12 NA 0100 Device selects GPIO Program Registers for programming.
DI11-10 00 00 Do not program these bits to any logic state other than ‘00’
DI09 0 1 Device resets all registers in the next CS frame to the reset state shown in the corresponding tables (it
also resets itself).
0 Device normal operation
DI08 0 1 Device configures GPIO3 as the device power-down input.
0 GPIO3 remains general purpose I or O. Program 0 for QFN packaged devices.
DI07 0 1 Device configures GPIO2 as device range input.
0 GPIO2 remains general purpose I or O. Program 0 for QFN packaged devices.
DI06-04 000 000 GPIO1 and GPIO0 remain general purpose I or O. Valid setting for QFN packaged devices.
xx1 Device configures GPIO0 as ‘high or low’ alarm output. This is an active high output. GPIO1 remains
general purpose I or O. Valid setting for QFN packaged devices.
010 Device configures GPIO0 as high alarm output. This is an active high output. GPIO1 remains general
purpose I or O. Valid setting for QFN packaged devices.
100 Device configures GPIO1 as low alarm output. This is an active high output. GPIO0 remains general
purpose I or O. Setting not allowed for QFN packaged devices.
110 Device configures GPIO1 as low alarm output and GPIO0 as a high alarm output. These are active high
outputs. Setting not allowed for QFN packaged devices.
Note: The following settings are valid for GPIO which are not assigned a specific function through bits DI08..04
DI03 0 1 GPIO3 pin is configured as general purpose output. Program 1 for QFN packaged devices.
0 GPIO3 pin is configured as general purpose input. Setting not allowed for QFN packaged devices.
DI02 0 1 GPIO2 pin is configured as general purpose output. Program 1 for QFN packaged devices.
0 GPIO2 pin is configured as general purpose input. Setting not allowed for QFN packaged devices.
DI01 0 1 GPIO1 pin is configured as general purpose output. Program 1 for QFN packaged devices.
0 GPIO1 pin is configured as general purpose input. Setting not allowed for QFN packaged devices.
DI00 0 1 GPIO0 pin is configured as general purpose output. Valid setting for QFN packaged devices.
38 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
Table 10. GPIO Program Register Settings (continued)
DESCRIPTION
RESET
BITS LOGIC
STATE FUNCTION
STATE
0 GPIO0 pin is configured as general purpose input. Valid setting for QFN packaged devices.
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 39
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
MXO AINP
Ch0
Chn*
Ch2
Ch1
ADC
GPIO0,H Alarm
GPIO1,L Alarm
SDI
GPIO2,Range
SCLK
CS
SDO To
Host
REF
10 Fm
REF5025
o/p
Fromsensors,INA etc.
Thereisarestrictionon
sourceimpedance.
R 50
SOURCE £ W
GPIO3, PD
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
APPLICATION INFORMATION
ANALOG INPUT
The ADS79XX device family offers 12/10/8-bit ADCSs with 16/12/8/4 channel multiplexers for analog input. The
multiplexer output is available on the MXO pin. AINP is the ADC input pin. The devices offers flexibility for a
system designer as both signals are accessible esternally.
Typically it is convenient to short MXO to the AINP pin so that signal input to each multiplexer channel can be
processed independently. In this condition it is recommended to limit source impedance to 50Ωor less. Higher
source impedance may affect the signal settling time after a multiplexer channel change. This condition can
affect linearity and total harmonic distortion.
GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers 'GPIO 0' only. As a result all
references related to 'GPIO 0' only are valid in case of QFN package devices.
Figure 57. Typical Application Diagram Showing MXO Shorted to AINP
Another option is to add a common ADC driver buffer between the MXO and AINP pins. This relaxes the
restriction on source impedance to a large extent. Refer to the typical characteristics section for the effect of
source impedance on device performance. The typical characteristics show that the device has respectable
performance with up to 1kΩsource impedance. This topology (including a common ADC driver) is useful when
all channel signals are within the acceptable range of the ADC. In this case the user can save on signal
conditioning circuit for each channel.
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Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
MXO AINP
Ch0
Chn*
Ch2
Ch1
ADC
HighInput
impedancePGA
(ornoninvertingbuffer
like THS4031)
GPIO
1,2,3
PGA Gain
Control
GPIO0
H/L Alarm
SDI
SCLK
CS
SDO To
Host
REF
10 Fm
REF5025
o/p
Fromsensors,INA etc.
Sourceimpedancehasvery
littleeffectonperformance.
Referto TypicalCharacteristics
fordetails.
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers 'GPIO 0' only. As a result all
references related to 'GPIO 0' only are valid in case of QFN package devices.
Figure 58. Typical Application Diagram Showing Common Buffer/PGA for all Channels
When the converter samples an input, the voltage difference between AINP and AGND is captured on the
internal capacitor array. The (peak) input current through the analog inputs depends upon a number of factors:
sample rate, input voltage, and source impedance. The current into the ADS79XX charges the internal capacitor
array during the sample period. After this capacitance has been fully charged, there is no further input current.
When the converter goes into hold mode, the input impedance is greater than 1 GΩ.
Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the Ch0 ..
Chn and AINP inputs should be within the limits specified. Outside of these ranges, converter linearity may not
meet specifications.
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Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
200 ohm
7 pF3 pF
20M ohm
3 pF
5 pF
80 ohm
Ch0 assumed to be on
Chn assumed to be off
Ch0
Chn
MXO
AINP
W
W
W
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
Figure 59. ADC and Mux Equivalent Circuit
REFERENCE
The ADS79XX can operate with an external 2.5V ± 10mV reference. A clean, low noise, well-decoupled
reference voltage on the REF pin is required to ensure good performance of the converter. A low noise band-gap
reference like the REF5025 can be used to drive this pin. A 10-mF ceramic decoupling capacitor is required
between the REF and GND pins of the converter. The capacitor should be placed as close as possible to the
pins of the device.
POWER SAVING
The ADS79XX devices offer a power-down feature to save power when not in use. There are two ways to
powerdown the device. It can be powered down by writing DI05 = 1 in the Mode Control register (refer to
Table 1,Table 2 and Table 5); in this case the device powers down on the 16th falling edge of SCLK in the next
data frame. Another way to powerdown the device is through GPIO. GPIO3 can act as a PD input (refer to
Table 10, for assigning this functionality to GPIO3). This is an asynchronous and active low input. The device
powers down instantaneously after GPIO3 (PD) = 0. The device will powerup again on the CS falling edge while
DI05 = 0 in the Mode Control register and GPIO3 (PD) = 1.
DIGITAL OUTPUT
As discussed previously in the Device Operation section, the digital output of the ADS79XX devices is SPI
compatible. The following table lists the output codes corresponding to various analog input voltages.
Table 11. Ideal Input Voltages and Output Codes for 12-Bit Devices (ADS7950/51/52/53)
DESCRIPTION ANALOG VALUE DIGITAL OUTPUT
Full scale range Range 1 →Vref Range 2 →2×Vref STRAIGHT BINARY
Least significant bit (LSB) Vref/4096 2Vref/4096 BINARY CODE HEX CODE
Full scale Vref – 1 LSB 2Vref – 1 LSB 1111 1111 1111 FFF
Midscale Vref/2 Vref 1000 0000 0000 800
Midscale – 1 LSB Vref/2 – 1 LSB Vref – 1 LSB 0111 1111 1111 7FF
Zero 0 V 0 V 0000 0000 0000 000
Table 12. Ideal Input Voltages and Output Codes for 10-Bit Devices (ADS7954/55/56/57)
DESCRIPTION ANALOG VALUE DIGITAL OUTPUT
Full scale range Range 1 →Vref Range 2 →2×Vref STRAIGHT BINARY
Least significant bit (LSB) Vref/1024 2Vref/1024 BINARY CODE HEX CODE
Full scale Vref – 1 LSB 2Vref – 1 LSB 11 1111 1111 3FF
Midscale Vref/2 Vref 10 0000 0000 200
Midscale – 1 LSB Vref/2 – 1 LSB Vref – 1 LSB 01 1111 1111 1FF
Zero 0 V 0 V 00 0000 0000 000
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Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
Table 13. Ideal Input Voltages and Output Codes for 8-Bit Devices (ADS7958/59/60/61)
DESCRIPTION ANALOG VALUE DIGITAL OUTPUT
Full scale range Range 1 →Vref Range 2 →2×Vref STRAIGHT BINARY
Least significant bit (LSB) Vref/256 2Vref/256 BINARY CODE HEX CODE
Full scale Vref – 1 LSB 2Vref – 1 LSB 1111 1111 FF
Midscale Vref/2 Vref 1000 0000 80
Midscale – 1 LSB Vref/2 – 1 LSB Vref – 1 LSB 0111 1111 7F
Zero 0 V 0 V 0000 0000 00
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Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
REVISION HISTORY
Changes from Original (June 2008) to Revision A Page
• Added QFN information to Features ..................................................................................................................................... 1
• Added QFN information to Description ................................................................................................................................. 1
• Added QFN information to 12-bit ordering information ......................................................................................................... 3
• Added QFN information to 10-bit ordering information ......................................................................................................... 3
• Added QFN information to 8-bit ordering information ........................................................................................................... 4
• Changed thermal impedance for DBT package in absolute maximum ratings .................................................................... 4
• Changed thermal impedance for RHB package in absolute maximum ratings .................................................................... 4
• Changed thermal impedance for RGE package in absolute maximum ratings .................................................................... 4
• Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7950/51/52/53 ..................................................... 5
• Added while 2Vref ≤+VA to full-scale input span range 2 test conditions ........................................................................... 5
• Added while 2Vref ≤+VA to full-scale input span range 2 test conditions ........................................................................... 5
• Added Total unadjusted error (TUE) specification ................................................................................................................ 5
• Changed reference voltage at REFP min and max values .................................................................................................. 6
• Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7950/51/52/53 ..................................................... 6
• Added Note to ELECTRICAL CHARACTERISTICS, ADS7950/51/52/53 ............................................................................ 6
• Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7954/55/56/57 test conditions ............................. 6
• Added while 2Vref ≤+VA to full-scale input span range 2 test conditions ........................................................................... 6
• Added while 2Vref ≤+VA to full-scale input span range 2 test conditions ........................................................................... 6
• Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7954/55/56/57 test conditions ............................. 7
• Changed Vref reference voltage at REFP min value from 2.49 V to 2.0 V ........................................................................... 7
• Changed Vref reference voltage at REFP max value from 2.51 V to 3.0 V .......................................................................... 7
• Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7954/55/56/57 test conditions ............................. 8
• Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7958/59/60/61 test conditions ............................. 8
• Added while 2Vref ≤+VA to full-scale input span range 2 test conditions ........................................................................... 8
• Added while 2Vref ≤+VA to full-scale input span range 2 test conditions ........................................................................... 8
• Changed Vref reference voltage at REFP min value from 2.49 V to 2.0 V ........................................................................... 9
• Changed Vref reference voltage at REFP max value from 2.51 V to 3.0 V .......................................................................... 9
• Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7958/59/60/61 test conditions ............................. 9
• Changed tsu1 values from max to min ................................................................................................................................. 10
• Changed tsu2 values from max to min ................................................................................................................................. 10
• Changed VEE to AGND and VCC to +VA on 38-pin TSSOP pinout ................................................................................. 11
• Added QFN pinout .............................................................................................................................................................. 11
• Added QFN pinout .............................................................................................................................................................. 12
• Added QFN pinout .............................................................................................................................................................. 12
• Added QFN pinout .............................................................................................................................................................. 12
• Added terminal functions for QFN packages ...................................................................................................................... 14
• Changed ADS7950/4/8 QFN package MXO pin from 7 to 3 .............................................................................................. 14
• Added TOTAL UNADJUSTED ERROR (TUE Max) graph ................................................................................................. 21
• Added TOTAL UNADJUSTED ERROR (TUE Min) graph .................................................................................................. 21
• Changed GPIO pins description ......................................................................................................................................... 23
• Added device powerdown through GPIO in the case of the TSSOP packaged devices ................................................... 25
• Added note to Table 1 ........................................................................................................................................................ 29
• Added note to Table 1 ........................................................................................................................................................ 29
44 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
• Added note to Table 2 ........................................................................................................................................................ 31
• Added note to Table 2 ........................................................................................................................................................ 31
• Added note to Table 5 ........................................................................................................................................................ 34
• Changed DI12 = 1? from No or No to Yes or No in Figure 55 ........................................................................................... 36
• Added note to Programming GPIO Registers description .................................................................................................. 37
• Added QFN information to Table 10 ................................................................................................................................... 38
• Added note to Figure 57 ..................................................................................................................................................... 40
• Added note to Figure 58 ..................................................................................................................................................... 41
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 45
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
PACKAGE OPTION ADDENDUM
www.ti.com 29-Jul-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS7950SBDBT ACTIVE TSSOP DBT 30 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7950SBDBTG4 ACTIVE TSSOP DBT 30 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7950SBDBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7950SBDBTRG4 ACTIVE TSSOP DBT 30 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7950SBRGER ACTIVE VQFN RGE 24 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
ADS7950SBRGET ACTIVE VQFN RGE 24 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
ADS7950SDBT ACTIVE TSSOP DBT 30 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7950SDBTG4 ACTIVE TSSOP DBT 30 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7950SDBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7950SDBTRG4 ACTIVE TSSOP DBT 30 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7950SRGER ACTIVE VQFN RGE 24 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
ADS7950SRGET ACTIVE VQFN RGE 24 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
ADS7951SBDBT ACTIVE TSSOP DBT 30 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7951SBDBTG4 ACTIVE TSSOP DBT 30 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7951SBDBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7951SBDBTRG4 ACTIVE TSSOP DBT 30 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7951SBRGER ACTIVE VQFN RGE 24 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
PACKAGE OPTION ADDENDUM
www.ti.com 29-Jul-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS7951SBRGET ACTIVE VQFN RGE 24 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7951SDBT ACTIVE TSSOP DBT 30 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7951SDBTG4 ACTIVE TSSOP DBT 30 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7951SDBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7951SDBTRG4 ACTIVE TSSOP DBT 30 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7951SRGER ACTIVE VQFN RGE 24 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7951SRGET ACTIVE VQFN RGE 24 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7952SBDBT ACTIVE TSSOP DBT 38 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7952SBDBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7952SBDBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7952SBDBTRG4 ACTIVE TSSOP DBT 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7952SBRHBR ACTIVE QFN RHB 32 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
ADS7952SBRHBT ACTIVE QFN RHB 32 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
ADS7952SDBT ACTIVE TSSOP DBT 38 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7952SDBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7952SDBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7952SDBTRG4 ACTIVE TSSOP DBT 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7952SRHBR ACTIVE QFN RHB 32 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
PACKAGE OPTION ADDENDUM
www.ti.com 29-Jul-2011
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS7952SRHBT ACTIVE QFN RHB 32 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
ADS7953SBDBT ACTIVE TSSOP DBT 38 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7953SBDBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7953SBDBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7953SBDBTRG4 ACTIVE TSSOP DBT 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7953SBRHBR ACTIVE QFN RHB 32 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
ADS7953SBRHBT ACTIVE QFN RHB 32 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
ADS7953SDBT ACTIVE TSSOP DBT 38 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7953SDBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7953SDBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7953SDBTRG4 ACTIVE TSSOP DBT 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7953SRHBR ACTIVE QFN RHB 32 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
ADS7953SRHBT ACTIVE QFN RHB 32 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
ADS7954SDBT ACTIVE TSSOP DBT 30 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7954SDBTG4 ACTIVE TSSOP DBT 30 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7954SDBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7954SDBTRG4 ACTIVE TSSOP DBT 30 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7954SRGER ACTIVE VQFN RGE 24 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
PACKAGE OPTION ADDENDUM
www.ti.com 29-Jul-2011
Addendum-Page 4
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS7954SRGET ACTIVE VQFN RGE 24 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
ADS7955SDBT ACTIVE TSSOP DBT 30 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7955SDBTG4 ACTIVE TSSOP DBT 30 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7955SDBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7955SDBTRG4 ACTIVE TSSOP DBT 30 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7955SRGER ACTIVE VQFN RGE 24 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
ADS7955SRGET ACTIVE VQFN RGE 24 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
ADS7956SDBT ACTIVE TSSOP DBT 38 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7956SDBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7956SDBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7956SDBTRG4 ACTIVE TSSOP DBT 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7956SRHBR ACTIVE QFN RHB 32 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
ADS7956SRHBT ACTIVE QFN RHB 32 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
ADS7957SDBT ACTIVE TSSOP DBT 38 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7957SDBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7957SDBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7957SDBTRG4 ACTIVE TSSOP DBT 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7957SRHBR ACTIVE QFN RHB 32 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
PACKAGE OPTION ADDENDUM
www.ti.com 29-Jul-2011
Addendum-Page 5
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS7957SRHBT ACTIVE QFN RHB 32 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
ADS7958SDBT ACTIVE TSSOP DBT 30 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7958SDBTG4 ACTIVE TSSOP DBT 30 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7958SDBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7958SDBTRG4 ACTIVE TSSOP DBT 30 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7958SRGER ACTIVE VQFN RGE 24 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
ADS7958SRGET ACTIVE VQFN RGE 24 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
ADS7959SDBT ACTIVE TSSOP DBT 30 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7959SDBTG4 ACTIVE TSSOP DBT 30 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7959SDBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7959SDBTRG4 ACTIVE TSSOP DBT 30 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7959SRGER ACTIVE VQFN RGE 24 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
ADS7959SRGET ACTIVE VQFN RGE 24 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
ADS7960SDBT ACTIVE TSSOP DBT 38 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7960SDBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7960SDBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7960SDBTRG4 ACTIVE TSSOP DBT 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7960SRHBR ACTIVE QFN RHB 32 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
PACKAGE OPTION ADDENDUM
www.ti.com 29-Jul-2011
Addendum-Page 6
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS7960SRHBT ACTIVE QFN RHB 32 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
ADS7961SDBT ACTIVE TSSOP DBT 38 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7961SDBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7961SDBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7961SDBTRG4 ACTIVE TSSOP DBT 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart
ADS7961SRHBR ACTIVE QFN RHB 32 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
ADS7961SRHBT ACTIVE QFN RHB 32 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Add to cart
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 29-Jul-2011
Addendum-Page 7
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS7950SBDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
ADS7950SBRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
ADS7950SBRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
ADS7950SDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
ADS7950SRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
ADS7950SRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
ADS7951SBDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
ADS7951SBRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
ADS7951SBRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
ADS7951SDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
ADS7951SRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
ADS7951SRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
ADS7952SBDBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
ADS7952SBRHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
ADS7952SBRHBT QFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
ADS7952SDBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
ADS7952SRHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
ADS7952SRHBT QFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS7953SBDBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
ADS7953SBRHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
ADS7953SBRHBT QFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
ADS7953SDBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
ADS7953SRHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
ADS7953SRHBT QFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
ADS7954SDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
ADS7954SRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
ADS7954SRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
ADS7955SDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
ADS7955SRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
ADS7955SRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
ADS7956SDBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
ADS7957SDBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
ADS7958SDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
ADS7958SRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
ADS7958SRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
ADS7959SDBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
ADS7959SRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
ADS7959SRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
ADS7960SDBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
ADS7961SDBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS7950SBDBTR TSSOP DBT 30 2000 367.0 367.0 38.0
ADS7950SBRGER VQFN RGE 24 3000 367.0 367.0 35.0
ADS7950SBRGET VQFN RGE 24 250 210.0 185.0 35.0
ADS7950SDBTR TSSOP DBT 30 2000 367.0 367.0 38.0
ADS7950SRGER VQFN RGE 24 3000 367.0 367.0 35.0
ADS7950SRGET VQFN RGE 24 250 210.0 185.0 35.0
ADS7951SBDBTR TSSOP DBT 30 2000 367.0 367.0 38.0
ADS7951SBRGER VQFN RGE 24 3000 367.0 367.0 35.0
ADS7951SBRGET VQFN RGE 24 250 210.0 185.0 35.0
ADS7951SDBTR TSSOP DBT 30 2000 367.0 367.0 38.0
ADS7951SRGER VQFN RGE 24 3000 367.0 367.0 35.0
ADS7951SRGET VQFN RGE 24 250 210.0 185.0 35.0
ADS7952SBDBTR TSSOP DBT 38 2000 367.0 367.0 38.0
ADS7952SBRHBR QFN RHB 32 3000 367.0 367.0 35.0
ADS7952SBRHBT QFN RHB 32 250 210.0 185.0 35.0
ADS7952SDBTR TSSOP DBT 38 2000 367.0 367.0 38.0
ADS7952SRHBR QFN RHB 32 3000 367.0 367.0 35.0
ADS7952SRHBT QFN RHB 32 250 210.0 185.0 35.0
ADS7953SBDBTR TSSOP DBT 38 2000 367.0 367.0 38.0
ADS7953SBRHBR QFN RHB 32 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 3
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS7953SBRHBT QFN RHB 32 250 210.0 185.0 35.0
ADS7953SDBTR TSSOP DBT 38 2000 367.0 367.0 38.0
ADS7953SRHBR QFN RHB 32 3000 367.0 367.0 35.0
ADS7953SRHBT QFN RHB 32 250 210.0 185.0 35.0
ADS7954SDBTR TSSOP DBT 30 2000 367.0 367.0 38.0
ADS7954SRGER VQFN RGE 24 3000 367.0 367.0 35.0
ADS7954SRGET VQFN RGE 24 250 210.0 185.0 35.0
ADS7955SDBTR TSSOP DBT 30 2000 367.0 367.0 38.0
ADS7955SRGER VQFN RGE 24 3000 367.0 367.0 35.0
ADS7955SRGET VQFN RGE 24 250 210.0 185.0 35.0
ADS7956SDBTR TSSOP DBT 38 2000 367.0 367.0 38.0
ADS7957SDBTR TSSOP DBT 38 2000 367.0 367.0 38.0
ADS7958SDBTR TSSOP DBT 30 2000 367.0 367.0 38.0
ADS7958SRGER VQFN RGE 24 3000 367.0 367.0 35.0
ADS7958SRGET VQFN RGE 24 250 210.0 185.0 35.0
ADS7959SDBTR TSSOP DBT 30 2000 367.0 367.0 38.0
ADS7959SRGER VQFN RGE 24 3000 367.0 367.0 35.0
ADS7959SRGET VQFN RGE 24 250 210.0 185.0 35.0
ADS7960SDBTR TSSOP DBT 38 2000 367.0 367.0 38.0
ADS7961SDBTR TSSOP DBT 38 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 4
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