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Mar 29, 2019
Features
On-Chip 32-bit Arm Cortex-A7 MPCore
● Up to 500 MHz
● Single or Dual core
● FPU, VFPv4-D16
● MMU
● L1 cache: 16 KB (instruction)/16 KB (data) per core
● L2 cache: up to 256 KB
On-Chip 32-bit Arm Cortex-M3 Processor
● Up to 125 MHz
● Memory Protection Unit (MPU) supported
Low Power Features
● Clock gating management
● Clock frequency scaling
On-Chip Extended SRAM
● Up to 6 MB with ECC
Data Transfer
● 2 × DMAC with 8 channels each
Memory Interfaces
● Up to 2 × Quad SPI/XIP
● NAND Flash with advanced ECC management
● 16-bit DDR interface (DDR2-500/DDR3-1000)
● Up to 2 × SD/SDIO/eMMC
IO Multiplexing Controller
● Locations of I/Os for peripherals are selectable from
multiple pins
Clock Oscillator
● External clock/oscillator input frequency: 40 MHz
● RTC with 32 kHz oscillator
Peripherals
● CPU resources
− Mailbox
− 2 × Timer block (16bit × 6ch, 32bit × 2ch)
− 1 × Watchdog per CPU
− Semaphore
● General Connectivity
− 1 × USB2.0 Host
− 1 × USB2.0 Host & Function
− 8 × UART
− 6 × SPI (4 masters/2 slaves)
− 2 × I2C
− 2 × CAN
− Up to 2 × 12-bit ADC (up to 1 MSPS)
− MSEBI (Parallel Bus Interface)
● Other features
− LCD controller
− GPIO pins (up to 170)
R-IN Engine
● Arm Cortex-M3 CPU
● Hardware RTOS accelerator (HW-RTOS)
● Hardware Ethernet accelerator
Advanced real-time Ethernet features
● SercosIII Slave Controller
● EtherCAT 3 ports slave controller
● Advanced 5 (4 + 1) Port Switch (A5PSW)
− Switch 5 ports with QoS and IEEE1588
Up to 5 Gbit ports
− PRP compliant to IEC62439-3 Ed2.0-2012 (option)
● HSR compliant to IEC62439-3 Ed2.0-2012 (option)
● Up to 2 independent GMAC, IEEE1588
● Up to 5 external ports with MII/RMII/RGMII
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group
Industrial Communication Embedded solution based on dual 500
MHz Arm® Cortex®-A7 CPU, and
Cortex
®-M3 at 125 MHz. On-chip FPU, up to 6 Mbytes of on-chip extended SRAM with ECC,
extended Ethernet functionalities including Advanced 5
port Ethernet switch, independent Ethernet
GMAC,
support for EtherCAT®, Sercos®, Profinet®, ETHERNET Powerlink®, EtherNet/IP™, DLR,
PRP, HSR.
Various peripherals such as Quad SPI, DDR controller, NAND Flash Controller, LCD
controller, SD
/SDIO/eMMC, ADCs.
R01DS0323EJ0100
Rev.1.00
Mar 29, 2019
DATASHEET
CAN (Controller Area Network): An automotive network specification developed by Robert Bosch GmbH of Germany.
Arm is a registered trademark of Arm Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved.
EtherCAT is registered trademark and patented technology, licensed by Beckhoff Automation GmbH, Germany.
Sercos is a registered trademark of Sercos International e.V.
All trademarks and registered trademarks are the property of their respective owners.
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group Section 1 Overview
R01DS0323EJ0100 Rev.1.00 Page 2 of 25
Mar 29, 2019
Section 1 Overview
The Renesas RZ/N1D group, RZ/N1S group, RZ/N1L group are specifically tailored to meet the demands of Industrial
Ethernet based applications.
1.1 Outline of Specifications
Table 1.1 Outline of Specifications (1/8)
Classification Module/Function Description
CPU Arm Cortex-A7
●
Arm 32-bit CPU Cortex-A7 (Revision r0p5)
● Dual core or single core
● Maximum operating frequency: 500 MHz
● Clock frequency scaling
● L1 cache: 16 KB (instruction)/16 KB (data) per core
● L2 cache: up to 256 KB
● FPU, VFPv4-D16
● MMU
● Hardware coherent caches
● Little endian
Arm Cortex-M3
●
Arm 32-bit CPU Cortex-M3 (Revision r2p1)
● Maximum operating frequency: 125 MHz
● Memory Protection Unit (MPU)
● Little endian
Memory On-chip 2 MB SRAM
●
Capacity: 2 MB (1 MB + 1 MB)
● Separated access ports per 512 KB unit
● SEC-DED (Single Error Correction, Double Error Detection)
On-chip 4 MB SRAM
●
Capacity: 4 MB
● Separated access ports per 1 MB unit
● SEC-DED (Single Error Correction, Double Error Detection)
Watchdog
●
Free running 12-bit decrementing counters with reload register
● Output can be used to activate a system reset or as an interrupt
● Stop of watchdog effect while CPU is being stopped by debugger (e.g. by
breakpoint execution)
Operating Modes
●
Three boot modes (CA7)
– NAND Flash
– QSPI Flash
– USB DFU
Clock Clock Generation Circuit
●
Input 40 MHz clock selectable from an oscillator or crystal
● System clock up to 125 MHz
● Cortex-A7 clock ×1/×2/×4 with system clock
● DDR memory clock 250 MHz/500 MHz
RTC
●
Time-of-day clock in 24-hour mode
● Calendar
● Alarm capability
● XTAL 32 kHz
● Separate and isolated power supply for RTC backup mode
Reset
●
Master Reset input
● Internal System Reset (Software, watchdog)
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group Section 1 Overview
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Mar 29, 2019
Table 1.1 Outline of Specifications (2/8)
Classification Module/Function Description
Data Transfer Direct Memory Access
Controller (DMAC)
●
2 units:
– 8 channels, 16 request sources for DMAC1
– 8 channels, 16 request sources for DMAC2
● Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-
to-peripheral transfers
● Transfer size:
– 8, 16, 32, 64 bits
● Programmable DMA burst size
Mailbox
●
3 × programmable mailboxes
– 7 × 32-bit data registers per mailbox
Semaphore
●
Hardware lock mechanism of internal shared resources
Parallel Bus
Interface
Medium Speed External
Bus Interface (MSEBI)
●
Master and slave modes
– Data bus width selectable from 8, 16 and 32 bits
● Address/data/control-data are multiplexed on data bus
● Burst mode
● DMA Support
– Master mode: Coupling with 4 DMA channels (external request reception
capability)
– Slave Mode: External request transmission capability
● Up to 4 chip selects
● Programmable address capability from 2B to 4GB
● Programmable setup and hold time
● External wait request
I/O Ports IO Multiplexing
●
Locations of IOs for peripherals are selectable
● Output drive strength selectable
● On-chip Pull-up/Pull-down select
Memory Interfaces DDR2/3 Controller
●
DDR2-500/DDR3-1000
● Programmable memory data path size: 16 bits, 8 bits, 8 + ECC bits
● Up to 2 chip selects and 2 ODT
● Up to 2 GB address capability
● ECC SEC/DED software configurable (enable/disable)
● Programmable on die termination
● Configurable impedance drive and slew rate
● DDR2/DDR3 low power control management (by software)
● Port Address Protection Check
– Up to 16 address protection regions per port
NAND Flash Controller
●
NAND interface with 8-bit bus width
● Support for asynchronous mode
● 4 chip selects
● Write protection
● Programmable address cycle (0/1/2/3/4/5)
● Integrated DMA
● Support for 256 B, 512 B, 2 KB, 1 KB, 4 KB, 8 KB, 16 KB pages
● BCH ECC (Error detection and data correction)
– ECC data block size: 256 B, 512 B, 1024 B
– ECC correction capability: 2, 4, 8, 16, 24, 32 bits errors
● Bad Block Management (BBM)
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group Section 1 Overview
R01DS0323EJ0100 Rev.1.00 Page 4 of 25
Mar 29, 2019
Table 1.1 Outline of Specifications (3/8)
Classification Module/Function Description
Memory Interfaces Quad SPI (QSPI)
●
Up to 2 units
● Single, dual or quad I/O instructions supported
● Execute in Place (XIP) supported
● Remap address direct access
● Programmable device sizes
● Up to 4 chip selects
● Support for 1/2/3/4 byte addressing
● Support for programmable page size (default 256 bytes)
● Support for programmable number of bytes per device block
● Programmable write protected regions
● Transmit and receive FIFOs are 16 bytes
● Legacy mode allowing software direct access to low level transmit and receive
FIFOs
● Set of control registers to perform any FLASH command
● Support for write burst in direct access
SD/SDIO/eMMC
●
Up to 2 units
● SD/SDIO Card interface
– Transfers data in 1 bit or 4 bits mode
– Transfers data in Default or High Speed mode
● eMMC interface
– Transfers data in 1 bit, 4 bits, or 8 bits mode
● Speeds
– Default mode up to 25 MHz
– High Speed mode up to 50 MHz
● Support for PIO/SDMA/ADMA2 transfer
Networking
Elements
R-IN Engine
●
ITRON-like system calls
– 30 system calls for elements such as events, semaphores, and mailboxes
● Task Scheduler
– Hardware ISR: Maximum 32 selectable from 128 interrupts
– Number of context elements: 64
– Number of semaphore identifiers: 128
– Number of event identifiers: 64
– Number of mailbox identifiers: 64
– Number of mailbox elements: 192
– Number of context priority levels: 16
● Hardware function manager
● Internal DMA controller
● Buffer allocator
● Header EnDec
● Dedicated Gigabit Ethernet MAC (with built-in MACDMAC)
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group Section 1 Overview
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Mar 29, 2019
Table 1.1 Outline of Specifications (4/8)
Classification Module/Function Description
Networking
Elements
Advanced 5 Port Switch
●
Operation modes:
– 10 Mbps half- and full-duplex
– 100 Mbps half- and full-duplex
– 1000 Mbps full-duplex only
● MAC based RMON statistics counters/per port
● Port statistics on per port basis (no aggregation)
● Look-up table up to 8192 MAC addresses (static and learned)
● Packet buffer size: 1 Mbit
● 4 queues with individual QoS levels, supporting frame priority classification for the
flexible handling of output queues
– Optional arbitration management through weighted fair queuing
● Support for Ethernet multicast and broadcast frames with flooding control to avoid
unnecessary duplication of frames
● Programmable multicast destination port mask to restrict frame duplication for
individual multicast addresses
● IEEE 1588-2008 compatible
– Support for 1 step Peer-to-Peer (P2P) (Layer 2 only)
– Support for 1 step End-to-End (E2E) (Layer 2 only)
● Multicast and broadcast resolution with VLAN domain filtering providing a strict
separation of up to 32 VLANs
● Support for reception and transmission of VLAN frames
● Programmable addition, removal and manipulation of ingress and egress VLAN
tags, supporting single and double-tagged VLAN frames on each port
● Support for standard frame size (1536 bytes), extended frame sizes up to 1700
bytes and jumbo frames up to 10 Kbytes
● Port mirroring programmable per port
● RSTP port states (3 for RSTP/ 5 for STP)
– RSTP Port states learning, discarding, forwarding configurable per port
– BPDU frame supported
– MSTP BPDU frame supported (software)
● Start in Managed mode
● Frame snooping engine
● Standalone Energy-Efficient-Ethernet (EEE) management
● Programmable egress rate limit per port
● Ingress Configurable Broadcast storm protection per port
● Ingress Configurable Multicast storm protection per port
● 802.1X source address authentication supported
● 802.1X guest VLAN supported
● PRP functionality (IEC 62439-3 edition 2.0- 2012)
● DLR module
● Cut-through
● TDMA (Time Division Multiple Access) 4 time slots
● Pattern Matchers 8 channels
● Remote monitoring via SNMP and the (RMON/MIB)
● Powerlink capable Hub
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group Section 1 Overview
R01DS0323EJ0100 Rev.1.00 Page 6 of 25
Mar 29, 2019
Table 1.1 Outline of Specifications (5/8)
Classification Module/Function Description
Networking
Elements
HSR Switch
●
HSR functionality (IEC 62439-3 edition 2.0- 2012)
– DANH
– Redundancy Box (Red Box)
– Generation of redundant transmit frames
– Filtering of duplicated received frames
– Redundancy header generation and detection
– Table to keep track of received frames
● 100 Mbps full-duplex Ethernet
● Dynamic frame buffer allocation (page manager)
● 128 proxy nodes (VDANs) supported
● Support for link-local protocols
● Duplicate detection memory
● MAC address filtering
● 1 × VLAN tag supported
● Port statistics on per port basis (no aggregation)
● 144 KB frame buffer
● IEEE 1588-2008
● Support for Ethernet multicast frames with flooding control
● Extended frame size: up to 2000 bytes (Jumbo frames not supported)
● Support for a minimum of 16 nodes in an HSR loop
● Configurable duplicate detection residence time
EtherCAT Slave
Controller
●
Up to 3 ports
● Automatic TX Shift
● Enhanced Link Detection
● 8 FMMU (Fieldbus Memory Management Unit)
● 8 SyncManagers
● 64-bit Distributed Clocks
● Mapping to global IRQ
● Read/Write Offset
● Write Protection
● AL Status Code Register
● Extended Watchdog
● AL Event Mask Register
● Watchdog Counter
● SyncManager Event Times
● EPU Error Counter
● Lost Link Counter
● I2C interface for external EEPROM
SercosIII Slave Controller
●
2 ports
● The serial interface operates with 100 Mbaud
● Telegram processing for automatic transmission, and monitoring of
synchronization
telegrams and data telegrams
● Switch over function between Sercos protocol and standard Ethernet protocol via
multiplexer
● Monitors the received data stream to detect the frame type and starts operation
when SercosIII frame type is detected
● Handling of the data transfers to and from SRAM based on telegram type
(MST/MDT or AT)
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group Section 1 Overview
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Mar 29, 2019
Table 1.1 Outline of Specifications (6/8)
Classification Module/Function Description
Networking
Elements
Independent GMAC
●
2 × MAC instances (GMAC1, GMAC2)
● Compliance with the following standards:
– IEEE 1588-2008 v2 standard for precision networked clock synchronization
– IEEE 1588-2008 v2 is compliant with Power IEEE C37.238 profile
– IEEE 802.3-az-2010 for Energy Efficient Ethernet (EEE)
● Support for 10/100/1000 Mbps data transfer rates
● Support for both half-duplex and full-duplex operation
● Programmable frame length to support both standard and “jumbo” Ethernet frames
with size up to 16 Kbytes (16KB-1)
● 17 MAC address registers for the address filter block
● Variety of flexible addresses filtering modes are supported
● Native DMA with simple-independent channels for transmit and receive engines
● Advanced IEEE 1588-2002 & 2008 Ethernet frame time-stamping supported
● Provides the flexibility to control the Pulse-Per-Second (PPS) output signal
(GMAC1 only)
● Programmable CRC generation and checking
● Support for RMON statistics (L2 layer only)
● Station Management Block, MDIO interface
Subsystem
Elements
USB2.0 HOST
●
1 dedicated port + 1 configurable port (Host or Function)
● Supports:
– High speed (HS): 480 Mbps (USB 2.0)
– Full speed (FS): 12 Mbps (USB 1.1)
– Low speed (LS): 1.5 Mbps (USB 1.1)
● USB Plug Detect (UPD)
● Output port power switch management
● Overcurrent indication from application
● Integrated DMA
● Transmit and receive FIFOs
USB2.0 Function
●
1 configurable port (Host or Function)
● Supports:
– High speed (HS): 480 Mbps (USB 2.0)
– Full speed (FS): 12 Mbps (USB 1.1)
● USB Plug Detect (UPD) which detects the connection of a host via VBUS
● 16 physical endpoints
● Integrated DMA
● Endpoint buffer
UART 1, 2, 3
●
Compliant with 16550 UART
● Separate 16×8 (16 location depth × 8-bit width) transmit and 16×8 receive FIFOs
● RS485 & MODBUS® enhanced features
● Baud rate generation up to 5.2 Mbaud
● Generation and detection of line breaks
● Programmable hardware flow control
● Auto Flow Control mode as specified in the 16750 standard
● Supports TXD, RXD, CTS_N, RTS_N, DTR_N, DSR_N, DCD_N, RI_N
UART 4, 5, 6, 7, 8
●
In addition to UART 1, 2, 3, the following function is available:
– DMA coupling with burst-mode management
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group Section 1 Overview
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Mar 29, 2019
Table 1.1 Outline of Specifications (7/8)
Classification Module/Function Description
Subsystem
Elements
SPI 1, 2, 3, 4
(Master)
●
Transmit and receive FIFOs (16 × 16)
● Programmable RXD sampling logic
● Programmable data-size for frames (from 4 to 16 bits)
● 4 chip selects
● DMA controller interface
SPI 5, 6
(Slave)
●
Transmit and receive FIFOs (16 × 16)
● Programmable data-size for frames (from 4 to 16 bits)
● DMA controller interface
I2C 1, 2
●
Two speeds:
– Standard mode (0 to 100 Kbps)
– Fast mode (≤ 400 Kbps)
● Separated 8×8 transmit and 8×8 receive FIFOs
● Master or slave I2C operation
● 7- or 10-bit addressing
● 7- or 10-bit combined format transfers
● Bulk transmit mode
● Programmable SDA hold time (tHD; DAT)
CAN 1, 2
●
Supports both 11-bit and 29-bit identifiers
● Supports bit rates from 125 Kbps to 1 Mbps
● Acceptance filtering
● Software-driven bit-rate detection (offering hot plug-in support)
● Single-shot transmission option, listen-only mode, reception of ‘own’ messages
● Arbitration lost interrupt with data of bit position
● Read/write error counters
● Last error register
● Programmable error limit warning
● Transmit periodic “Sync frame”
● Programmable time base
General Purpose
Timers(Timer)
●
2 units, each supporting:
– 6 programmable 16-bit timers
– 2 programmable 32-bit timers
● Prescaler selectable between 2 time bases
● Auto-reload mode or single-shot mode
● DMA coupling (only for the 32-bit timers)
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group Section 1 Overview
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Mar 29, 2019
Table 1.1 Outline of Specifications (8/8)
Classification Module/Function Description
ADC ADC
●
Up to 2 units
● Resolution 12 bits
● Sampling rate from 0.0625 MSPS to 1 MSPS
● Analog inputs
– 8 channels: (5 ch + 3 ch S/H)
● Individual trigger per channel
● DNL, ± 1.0 LSB (Max.) [at VAIN = 0.0 V to AVDD, fCLK = 20 MHz]
● INL, ± 4.0 LSB (Max.) [at VAIN = 0.0 V to AVDD, fCLK = 20 MHz]
● Power-down mode
● Two level of priority
● Round-robin management of simultaneous conversion requests with the same
level of priority.
● DMA coupling
● Virtual channel capability
Multimedia LCD Controller
●
Programmable LCD Panel resolutions
● Interface for 1 Port TFT LCD Panel:
– 18-bit digital (6 bits/color)
– 24-bit digital (8 bits/color)
● Programmable frame buffer bits per pixel (bpp)
– 1, 2, 4, 8 bpp mapped through Color Palette to 18-bit LCD pixel
– 16, 18, bpp directly drive 18-bit LCD pixel
– 24 bpp directly drive 24-bit LCD pixel
● Hardware blink supported
● Pulse Width Modulation module for LCD panel LED backlight brightness control
● Power up and down sequencing supported
● Integrated DMA
Debugging
Interface
●
ETM coupled with JTAG debugger
● Single Embedded Trace Buffer (32 KB) shared by Cortex-A7 and Cortex-M3 cores
● Arm JTAG
● Arm SWD
Power Supply
Voltage
●
Core Voltage: 1.15 V ± 0.05 V
● IO voltage: 3.3 V ± 0.3 V
● DDR IO voltage: 1.8 V ± 0.1 V; 1.5 V ± 0.075 V
Operating
Temperature
Junction temperature: −40°C to +110°C
Packages
●
RZ/N1D:
– 400LFBGA, 17×17 mm, 0.8 mm pitch
– 324LFBGA, 15×15 mm, 0.8 mm pitch
● RZ/N1S
– 324LFBGA, 15×15 mm, 0.8 mm pitch
– 196LFBGA, 12×12 mm, 0.8 mm pitch
● RZ/N1L
196LFBGA, 12×12 mm, 0.8 mm pitch
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group Section 1 Overview
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Mar 29, 2019
1.2 SoC Block Diagram
Please refer to Section 1.3, Function Comparison per Device Family and Package about available functions
according to the package.
1.2.1 RZ/N1D
Figure 1.1 Block Diagram of RZ/N1D
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group Section 1 Overview
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Mar 29, 2019
1.2.2 RZ/N1S
Network-on-Chip
Memory Interfaces
NAND Flash
Controller
2× SD/SDIO/eMMC
Up to 2× QSPI
Embedded Memory
4 MB with ECC
Arm Cortex-A7 MPCore
L2 cache 128 KB
Arm Cortex-A7
500 MHz
FPU MMU GIC
16KB_D16KB_I
Peripherals
2× CAN
4× SPI Master
2× SPI Slave
8× UART
2× I
2
C
8/16/32 bits
parallel interface GPIOs
2× timer blocks
(6× 16b + 2× 32b)
System Peripherals
2× USB 2.0
LCD Controller
Mailbox
2× DMAC
Watchdog for CPU
Arm Cortex-M3
125 MHz
NVIC Debug
Analog
1
×
12bADC
1 Msps
RTC
R-IN Engine
HW-RTOS
Advanced 5port Switch
EtherCAT Slave Controller
SercosIII Slave Controller
2
×
Gb Ethernet MAC
2 MB with ECC
Ethernet Peripherals
HW-RTOS GMAC
Figure 1.2 Block Diagram of RZ/N1S
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group Section 1 Overview
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Mar 29, 2019
1.2.3 RZ/N1L
Network-on-Chip
R-IN Engine
Embedded Memory
4 MB with ECC
Peripherals
2× CAN
4× SPI Master
2× SPI Slave
8× UART
2× I
2
C
8 bits parallel
interface (slave)GPIOs
2× timer blocks
(6× 16b + 2× 32b)
System Peripherals
2× USB 2.0
2× DMAC
Watchdog for CPU
Memory Interfaces
NAND Flash
Controller
2× SD/SDIO/eMMC
1× QSPI
Arm Cortex-M3
125 MHz
NVIC Debug
Analog
1
×
12bADC
1 Msps
HW-RTOS
Advanced 5port Switch
EtherCAT Slave Controller
SercosIII Slave Controller
2
×
Gb Ethernet MAC
2 MB with ECC
Ethernet Peripherals
HW-RTOS GMAC
Figure 1.3 Block Diagram of RZ/N1L
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group Section 1 Overview
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Mar 29, 2019
1.3 Function Comparison per Device Family and Package
Table 1.2 Renesas CPU Subsystem Part Description
Hardware Features RZ/N1D RZ/N1S RZ/N1L
Package Type: 400BGA 324BGA 324BGA 196BGA 196BGA
Processor Unit Arm Cortex-A7 Dual Single ―
Arm Cortex-M3 Available
Memory Unit 2 MB with ECC Available
4 MB with ECC ― Available
DDR Memory Controller Available*1 ―
Quad SPI 1 ch 2 ch 1 ch*2
SDIO/SD/eMMC 2 ch
NAND Flash Available
Networking
elements
R-IN Engine & HWRTOS Available*5
Ethernet Port 5 ports 3 ports*3 5 ports 3 ports*3
Independent GMAC Up to 2 N/A*4 Up to 2 Up to 1*4
EtherCAT Slave Controller Available*6 *7
SercosIII Slave Controller Available*6 *7
Advanced 5port Switch 5 ports (4 + 1) 4 ports (3 + 1) 5 ports (4 + 1) 3 ports (2 + 1)*7
PRP Optional ― Available ―
HSR Switch*5 *6 Optional ―
Peripheral Group ADC 2 units 1 unit
RTC Available N/A
DMAC 2 ch
UART 8 ch
I2C 2 ch
Parallel bus Master & Slave*8 Available Slave only
USB Host & Function Available
Mailbox Available N/A
Watchdog for CA7 Available, 2 Available, 1 N/A
Watchdog for CM3 Available
SPI Master 4 ch
SPI Slave 2 ch
CAN 2 ch
LCDC Available N/A
Semaphore Available
Timer block 2 units
GPIO pin*9 170 132 160 95 95
Note 1. RZ/N1D-324 has 1 Chip Select and 1 ODT.
Note 2. RZ/N1S-196 and RZ/N1L have up to 2 chip selects.
Note 3. Please refer to Restriction of Ethernet Interface Modes chapter for more details about N/A port numbers.
Note 4. GMAC2 is available via A5PSW in RZ/N1D-324, RZ/N1S-196 and RZ/N1L.
Note 5. HW-RTOS and HSR are not available simultaneously.
Note 6. SERCOSIII, ETHERCAT and HSR function are not available simultaneously.
Note 7. A5PSW, SERCOSIII and ETHERCAT function are not available simultaneously in RZ/N1S-196 and RZ/N1L.
Note 8. RZ/N1D-324 is not able to use 32-bit mode. RZ/N1S-196 and RZ/N1L are only able to use 8-bit mode and 2 external wait
requests. RZ/N1S-196 is only able to use ALE serial mode in Master.
Note 9. Shared with peripheral signals.
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group Section 1 Overview
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Mar 29, 2019
1.4 List of Products
Table 1.3 List of Products
Name P/N Package(s) Main CPU PRP/HSR
RZ/N1D R9A06G032VGBG 400BGA Dual Cortex-A7 ―
R9A06G032VGBA 324BGA
R9A06G032NGBG 400BGA Dual Cortex-A7 PRP/HSR
RZ/N1S R9A06G033VGBA 196BGA Single Cortex-A7 ―
R9A06G033NGBG 324BGA Single Cortex-A7 PRP
RZ/N1L R9A06G034VGBA 196BGA Cortex-M3 ―
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group Section 1 Overview
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Mar 29, 2019
1.5 Pin Assignments
1.5.1 RZ/N1D BGA-400 Package
A B C D E F G H J K L M N P R T U V W Y
20 GND GPIO75 GPIO77 GPIO36 GPIO37 GPIO42 GPIO48 GPIO53 GPIO54 GPIO59 GPIO12 GPIO18 GPIO20 GPIO62 GPIO63 GPIO90 GPIO88 GPIO86 GPIO84 GND 20
19 GPIO78 GPIO76 GPIO74 GPIO68 GPIO38 GPIO41 GPIO45 GPIO51 GPIO56 GPIO58 GPIO13 GPIO17 GPIO64 GPIO106 GPIO91 GPIO89 GPIO87 GPIO85 GPIO93 GPIO82 19
18 GPIO30 GPIO79 GPIO73 GPIO71 GPIO66 GPIO39 GPIO44 GPIO47 GPIO52 GPIO55 GPIO19 GPIO15 GPIO22 GPIO102 GPIO107 GPIO96 GPIO95 GPIO100 GPIO80 GPIO81 18
17 GPIO27 GPIO32 GPIO34 GPIO69 GPIO70 GPIO67 GPIO40 GPIO46 GPIO49 GPIO57 GPIO16 GPIO21 GPIO104 GPIO99 GPIO98 GPIO97 GPIO105 GPIO103 GPIO92 GPIO83 17
16 GPIO24 GPIO28 GPIO29 GPIO129
GPIO128
GPIO72 GPIO65 GPIO43 GPIO50 GND GPIO14 GPIO23 GPIO108 GPIO101 VDD11_C
A7 GPIO120 GPIO109 GPIO118 GPIO94 GPIO117 16
15 GPIO6 GPIO8 GPIO31 GPIO33 GPIO35 GND GND GND RGMII5
_VDDQ
RGMII5
_VDDQ GND GND VDD33 GND VDD11_C
A7 GPIO125 GPIO126 GPIO121 GPIO116 GPIO119 15
14 GPIO5 GPIO9 GPIO10 GPIO26 RGMII3
_VDDQ
RGMII3
_VDDQ VDD33 RGMII4
_VDDQ
RGMII4
_VDDQ GND RGMII2
_VDDQ
RGMII2
_VDDQ VDD33 GND GPIO124 GPIO123 GPIO122 GPIO111 GPIO115 GPIO113 14
13 GPIO2 GPIO4 GPIO3 GPIO11 GPIO25 GND VDD11 GND VDD11 VDD11 GND VDD11 GND VDD33 GPIO127 JTAG
_TDO
JTAG
_TCK GPIO114 GPIO112 GPIO110 13
12 GPIO0 GPIO131 GPIO1 GPIO7 RGMII1
_VDDQ GND VDD11 GND GND GND GND GND VDD11 VDD33 GND JTAG
_TRST_N
JTAG
_TDI
JTAG
_TMS GPIO61 GPIO60 12
11 GPIO137
GPIO135 GPIO133
GPIO132
GPIO130
RGMII1
_VDDQ GND GND GND GND GND GND GND USB
_AVSS
USB
_RREF
USB
_AVDD
USB
_VBUS
MRESET
_N
MRESET
_OUT
USB
_GND 11
10 GPIO139
GPIO136 GPIO138
GPIO140
GPIO134
GND VDD33 GND GND GND GND GND VDD11 USB
_AVSS
USB
_GND
USB
_GND
USB
_GND
USB
_GND
USB
_DM1
USB
_DP1 10
9 GPIO141
GPIO143 GPIO147
GPIO144
CTRSTBY
B VDD33 VDD33 VDD11 GND GND GND GND VDD11 GND USB
_VD33
USB
_VD33
USB
_GND
USB
_GND
USB
_DM2
USB
_DP2 9
8 GPIO145
GPIO149 GPIO142
GPIO148
ANF_VDD
_PRG
RTC_VDD
33 GND VDD11 VDD11 DVSS DVDD VDD11 GND VDD33 ADC2
_AGND
ADC2
_AVDD
ADC2
_IN6
ADC2
_IN7
ADC2
_IN8
USB
_GND 8
7 RTC_XI GPIO146
RTC
_PWRGO
OD
GPIO152
GPIO150
GND VDD33 DVDDQ GND DVSS DVDD DVDDQ VDD33 TMC2 THMODE
ADC2
_VREFN
ADC2
_VREFP
ADC2
_IN3
ADC2
_IN2
ADC2
_IN4 7
6 RTC_XO
GPIO151 GPIO153
GPIO154
GPIO158
GND VDD33 GND DVDDQ DVDDQ DVDDQ DVDDQ GND CONFIG1
CONFIG0
ADC1
_AVDD
ADC1
_VREFP
ADC1
_IN8
ADC2
_IN1
ADC2
_IN0 6
5 GPIO155
GPIO157 GPIO159
GPIO163
GPIO162
DDR
_DQ6 GND GND GND DDR
_VREF GND DDR
_ADDR0 GND DDR
_ADDR5 CONFIG2
ADC1
_AGND
ADC1
_VREFN
ADC1
_IN4
ADC1
_IN6
ADC1
_IN7 5
4 GPIO160
GPIO156 GPIO167
GPIO165
GND DDR
_DQ0
DDR
_DQS_N0
DDR
_DQ7
DDR
_DQ5
DDR
_MZQ
DDR
_CS1
DDR
_ADDR12
DDR
_ADDR15
DDR
_BA0
DDR
_ADDR7
DDR
_ADDR1 TMC1 ADC1
_IN3
ADC1
_IN0
ADC1
_IN2 4
3 GPIO161
GPIO169 GPIO166
GND DDR
_DQ4
DDR
_DQS0
DDR
_DM0
DDR
_DQ1
DDR
_DQ3 GND DDR
_ADDR10
DDR
_RAS
DDR
_CAS
DDR
_ADDR3
DDR
_ADDR4
DDR
_ADDR9
DDR
_ADDR14
DDR
_RESET_
N
GND ADC1
_IN1 3
2 GPIO164
GPIO168 DDR
_DQ14
DDR
_DQ8
DDR
_DQ2
DDR
_DM1
DDR
_DQS_N1
DDR
_DQ9
DDR
_DQ15
DDR
_CLKP
DDR
_CLKEN
DDR
_WE
DDR
_ODT0
DDR
_BA2
DDR
_ADDR2
DDR
_ADDR11
DDR
_ADDR13
GND MCLK_XO
GND 2
1 GND GND DDR
_DQ12
DDR
_DQ10 GND DDR
_DQS1 GND DDR
_DQ11
DDR
_DQ13
DDR
_CLKN GND DDR
_CS0
DDR
_ODT1
DDR
_BA1 GND DDR
_ADDR6
DDR
_ADDR8 GND MCLK_XI GND 1
A B C D E F G H J K L M N P R T U V W Y
Figure 1.4 RZ/N1D Pinout BGA-400 (Top View)
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group Section 1 Overview
R01DS0323EJ0100 Rev.1.00 Page 16 of 25
Mar 29, 2019
1.5.2 RZ/N1D BGA-324 Package
A B C D E F G H J K L M N P R T U V
18 GND GPIO75 GPIO77 GPIO36 GPIO41 GPIO42 GPIO46 GPIO48 GPIO51 GPIO54 GPIO64 GPIO101 GPIO107 GPIO90 GPIO88 GPIO86 GPIO84 GND 18
17 GPIO78 GPIO76 GPIO74 GPIO66 GPIO39 GPIO44 GPIO47 GPIO52 GPIO53 GPIO56 GPIO108 GPIO99 GPIO91 GPIO89 GPIO87 GPIO85 GPIO93 GPIO82 17
16 GPIO79 GPIO69 GPIO72 GPIO68 GPIO37 GPIO40 GPIO45 GPIO50 GPIO57 GPIO58 GPIO106 GPIO96 GPIO97 GPIO95 GPIO120 GPIO100 GPIO80 GPIO81 16
15 GPIO30 GPIO33 GPIO73 GPIO70 GPIO67 GPIO38 GPIO43 GPIO49 GPIO55 GPIO102 GPIO104 GPIO98 GPIO105 VDD11_C
A7 GPIO125 GPIO103 GPIO92 GPIO83 15
14 GPIO35 GPIO28 GPIO31 GPIO128
GPIO71 GPIO65 RGMII4
_VDDQ GND GPIO59 GPIO62 GPIO63 GPIO109 GND VDD11_C
A7 GPIO124 GPIO126 GPIO94 GPIO115 14
13 GPIO29 GPIO32 GPIO34 GPIO129
VDD33 GND RGMII4
_VDDQ
RGMII5
_VDDQ
RGMII5
_VDDQ VDD33 VDD33 GND GND GPIO123 GPIO122 GPIO118 GPIO116 GPIO113 13
12 GPIO24 GPIO27 GPIO25 GPIO26 RGMII3
_VDDQ GND VDD11 GND GND VDD11 GND VDD11 VDD33 GPIO127 GPIO121 GPIO117 GPIO119 GPIO114 12
11 GPIO133 GPIO131
GPIO132
GPIO130
RGMII3
_VDDQ VDD33 GND GND GND GND GND VDD11 VDD33 JTAG
_TDO
JTAG
_TDI GPIO111 GPIO112 GPIO110 11
10 GPIO135 GPIO137
GPIO136
GPIO134
GND VDD11 GND GND GND GND GND USB
_AVSS GND JTAG
_TRST_N
JTAG
_TMS
JTAG
_TCK GPIO61 GPIO60 10
9 GPIO139 GPIO138
GPIO147
GPIO142
VDD33 VDD33 GND GND GND GND GND USB
_AVSS
USB
_RREF
USB
_AVDD
USB
_VBUS
MRESET
_N
MRESET
_OUT
USB
_GND 9
8 GPIO141 GPIO143
GPIO140
GPIO146
ANF_VDD
_PRG VDD33 GND GND DVSS DVDD VDD11 USB
_VD33
USB
_VD33
USB
_GND
USB
_GND
USB
_GND
USB
_DM1
USB
_DP1 8
7 GPIO145 GPIO149
GPIO144
CTRSTBY
B
RTC_VDD
33 VDD11 GND DVDDQ DVSS DVDD VDD11 GND VDD33 CONFIG0
USB
_GND
USB
_GND
USB
_DM2
USB
_DP2 7
6 RTC_XI GPIO148
GPIO150
RTC
_PWRGO
OD
GND VDD33 VDD11 DVDDQ DVDDQ DVDDQ DVDDQ VDD33 TMC2 ADC1
_AVDD
ADC1
_VREFP
ADC1
_IN6
ADC1
_IN8
USB
_GND 6
5 RTC_XO GPIO151
GPIO154
GND DDR
_DQ6 GND GND GND DDR
_VREF
DDR
_ADDR0 GND THMODE
TMC1 CONFIG2
ADC1
_AGND
ADC1
_VREFN
ADC1
_IN4
ADC1
_IN7 5
4 GPIO152 GPIO153
GND DDR
_DQ0
DDR
_DQS0
DDR
_DQ1
DDR
_DQ7
DDR
_MZQ GND DDR
_ADDR12
DDR
_BA0
DDR
_ADDR5
DDR
_ADDR7
DDR
_ADDR1 CONFIG1
ADC1
_IN1
ADC1
_IN2
ADC1
_IN0 4
3 GPIO155 DDR
_DQ14
DDR
_DQ4
DDR
_DQS_N0
DDR
_DM0
DDR
_DQ3
DDR
_DQ5 GND DDR
_ADDR10
DDR
_RAS
DDR
_ADDR15
DDR
_ADDR3
DDR
_ADDR4
DDR
_ADDR9
DDR
_ADDR14
DDR_
RESET_N
GND ADC1
_IN3 3
2 DDR
_DQ12
DDR
_DQ10
DDR
_DQ2
DDR
_DM1
DDR
_DQS_N1
DDR
_DQ9
DDR
_DQ15
DDR
_CLKP
DDR
_CLKEN
DDR
_WE
DDR
_CAS
DDR
_BA2
DDR
_ADDR2
DDR
_ADDR11
DDR
_ADDR13
GND MCLK_XO
GND 2
1 GND DDR
_DQ8 GND DDR
_DQS1 GND DDR
_DQ11
DDR
_DQ13
DDR
_CLKN GND DDR
_CS0
DDR
_ODT0
DDR
_BA1 GND DDR
_ADDR6
DDR
_ADDR8 GND MCLK_XI GND 1
A B C D E F G H J K L M N P R T U V
Figure 1.5 RZ/N1D Pinout BGA-324 (Top View)
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group Section 1 Overview
R01DS0323EJ0100 Rev.1.00 Page 17 of 25
Mar 29, 2019
1.5.3 RZ/N1S BGA-324 Package
A B C D E F G H J K L M N P R T U V
18 GND GPIO69 GND GPIO48 GPIO55 GPIO59 GPIO12 GPIO17 GPIO20 GND GPIO0 GPIO2 GPIO6 GND GPIO88 GPIO86 GPIO84 GND 18
17 GPIO67 GPIO68 GPIO70 GPIO50 GPIO51 GPIO57 GND GPIO14 GPIO19 GPIO21 GPIO1 GPIO3 GPIO8 GPIO90 GPIO89 GPIO87 GPIO85 GPIO93 17
16 GPIO66 GPIO65 GPIO64 GPIO71 GPIO53 GPIO49 GPIO56 GPIO13 GPIO18 GPIO23 GPIO5 GPIO7 GPIO9 GPIO153 GPIO91 GPIO81 GPIO82 GPIO80 16
15 GND GPIO62 GPIO63 GPIO72 GPIO52 GPIO54 GPIO58 GPIO15 GPIO16 GPIO22 GPIO4 GPIO11 GPIO10 GPIO154 GPIO152 GPIO151 GPIO92 GND 15
14 GPIO43 GPIO45 GPIO46 GPIO73 VDD33 VDD33 RGMII5
_VDDQ
RGMII5
_VDDQ
RGMII2
_VDDQ
RGMII2
_VDDQ
RGMII1
_VDDQ
RGMII1
_VDDQ VDD33 GPIO155 GPIO157 GPIO150 GPIO83 GPIO94 14
13 GPIO38 GPIO39 GPIO44 GPIO47 GND GND GND GND GND GND GND GND VDD33 GPIO156 GPIO158 GPIO159 MRESET
_OUT GND 13
12 GPIO36 GPIO37 GPIO41 GPIO42 RGMII4
_VDDQ GND VDD11 VDD11 VDD11 VDD11 VDD11 VDD11 GND GND GND MRESET
_N
MCLK
_XO
MCLK
_XI 12
11 GND GPIO34 GPIO33 GPIO40 RGMII4
_VDDQ GND VDD11 GND GND GND GND VDD11 PLL
_AVDD GND GND USB
_VBUS
USB
_GND
USB
_GND 11
10 GPIO32 GPIO35 GPIO31 GPIO30 RGMII3
_VDDQ GND VDD11 GND GND GND GND VDD11 PLL
_AGND
USB
_AVDD
USB
_RREF
USB
_GND
USB
_DM1
USB
_DP1 10
9 GPIO28 GPIO27 GPIO29 GPIO25 RGMII3
_VDDQ GND VDD11 GND GND GND GND VDD11 VDD33 USB
_VD33
USB
_VD33
USB
_GND
USB
_DM2
USB
_DP2 9
8 GPIO24 GPIO26 GPIO77 GND GND VDD33 VDD11 GND GND GND GND VDD11 GND ADC1
_AVDD
ADC1
_VREFN
ADC1
_IN7
USB
_GND
USB
_GND 8
7 GND GPIO79 GPIO76 GPIO74 GND VDD33 VDD11 VDD11 VDD11 VDD11 VDD11 VDD11 GND ADC1
_AGND
ADC1
_VREFP
ADC1
_IN2
ADC1
_IN8
ADC1
_IN6 7
6 GPIO61 GPIO78 GPIO75 GPIO133
GND VDD33 GND GND GND GND GND GND GND VDD33 TMC2 ADC1
_IN0
ADC1
_IN1
ADC1
_IN3 6
5 GPIO60 VDD33 GPIO149
RTC
_VDD33 GND GND VDD33 VDD33 VDD33 GND GND GND VDD33 VDD33 JTAG
_TRST_N
JTAG
_TDI
JTAG
_TMS
ADC1
_IN4 5
4 GND
ANF_VDD
_PRG
RTC_PWR
GOOD GPIO123
GPIO125
GPIO127
GPIO129 GPIO130 GPIO131 GPIO132 GPIO134 GPIO136 CTRSTBY
B CONFIG1
TMC1 JTAG
_TCK GPIO148 GND 4
3 RTC_XO GPIO120
GPIO121
GPIO122
GPIO124
GPIO126
GPIO128 GPIO106 GPIO109 GPIO112 GPIO114 GPIO135 THMODE
CONFIG0
JTAG_TD
O GPIO145 GPIO146 GPIO147 3
2 RTC_XI GPIO119
GPIO97 GPIO98 GPIO100
GPIO102
GPIO104 GPIO105 GPIO108 GPIO111 GPIO113 GPIO116 GPIO137 GPIO138 GPIO139 GPIO142 GPIO143 GPIO144 2
1 GND GPIO95 GPIO96 GND GPIO99 GPIO101
GPIO103 GND GPIO107 GPIO110 GND GPIO115 GPIO117 GPIO118 GND GPIO140 GPIO141 GND 1
A B C D E F G H J K L M N P R T U V
Figure 1.6 RZ/N1S Pinout BGA-324 (Top View)
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group Section 1 Overview
R01DS0323EJ0100 Rev.1.00 Page 18 of 25
Mar 29, 2019
1.5.4 RZ/N1S BGA-196 Package
A B C D E F G H J K L M N P
14 GND GPIO70 GND GPIO48 GPIO51 GPIO57 GND GPIO3 GPIO7 GPIO8 GND GPIO89 GPIO87 GND 14
13 GPIO64 GPIO68 GPIO71 GPIO50 GPIO49 GPIO56 GPIO0 GPIO2 GPIO6 GPIO90 GPIO86 GPIO84 GPIO81 GPIO93 13
12 GPIO63 GPIO67 GPIO72 GPIO52 GPIO54 GPIO58 GPIO1 GPIO5 GPIO9 GPIO88 GPIO91 GPIO82 GPIO80 GPIO83 12
11 GPIO66 GPIO65 GPIO69 GPIO53 GPIO55 GPIO59 GPIO4 GPIO11 GPIO10 VDD33 GPIO85 GPIO92 GPIO94 GND 11
10 GND GPIO45 GPIO62 GPIO73 VDD33 RGMII5
_VDDQ
RGMII5
_VDDQ
RGMII1
_VDDQ
RGMII1
_VDDQ GND VDD11 MRESET
_OUT
MCLK
_XO
MCLK
_XI 10
9 GPIO47 GPIO43 GPIO42 GPIO44 VDD11 GND VDD11 GND VDD11 PLL
_AVDD
PLL
_AGND
MRESET
_N
USB_VBU
S
USB
_GND 9
8 GPIO46 GPIO39 GPIO38 GPIO41 RGMII4
_VDDQ GND GND GND GND USB
_AVDD
USB
_RREF
USB
_GND
USB
_DM1
USB
_DP1 8
7 GND GPIO36 GPIO37 GPIO40 RGMII4
_VDDQ VDD11 GND GND VDD11 USB
_VD33
USB
_VD33
USB
_GND
USB
_DM2
USB
_DP2 7
6 GPIO61 GPIO77 GPIO79 GPIO76 VDD33 GND GND GND GND GND ADC1
_AVDD
ADC1
_VREFN
USB
_GND
USB
_GND 6
5 GPIO60 GPIO75 GPIO78 GPIO74 VDD11 GND VDD11 VDD11 GND VDD11 ADC1
_AGND
ADC1
_VREFP
ADC1
_IN8
ADC1
_IN7 5
4 GND RTC
_VDD33 VDD33 ANF_VDD
_PRG VDD33 GPIO105
GPIO107 GPIO112 VDD33 VDD33 TMC2 ADC1
_IN2
ADC1
_IN0
ADC1
_IN6 4
3 RTC
_XO
RTC_PWR
GOOD GPIO97 GPIO95 GPIO100 GPIO103
GPIO111 GPIO115 GPIO117
CTRSTBY
B CONFIG1
TMC1 ADC1
_IN4
ADC1
_IN3 3
2 RTC
_XI GPIO98 GPIO96 GPIO102
GPIO104 GPIO108
GPIO110 GPIO114 GPIO116 THMODE
CONFIG0
JTAG
_TCK
JTAG
_TMS
ADC1
_IN1 2
1 GND GPIO99 GPIO101
GND GPIO106 GPIO109
GND GPIO113 GPIO118 GND JTAG
_TDO
JTAG
_TRST_N
JTAG
_TDI GND 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Figure 1.7 RZ/N1S Pinout BGA-196 (Top View)
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group Section 1 Overview
R01DS0323EJ0100 Rev.1.00 Page 19 of 25
Mar 29, 2019
1.5.5 RZ/N1L BGA-196 Package
A B C D E F G H J K L M N P
14 GND GPIO70 GND GPIO48 GPIO51 GPIO57 GND GPIO3 GPIO7 GPIO8 GND GPIO89 GPIO87 GND 14
13 GPIO64 GPIO68 GPIO71 GPIO50 GPIO49 GPIO56 GPIO0 GPIO2 GPIO6 GPIO90 GPIO86 GPIO84 GPIO81 GPIO93 13
12 GPIO63 GPIO67 GPIO72 GPIO52 GPIO54 GPIO58 GPIO1 GPIO5 GPIO9 GPIO88 GPIO91 GPIO82 GPIO80 GPIO83 12
11 GPIO66 GPIO65 GPIO69 GPIO53 GPIO55 GPIO59 GPIO4 GPIO11 GPIO10 VDD33 GPIO85 GPIO92 GPIO94 GND 11
10 GND GPIO45 GPIO62 GPIO73 VDD33 RGMII5
_VDDQ
RGMII5
_VDDQ
RGMII1
_VDDQ
RGMII1
_VDDQ GND VDD11 MRESET
_OUT
MCLK
_XO
MCLK
_XI 10
9 GPIO47 GPIO43 GPIO42 GPIO44 VDD11 GND VDD11 GND VDD11 PLL
_AVDD
PLL
_AGND
MRESET
_N
USB_VBU
S
USB
_GND 9
8 GPIO46 GPIO39 GPIO38 GPIO41 RGMII4
_VDDQ GND GND GND GND USB
_AVDD
USB
_RREF
USB
_GND
USB
_DM1
USB
_DP1 8
7 GND GPIO36 GPIO37 GPIO40 RGMII4
_VDDQ VDD11 GND GND VDD11 USB
_VD33
USB
_VD33
USB
_GND
USB
_DM2
USB
_DP2 7
6 GPIO61 GPIO77 GPIO79 GPIO76 VDD33 GND GND GND GND GND ADC1
_AVDD
ADC1
_VREFN
USB
_GND
USB
_GND 6
5 GPIO60 GPIO75 GPIO78 GPIO74 VDD11 GND VDD11 VDD11 GND VDD11 ADC1
_AGND
ADC1
_VREFP
ADC1
_IN8
ADC1
_IN7 5
4 GND VDD33 VDD33 GND VDD33 GPIO105
GPIO107 GPIO112 VDD33 VDD33 TMC2 ADC1
_IN2
ADC1
_IN0
ADC1
_IN6 4
3 N.C. VDD33 GPIO97 GPIO95 GPIO100 GPIO103
GPIO111 GPIO115 GPIO117
CTRSTBY
B CONFIG1
TMC1 ADC1
_IN4
ADC1
_IN3 3
2 GND GPIO98 GPIO96 GPIO102
GPIO104 GPIO108
GPIO110 GPIO114 GPIO116 THMODE
CONFIG0
JTAG
_TCK
JTAG
_TMS
ADC1
_IN1 2
1 GND GPIO99 GPIO101
GND GPIO106 GPIO109
GND GPIO113 GPIO118 GND JTAG
_TDO
JTAG
_TRST_N
JTAG
_TDI GND 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Figure 1.8 RZ/N1L Pinout BGA-196 (Top View)
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group Section 1 Overview
R01DS0323EJ0100 Rev.1.00 Page 20 of 25
Mar 29, 2019
1.6 Package Dimensions
1.6.1 BGA-400 Package
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group Section 1 Overview
R01DS0323EJ0100 Rev.1.00 Page 21 of 25
Mar 29, 2019
1.6.2 BGA-324 Package
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group Section 1 Overview
R01DS0323EJ0100 Rev.1.00 Page 22 of 25
Mar 29, 2019
1.6.3 BGA-196 Package
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group REVISION HISTORY
R01DS0323EJ0100 Rev.1.00 Page 23 of 25
Mar 29, 2019
REVISION HISTORY RZ/N1D Group, RZ/N1S Group, RZ/N1L Group Datasheet
Description
Rev. Date Page Summary
0.50 Mar 13, 2017 First Edition issued
0.80 Oct 31, 2017 1 Features, revised
2 1.1, Table 1.1 (1/9), modified
3 1.1, Table 1.1 (2/9): General Purpose I/O Ports → IO Multiplexing, modified. IO
Multiplexing: Locations of IOs for Peripherals are selectable, added. DDR2/3 Controller:
Description, modified.
4 1,1, Table 1.1 (3/9): SD/SDIO/eMMC: Normal mode → Default mode, revised
8 1.1, Table 1.1 (7/9): SPI Master: ssi_clk → SPI_SCLK, corrected. SPI Slave: DMA Transmit
and Receive transfer enabling by external event (rising or falling edge), deleted. CAN: 2×
triggers, deleted.
9 1.1, Table 1.1 (8/9), modified
11 to 13 1.2, Figure 1.1, 1.2, and 1.3, corrected
14 1.3, corrected and modified
15 1.4, modified
16 1.5.1, VDD11 (R15 and R16) → VDD11_CA7
17 1.5.2, VDD11 (P14 and P15) → VDD11_CA7
16 and 17 1.5.1 and 1.5.2, TDO → JTAG_TDO, TCK → JTAG_TCK, TRST_N → JTAG_TRST_N, TDI
→ JTAG_TDI, TMS → JTAG_TMS, USB_AGND → USB_AVSS, USB_VDD33 →
USB_VD33, DGND → DVSS, XTAL → MCLK_XO, EXTAL → MCLK_XI
20 1.5.5, RTC_VDD33 → VDD33, RTC_PWRGOOD → VDD33, RTC_XO → N.C., RTC_XI →
GND, ANF_VDD_33V → VDD33, ANF_VDD_PRG → GND
0.90 Dec 28, 2017 1, 7 Features and 1.1 add trademarks
1, 2, 9, 11 to 14
Features, 1.1, 1.2, and 1.3, ARM → Arm, changed
1 Features, Low Power Features: revised. Advanced real-time Ethernet features: Advanced 5
(4 + 1) Port Switch (A5PSW): Optional bypass switch, deleted
2 1.1, Table 1.1 (1/9): Cortex-A7: Dynamic frequency → Clock frequency scaling, changed.
Cortex-A7 and Cortex-M3: Unaligned memory access supported, deleted
3 1.1, Table 1.1 (2/9): DMAC: Undirectional transfer supported, deleted
3 1.1, Table 1.1 (2/9): MSEBI: Address/data/control-data are multiplexed on data bus, added
3 1.1, Table 1.1 (2/9): DDR2/3 Controller: Programmable output slope in DDR2/3 and
configurable on die termination → Programmable on die termination, modified.
4 1.1, Table 1.1 (3/9): QSPI: revised
4 1.1, Table 1.1 (3/9): SD/SDIO/eMMC: Designed to work with I/O cards, read-
only cards, and
read/write cards, Variable-length data transfers, Password protection of cards, deleted
7 1.1, Table 1.1 (6/9): USB2.0 HOST: 1 dedicated port → 1 dedicated port + 1 configurable
port (Host or Function), revised
7 1.1, Table 1.1 (6/9): UART 4, 5, 6, 7, 8: Same as UART 1, 2, 3 with following features → In
addition to UART 1, 2, 3, the following function is available, modified
8 1.1, Table 1.1 (7/9): SPI 1, 2, 3, 4: Programmable RXD sampling logic with RXD sampling
delays of up to 64 SPI_SCLK cycles → Programmable RXD sampling logic, modified
8 1.1, Table 1.1 (7/9): I2C 1, 2: Handles bit and byte waiting at all bus speeds, deleted
9 1.1, Table 1.1 (8/9): LCD Controller: description about resolutions, revised
9 1.1, Table 1.1 (8/9): Clock Monitoring: from the PLL circuit or low speed on-chip oscillator →
from the PLL circuit or on-chip oscillator, modified
11 1.2, description, added
11 to 13 1.2, Figure 1.1 to 1.3, modified
16 to 19 1.5.1 to 1.5.4, ANF_VDD_33V → VDD33, modified
RZ/N1D Group, RZ/N1S Group, RZ/N1L Group REVISION HISTORY
R01DS0323EJ0100 Rev.1.00 Page 24 of 25
Mar 29, 2019
Description
Rev. Date Page Summary
0.95 Oct 19, 2018 All All sections, spelling, syntax errors and appearances are corrected, and expressions are
modified properly
1 Beginning of product overview, description modified
1 Features, DMA (2 × DMA with 16 channels → 2 × DMA with 8 channels each), description
modified
1 Features, Timer (6 × 16 bits + 2 × 32 bits → 16bit × 6ch, 32bit × 2ch), expression modified
1 Features, ADC (ADC @ 1 MHz → ADC (up to 1 MSPS)), description modified
1 Features, MSEBI (Parallel Bus Interface), description added
1 Features, Complement part (EtherCAT trademark), description modified
2 1.1 Outline of Specifications, Table 1.1 Outline of Specifications (1/8), CPU (16 KB/16 KB
→ 16 KB (instruction)/16 KB (data)), expression modified
2 1.1 Outline of Specifications, Table 1.1 Outline of Specifications (1/8), Watchdog,
description modified
3 1.1 Outline of Specifications, Table 1.1 Outline of Specifications (2/8), Semaphore,
description added
3 1.1 Outline of Specifications, Table 1.1 Outline of Specifications (2/8), DDR2/3 Controller,
description added
4 1.1 Outline of Specifications, Table 1.1 Outline of Specifications (3/8), Quad SPI (QSPI),
description added
4 1.1 Outline of Specifications, Table 1.1 Outline of Specifications (3/8), SD/SDIO/eMMC
(eMMC card interface → eMMC interface, ADMA → ADMA2), description modified
4 1.1 Outline of Specifications, Table 1.1 Outline of Specifications (3/8), R-IN Engine,
description modified
5 1.1 Outline of Specifications, Table 1.1 Outline of Specifications (4/8), Advanced 5 Port
Switch, description modified
6 1.1 Outline of Specifications, Table 1.1 Outline of Specifications (5/8), SercosIII Slave
Controller, description modified
7 1.1 Outline of Specifications, Table 1.1 Outline of Specifications (6/8), Independent GMAC,
description modified
8 1.1 Outline of Specifications, Table 1.1 Outline of Specifications (7/8), CAN 1, 2 (with record
of bit → with data of bit), description modified
8 1.1 Outline of Specifications, Table 1.1 Outline of Specifications (7/8), General Purpose
Timers, expression modified
9 1.1 Outline of Specifications, Table 1.1 Outline of Specifications (8/8), Power Supply
Voltage (3.3V → 3.3 V ± 0.3 V, 1.8 V; 1.5 V → 1.8 V ± 0.1 V; 1.5 V ± 0.075 V), others,
description modified
13 1.3 Function Comparison per Device Family and Package, Table 1.2 Renesas CPU
Subsystem Part Description (Peripherals SoC → Peripheral Group), others, description
modified
20 1.6 Package Dimensions, 1.6.1 BGA-400 Package, figure modified
21 1.6 Package Dimensions, 1.6.2 BGA-324 Package, figure modified
22 1.6 Package Dimensions, 1.6.3 BGA-196 Package, figure modified
1.00 Mar 29, 2019 All All sections, spelling, syntax errors and appearances are corrected, and expressions are
modified properly
14 1.4 List of Products, Table 1.3 List of Products, RZ/N1D, description modified
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Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics Corporation
TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan
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Tel: +60-3-5022-1288, Fax: +60-3-5022-1290
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No.777C, 100 Feet Road, HAL 2nd Stage, Indiranagar, Bangalore 560 038, India
Tel: +91-80-67208700
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17F, KAMCO Yangjae Tower, 262, Gangnam-daero, Gangnam-gu, Seoul, 06265 Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5338
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© 2019 Renesas Electronics Corporation. All rights reserved.
Colophon 8.0
(Rev.4.0-1 November 2017)
Notice
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the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by
you or third parties arising from the use of these circuits, software, or information.
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