2002-2012 Microchip Technology Inc. DS21703K-page 1
24AA16/24LC16B
Device Selection Table
Features:
Single Supply with Operation down to 1.7V
for 24AA16 Devices, 2.5V for 24LC16B Devices
Low-Power CMOS Technology:
- Active current 1 mA, typical
- Standby current, 1 A, typical
2-Wire Serial Interface, I2C™ Compatible
Schmitt Trigger inputs for Noise Suppression
Output Slope Control to eliminate Ground Bounce
100 kHz and 400 kHz Clock Compatibility
Page Write Time 5 ms Max.
Self-Timed Erase/Write Cycle
16-Byte Page Write Buffer
Hardware Write-Protect
ESD Protection > 4,000V
More than 1 Million Erase/Write Cycles
Data Retention > 200 Years
Factory Programming Available
Packages include 8-lead PDIP, SOIC, TSSOP,
MSOP, DFN, TDFN, 5-lead SOT-23 and Chip Scale
Pb-Free and RoHS Compliant
Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Description:
The Microchip Technology Inc. 24AA16/24LC16B
(24XX16*) is a 16 Kbit Electrically Erasable PROM.
The device is organized as eight blocks of 256 x 8-bit
memory with a 2-wire serial interface. Low-voltage
design permits operation down to 1.7V with standby
and active currents of only 1 A and 1 mA,
respectively. The 24XX16 also has a page write
capability for up to 16 bytes of data. The 24XX16 is
available in the standard 8-pin PDIP, surface mount
SOIC, TSSOP, 2x3 DFN, 2x3 TDFN and MSOP pack-
ages, and is also available in the 5-lead SOT-23, and
Chip Scale packages.
Block Diagram
Part
Number
VCC
Range
Max. Clock
Frequency
Temp.
Ranges
24AA16 1.7-5.5 400 kHz(1) I
24LC16B 2.5-5.5 400 kHz I, E
Note 1: 100 kHz for VCC <2.5V.
HV
EEPROM
Array
Page
YDEC
XDEC
Sense Amp.
Memory
Control
Logic
I/O
Control
Logic
I/O
WP
SDA
SCL
VCC
VSS
R/W Control
Latches
Generator
A0
A1
A2
VSS
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
PDIP/MSOP/SOIC/TSSOP DFN/TDFN
A0
A1
A2
VSS
WP
SCL
SDA
VCC
8
7
6
5
1
2
3
4
SOT-23
1
2
34
5WP
VCC
SCL
VSS
SDA
Note 1: Pins A0, A1 and A2 are not used by the 24XX16 (no internal connections).
2: Available in I-temp, “AA” only.
CS (Chip Scale)(1)
12
3
45
VCC
WP
SDA
SCL
VSS
(Top Down View,
Balls Not Visible)
16K I2C Serial EEPROM
*24XX16 is used in this document as a generic part number for the 24AA16/24LC16B devices.
24AA16/24LC16B
DS21703K-page 2 2002-2012 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins  4 kV
TABLE 1-1: DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V
Automotive (E): T
A = -40°C to +125°C, VCC = +2.5V to +5.5V
Param.
No. Symbol Characteristic Min. Typ. Max. Units Conditions
D1 VIH WP, SCL and SDA pins ——
D2 High-level input voltage 0.7 VCC ——V
D3 VIL Low-level input voltage 0.3 VCC V—
D4 VHYS Hysteresis of Schmitt
Trigger inputs
.05 VCC ——V(Note 1)
D5 VOL Low-level output voltage 0.40 V IOL = 3.0 mA, VCC = 2.5V
D6 ILI Input leakage current ——±1AVIN = VSS or VCC
D7 ILO Output leakage current ——±1AVOUT = VSS or VCC
D8 CIN,
COUT
Pin capacitance
(all inputs/outputs)
——10pFVCC = 5.0V (Note 1)
T
A = 25°C, FCLK = 1 MHz
D9 ICC write Operating current —— 3mAVCC = 5.5V, SCL = 400 kHz
D10 ICC read 0.01 1 mA
D11 ICCS Standby current
0.3
0.01
1
5
A
A
Industrial
Automotive
SDA = SCL = VCC
WP = VSS
Note 1: This parameter is periodically sampled and not 100% tested.
2: Typical measurements taken at room temperature.
2002-2012 Microchip Technology Inc. DS21703K-page 3
24AA16/24LC16B
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V
Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V
Param.
No. Symbol Characteristic Min. Max. Units Conditions
1F
CLK Clock frequency
400
100
kHz 2.5V VCC 5.5V
1.7V VCC 2.5V (24AA16)
2THIGH Clock high time 600
4000
ns 2.5V VCC 5.5V
1.7V VCC 2.5V (24AA16)
3T
LOW Clock low time 1300
4700
ns 2.5V VCC 5.5V
1.7V VCC 2.5V (24AA16)
4TRSDA and SCL rise time
(Note 1)
300
1000
ns 2.5V VCC 5.5V (Note 1)
1.7V VCC 2.5V (24AA16)
(Note 1)
5T
FSDA and SCL fall time 300 ns (Note 1)
6T
HD:STA Start condition hold time 600
4000
ns 2.5V VCC 5.5V
1.7V VCC 2.5V (24AA16)
7TSU:STA Start condition setup time 600
4700
ns 2.5V VCC 5.5V
1.7V VCC 2.5V (24AA16)
8THD:DAT Data input hold time 0 ns (Note 2)
9TSU:DAT Data input setup time 100
250
ns 2.5V VCC 5.5V
1.7V VCC 2.5V (24AA16)
10 TSU:STO Stop condition setup time 600
4000
ns 2.5V VCC 5.5V
1.7V VCC 2.5V (24AA16)
11 TAA Output valid from clock
(Note 2)
900
3500
ns 2.5V VCC 5.5V
1.7V VCC 2.5V (24AA16)
12 TBUF Bus free time: Time the bus
must be free before a new
transmission can start
1300
4700
ns 2.5V VCC 5.5V
1.7V VCC 2.5V (24AA16)
13 TOF Output fall time from VIH
minimum to VIL maximum
20+0.1CB
250
250
ns 2.5V VCC 5.5V
1.7V VCC 2.5V (24AA16)
14 TSP Input filter spike suppression
(SDA and SCL pins)
—50ns(Notes 1 and 3)
15 TWC Write cycle time
(byte or page)
—5ms
16 Endurance 1M cycles 25°C, (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site
at www.microchip.com.
24AA16/24LC16B
DS21703K-page 4 2002-2012 Microchip Technology Inc.
FIGURE 1-1: BUS TIMING DATA
FIGURE 1-2: BUS TIMING START/STOP
7
524
8910
12
11
14
6
SCL
SDA
IN
SDA
OUT
3
76
D4
10
Start Stop
SCL
SDA
2002-2012 Microchip Technology Inc. DS21703K-page 5
24AA16/24LC16B
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
2.1 Serial Address/Data Input/Output
(SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. Since it is an open-
drain terminal, the SDA bus requires a pull-up resistor
to VCC (typical 10 k for 100 kHz, 2 k for 400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating Start and Stop conditions.
2.2 Serial Clock (SCL)
The SCL input is used to synchronize the data transfer
to and from the device.
2.3 Write-Protect (WP)
The WP pin must be connected to either VSS or VCC.
If tied to VSS, normal memory operation is enabled
(read/write the entire memory 000-7FF).
If tied to VCC, write operations are inhibited. The entire
memory will be write-protected. Read operations are
not affected.
2.4 A0, A1, A2
The A0, A1 and A2 pins are not used by the 24XX16.
They may be left floating or tied to either VSS or VCC.
Name PDIP SOIC TSSOP DFN TDFN MSOP SOT-23 CS Description
A0 1 1 1 1 1 1 Not Connected
A1 2 2 2 2 2 2 Not Connected
A2 3 3 3 3 3 3 Not Connected
VSS 4 4 4 4 4 4 2 2 Ground
SDA 5 5 5 5 5 5 3 5 Serial Address/Data I/O
SCL 6 6 6 6 6 6 1 4 Serial Clock
WP 7 7 7 7 7 7 5 3 Write-Protect Input
VCC 8 8 8 8 8 8 4 1 +1.7V to 5.5V Power Supply
24AA16/24LC16B
DS21703K-page 6 2002-2012 Microchip Technology Inc.
3.0 FUNCTIONAL DESCRIPTION
The 24XX16 supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, while a device
receiving data is defined as a receiver. The bus has to
be controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24XX16 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1 Bus Not Busy (A)
Both data and clock lines remain high.
4.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3 Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between Start and Stop conditions is
determined by the master device and is, theoretically,
unlimited (although only the last sixteen will be stored
when doing a write operation). When an overwrite does
occur it will replace data in a first-in first-out (FIFO)
fashion.
4.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable-low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XX16) will leave the data line
high to enable the master to generate the Stop
condition.
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Note: The 24XX16 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
SCL
SDA
(A) (B) (D) (D) (A)(C)
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
2002-2012 Microchip Technology Inc. DS21703K-page 7
24AA16/24LC16B
5.0 DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consists of a four-bit control code.
For the 24XX16, this is set as ‘1010’ binary for read
and write operations. The next three bits of the control
byte are the block-select bits (B2, B1, B0). They are
used by the master device to select which of the eight
256 word-blocks of memory are to be accessed.
These bits are in effect the three Most Significant bits
(MSb) of the word address. It should be noted that the
protocol limits the size of the memory to eight blocks
of 256 words, therefore, the protocol can support only
one 24XX16 per system.
The last bit of the control byte defines the operation to
be performed. When set to ‘1’, a read operation is
selected. When set to ‘0, a write operation is selected.
Following the Start condition, the 24XX16 monitors the
SDA bus, checking the device type identifier being
transmitted and, upon receiving a ‘1010’ code, the
slave device outputs an Acknowledge signal on the
SDA line. Depending on the state of the R/W bit, the
24XX16 will select a read or write operation.
FIGURE 5-1: CONTROL BYTE
ALLOCATION
FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS
Operation Control
Code Block Select R/W
Read 1010 Block Address 1
Write 1010 Block Address 0
10 10B2 B1 B0 R/W ACK
Start Bit
Read/Write Bit
S
Slave Address
Acknowledge Bit
Control Code
Block
Select
Bits
1 010B
2
B
1B
0R/W A
7
A
0
••••
Control Byte Address Low Byte
Control
Code
Block
Select
bits
24AA16/24LC16B
DS21703K-page 8 2002-2012 Microchip Technology Inc.
6.0 WRITE OPERATION
6.1 Byte Write
Following the Start condition from the master, the
device code (4 bits), the block address (3 bits) and the
R/W bit, which is a logic-low, is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will
follow once it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte transmit-
ted by the master is the word address and will be
written into the Address Pointer of the 24XX16. After
receiving another Acknowledge signal from the
24XX16, the master device will transmit the data word
to be written into the addressed memory location. The
24XX16 acknowledges again and the master
generates a Stop condition. This initiates the internal
write cycle and, during this time, the 24XX16 will not
generate Acknowledge signals (Figure 6-1).
6.2 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24XX16 in the same way as
in a byte write. However, instead of generating a Stop
condition, the master transmits up to 16 data bytes to
the 24XX16, which are temporarily stored in the on-
chip page buffer and will be written into memory once
the master has transmitted a Stop condition. Upon
receipt of each word, the four lower-order Address
Pointer bits are internally incremented by ‘1’. The
higher-order 7 bits of the word address remain
constant. If the master should transmit more than 16
bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received an
internal write cycle will begin (Figure 6-2).
6.3 Write Protection
The WP pin allows the user to write-protect the entire
array (000-7FF) when the pin is tied to VCC. If tied to
VSS the write protection is disabled.
FIGURE 6-1: BYTE WRITE
Note: Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page-size’) and end at addresses that are
integer multiples of [page size – 1]. If a
page write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
S P
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
S
T
O
P
Control
Byte
Word
Address Data
A
C
K
A
C
K
A
C
K
1010B2 B1 B0 0
Block
Select
Bits
2002-2012 Microchip Technology Inc. DS21703K-page 9
24AA16/24LC16B
FIGURE 6-2: PAGE WRITE
S P
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
Control
Byte
Word
Address (n) Data (n) Data (n + 15)
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Data (n + 1)
B1
B2 B0
10100
Block
Select
Bits
24AA16/24LC16B
DS21703K-page 10 2002-2012 Microchip Technology Inc.
7.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a write
command has been issued from the master, the device
initiates the internally-timed write cycle and ACK polling
can then be initiated immediately. This involves the
master sending a Start condition followed by the control
byte for a write command (R/W = 0). If the device is still
busy with the write cycle, no ACK will be returned. If the
cycle is complete, the device will return the ACK and
the master can then proceed with the next read or write
command. See Figure 7-1 for a flow diagram of this
operation.
FIGURE 7-1: ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes
2002-2012 Microchip Technology Inc. DS21703K-page 11
24AA16/24LC16B
8.0 READ OPERATION
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to1’. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1 Current Address Read
The 24XX16 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by ‘1’. Therefore, if the previous access
(either a read or write operation) was to address n, the
next current address read operation would access data
from address n + 1. Upon receipt of the slave address
with R/W bit set to ‘1’, the 24XX16 issues an acknowl-
edge and transmits the 8-bit data word. The master will
not acknowledge the transfer, but does generate a Stop
condition and the 24XX16 discontinues transmission
(Figure 8-1).
8.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is accomplished by sending the word
address to the 24XX16 as part of a write operation.
Once the word address is sent, the master generates a
Start condition following the acknowledge. This
terminates the write operation, but not before the inter-
nal Address Pointer is set. The master then issues the
control byte again, but with the R/W bit set to a ‘1’. The
24XX16 will then issue an acknowledge and transmit
the 8-bit data word. The master will not acknowledge
the transfer, but does generate a Stop condition and the
24XX16 will discontinue transmission (Figure 8-2).
8.3 Sequential Read
Sequential reads are initiated in the same way as a
random read, except that once the 24XX16 transmits
the first data byte, the master issues an acknowledge
as opposed to a Stop condition in a random read. This
directs the 24XX16 to transmit the next sequentially-
addressed 8-bit word (Figure 8-3).
To provide sequential reads, the 24XX16 contains an
internal Address Pointer that is incremented by one
upon completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
8.4 Noise Protection
The 24XX16 employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 1.5V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
FIGURE 8-1: CURRENT ADDRESS READ
SP
Bus Activity
Master
SDA Line
Bus Activity
S
T
O
P
Control
Byte Data (n)
A
C
K
N
o
A
C
K
S
T
A
R
T
1010 1
B2 B1 B0
Block
Select
Bits
24AA16/24LC16B
DS21703K-page 12 2002-2012 Microchip Technology Inc.
FIGURE 8-2: RANDOM READ
FIGURE 8-3: SEQUENTIAL READ
S P
S
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
S
T
O
P
Control
Byte
A
C
K
Word
Address (n)
Control
Byte
S
T
A
R
T
Data (n)
A
C
K
A
C
K
N
o
A
C
K
10 10 0
B2B1B0 11
001
B2 B1B0
Block
Select
Bits
Block
Select
Bits
P
Bus Activity
Master
SDA Line
Bus Activity
S
T
O
P
Control
Byte
A
C
K
N
o
A
C
K
Data (n) Data (n + 1) Data (n + 2) Data (n + x)
A
C
K
A
C
K
A
C
K
1
2002-2012 Microchip Technology Inc. DS21703K-page 13
24AA16/24LC16B
9.0 PACKAGING INFORMATION
9.1 Package Marking Information
XXXXXXXX
T/XXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Lead SOIC (3.90 mm) Example:
XXXXXXXT
XXXXYYWW
NNN
8-Lead TSSOP Example:
24LC16B
I/P 13F
0527
24LC16BI
SN 0527
13F
8-Lead MSOP Example:
XXXX
TYWW
NNN
XXXXXT
YWWNNN
4L16
I527
13F
4L16I
52713F
5-Lead SOT-23 Example:
XXNN B53F
8-Lead 2x3 DFN Example:
254
527
13
XXX
YWW
NN
3
e
3
e
8-Lead 2x3 TDFN Example:
A54
527
13
XXX
YWW
NN
24AA16/24LC16B
DS21703K-page 14 2002-2012 Microchip Technology Inc.
Part Number
1st Line Marking Codes
TSSOP MSOP
SOT-23 DFN TDFN
I Temp. E Temp. I Temp. E Temp. I Temp. E Temp.
24AA16 4A16 4A16T B5NN 251 A51
24LC16B 4L16 4L16T M5NN N5NN 254 255 A54 A55
Note: T = Temperature grade (I, E)
NN = Alphanumeric traceability code
5-Lead Chip Scale
XW
Example:
57
Legend: XX...X Part number or part number code
T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
Note: For very small packages with no room for the Pb-free JEDEC designator
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
Note: Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.
*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.
2002-2012 Microchip Technology Inc. DS21703K-page 15
24AA16/24LC16B


 
 
 
 

 

 
   

 
 
    
  
   
    
   
   
   
    
   
  
N
E1
NOTE 1
D
123
A
A1
A2
L
b1
b
e
E
eB
c
   
24AA16/24LC16B
DS21703K-page 16 2002-2012 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2002-2012 Microchip Technology Inc. DS21703K-page 17
24AA16/24LC16B
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA16/24LC16B
DS21703K-page 18 2002-2012 Microchip Technology Inc.
 ! ""#$%& !'
 

2002-2012 Microchip Technology Inc. DS21703K-page 19
24AA16/24LC16B
() )"* ! (+%+( !

 
 
 
 
 
 

 
   

 
 
    
   
 
    
   
   
  
  
  
  
D
N
E
E1
NOTE 1
12
b
e
c
A
A1
A2
L1 L
φ
   
24AA16/24LC16B
DS21703K-page 20 2002-2012 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2002-2012 Microchip Technology Inc. DS21703K-page 21
24AA16/24LC16B
,$*-.'/00%&,

 
 
 
 
 
 
 

 
   

 
   
    
 
 
 
   
   
   
   
 
D
N
E
NOTE 1
12
EXPOSED PAD
NOTE 1
21
D2
K
L
E2
N
e
b
A3 A1
A
NOTE 2
BOTTOM VIEW
TOP VIEW
   
24AA16/24LC16B
DS21703K-page 22 2002-2012 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging