Universe II™ User Manual
Spring 1998
http://www.tundra.com
The information in this document is subject to change without notice and should not be construed as a
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Universe II™ User Manual
Copyright 1998, Tundra Semiconductor Corporation
All right s reserv ed.
Document: 8091142.MD300.01
Printed in Canada
Tundra and Tundra logo are registered trademarks of Tundra Semic onductor Corporation. Universe II,
Univ erse, SC V6 4, Trooper II and QS pan are trademarks of Tundra Semiconductor Corpo ration. BI-Mode is
i s a r egistered trade mark of DY-4 Sys tems, I n c.
iii
Overview
Chapter 1 Introduction
Chapter 2 Functional Description
Chapter 3 Description of Signals
Chapter 4 Signals and DC Characteristics
Appendix A Registers
Append i x B Performance
Appendix C Typical Applications
Appendix D Reliability Prediction
Appendix E Cycle Mapping
Appendix F O perating and Storage Conditions
Appendix G Mechanical and Ordering Information
iv
v
Table of Contents
1 Introduction.......................................................................................................... 1-1
1.1 Features................................................................................................... 1-1
1.2 Benefits of the Universe II...................................................................... 1-2
1.3 Past and Future of the Universe.............................................................. 1-3
1.4 About This Document....................... ...................................................... 1-4
1.5 Universe II Tec hnical Support................................................................ 1-5
1.6 Universe II Documentation..................................................................... 1-5
1.7 Conventions ............................................................................................ 1-6
1.7.1 Signals.................................................................................... 1-6
1.7.2 Symbols.................................................................................. 1-6
1.7.3 Terminology........................................................................... 1-7
2 Functional Description......................................................................................... 2-1
2.1 Architectural Overview........................................................................... 2-2
2.1.1 VMEbu s In ter face...... ..... .... .... .... .... .... .... .... .... .... .... .... .... .... .. 2- 2
2.1.1.1 Universe II as VMEbus Slave......................................... 2-2
2.1.1.2 Universe II as VMEbus Master ...................................... 2-3
2.1.2 PCI Bus Interface ................................................................... 2-4
2.1.2.1 Universe II as PCI Target ............................................... 2-4
2.1.2.2 Universe II as PCI Master............................................... 2-4
2.1.3 Interrupter and Interrupt Handler...........................................2-4
2.1.3.1 Interrupter ....................................................................... 2-4
2.1.3.2 VMEbus Interrupt Handling........................................... 2-5
2.1.4 DMA Controller..................................................................... 2-5
2.2 VMEbus Interface................................................................................... 2-6
2.2.1 VMEbus Requester ................................................................ 2-6
2.2.1.1 Internal Arbitration for VMEbus Requests..................... 2-6
2.2.1.2 Request Modes................................................................ 2-7
2.2.1.3 VMEbus Release............................................................. 2-8
vi
2.2.2 Universe II as VMEbus Master..............................................2-9
2.2.2.1 Addressing Capabilities.................................................. 2-9
2.2.2.2 Data Transfer Capabilities ...... .......... .......... .......... ........ 2-10
2.2.2.3 Cycle Terminations....................................................... 2-13
2.2.3 Universe as VMEbus Slave.................................................. 2-13
2.2.3.1 Coupled Transfers. ........ ................... .......... .......... ......... 2-14
2.2.3.2 Posted Writes ................................................................ 2-15
2.2.3.3 Prefetched Block Reads................................................ 2-16
2.2.3.4 VMEbus Lock Commands (ADOH Cycles)................. 2-18
2.2.3.5 VMEbus Read-Modify-Write Cycles (RMW Cycles) . . 2-19
2.2.3.6 Register Accesses.......................................................... 2-19
2.2.3.7 Location Monitors......................................................... 2-19
2.2.3.8 Generating PCI Configuration Cycles.......................... 2-20
2.2.4 VMEbus Configuration........................................................ 2-23
2.2.4.1 First Slot Detector......................................................... 2-23
2.2.4.2 VMEbus Register Access at Power-up......................... 2-23
2.2.5 Au t o matic Slo t Id en tific at ion... .... .... .... .... .... .... .... .... .... .... .... 2-24
2.2.5.1 Auto Slot ID: VME64 Specified................................... 2-24
2.2.5.2 Auto-ID: A Proprietary Tundra Method....................... 2-25
2.2.6 S y st e m Co n t rol ler Fu n c t i ons...... .... .... .... .... .... .... .... .... .... .... .. 2- 2 6
2.2.6.1 System Clock Driver..................................................... 2-26
2.2.6.2 VMEbus Arbiter............................................................ 2-27
2.2.6.3 IACK Daisy-Chain Driver Module............................... 2-27
2.2.6.4 VMEbus Time-out ........................................................ 2-28
2.2.7 BI-Mode .............................................................................. 2-28
2.3 PCI Bus Interface.................................................................................. 2-30
2.3.1 PCI Cycles—Overview........................................................ 2-30
2.3.1.1 32-Bit Versus 64-Bit PCI ............................................. 2-30
2.3.1.2 PCI Bus Request and Parking....................................... 2-31
2.3.1.3 Address Phase............................................................... 2-31
2.3.1.4 Data Transfer ................................................................ 2-33
vii
2.3.1.5 Termination Phase ........................................................ 2-33
2.3.1.6 Parity Checking............................................................. 2-34
2.3.2 Universe II as PCI Master.................................................... 2-35
2.3.2.1 PCI Burst Transfers ...................................................... 2-36
2.3.2.2 Termination................................................................... 2-37
2.3.2.3 Parity............................................................................. 2-37
2.3.3 Universe II as PCI Targe t.....................................................2-38
2.3.3.1 Overview....................................................................... 2-38
2.3.3.2 Data Transfer ................................................................ 2-39
2.3.3.3 Coupled Transfers............................ .......... .......... ......... 2-42
2.3.3.4 Posted Writes ................................................................ 2-44
2.3.3.5 The Special Cycle Generator ........................................ 2-45
2.3.3.6 Using the VOWN bit .................................................... 2-48
2.3.3.7 Terminations................................................................. 2-49
2.4 Slave Imag e Programming........... .... . .... ...... .... ...... .... ...... .... ...... .... ...... .. 2-50
2.4.1 VME Slave Images .............................................................. 2-50
2.4.1.1 VMEbus Fields ............................................................. 2-51
2.4.1.2 PCI Bus Fields .............................................................. 2-51
2.4.1.3 Control Fields ............................................................... 2-52
2.4.2 PCI Bus Target Images ........................................................ 2-53
2.4.2.1 PCI Bus Fields .............................................................. 2-54
2.4.2.2 VMEbus Fields ............................................................. 2-54
2.4.2.3 Control Fields ............................................................... 2-55
2.4.3 Special PCI Target Image ....................................................2-55
2.5 Bus Error Handling............................................................................... 2-58
2.5.1 Coupled Cycles ....................................................................2- 58
2.5.2 Decoupled Transactions....................................................... 2-58
2.5.2.1 Posted Writes ................................................................ 2-58
2.5.2.2 Prefetched Reads........................................................... 2-60
2.5.2.3 DMA Errors .................................................................. 2-60
2.5.2.4 Parity Errors.................................................................. 2-60
viii
2.6 Interrupt Generation.............................................................................. 2-62
2.6.1 PCI Interrupt Generation...................................................... 2-63
2. 6 .2 V MEbu s In ter ru p t Ge n e ra t i o n. .... .... .... .... .............................2-65
2.7 Interrupt Handling................................................................................. 2-68
2.7.1 PCI Interrupt Handling......................................................... 2-68
2.7.2 VMEbus Interrupt Handling................................................. 2-68
2.7.2.1 Bus Error During VMEbus IACK Cycle...................... 2-70
2.7.3 Internal Interrupt Handling................................................... 2-71
2.7.3.1 VMEbus and PCI Software Interrupts .......................... 2-73
2.7.3.2 Software IACK Interrupt .............................................. 2-74
2.7.3.3 VMEbus Ownership Interrupt....................................... 2-75
2.7.3.4 DMA Interrupt .............................................................. 2-75
2.7.3.5 Mailbox Register Access Interrupts..................... ......... 2-75
2.7.3.6 Location Monitors......................................................... 2-75
2.7.3.7 PCI and VMEbus Error Interrupts................................ 2-76
2.7.4 VME64 A u t o -ID ... .... .... .... ..... .... .... .... .... .... .... .... .... .... .... .... .. 2- 7 6
2.8 DMA Controller.................................................................................... 2-77
2.8.1 DMA Registers Outline........................................................ 2-77
2.8.1.1 Source and Destination Addresses................................ 2-78
2.8.1.2 Transfer Size ................................................................. 2-79
2.8.1.3 Transfer Data Width ..................................................... 2-79
2.8.1.4 DMA Command Packet Pointer ................................... 2-80
2.8.1.5 DMA Control and Status .............................................. 2-80
2.8.2 Di rect Mod e O p e r a t ion.... .... ..... .... .... .... .... .... .... .... .... .... .... .... 2-8 3
2.8.3 L ink ed -List O p e r a t i on... .... ..... .... .... .... .... .... .... .... .... .... .... .... .. 2- 8 6
2.8.3.1 Linked List Updating.................................................... 2-91
2.8.4 FIFO Operation and Bus Ownership.................................... 2-92
2. 8 .4 .1 PCI t o VM Eb u s Tran sfer s............................................. 2-9 2
2.8.4.2 VMEbus to PCI Transfers ............................................. 2-94
2.8.5 DMA Interrupts.................................................................... 2-95
2.8.6 Interactions with Other Channels.........................................2-96
ix
2.8.7 DMA Error Handling........................................................... 2-96
2.8.7.1 DMA Software Response to Error. ............................... 2-97
2.8.7.2 DMA Hardware Response to Error .............................. 2-97
2.8.7.3 Resuming DMA Transfers............................................ 2-98
2.9 Registers.............................................................................................. 2-100
2.9.1 Overview of Universe II Registers.....................................2-100
2.9.2 Register Access from the PCI Bus.....................................2-101
2.9.2.1 PCI Configuration Access ......................................... 2-102
2.9.2.2 Memory or I/O Access............... .......... .......... .......... ... 2-103
2.9.2.3 Locking the Register Block from the PCI bus............ 2-103
2.9.3 Register Access from the VMEbus.................................... 2-104
2.9.3.1 VMEbus Regis ter Access Image (VRAI)........ .. .... .... . 2-104
2.9.3.2 CR/CSR Accesses....................................................... 2-106
2.9.3.3 RM W and ADOH Register Access Cycles.......... .... ... 2-106
2.9.4 M ailbox Registers . ............................................................. 2-108
2.9.5 Semaphores ........................................................................ 2-109
2.10 Utility Functions ................................................................................. 2-110
2.10.1 Resets ................................................................................. 2-110
2.10.1.1 Overview of Reset Support......................................... 2-110
2.10.1.2 Universe II Reset Circuitry......................................... 2-112
2. 1 0 .1 .3 Rese t Imp l eme n tatio n Cauti o n s.... .... .... .... .... .............. 2-1 1 4
2.10 .2 P o w er-Up O p t i o n s..... .... ..... .... .... .... .... .... .... .... .... .... .... .... .... 2-1 1 5
2.10.2.1 Power-up Option Descriptions.................................... 2-117
2.10.2.2 Power-Up Option Implementation.............................. 2-119
2.10.3 Hardware Initializ ation (Norma l Operating Mode) .... .......2-121
2.10 .4 Test Mo d e s.. .... .... .... .... ..... .... .... .... .... .... .... .... .... .... .... .... .... .. 2- 1 2 2
2.10.4.1 Auxiliar y Test Modes ..... .......... .......... .......... .......... .... 2-122
2.10.4.2 JTAG support.............................................................. 2-123
2.10.5 Clocks................................................................................. 2-123
3 Description of Signals .......................................................................................... 3-1
3.1 VMEbus Signals ............................................................................................................ 3-1
x
3.2 PCI Bus Signals ..................................................................................... 3-5
4 Signals and DC Characteristics .......................................................................... 4-1
4.1 Terminology............................................................................................ 4-1
4.2 DC Characteristics and Pin Assignments................................................ 4-2
Appe ndix A – Registers .............................................................................................App A-1
Appe ndix B – Performance .......................................................................................App B-1
B.1 PCI Slave Channel .......................................................................... App B-2
B.1.1 Coupled Cycles ..............................................................App B-2
B.1.1.1 Request of VMEbus................................................ App B-2
B.1.1.2 Read Cycles ............................................................ App B-2
B.1.1.3 Write Cycles............................................................ App B-4
B.1.2 Decoupled Cycles.................. .........................................App B-4
B.2 VME Slave Channel........................................................................ App B-6
B.2.1 Coupled Cycles ..............................................................App B-6
B.2.1.1 Block vs. non-Block Transfers ...................... ......... App B-6
B.2.1.2 Read Cycles ............................................................ App B-7
B.2.1.3 Write Cycles............................................................ App B-8
B.2.2 Decoupled Cycles.................. .........................................App B-9
B.2.2.1 Write Cycles............................................................ App B-9
B.2.2.2 Prefetched Read Cycles ........................................ App B-12
B.3 DMA Channel............................................................................... App B-14
B.3.1 Relative FIFO sizes......................................................App B-14
B.3.2 VMEbus Ownership Modes.........................................App B-14
B.3. 3 VM E Tran sf e rs.... .... .... .... .... ..... .... .... .... .... .... .... .... .... ....App B-14
B.3.3.1 Read Transfers ...................................................... App B-15
B.3.3.2 Write Transfers ..................................................... App B-15
B.3.4 PCI Transfers................................................................App B-15
B.4 Summary....................................................................................... App B-17
xi
Appendix C – Typical Applications .........................................................................App C-1
C.1 VME Interface................................................................................. App C-1
C.1. 1 Tra n scei v e rs .. .... .... .... .... ..... .... .... .... .... .... .... .... .... .... .... ....App C- 1
C.1.1.1 Pull-down resistors ................................................. App C-5
C.1.2 Direction control ............................................................App C-5
C.1. 3 Po w er-up O p t i o n s.. .... .... ..... .... .... .... .... .... .... .... .... .... .... ....App C-5
C.2 PCI Bus Interface............................................................................ App C-7
C.2. 1 Re se t s .... .... .... .... .... .... .... ..... .... .... .... .... .... .... .... .... .... .... ....App C-8
C.2.2 Local Interrupts..............................................................App C-9
C.3 Manufacturing Test Pins............................................................... App C-10
C.4 Decoupling VDD and VSS on the Universe II............................. App C-10
Appendix D – Reliab ility Predic tion ............. .......... ... ........ .......... .......... .......... ........App D-1
D.1 Physical characteristics.................................................................. App D-1
D.2 Thermal characteristics .................................................................. App D-1
D.3 Universe II Ambie nt Operating Calculations................................. App D-2
D.4 Thermal vias................................................................................... App D-3
Appendix E – Cycle Mapping ................................................................................... App E-1
E.1 Little-endian Mode .......................................................................... App E-1
Appendix F – Operating and Storage Conditions ................................................... App F-1
Appendix G – Mechanical and Ordering Information ...........................................App G-1
G.1 Mechanical Information................................................................. App G-1
G.2 Ordering Information..................................................................... App G-5
Index ......................................................................................................................... Index-1
xii
xiii
List of Figures
Figure 2.1 : Architectural Diagram for the Universe II............................................ 2-3
Figure 2.2 : Influence of Transaction Data Width and Target Image
Data Width on Data Packing/Unpacking ............................................ 2-12
Figure 2.3 : VMEbus Slave Channel Dataflow....................................................... 2-14
Figure 2.4 : Timing for Auto-ID Cycle................................................................... 2-26
Figure 2.5 : PCI Bus Target Channel Dataflow...................................................... 2-40
Figure 2.6 : Influence of Transaction Data Width and Target Image Data
Wi d th o n Da t a P a ckin g / U n p ackin g..... .... ............................................ 2-41
Figure 2.7 : Address Translation Mechanism for VMEbus to PCI Bus Trans fers . 2-52
Figure 2.8 : Address Transl ation Mechanism for PCI Bus to VMEbus Transfers . 2-54
Figure 2.9 : Memory Mapping in the Special PCI Target Image ........................... 2-57
Figure 2.10 : Universe Interrupt Circuitry ................................................................ 2-62
Figure 2.11 : STATUS/ID Provided by Universe II................................................. 2-67
Figure 2.12 : Sources of Internal Interrupts.............................................................. 2-72
Figure 2.13 : Direct Mode DMA transfers................................................................ 2-84
Figure 2.14 : Command Packet Structure and Linked List Operation...................... 2-87
Figure 2.15 : DMA Linked List Operation............................................................... 2-88
Figure 2.16 : Universe II Control and Status Register Space ................................. 2-101
Figure 2.17 : PCI Bus Access to UCSR as Memory or I/O Space ......................... 2-102
Figure 2.18 : UCSR Access from the VMEbus Regi ster Access Image...... .. .. .... .. . 2-105
Figure 2.19 : UCSR Access in VMEbus CR/CSR Space....................................... 2-107
Figure 2.20 : Reset Circuitry................................................................................... 2-113
Figure 2.21 : Resistor-Capacitor Circuit Ensuring Power-Up Reset Duration....... 2-114
Figure 2.22 : Power-up Options Timing................................................................. 2-120
Figure A.1 : UCSR Access Mechanisms.......................................................... App A-1
Figure B.1 : Coupled Read Cycle - Universe II as VME Master ...................... App B-3
Figure B.2 : Several Coupled Read Cycles - Universe II as VME Master........ App B-3
Figure B.3 : Coupled Write Cycle - Universe II as VME Master ...... .......... ..... App B-4
xiv
Figure B.4 : Several Non-Block Decoupled Writes - Universe II as VME
Master............................................................................................ App B-6
Figure B.5 : BLT Decoupled Write - Universe I I as VME Master ................... App B-6
Figure B.6 : Coupled Read Cycle - Universe II as VME Slave ........................ App B-8
Figure B.7 : Coupled Write Cycle - Universe II as VME Slave
(bus parked at Universe II)............................................................ App B-9
Figure B.8 : Non-Block Decoupled Write Cycle - Universe II as VME Slave App B-10
Figure B.9 : BLT De coupled Write Cycle - Universe II as VME Slave ......... App B-11
Figure B.10 : MBLT Decoupled Wri te Cycle - Universe II as VME Slave...... App B-11
Figure B.11 : BLT Pre-fetched Read Cycle - Universe II as VME Slave......... App B-13
Figure B.12 : PCI Read Transactions During DMA Operation......................... App B-16
Figure B.13 : Multipl e PCI Read Transactio ns During DMA Oper ation.......... App B-17
Figure C.1 : Universe II Connections to the VME bus Through TTL Buffers .. App C-2
Figure C.2 : Power-up Configuration Using Passive Pull-ups.......................... App C-6
Figure C.3 : Power-up Configuration Using Active Circuitry .......................... App C-7
Figure C.4 : Analog Isolation Scheme............................................................. App C-10
Figure C.5 : Noise F ilter Sc he me ......... .... ...... .... . .... ...... .... ...... .... ...... .... ...... .... App C-11
Figure G.1 : Mechanical Dimensions for the 324-Pin Ceramic BGA Package App G-1
Figure G.2 : 313-PBGA (Gener ic).................................................................... App G-3
Figure G.3 : 313-PBGA Top View (OMPAC a nd GTPAC Drawings )............ App G-4
xv
List of Tables
Table 1.1 : Suffixes for Active Low Signals ........................................................... 1-6
Table 2.2 : PCI Address Line Asserted as a Function of VA[15:11].................... 2-21
Table 2.3 : Command Type Encoding for Transfer Type ..................................... 2-32
Table 2.4 : Register Fields for the Special Cycle Generator ................................. 2-45
Table 2.5 : VMEbus Fields for VMEbus Slave Image.......................................... 2-50
Table 2.6 : PCI Bus Fields for VMEbus Slave Image........................................... 2-50
Table 2.7 : Control Fields for VMEbus Slave Image............................................ 2-50
Table 2.8 : PCI Bus Fields for the PCI Bus Target Image .................................... 2-53
Table 2.9 : VMEbus Fields for the PCI Bus Target Image ................................... 2-53
Table 2.10 : Control Fields for PCI Bus Target Image............................................ 2-53
Table 2.11 : PCI Bus Fields for the Special PCI Target Image............................... 2-56
Table 2.12 : VMEbus Fields for the Special PCI Bus Target Image....................... 2-56
Table 2.13 : Control Fields for the Special PCI Bus Target Image......................... 2-56
Table 2.14 : Source, Enabling, Mapping, and Status of PCI Interrupt Output........ 2-64
Table 2.15: Source, Enabling, Mapping, and St atus of VMEbus
Interrupt Outputs ................................................................................. 2-66
Table 2.16 : Internal Interrupt Routing.................................................................... 2-71
Table 2.17 : DMA Interrupt Sources and Enable Bits............................................. 2-95
Table 2.18 : Programming the VMEbus Register Access Image.......................... 2-104
Table 2.19 : Hardware Reset Mechanism.............................................................. 2-110
Table 2.20 : Software Reset Mechanism............................................................... 2-111
Table 2.21 : Functions Affected by Reset Initiatiors................................. .......... .. 2-112
Table 2.22 : Power-Up Options............................................................................. 2-116
Table 2.23 : VRAI Base Address Power-up Options............................................ 2-117
Table 2.24 : Manufactur ing Pin Requirements for Normal Operating Mode........ 2-121
Table 2.25 : Test Mode Operation......................................................................... 2-122
Table 4.1 : DC Electrical Characteri stics (VDD = 5 V ± 10%) ............................... 4-2
Table 4.2 : Pin List and DC Characteristics for Universe II Signals ...................... 4-3
xvi
Table 4.3 : PCI Bus Address/Data Pins................................................................... 4-7
Table 4.4 : VMEbus Address Pins........................................................................... 4-9
Table 4.5 : VMEbus Data Pins .............................................................................. 4-10
Table 4.6 : Pin Assi gnments for Power and Ground............................................. 4-11
Table 4.7 : Pinout for 313-pin Plastic BGA Package............................................ 4-12
Table 4.8 : Pinout for 324–pin Ceramic BGA Pack age......................................... 4-13
Table A.1 : Universe II Register Map ........................................................... App A-2
Table A.2 : PCI Configuration Space ID Register (PCI_ID).......................... App A-7
Table A.3 : PCI Configuration Space Control and Status Register
(PCI_CSR).................................................................................... App A-8
Table A.4 : PCI Configuration Class Register (P CI_CLASS)...................... App A-10
Table A.5 : PCI Configuration Miscellaneous 0 Register (PCI_MISC0) ..... App A-11
Table A.6 : PCI Configuration Base Address Register (PCI_BS0) .............. App A-12
Table A.7 : PCI Configuration Base Address 1 Reg ister (PCI_BS1) ........... App A-13
Table A.8 : PCI Configuration Miscellaneous 1 Register (PCI_MISC1)..... App A-14
Table A.9 : PCI Target Image 0 Control (LSI0_CTL).................................. App A-15
Table A.10 : PCI Target Image 0 Base Address Register (L SI0_BS)......... .... App A-16
Table A.11 : PCI Target Image 0 Bound Address Register (LSI0_BD)......... App A-17
Table A.12 : PCI Target Image 0 Translation Offset (LSI0_TO)................... App A-18
Table A.13 : PCI Target Image 1 Control (LSI1_CTL).................................. App A-19
Table A.14 : PCI Target Image 1 Base Address Register (L SI1_BS)......... .... App A-20
Table A.15 : PCI Target Image 1 Bound Address Register (LSI1_BD)......... App A-21
Table A.16 : PCI Target Image 1 Translation Offset (LSI1_TO)................... App A-22
Table A.17 : PCI Target Image 2 Control (LSI2_CTL).................................. App A-23
Table A.18 : PCI Target Image 2 Base Address Register (L SI2_BS)......... .... App A-24
Table A.19 : PCI Target Image 2 Bound Address Register (LSI2_BD)......... App A-25
Table A.20 : PCI Target Image 2 Translation Offset (LSI2_TO)................... App A-26
Table A.21 : PCI Target Image 3 Control (LSI3_CTL).................................. App A-27
Table A.22 : PCI Target Image 3 Base Address Register (L SI3_BS)......... .... App A-28
Table A.23 : PCI Target Image 3 Bound Address Register (LSI3_BD)......... App A-29
Table A.24 : PCI Target Image 3 Translation Offset (LSI3_TO)................... App A-30
xvii
Table A.25 : Special Cycle Control Register (SCYC_CTL)........................... App A-31
Table A.26 : Special Cycle PCI Bus Address Register (SCYC_ADDR)........ App A-32
Table A.27 : Special Cycle Swap/Compare Enable Regi ster (SCYC_EN) .... App A-33
Table A.28 : Special Cycle Compare Data Register (SCYC_CMP)............... App A-34
Table A.29 : Special Cycle Swap Data Register (SCYC_SWP)..................... App A-35
Table A.30 : PCI Miscellaneous Register (LMISC)........................................ App A-36
Table A.31 : Special PCI Target Image (SLSI)............................................... App A-37
Table A.32 : PCI Command Error Log Register (L_CMDERR).................... App A-39
Table A.33 : PCI Address Error Log (LAERR).............................................. App A-40
Table A.34 : PCI Target Image 4 Control Registe r (LSI4_CTL).................... App A-41
Table A.35 : PCI Target Image 4 Base Address Register (L SI4_BS)......... .... App A-42
Table A.36 : PCI Target Image 4 Bound Address Register (LSI4_BD)......... App A-43
Table A.37 : PCI Target Image 4 Translation Offset (LSI4_TO)................... App A-44
Table A.38 : PCI Target Image 5 Control Registe r (LSI5_CTL).................... App A-45
Table A.39 : PCI Target Image 5 Base Address Register (L SI5_BS)......... .... App A-46
Table A.40 : PCI Target Image 5 Bound Address Register (LSI5_BD)......... App A-47
Table A.41 : PCI Target Image 5 Translation Offset (LSI5_TO)................... App A-48
Table A.42 : PCI Target Image 6 Control Registe r (LSI6_CTL).................... App A-49
Table A.43 : PCI Target Image 6 Base Address Register (L SI6_BS)......... .... App A-50
Table A.44 : PCI Target Image 6 Bound Address Register (LSI6_BD)......... App A-51
Table A.45 : PCI Target Image 6 Translation Offset (LSI6_TO)................... App A-52
Table A.46 : PCI Target Image 7 Control Registe r (LSI7_CTL).................... App A-53
Table A.47 : PCI Target Image 7 Base Address Register (L SI7_BS)......... .... App A-54
Table A.48 : PCI Target Image 7 Bound Address Register (LSI7_BD)......... App A-55
Table A.49 : PCI Target Image 7 Translation Offset (LSI7_TO)................... App A-56
Table A.50 : DMA Transfer Control Register (DCTL)................................... App A-57
Table A.51 : DMA Transfer Byte Count Register (DTBC)............................ App A-58
Table A.52 : DMA PCI Bus Address Register (DLA).................................... App A-59
Table A.53 : DMA VMEbus Address Register (DVA)................................... App A-60
Table A.54 : DMA Command Packet Pointer (DCPP) ................................... App A-61
Table A.55 : DMA General Control/Status Register (DGCS) ........................ App A-62
xviii
Table A.56 : DMA Linked List Update Enable Register (D_LLUE) ......... .... App A-64
Table A.57 : PCI Interrupt Enable Register (LINT_EN) ................................ App A-65
Table A.58 : PCI Interrupt Status Register (LINT_STAT)............................. App A-67
Table A.59 : PCI Interrupt Map 0 Register (LINT_MAP0)............................ App A-69
Table A.60 : PCI Interrupt Map 1 Register (LINT_MAP1) ............................ App A-70
Table A.61 : VMEbus Interrupt Enable Register (VINT_EN)........................ App A-71
Table A.62 : VMEbus Interrupt Status Register (VINT_STAT) .................... App A-73
Table A.63 : VME Interrupt Map 0 Register (VINT_MAP0)......................... App A-75
Table A.64 : VME Interrupt Map 1 Register (VINT_MAP1)......................... App A-76
Table A.65 : Interrupt STATUS/ID Out Register (STATID) ......................... App A-77
Table A.66 : VIRQ1 STATUS/ID Register (V1_STATID)............................ App A-78
Table A.67 : VIRQ2 STATUS/ID Register (V2_STATID)............................ App A-79
Table A.68 : VIRQ3 STATUS/ID Register (V3_STATID)............................ App A-80
Table A.69 : VIRQ4 STATUS/ID Register (V4_STATID)............................ App A-81
Table A.70 : VIRQ5 STATUS/ID Register (V5_STATID)............................ App A-82
Table A.71 : VIRQ6 STATUS/ID Register (V6_STATID)............................ App A-83
Table A.72 : VIRQ7 STATUS/ID Register (V7_STATID)............................ App A-84
Table A.73 : PCI Interrupt Map 2 Register (LINT_MAP2)............................ App A-85
Table A.74 : VME Interrupt Map 2 Register (VINT_MAP2)......................... App A-86
Table A.75 : Mailbox 0 Register (MBOX0).................................. .......... ........ App A-87
Table A.76 : Mailbox 1 Register (MBOX1).................................. .......... ........ App A-88
Table A.77 : Mailbox 2 Register (MBOX2).................................. .......... ........ App A-89
Table A.78 : Mailbox 3 Register (MBOX3).................................. .......... ........ App A-90
Table A.79 : Semaphore 0 Register (SEMA0)..... ........................................... App A-91
Table A.80 : Semaphore 1 Register (SEMA1)..... ........................................... App A-92
Table A.81 : Master Control Register (MAST_CTL)..................................... App A-93
Table A.82 : Miscellaneous Control Register (MISC_CTL) .......................... App A-95
Table A.83 : Miscellaneous Status Register (MISC_STAT) .......................... App A-97
Table A.84 : User AM Codes Register (USER_AM) ..................................... App A-98
Table A.85 : VMEbus Slave Ima ge 0 Control (VSI0_CTL)........................... App A-99
Table A.86 : VME bus Slave Image 0 Base Add ress Register (VSI0_BS).... App A-100
Table A.87 : VMEbus Slave Image 0 Bound Address Register (VSI0_BD) App A-101
Table A.88 : VMEbus Slave Image 0 Translati on Offset (VSI0_TO). ......... App A-102
xix
Table A.89 : VMEbus Slave Ima ge 1 Control (VSI1_CTL)......................... App A-103
Table A.90 : VME bus Slave Image 1 Base Add ress Register (VSI1_BS).... App A-104
Table A.91 : VMEbus Slave Image 1 Bound Address Register (VSI1_BD) App A-105
Table A.92 : VMEbus Slave Image 1 Translati on Offset (VSI1_TO). ......... App A-106
Table A.93 : VMEbus Slave Ima ge 2 Control (VSI2_CTL)......................... App A-107
Table A.94 : VME bus Slave Image 2 Base Add ress Register (VSI2_BS).... App A-108
Table A.95 : VMEbus Slave Image 2 Bound Address Register (VSI2_BD) App A-109
Table A.96 : VMEbus Slave Image 2 Translati on Offset (VSI2_TO). ......... App A-110
Table A.97 : VMEbus Slave Ima ge 3 Control (VSI3_CTL)......................... App A-111
Table A.98 : VME bus Slave Image 3 Base Add ress Register (VSI3_BS).... App A-112
Table A.99 : VMEbus Slave Image 3 Bound Address Register (VSI3_BD) App A-113
Table A.100 : VMEbus Slave Image 3 Translation Offset (VSI3_TO).......... App A-114
Table A.101 : Location Monitor Control Register (LM_CTL)....................... App A-115
Table A.102 : Location Monitor Base Address Register (LM_BS)................ App A-116
Table A.103 : VME bus Register Access Image Control Register
(VRAI_CTL)............................................................................ App A-117
Table A.104 : VME bus Register Access Image Base Address Register
(VRAI_BS)............................................................................... App A-118
Table A.105 : VMEbus CSR Control Register (VCSR_CTL)........................ App A-119
Table A.106 : VMEbus CSR Translation Offset (VCSR_TO) ....................... App A-120
Table A.107 : VMEbus AM Code Error Log (V_AMERR)........................... App A-121
Table A.108 : VMEbus Address Error Log (VAERR) ............. .......... .......... .. App A-122
Table A.109 : VMEbus Slave Image 4 Control (VSI4_C TL)......................... App A-123
Table A.110 : VMEbus Slave Image 4 Base Address Register (VSI4_BS).... App A-124
Table A.111 : VMEbus Slave Ima ge 4 Bound Address Register (VSI4_BD) App A-125
Table A.112 : VMEbus Slave Image 4 Translation Offset (VSI4_TO).......... App A-126
Table A.113 : VMEbus Slave Image 5 Control (VSI5_C TL)......................... App A-127
Table A.114 : VMEbus Slave Image 5 Base Address Register (VSI5_BS).... App A-128
Table A.115 : VMEbus Slave Ima ge 5 Bound Address Register (VSI5_BD) App A-129
Table A.116 : VMEbus Slave Image 5 Translation Offset (VSI5_TO).......... App A-130
Table A.117 : VMEbus Slave Image 6 Control (VSI6_C TL)......................... App A-131
Table A.118 : VMEbus Slave Image 6 Base Address Register (VSI6_BS).... App A-132
xx
Table A.119 : VMEbus Slave Ima ge 6 Bound Address Register (VSI6_BD) App A-133
Table A.120 : VMEbus Slave Image 6 Translation Offset (VSI6_TO).......... App A-134
Table A.121 : VMEbus Slave Image 7 Control (VSI7_C TL)......................... App A-135
Table A.122 : VMEbus Slave Image 7 Base Address Register (VSI7_BS).... App A-136
Table A.123 : VMEbus Slave Ima ge 7 Bound Address Register (VSI7_BD) App A-137
Table A.124 : VMEbus Slave Image 7 Translation Offset (VSI7_TO).......... App A-138
Table A.125 : VMEbus CSR Bit Clear Register (VCSR_CLR) ..................... App A-139
Table A.126 : VMEbus CSR Bit Set Register (VCSR_S ET).......................... App A-140
Table A.127 : VMEbus CSR Base Address Register (VCSR_BS)................. App A-141
Table B.1 : PCI Slave Channel Performance ................................................. App B-17
Table B.2 : VME Slave Channel Performance............................................... App B-18
Table B.3 : DMA Channel Performance........................................................ App B-19
Table C.1 : VMEbus Signal Drive Strength Requirements............................. App C-4
Table C.2 : V MEbus Transceiver Requirements.............................................. App C-4
Table C.3 : Reset Signals ................................................................................. App C-8
Table D.1 : Ambient to Junction Thermal Impedance.................................... App D-2
Table D.2 : Maximum Universe II Junction Temperature .............................. App D-2
Table E.1 : Mapping of 32 -bit Little- Endian PCI Bus to 32-bit VMEbus ...... App E-1
Table E.2 : Mapping of 32 -bit Little- Endian PCI Bus to 64-bit VMEbus ...... App E-2
Table F.1 : Recommended Operating Conditions............................................ App F-1
Table F.2 : Absolute Maximum Ratings.......................................................... App F-1
Table F.3 : Power Dissipation.......................................................................... App F-2
Table G.1 : Standard Ordering Information .................................................... App G-5
VMEbus Interface Components—Universe II User Manual
Tundra Semiconduc tor Corporation 1-1
1 Introduction
1.1 Features
The Universe II (CA91C142) is the de facto industry standard PCI bus to VMEbus bridge ,
providing:
• 64-bit, 33 MHz PCI bus interface,
• fully compliant, high performance 64-bit VMEbus interface,
• integral FIFOs buffer multiple transactions in both directions,
• programmable DMA controller with linked-list support,
• industry leading performance,
• Wide range of VMEbus address and data transfe r modes,
- A32/A24/A16 master and slave, (not A64 or A40)
- D64/D32/D16/D08 master and slav e, (no MD32)
-MBLT, BLT, ADOH, RMW, LOCK, locat ion monitors,
• nine user programmable slave images on VMEbus and PCI b us ports,
• seven interrupt lines on either bus and flexible mapping of software and hardware
sources of hardware interrupt,
• automatic initia liza tion for sla ve-only applications,
• flexible register set, progra mmable from both the VMEbus and the PCI bus,
• four mailboxes and loca tion monitor for message-oriented system,
• support for RMWs, lock cycles, and semaphores guarantee exclusive access,
• bus isolation mode for board maintenance, diagnostics, and live fa ult recovery,
• full VMEbus syste m controller functionality,
• several powe r-up options,
• IEEE 1149.1 JTAG testability support,
• commercial (0º to 70ºC), industrial (-40º to 85ºC ) and extended temperature (-55º to
125ºC) options, and
• a vailable in 313-pin Plastic BGA and 324-pin Ceramic BGA.
Benefits of the Universe II Universe II User Manual
1-2 Tundra Semiconductor Corporation
1.2 Benefits of the Universe II
Interfacing the VMEbus with PCI presents a number of opportunities and challenges. The
Univ erse II solves the problems and allo ws you to benefit from the opportunities.
The opportunities involve mer ging the best of the VMEb us and PC I b us worlds. The VMEbus
is a proven standard specifically designed to support e mbedded systems. The distributed
environment of the VMEbus supports multiprocessing and real-time intensiv e applications. A
large number of off-the-shelf boards, software, and chassis components are a vailable.
VMEbus supports 21-s lot systems without bridging and is continually evolving while
providing backward compatibility. Hot swap solutions, and higher performance protocols
ha ve been defined and will be incorporated in future revisions of VMEb us.
Meanwhile, PCI has become a standard local bus. As a result, the leading semiconductor
ve ndors have built PCI support into their ne west processor and peripheral families.
The challenges involved in interfacing VMEbus to PCI include: address mapping, byte-lane
swapping, and cycle ma pping.
To allow VMEb us single-board computer ve ndors to benefit from PCI components, while
overcoming the challenges involved in merging PCI with VMEbus, Tundra has developed a
PCI to VMEbus interface controller, the Univ erse II. The Uni verse II is the industry prov en,
high perfor manc e 64-bit VMEb us to PCI interf a ce, fully compli ant with VME64 and t ailore d
for the new generation of high performan ce PCI processors and peri pherals.
The availability of the Universe II eases the development of multi-master, multi-processor
architectures on VMEbus systems using PCI. The Uni verse II is ideally suited for CPU boards
acting as both master and slave in the VMEb us system and that require access to PCI systems.
With the Universe II, you know that as your system increases in complexity, you have silicon
that continues to provide everything you ne ed in a bridge. The elegant design of the Tundra
Uni v erse II, som e of the best applications engineers in the industry, and this manual will mak e
it as easy as poss ible for you to use the most sophisticated VMEb us interface.
Universe II User Manua l Past a nd F uture of the Univers e
Tundra Semiconduc tor Corporation 1-3
1.3 Past and Future of the Universe
The Universe II (CA91C142) is a pin- and software -compatible revision of the Universe
(CA91C042). The Universe was developed subsequently to the SCV64, Tundr a’s VME
interf ace for non-PCI applications. The Univ erse II is the next generation of the Universe, and
has been designed to exceed new cus tomer expectations and to corr ect errata in the original
Univ erse. The rich set of feature and performance enhancements are based on ext ensi v e
consultation with our customers.
Giv en its history, the Universe II of f e rs a lo w-r isk, feature-rich, high performance solution f or
VMEbus -based PCI applicati ons. Some of the performance enhancem ents off ered by the
Univ erse II include:
• improv ed PCI b us bandwidth utilization,
• improved register acces s per formance,
• impro ved VMEb us slave and VME master performance,
• increased FIFO depth,
• DMA improved to optimize transfer rate on each bus,
• improved linke d-list DMA performance,
• signif icantly improv ed coupled transfer performance,
• reduced power consumption.
Additio nal features include:
• four ma ilbox registers,
• eight semaphores,
• four location monitors,
• new software interrupts,
• more slave images .
The Universe II revision is another example of Tundra ’s commitment to supporting the
VMEbus community. Tundra is actively participating in VMEbus, PCI bus , and CompactPCI
bus standards and vendor associations, as well as related SIGs. Tundra will continue to
propose and support enhancements to these specifications, while increasing both the range of
options available to our customers and the compatibility between VME and PCI. Ple ase visit
our web site to ke ep abreast of these developments: http://www. t undra.com
About This Document Universe I I User Manual
1-4 Tundra Semiconductor Corporation
1.4 A bo ut This Do cu me nt
This manual is intended for users of the Tundra Univ erse II. Because of the differences
between Universe and Universe II, this manual is not suitable for users of the original Tundra
Univ erse. Uni verse users should continue to consult the pre vious VM Eb us manual (document
number 9000000.MD303.01).
The current manual is organized as follows:
• Chapter 1 - General I nformation,
• Chapter 2 - Functional Description,
• Chapter 3 - Signal Description,
• Chapter 4 - Signals and DC Characteristics,
• Appendix A - Regis ters,
• Appendix B - Performance,
• Appendix C- Typical Applications,
• Appendix D- Reliability,
• Appendix E- Cycl e Mapping,
• Appendix F- Operating and Storage Conditions
• Appendix G- Mechanical and Ordering Information , and
• Index.
Chapter 1 introduces the Universe II and pr ovides the rea der with information about the
necessar y concepts and conventi ons required to use the manual.
Chapters 2 to 4 descr ibe Universe II function, beginning with ov erall functionalit y in Chapter
2 to detailed signal descriptions in Chapters 3 and 4.
The Appendices are reference sources necessary fo r the implementation of the Universe II. In
addition, the Appendices contain application information to aid the user in system design.
The Index pr ovides a means to quickly access informati on on a keyword basis.
Universe II User Manual Universe II Technical Support
Tundra Semiconduc tor Corporation 1-5
1.5 Universe II Technical Support
Tundra is dedicated to providing our customers with superior technical documentation and
support. The following means of support are available:
1.
The Universe II User’s Manual. This is the main source of technical
information. We strive hard to produce excellent documentation, and this
manual conta ins the answers to most of our customers’ questions.
2.
The Universe II Documentation Web P age. This cont ains the latest manual,
application notes, FA Q, articles, and any device errat a and manual addenda.
Please visit and bookmark http://www.tundra.com.
3.
The Desi g n er’s Resourc e Forum. This is a public discussion forum at
http://www.tundra.com which allows you to post questions and r ead threads
pertaining specifically to the Universe II . Tundra technical support staff
moderate this forum and promptly respond to customer inquiries.
4.
support@tundra.com. You may also direct questions and feedback to
Tundra using this e-mail address. Ple ase include “Universe II” in the subje ct
header of your message.
5. Phone suppor t. Tundra’s technical support staff may be reached at
(613) 592-1320. Please ask for Universe II t echnical support.
1.6 Un iver se II Documentation
Tundra is dedicated to providing our customers with superior technical documentation and
support.
1.
The Universe II User’s Manual. This is the main source of technical
informa tion.
2.
The Universe II Documentation Web P age. This cont ains the latest manual,
application notes, FA Q, articles, and any device errat a and manual addenda.
Please visit and bookmark http://www.tundra.com. Our document s are avail-
able as PD F files. These files are searchable and replete with hypertext links.
You may read our documents on-line (w ith a PDF plug-in in your bro wser), or
do wnload them to your machine. The Acrobat index es to these files al low you
to perform v ery rapid searches through our documents.
3. The Designer’s Resource Center. You can tailor how the Tundra web site is
presented to you by using this web res ource, available from
http://www.tundra.com. There, you m ay also re gis ter to receive automatic e-
Conventions Universe II User Manual
1-6 Tundra Semiconductor Corporation
mail notific ation when the adde ndum, manual, or any other “re source” has
changed. This is the best way to ensure that you always hav e the latest
Univ erse II documentation.
1.7 Conventions
1.7.1 Signals
Signals on the VMEbus and PC I b us are either activ e high or acti ve lo w. Acti ve lo w signals are
defined as true (asserted) when they are at logic low. Similarly, activ e high signals are defined
as true at a logic high. Signals are considered asserted when acti ve and ne gated when inactiv e,
irre spective of v olta ge levels.
For volt age lev e ls, the use of ‘0’ indicates a low voltage while a ‘1’ indicates a high volt age.
The names of Universe II signals on the VMEbus interface start with the letter ‘V’ (e.g.,
VRSYSRST #). Input signals on that interface start with ‘VR’ (e.g.,VRSYSRST#), output
signals sta rt with ‘VX’ (e.g., VXBERR). Table 1.1 shows how the convention for denoting
activ e lo w signals.
1.7.2 Symbols
Caution: This symbol alerts the r e ader to procedures or operating levels which
may res ult in misuse of or damage to the Universe II.
Note: This symbol directs the reader’s attention to useful information or
suggestions.
Table 1.1 : Suffixes for Active Low Signals
Suffix Used for Example
# active l ow signals on P C I, and RST#
active lo w signal s on VMEbu s interface of the Universe II VRSYSRST#
SIGNAL* act ive low signals on the VMEbus backplane SYSRESET*
!
Univer se II User Manual Conventions
Tundra Semiconduc tor Corporation 1-7
1.7.3 Terminology
The term “c ycle” refers to a single data beat, while a “transaction” is composed of one or more
“cycles”.
To eliminate ambiguity, the expression “external mas ter” is used to denote a ma s ter that is not
the Uni verse II (or is a different Uni verse II). The capitalized expression “Master Interface” is
used to denote the Univ erse II as bus master. The e xpression “external tar get” is used to denote
a target that is not the Univer se II (or is a diff erent Uni v erse II). The capitalized e xpression
“Target Inter face” or “Slave Interface” is used to denote the Universe II as target (o r slave) of
the bus. F or example if the Univ erse II accesses a memory chip on the PCI bus, we might
write : “The PCI Master Interface writes to the externa l PCI target.”
Conventions Universe II User Manual
1-8 Tundra Semiconductor Corporation
VMEbus Interface Components —Univ erse II User Manua l
Tundra Semiconduc tor Corporation 2-1
2 Functional Description
This chapter is organized as follows.
• Section 2.1, “Architectural Overview”, on page 2-2 summarizes the overall
architecture of the Universe II,
• Section 2.2, “VMEbus Interface”, on page 2-6 presents the capabilitie s of the
Univ erse II as VMEbus slave and VMEbus master,
• Section 2.3, “PCI Bus Interface”, on page 2-30 presents the capabilities of the
Un iv erse II as PCI bus tar g e t and P CI bus maste r,
• Section 2.4, “Slav e Image Programming”, on page 2-50 e xplains how to pr ogram the
mapping of cycles from one bus to the other,
• Section 2.5, “Bus Error Handling”, on page 2-58 explains how the Univers e II
handles and generates bus errors,
• Section 2.6, “Inte rrupt Generation”, on page 2-62 describes the interrupts which the
Univ erse II can generate,
• Section 2.7, “Inte rrupt Handling”, on page 2-68 describes how the Universe II
responds to interrupt conditions,
• Section 2.8, “DMA Contr oller”, on page 2-77 describes the operation of the Uni v erse
II’s Direc t Me mory Access Controller,
• Section 2.9, “Reg isters”, on page 2-100 gives an o verview of the Univ erse II’s
registers and how they can be accessed,
• Section 2.10, “Utility Functions”, on page 2-110 describes resets, power-up options,
test modes, and clocks.
Ar chitec tural Ove rview Univ erse II User Manua l
2-2 Tundra Semiconductor Corporation
2.1 Architectural Overv iew
This section introduces the general architecture of the Univ erse II. This description makes
frequent reference to the functional block diagram provided in Figure 2.1 on page 2-3. Notice
that for each of the interfaces, VMEbus and PCI bus, there are three functionally distinct
modules: master module, slav e module, and interr upt module. These modules are connected
to the different functional channels ope rating in the Universe II. Thes e channels are:
• the VMEbus Sla ve Channel,
• the PCI Bus Target Channel,
• the DMA Channel,
• the Interrupt Channel, and
• the Register Channel.
The Architectural Ov erview is organized into the follo wing sections:
• “VME bu s In terface ”,
• “PCI Bus Interface”,
• “Interrupter and Interrupt Handler”, and
• “DMA Controller”.
These sections describe the operation of the Uni verse II in terms of the dif ferent modules and
channels illustrated in Figure 2.1.
2.1.1 VMEbus Inter face
2.1.1.1 Universe II as VMEb us Slave
The Universe II VMEbus Slav e Channel accepts all of the addressing and data transfer modes
documented in the VME64 specification (except A64 and those intended to augment 3U
applications, i.e., A40 and MD32). Incoming write transactions from the VMEbus may be
treated as either coupled or posted, depending upon the programming of the VMEbus sla ve
image (see “VME Sla v e Images” on page 2-50). With posted write transactions, data is
written to a Posted Write Receive FIFO (RXFIFO), and the VMEbus master receives data
acknowledgmen t from the Univers e II. Write data is transfe rred to t he PCI resour c e from the
RXFIFO without the involvement of the initiating VMEbus master (see “Posted Writes” on
page 2-15 for a full explanation of this operation). With a coupled cycle, the VMEbus master
only receiv es data ackno wledgment when the transaction is complete on the PCI bus. This
means that the VMEbus is unavailable to other masters while the PCI bus transaction is
executed.
Universe II User Ma nual Ar chitect ural Overview
Tundra Semiconduc tor Corporation 2-3
Read transactions may be either prefetched or coupled. If enabled by the user, a prefetched
read is initiate d when a VMEb us master requests a bloc k read transaction ( BLT or MBLT) and
this mode is enabled. When the Universe II receives the block read request, it begins to fill its
Read Data FIFO (RDFIFO) using burst transactions from the PCI resource. The initiating
VMEbus master then acquires its block read data from the RDFIFO rather than from the PCI
resources directly.
2.1.1.2 Uni verse II as VMEbu s Maste r
The Univer se II becomes VMEb us master when the VMEbus Mast er Interface is internally
requested by the PCI B us Target Channel, the DMA Channel, or the Interrupt Channel. The
Interrupt Channel always has priority ove r the other two channels. Several mechanisms are
a v ailable to configure the r elati ve priority that the PCI Bus Target Channel and DMA Cha nnel
ha v e ov er o wnership of the VMEb us Master Interface.
Figure 2.1 : Architectural Diagram for the Universe II
PCI
Slave
PCI
Interrupts
Register Channel
DMA Channel
PCI
Master
VME
Master
VME
Interrupts
VME
Slave
VMEbus Slave Channel
VMEbu
s
PCI
B
US
Interrupt Channel
PCI Bus Slave Channel
PCI Bus
Interface VMEbus
Interface
DMA bidirectional FIFO
prefetch read FIFO
coupled read
posted writes FIFO
coupled read logic
posted writes FIFO
Interrupter
Interrupt Handler
Ar chitec tural Ove rview Univ erse II User Manua l
2-4 Tundra Semiconductor Corporation
The Univ er se II’s VMEbus Master Interface generates all of the addressing and data transfer
modes documented in the VME64 spe cification (except A64 and those intended to augment
3U applications, i.e. A40 and MD32). The Uni ve r se II is also compatible with all VMEb us
modules conforming to pre-VME64 specifications. As VMEbus master, the Universe II
supports Read-Modify-Write (RMW), and Address-Only- with-Handshake (ADOH) but does
not accept RETRY* as a termination from the VMEbus slave. The ADOH cycle i s used to
impleme nt the VMEbus Lock command allowing a PCI mast er to lock VMEbus resources.
2.1.2 PCI Bus Interface
2.1.2.1 Uni verse II as PCI Target
Read transactions from the PCI bus a re always proces sed as coupled. Write transactions ma y
be either coupled or posted, depending upon the setti ng of the PCI b us target image (see “PCI
Bus Tar ge t Image s” on page 2-53). With a posted write transaction, write data is written to a
Posted Write T ransmit FIFO (TXFIFO) and the PCI bus master receives data ackno wledgment
from the Univ er se II with zero wait-states. Meanwhile, the Uni ver se II obtains the VMEb us
and writes the data to the VMEbus resourc e independent of the initiating PCI master (see
“Posted Writes” on page 2-44 for a full description of this operation).
To allo w PCI masters to perform RMW and ADOH c ycles, the Uni v erse II pro vides a Special
Cycle Generator. The Special Cycle Generator can be used in combination with a VMEbus
ownership function to guarantee PCI masters exclusi v e access to VMEb us resources over
several VMEbus transactions (see “The Special Cycle Generator” on page 2-45 and “Using
the VOWN bit” on page 2-48 for a full des cription of this functionality).
2.1.2.2 Uni verse II as PCI Master
The Universe II becomes PCI master when the PCI Master Interface is internally requested b y
the VMEbus Slave Channel or the DMA Channel. There are mechanisms provided which
allow the user to configure the relative priority of the VMEbus Sla ve Channel and the DMA
Channel.
2.1.3 Interru pter and Interrupt Handler
2.1.3.1 Interrupter
The Univ e rse II Int errupt Channel pr ovides a f lexible s cheme t o ma p inter rupts to the PCI b u s
or VMEbus Interface. Interrupts are generated from hardware or software sources (see
“Interrupt Generation” on page 2-62 and “Interrupt Handling” on page 2-68 for a full
description of hardware and software sources). Interrupt sources can be mapped to any of the
PCI bus or VME bus interrupt output pins. Interrupt sources mapped to VMEbus interrupts are
generated o n the VMEbus interrupt output pins VIRQ# [ 7:1]. When a software and hardware
source are assigned to the same VIRQn# pin, the software source al ways has higher priority.
Universe II User Ma nual Ar chitect ural Overview
Tundra Semiconduc tor Corporation 2-5
Interrupt sources mapped to P CI bus interrupts are generated on one of t he INT# [7:0] pins. To
be fully PCI compli ant, all interrupt sources must be routed to a single INT# pin.
For VMEbus interrupt outputs, the Universe II interr upter supplies an 8-bit STATUS/ID to a
VMEbus interrupt handler during the IACK cycle, and optionally generates an internal
interrupt to signal that the interrupt vector has been provided (see “VMEbus Interrupt
Generation” on page 2-65).
Interrupts ma pped to PCI bus outputs are se rviced by the PCI interrupt controller. The CPU
determine s which interrupt sour ces are active by readi ng an interrupt status register in the
Universe II. The source negates its interrupt when it has been serviced by the CPU (see “PCI
Interrupt Generation” on page 2-63).
2.1.3.2 VMEbus Interrupt Handling
A VMEbus interrupt triggers the Uni verse II to generate a normal VMEbus IACK c ycle and
generate the specified interrupt output. When the IACK cycle is complete, the Universe II
releases the VMEbus and the interrupt vector is read by the PCI resour ce ser vi cing the
interrupt output. Software interrupts are R OAK, while hardware, and intern al interrupts are
RORA.
2.1.4 DMA Control ler
The Universe II provides an internal DMA controller for high performance data transfer
between the PCI and VMEbus. DMA operations between the source and destination bus are
decoupled through th e use of a single bidirectional FIFO (DMAFIFO). Parameters for the
DMA transfer are software conf igurable in the Universe II registers (see “DMA Controller”
on page 2-77).
The principal mechani sm for DMA transfers is the same for operations in either direction
(PCI to VMEbus , or VMEb us to PCI), only the relati ve identity of the source and destination
bus changes. In a DMA transfer, the Universe II gains control of the source b us and reads data
into its DMAFIFO. Following specific rules of DMA FIFO operation (see “FIFO Operation
and Bus Ownership” on page 2-92), it then acquires the destination b us and writ es data from
its DMAFIFO.
The DMA controller can be programmed to perform multiple blocks of transfers using entries
in a linke d-list. The DMA will w ork thr ough the transfers in the linked-list following pointers
at the end of each linked-list entry. Linked-list operation is initiated through a pointer in an
interna l Universe II register, but the linked-list itself resides in PCI bus memory.
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2.2 VMEbus Interface
The VMEbu s Interf ace incorporates all operations associated with the VMEbus. This includes
master and slave functions, VMEbus configuration and sys tem controller functions. These
operations are co vered as follo ws:
• “VMEbus Requester ” below,
• “Universe II as VMEbus Master” on page 2- 9,
• “Universe as VMEbus Slave” on page 2-13,
• “VMEbus Configuration” on page 2- 23,
• “Aut omatic Slot Identif ication” on page 2-24, and
• “System Controller Functions” on page 2-26.
• “BI-Mode” on page 2- 28.
For information concerning th e Universe II VMEbus slave images, see “VME Slave Images”
on page 2-50.
2.2.1 VMEbus Requester
2.2.1 . 1 I nter nal Arbit r ati o n for VM E bus R e ques ts
Three different internal channel s within the Universe II require use of the VME bus: the
Interrupt Cha nnel, the PCI Target Channe l, and the DMA Channel. These three channels do
not directly request the VMEbus, instead they compete internally for ownership of the
VMEbus Mast er In terfa ce.
The Interrupt Channel (refer to Figure 2.1 on page 2-3) alw ays has the highest priority for
access t o the VME bus Master In terfa ce. The DMA and PCI Target Channel re que sts are
handled in a fair manner. The channel awarded VMEbus mastership maintains ownership of
the VMEbus until it is ‘done’. The definition of ‘done’ for each channel is given below in
“VMEbus Release” on page 2-8.
The Interrupt C hannel requests the VMEbus master when it detects an enabled VMEbus
interrupt line assert ed and needs to run an interrupt acknowledge cycle to acquire the
STATUS/ID.
The PCI Target Channel re quest s the VME bus M aster Interfac e to servi ce the following
conditions:
• the TXFIFO contains a complete transacti on, or
• if there is a coupled cycle request.
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The DMA Channel requests the VMEbus Master Interface if:
• the DMAFIFO has 64 bytes available (if it is reading from the VMEbus) or 64 bytes
in its FIFO (if it i s writing to the VMEbus), or
• the DMA block is complete (see “DMA Controller” on page 2-77).
In the case of the DMA Channel, the user can optionally use t he DMA Channel
VMEb us -off-timer to further qualify re quests from this channel. The VMEbus-of f -timer
controls how long the DMA remains off the VMEbus before making another request (see
“PCI to VMEb us Transfers” on page 2-92).
The Uni verse II provides a software mechanism for VMEb us acquisition t hrough the VMEbus
ownership bit (VOWN in the MAST_CTL register, Table A.81). When the VMEbus
ownership bit is set, the Universe II acquires the VMEbus and sets an acknowledgment bit
(VOWN_ACK in the MAST_C TL regis ter, Table A.81) and optionally generates an interrupt
to the PCI bus (see “VME Lock Cycles—Exclusive Access to VMEb us Resources” on
page 2-47). The Universe II maintains VMEb us o wne rs hip until the o wners hip bit is cleared.
During the VMEbus tenure initiated by setting the o wnership bit, only the PCI Tar get Channel
and Interrupt Channel can acces s the VMEbus Master Interface .
2.2.1.2 Request Modes
Request Levels
The Univ erse II is software configur able to re quest on all VMEbus request le vels: BR3*,
BR2*, BR1*, and BR0*. The d efault setting is for le vel 3 VMEbus request. The request level
is a global programming option set t hrough the VRL field in the MAST_CTL register
(Ta ble A.81). The programmed request level is used by the VMEbus Mast er Interface
reg ardless of the channel (Interrupt Channel, DMA Channel, or PCI Target Channel) currently
accessing the VMEbus Master Interface.
Fair and Dema nd
The Univ er se II requester may be programmed for either Fair or Demand mode. The request
mode is a global progra mming option set through the VRM bits in the MAST_CTL register
(Table A.81).
In Fair mode, the Universe II does not request the VMEbus until there are no other VMEbus
requests pending at its programmed level. This mode ensures that every requester on an equal
level has acces s to the bus.
In Demand mode (the default setti ng), the re quester asserts its bus request regardless of the
state of the BRn* line. By requesting the bus frequently, requesters far down the daisy c hain
may be prevented from ever obtaining bus o wnership. This is referred to as “starving” those
requesters. Note that in order to achieve fairness, all bus requesters in a VMEb us system must
be set to Fair mode.
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2.2.1.3 VMEbus Release
The Universe II VMEbus reques t er can be configured as either RWD (releas e when done) or
ROR (release on request) using the VREL bit in the MAST_CTL register (Table A.81). The
default setting is for RWD. R OR means t he Universe II releases BBSY* only if a bus request
is pending from another VMEbus master and once the channel that is the current owner of the
VMEbus Master Interface is done. Ownershi p of the bus may be assum ed by another channel
without re- arbitration on the bus i f t here are no pending requests on any lev el on the VMEb u s.
When set for RWD, the VMEbus Master Inter face releas es BBSY* when the channel
accessing the VMEbus Master Interface is done (see belo w). Note that the MYBBS Y status
bit in the M ISC_STAT registe r (Table A.83) is set while the Universe II asserts the BBSY*
output.
In RWD mode, the VM Ebus is relea sed when the cha nnel (for example, the DMA Channel) is
done, even if another channel has a request pending (for example, the PC I Target Channel). A
re-arbitration of the VMEbus is required for any pending channel requests. Each channel has a
set of rul es that determine when it is ‘done’ with its VMEbus transaction.
The Interrupt C hannel is done when a single interrupt acknowledge cycle is complete.
The PCI Target Channel is done under the following conditions:
• when the TXFIFO is empty (the TXFE bit is set by the Univ erse II in the
MISC_STAT register, Table A.83),
• when the maxi mum number of bytes per PCI Tar get Channel tenure has been reached
(as programmed with the PWON field in the MAST_CTL register, Table A.81)1,
• after each posted wri te, if the PWON is equal to 0b1111, as programmed in the
MAST_CTL re gister, Table A.81
• when the coupled cycle is complete and the Coupled Window Timer has expired,
• if the Coupled Request T imer (page 2-42) e xpires before a coupled cycle is retried b y
a PCI master, or
• when VMEb us o wnership is acquired with the VO WN bit in the MAST_CTL
regis ter and then the V O WN bit is cleared (i n other words, if the VMEbus is acquired
through the use of the V OWN bit, the Univ erse II does not release BBSY* until the
VOWN bit is clear ed—see “VME Lock Cycles—E xcl usive Access to VMEbus
Resources” on page 2-47).
1. This setting is overridden if the VOWN m echanism is used.
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The DMA Cha nnel is done under the following conditions (see “FIFO Operation and Bus
Ownership” on page 2-92 and “DMA Error Handling” on page 2-96):
• DMAFIFO full during VMEb us to PCI bus transfers,
• DMAFIFO empty during PCI bus to VMEbus tra nsfers,
• if an error is encountered during the DMA operation,
• the DMA VMEbus Tenure Byte Counter has e xpired, or
• DMA block is complete.
The Uni verse II does not monitor BCLR* and so its ownership of the VMEbus is not aff e cted
by the assertion of BCLR*.
2.2.2 Un i verse II as VMEb u s Master
The Universe II be com es VME bus master as a result of the following chain of events:
1. a PC I mast er acces ses a Universe II PCI target image (leading to VMEbus access )
or the DMA Channel initiates a transac tion,
2. either the Univ erse II PCI Target Channel or the DMA Channel wins access to the
VMEbus Master Interface through internal arbitration, and
3. the Universe II Master Interface requests and obtains ownership of the VMEbus.
The Universe II will also become VMEbus master if the VMEbus ownership bit is set (see
“VME Lock Cycles—Exclusi ve Access to VME bus Resources” on page 2-47) and in its role
in VMEbus interrupt handling (see “VMEbus Interrupt Handling” on p age 2-68).
The following s ections describe the function of the Universe II as a VMEbus master in terms
of the diffe rent phases of a VMEbus transaction: addressing, dat a transfer , cycle termination,
and bus release.
2.2 .2.1 A ddres s ing C apabil itie s
Depending upon the programming of the PCI target image (see “PCI Bus Target Images” on
page 2-53), the Universe II generates A16, A24, A32, and CR/CSR address phases on the
VMEbus . The ad dress mode and type (su pervisor/non-pri vileged and program/data) are also
programmed through t he PCI target image. Address pipelining is provided except during
MBLT cycles, where the VMEbus spe cification does not permit it.
The address and AM codes that are generated by the Universe II are functions of the PCI
address and PCI target image programming (see “PCI Bus Target Image s” on page 2-53) or
through DMA programming.
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The Universe II generates ADdress-Only-with-Handshake (ADOH) cycles in support of lock
commands for A16, A24, and A32 spac es. ADOH cyc les must be generated through the
Special Cycle Generator (see “The Special Cycle Generator” on page 2-45).
There are two User Defined AM codes that can be programmed through t he USER_AM
regis ter (Table A.84). The USER_AM register can only be used to generate and accept AM
codes 0x10 through 0x1F. These AM codes are designated as USE RAM codes in the VMEb us
specification. After power-up, the two values in the USER_AM register default to the same
VME64 user-defined AM code.
If USER_AM codes are used with the VMEbus Slave Interface, ensur e tha t the cycles use
32-bit addressing, and that only single cycle accesse s are used. BLT s and MBLTs with
USER_AM codes will lead to unpredictable behavior.
2.2.2.2 Data Tr an sfer Capabilities
The data transf er between the PCI bus and VMEbus is depicted in Figure 2.2 on pa ge 2-12.
The Uni verse II can be seen as a funnel where th e mouth of the funnel is the data width of the
PCI transaction. The end of the funnel is the maximum VM Eb us data width prog rammed into
the PCI target im age. For example , consider a 32-bit PCI transac t ion access ing a PCI target
image with VD W set to 16 bits . A data beat with all by te lanes enabled will be br oken into t wo
16-bit cycles on the VMEb us. If the PCI tar get i mag e is also programmed with block transfers
enabled, the 32-bit PCI data beat will result in a D16 block transfer on the VMEbus. Write
data is unpac ked to the VMEbus and read data is pac ked to the PCI bus data width.
If the data width of the PCI data be at is the same as the maximum data width of the PC I tar get
image, then the Universe II maps the data beat to an equivalent VMEb us cycle. For example,
conside r a 32-bit PCI transaction acces sing a PCI tar ge t image with VD W set to 32 bits. A
data beat with all byte lanes enabl ed is transl ated to a single 32-bit cycle on the V MEbus.
As the gene ral rule, if the PC I b us dat a width is le ss than the VM Ebus data width then there is
no packing or unpacking between the two buses. The only exception to this is during 32-bit
PCI multi- data beat transactions to a PCI target ima ge program med with maximum VMEbus
data width of 64 bits. In this cas e, packing/unpacking occurs to make maximum use of the full
bandwidth on both buse s.
Only aligned VMEbus transactions are generated, so if the requested PCI da ta beat has
unaligned or non-contiguous b yte enables, then it is broken into multiple aligned VMEbus
transactions no wider than the programmed VMEbus data width. F or exampl e, consider a
thre e-byte PCI data beat (on a 32-bit PCI bus ) acces sing a PCI tar ge t image with VDW set to
16 bits. The three-byte PCI data beat will be broken into two aligned VMEbus cycles: a
single-byte cycle and a double-byte cycle (the ordering of the two cycles depends on the
arrangement of the byte enables in the PCI data beat). If in the above example the PCI target
image has a VDW set to 8 bits , then the t hree -b y te PCI data beat will be broken into three
single-byte VMEb us cycles.
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BLT/MBLT cycles are initiate d on the VM Ebus if t he PCI ta r ge t image has been pr ogramme d
with this capacity (see “PCI Bus Target Images” on page 2-53). The length of the BLT/MBLT
transactions on the VMEbus will be determi ned b y the initiating PCI t ransaction or the sett ing
of the PWON field in the MAST_CTL registe r (Ta ble A. 81). For example, a single data beat
PCI transac tion queued in the TXFIFO results in a single data beat block transfer on the
VMEbus . With the PWON field, the user can specify a transfer byte count that will be
dequeued from the TXFIFO before the VMEbus Master Interface re linquishes the VMEbus.
The PW ON fi eld specifies the minimum tenure of the Universe II on the VMEbus. Ho wever,
tenure is extended if the VOWN bit in the MAST_CTL register is set (see “Using the VOWN
bit” on page 2-48).
During DMA operations, the Unive rse II will a ttempt block transfers to the maximum length
permitted by the VMEbus specification (256 bytes for BLT, 2 Kbytes for MBLT) and as
limited by the VON counter (see “DMA VM Ebus Ownership” on page 2-81).
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The Universe II provides indivisible transactions with the VMEbus lock commands and the
VMEbus ownership bit (see “VME Lock Cycles—Exclusive Ac cess to VMEbus Resources”
on page 2-47).
Data wi dth of PCI
transaction
Max imum data width
programmed into PCI
target image
PCI BUS SIDE VMEBUS SIDE
Data width exceeds
maximu m data width of the
PCI target im age
Data width fits with maximum
data width of the PCI target
image
Figure 2.2 : Influence of Transaction Data Wi dth and Target Image
Data Width on Data Packing/Unpacking
WRITE (UNPACKING)
READ (PACKING)
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2.2.2.3 Cycle Terminations
The Universe II accept s BERR* or DTACK* as cycle terminations from the VMEbus sla v e. It
does not support RETRY*. The assertion of BERR* indicates that some type of system error
occurred and the transaction did not complete properly. A VMEbus BERR* r eceiv ed by the
Uni v er se I I during a coupled transaction is communicated t o the PCI master as a Tar get-Abort.
No information is logged if the Univ erse II recei ves BERR* in a coupled transaction. If an
error occurs during a posted write to the VMEbus , the Univ er se II uses the V_AMERR
register (Table A.107) to log the AM code of the transaction (AMERR [5:0]), and the state of
the IACK* signal (IACK bi t, to indicate whether the error occurred during an IACK cycle).
The current transaction in the FIFO is purged. The V_AMERR regi ster also records if
multiple errors have occurred (with the M_ERR bit), although the actual number of errors is
not gi v en. The error log is qualified b y the v alue of the V_STAT bit. The address of the errored
transaction is latched in the V_AERR register (Table A.108). When the Uni verse II receiv es a
VMEbus error during a posted write, it generates an interrupt on the VMEbus and/or PCI bus
depending upon whether the VERR and LERR interrupts are enable d (see “Interrupt
Handling” on page 2-68, Table A.60 and Table A.61).
DTACK* signals the successful completion of the transaction.
2.2.3 Un iverse as VMEb us Slave
This section describes the VMEb us Slave Channel and other aspect s of the Uni verse II as
VMEbus slave. The following topics are discussed:
• “Coupled Transfers ” on page 2-14,
• “Posted Writes” on page 2- 15,
• “Prefetched Block Reads” on page 2-16,
• “VMEb us Lock Commands (ADOH Cycles)” on page 2-18,
• “VMEbus Read-Modify-Write Cycles (RMW Cycles)” on page 2-19,
• “Location Monitors” on page 2-19 and
• “Generating PC I Configuration Cycles” on page 2-20.
The Universe II becomes VMEbus slave when one of its eight programmed slave ima ges or
register images are accessed b y a VMEbus master (note that the Univ erse II cannot reflect a
c ycle on the VMEb us and access its elf). Depending upon the programming of the sla ve image,
different possible transaction types result (see “VME Sla ve Images” on page 2-50 for a
description of the types of accesses to which the Universe II responds).
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For reads, the transaction can be coupled or prefetched. Similarly, write transactions can be
coupled or posted. The type of read or write transaction allowed by the slave image depends
on the programming of that particular VMEb us slave image (see Figure 2.3 below and “VME
Slave Images” on page 2-50). To ensure sequential consistency, prefetched reads, coupled
reads, and coupled write operations are only proces sed once all previously posted write
operations hav e com pleted (i.e. the RXFIFO is empty).
Incoming cycles from the VMEbus can have data widths of 8-bit, 16-bit, 32-bit, and 64-bit.
Although the PCI bus supports only two port sizes (32- bit and 64-bit), the byte lanes on the
PCI bus can be individually enabled, which allo ws each type of VMEbus transaction to be
directly mapped to the PCI data bus .
In order for a VMEb us slave image to res pond to an incoming cycle, the PCI
Master Interface must be enabled (bit BM i n the PCI_CSR re gister, Table A.3).
If data is enqueued in the VMEbus Slave Channel FIFO and the PCI BM bit is
cleared, the FIFO will empty b ut no additional tr ans fer s will be received.
2.2.3.1 Coup led Transfers
A coupled transfer means that no FIFO is in volved in the transact ion and handshakes are
relayed directly through the Universe II. Coupled mode is the default setting for the VMEbus
sla ve images. Coupled transfers only proceed once all posted write entries in the RXF IFO
ha ve completed (s ee “Posted Writes ” belo w).
A coupled cycl e with multiple data beats (i.e. block transfers ) on the VMEbus side is always
mapped to single data beat transactions on the PCI bus, where each data beat on the VMEbus
is ma pped to a single data beat transaction on the PCI bus regardles s of data be at size. No
packing or unpacking is perfor med. The only e xception to this is when a D64 VMEbus
transaction is mapped to D 32 on the PCI bus. The data width of the PCI bus depends on the
Figure 2.3 : VMEbus Slave Channe l Dataflow
RDFIFO
RXFIFO
PCI BUS
MASTER
INTERFACE
VMEbus
SLAVE
INTERFACE
PREFETCHED READ DATA
COUPLED READ DATA
COUPLED WRITE DATA
POSTED WRITE DATA
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programming of the VMEbus sla ve image (32-bit or 64-bit, see “VME Slav e Images” on
page 2-50). The Uni verse II enables the appropriate byte lanes on the PCI bus as re quired by
the VMEbus tr ansaction. F or example, a VMEb us s lav e image programmed to generate 32-bit
transactions on the PCI bus is accessed by a VMEbus D08 BLT read transaction (prefetching
is not enabled in this slave image). The transaction is mapped to single data beat 32-bit
transfers on the PCI b us with only one byte lane enabled.
Target-Retry from a PCI ta rget is not communicated to the VMEbus ma st er. PC I transact ions
termina ted with Tar ge t-Abort or Maste r -Abor t are terminated on the VMEbus with BE RR*.
Note that the Uni verse II sets the R_TA or R_MA bits in the PCI_CS regi ster (Table A.3)
when it re ceives a Target-Abort or Master-Abort.
2.2.3.2 P osted Writes
A posted write involv es the VMEbus master writing data into the Uni verse II’s RXFIFO,
rather than directly to the PCI address. Write transacti ons from the VMEbus are processed as
posted if the PWEN bit is set in the VMEb us sla ve image control register (see “VME Slav e
Images” on page 2- 50). If the bit is cleared (the default setting) the trans action bypa sses the
FIFO and is performed as a coupled transfer (see above). Incoming posted writes from the
VMEbus are queued in the 32-entry deep RXFIFO. (The RXFIFO is the same structure as the
RDFIFO. The diffe rent names are used for the FIFO’s two roles , only one of which it can
implement at once.) Each entry in the RXFIFO can contain 64 address bits, or 64 data bits.
Each incoming VMEbus address phase, whether it is 16-bit, 24-bit, or 32-bit, constitutes a
single entry in the RXFIFO and is followed by subsequent data entries. The address entry
contains the translated PCI address space and command information mapping relevant to the
particula r VMEbus slave image that has been access ed (see “VME Slave Images” on
page 2-50). For this rea son, any re-programming of VMEbus slave image attributes will only
be reflected in RX FIFO entries queued after the re-programming. Transactions queued before
the re-pr ogra mming are de liv e red to the PCI bus with the VMEbus slave image attributes that
were in use before the re-programming.
Incoming non-block write transactions from the VMEbus require two entries in the RXFIFO:
one address entry (with accompan ying command inf ormation) and one data entry. The size of
the data entry corresponds to the dat a widt h of the VMEb us transfer. Block transfers require at
least two entries: one entry for address and command in formation, and one or more data
entries. The VM Ebus Slave Channel packs data received during block transf ers to the full
64-bit width of the RXFIFO. For example, a te n data phase D16 BLT transfer (20 bytes in
total) does not require ten data entries in the RXFIFO. Instead, eight of the ten data phases (16
bits per data phase for a total of 128 bits) are packed into two 64-bit data entries in the
RXFIFO. The final two data phases (32 bits combined) are queued in the ne xt RXFIFO entry.
When you add the address entry to the three data entries, this VMEbus block write has been
stored in a total of four RXFIFO entries.
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Unlike the PCI Tar get Channel ( see page 2-38), the VMEb us Slave Channel does not retry the
VMEbus if the RXFIFO does not have enough space to hold an incoming VMEbus write
transaction. Instead, the DTACK* response from the VMEbus Slave Interface is delayed until
space becom es available in the RXFIFO. Since single transfers require two entrie s in the
RXFIFO, two entries must be freed up before the VMEb us Sla ve Interface assert s DTACK*.
Similarly, the VMEbus Slave Channel requires two available RXFIFO entries before it can
acknowledge the first data phase of a BLT or MBLT transfer (one entry for the address phase
and one for the first data phase) . If the RXFIFO has no available space for subsequent data
phases in the block transfer, then the V MEbus Slave Interfa ce delays assertion of DTACK*
until a single entry is available f or the next data phase in the block transfer.
The PCI Master Interface uses transactions queued in the RXFIFO to generate transactions on
the PCI bus. No address phase delet ion is performed, so the length of a transaction on the PCI
bus corresponds to the length of the queued VMEbus transa ction. Non-block transfers are
generated on the PCI bus as s ingle data beat transactions. Block transfers are generated as one
or more burst transactions, where the length of the burst transaction is programmed by the
(PABS field in the MAST_CTL register, Table A. 81).
The Universe II always packs or unpacks data from the VMEbus transaction to the PCI bus
data width programmed into the VMEbus slave image (with all PCI bus byte lanes enabled).
For example, consider a VMEbus slave image programmed for posted writes and a D32 PCI
bus tha t is accessed with a VMEbus D16 bloc k write transaction. The VMEbus D16 wri te
transaction is mapped to a D32 write transaction on the PCI bus with all byte lanes enabled.
(Ho wever , note that a single D16 transaction from the VMEbus is map ped to the PCI bus as
D32 with only two byte lanes enabled).
During block transfers, the Universe II will pack d ata to the full negotiate d width of the PCI
bus. This may imply that for block tra nsfers that begin or end on addresses not aligned to the
PCI bus width different byte lanes may be enabled during each data beat.
If an err or occurs during a posted write to the PCI bus, the Universe II uses the L_CMDERR
regis ter (Table A.32) to log the command information for the transaction (CM DERR [3:0]).
The L_CMDERR register also rec ords if multiple e rrors have occur red (with the M_ERR bit)
although the actual number is not given. The error log is qualified with the L_STAT bit. The
address of the errored transaction is latched in the LAERR register (Table A.33). An interrupt
is generated on the VMEbus and/or PCI b us depending upon whether the VERR and LERR
interrupts are e nabled (see “Bus Error Handling” on page 2-58 and “ Interrupt Handling” on
page 2-68).
2.2.3.3 Prefetched Block Reads
Prefetching of read data occurs for VMEbus block transfers (B LT, MBLT) in those slave
images that ha ve the prefetch enable (PREN) bit set (see “VME Slave Images” on page 2-50).
In the VMEbus Slave Channel , prefetching is not supported for non BLT/MBLT transfers.
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Without prefetching, block read trans actions from a VMEbus master are handled by the
VMEbus Slave Channel as coupled reads. This means that each data phase of the block
transfer is translated to a single data beat transaction on the PCI bus. In addition, only the
amount of data requested during the relev a nt data phase is fetched from the PCI bus . F or
e xample, a D16 block read transaction with 32 data phases on the VMEb us maps to 32 PCI
bus trans act ions, where each PCI bus tr ansaction has only two byte l anes enabled. Note the
VMEbus lies idle during the arbitration time required for each PCI bus transaction, resulting
in a considerable performance degradation.
With prefetching enabled, the VMEbus Sla ve Channel uses a 32-entry deep RDFIFO to
provide read data to the VMEb us with minimum latency. (The RXFIFO is the same structure
as the RDFIFO. The different n ames are used for the FIFO’s two roles, only one of which it
can implement at once.) The RDFIFO is 64 bits wide, with additional bits for control
information. If a VMEbus slave image is programmed for prefetching (see “VME Slave
Images” on page 2-50), then a block read access to that image causes the VMEbus Slave
Channel to gene rate aligned bur s t read transactions on the PCI bus (the size of the burst read
tra nsactions is determin ed b y the setting of the aligned burs t size , PABS in the MAST_CT L
register). These PCI b urst read transaction are queued in the RDFIFO and the data i s then
delive red to the VMEbus. Note that the first data phase provided to the VMEbus master is
essentially a coupled read, b ut subsequent data phases in t he VMEb us block read are deliv ered
from the RDFIFO and are essentially decoupled (see “Pref etched Reads” on page 2-60 for the
impact on bus error handling).
The data width of the transaction on the PCI bus (32-bit or 64-bit) depends on the setting of
the LD64EN bit in the VMEbus slave image control register (e.g. see Table A.85) and the
capabilities of the accessed PCI target. Internally, the prefetched read data is packed to 64 bits ,
reg ardless of the width of the PCI b us or the dat a wi dth of the original VMEbus block read (no
address infor mation is stored with the data). Once one entry is queued in the RDFIFO, the
VMEbus Slave Interface delivers the data to the VMEbus, unpacking the data as necessary to
fit with the data width of the original VMEbus block r ead (e.g. D1 6, or D32). The VMEb us
Slave Interface continuously delivers data from the RDFIFO to the VMEbus master
performing the bl ock read transaction. Because PCI bus data transfer rates e xceed those of the
VMEb us , it is unlikely that the RDFIFO will e ver be unabl e to deliver data to the VMEbus
master. For this reason, block read performance on the VMEbus will be similar to that
observ ed with block writes. However, sho uld the RDFIFO be unable to del i ver data to the
VMEbus master (which may happen if there is considerable traff ic on the PCI b us or t he PCI
bus tar get has a slo w response) the VMEbus Sla ve Interf ace delays DTACK* assertion unti l an
entry is queued and is available for the VMEbus block read.
On the PCI side, prefetching continues as long as there is room for a nother transaction in the
RDFIFO and the initiating VMEbus block read is still acti ve. The space required in the
RDFIF O for another PC I bur st read trans action is determined b y the setting of the PCI aligned
burst size (PABS in the MAST_CTL register, Table A.81). If PABS is set for 32 bytes, the re
must be four entries available in the RDFIFO; for aligned burst size set to 64 bytes, eight
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entries must be available, for aligned burst si ze set to 128 bytes, there must be 16 entries
available. When there is insufficient room in the RDFIFO to hold another PCI burst read, the
read transactions on the P CI bus are terminated and only resum e if room becomes available
for another aligned burst AND the original VMEbus block read is still active. W hen the
VMEbus block transfer terminates, any remaining data in t he RDFIFO is purged.
Reading on the PCI side will not cross a 1024-byte boundary. The PCI Master Interf ace will
release FRAME# and the VMEbus Slave Channel will relinquish internal ownership of the
PCI Master Interface when it re aches this boundary. The VMEbus Slave Channel will
re-request internal ownership of the PCI PC I Master Interface a s soon a s possible, in orde r to
continue reading from the external PCI target. (As described elsewhere, the PABS setting
determines how much data must be available in the RDFIFO before the VMEbus Slave
Channel continues reading.)
Regardless of the read request, the data width of prefetching on the PCI s ide is full width with
all byte lanes enable d. If the request is unaligned, then the first PCI data beat will have only
the relevant byte lanes enabled. Subsequent data beats will have full data width with all b yte
lanes enabled. If LD64EN is set in the VMEbus Sla ve image, the Universe II requests D64 on
the PCI bus b y asserting REQ64# during the address phase. If the PCI tar get does not r espond
with ACK64#, subsequent data beats are D32.
If an err or occurs on the PCI bus, the Universe II does not translate the error condition into a
BERR* on the VMEbus. Indeed, the Universe II does not directly map the error. By doing
nothin g, the Universe II force s the exte rnal VME bus error timer to e xpire.
2.2.3.4 VMEbu s Lock Commands (ADOH Cycles)
The Universe II supports VMEbus lock commands as described in the VME64 specification.
Under the specification, ADOH cycles are used to execute the lock command (with a special
AM code). Any resource locked on the VMEbus cannot be accessed by any other resource
during the bus tenure of the VMEbus master.
When the Universe II receives a VM Ebus lock command, it asserts LOCK# to the addressed
resource on the PCI b us. The PCI Master Interface processes this as a read transfer (with no
data). All subsequent slave VMEbus transactions are coupled while t he Univ erse II owns PCI
LOCK#. Note that the VMEbus Sla ve Channel has dedicated access to the PCI Master
Inte rf a ce during the locked transa ction. The Univ e rse II holds the PCI bu s lock until the
VMEbus loc k command is terminated, i.e. when BBSY* is nega ted.
The Univ er se II accepts ADOH c ycles in any of th e slav e images when the Universe II PCI
Master Inter face is enable d (B M bit in PCI_CSR re gister) and the images are programmed to
map transactions into PCI Memory Space.
In the event that a Target-Abort or a Master-Abort occurs during a locked transaction on the
PCI bus, the Universe II will relinquish its ownership of LOCK# in accord with the PCI bus
Specification. It is the responsibility of the user to verify the R _MA and R_TA status bits of
the PCI_CSR status register to determine whether or not o wners hip of LOCK# was lost.
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Once an exter nal VMEbus masters locks the PCI bus, the Uni verse II DMA will not perf orm
transf ers on the PCI bus until the bus is unlocked.
2.2.3.5 VMEbus Read-Modify-Write Cycles (RMW Cycles)
A read-modify-write (RMW) c ycle allows a VMEbus master to read from a VMEbus slav e
and then write to the same resource without relinquishing bus tenure between the two
operations. Each of the Univ erse II slav e images can be programmed to map RMW
tra nsactions to PCI locke d transactions. If the LLRMW enable bit is set in the selecte d
VMEbus sla ve image control register (e.g. Table A.85), then ev ery non-block slave read is
mapped to a coupled PCI locked read. LOC K# will be held on the PCI bus until AS* is
negated on the VMEbus. Every non-block slave read is assumed to be a RMW since there is
no possible indication from the VM Ebus master that the single cycle re ad is just a read or the
be ginning of a RMW.
If the LLRMW enable bit is not se t and the Universe II receive s a VMEbus RM W cycle, the
read and write portions of the c ycle will be treated as independent transactions on the PCI b us:
i.e., a read foll owed by a write. The write may be coupled or decoupled depending on the state
of the PWEN bit in the accessed slave image.
Note: There may be an adverse performance impact for reads that are
proces sed through a RM W-capable slave image; this may be acce ntuated if
LOCK# is currently owned by another PCI master.
RMW cycles are not supported with unaligned or D24 cycles.
When an external VMEbus Master begins a RMW cycle, at some point a read cycle will
appear on the PCI b us . During the time b etween when the read cy cle occur s on the PCI b us
and when the associat ed write cycle occurs on the PCI bus, no DMA transfer s will occur on
the PCI bus.
2.2.3.6 Register Accesses
See “Registers” on page 2-100 for a full descript ion of re gis ter mapping and register access.
2.2.3.7 Location Monitors
Univ erse II has four location monitors to support a VMEbus broadcast capability. The
location monitors’ image is a 4-Kbyte ima ge in A16, A24 or A32 spa ce on the V MEbus. If
enabled, an access to a location monitor causes the PCI Master Interface to generate an
interrupt.
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The Loc ation Monitor Control Register (LM_CTL, Table A.101) controls the Univer se II’s
location monitoring. The EN field of the LM_CTL register enables the capability. The
PGM[1:0] f ield sets the Pr ogram/Data AM code. The SUPER[1:0] field of the LM_CTL
register sets the Supervisor/User AM code to which the Universe II responds. The VAS[3:0]
field of the LM_CTL register specifies the address space that is monitored. The B S[31:12]
field of the location monitor Base Address Register (LM_BS, Table A.102) specifies the
lowest address in the 4 Kbyte range that will be decoded as a location monitor access. W hile
the Universe II is said to have four location monitors, they all sha re the same LM_CTL and
LM_BS re gisters.
In address spaces A24 and A16, the respective upper address bits are ignored.
When an access to a location monitor is detected, an inte rrupt is generated on the PCI bus.
VMEb us address bits [4:3] determin e which Location Monitor will be used, and hence which
of four PCI interrupts to generate. (See “Location Monitors” on page 2- 75 for details on
mapping the interrupts from the location monitor.)
The location monitors do not store write data. Read data from the location monitors is
undefined. Location monitors do not support BLT or MBLT transfers.
Each Universe II on the VMEb us should be programmed to monitor the same 4 Kbytes of
addresses on the VMEbus. Note that the Universe II may access its own loca tion monitor. If
the Universe II accesses its own (enabled) locati on monitor, the same Universe II generates
DTACK* on the VMEb us and thereby terminates its own cycle. This removes the necessity of
the system integrator ensuring that there is another card enabled to generate DTACK*. The
generation of DTACK* happens after the Universe II has decoded and responded to the cycle.
If the location monitor is accessed b y a di fferent master , the Uni verse II does not respond with
DTACK*.
2.2.3.8 Generating PCI Configuration Cycles
PCI Configuration cy cles can be generated by accessing a VMEbus slave image whose Local
Address Space field (LAS) is set for Configuration Spac e.
Both Type 0 and Type 1 cycles are generated and handled through the same mechanism. Once
a VMEbus cycle is received and mapped to a configuration cycle, the Universe II compares
bits [23:16] of the incoming address with the va lue stored in the MAST_CTL Register’s Bus
Number fi eld (BUS_NO[7:0] in Table A.81). If the bits are the same as the BUS_NO field,
then a TYPE 0 access is generated. If the y are not the same, a Type 1 configuration access is
generated. The PCI b us-generated address then becomes an unsigned addition of the incoming
VMEbus address and the VMEbus slave image translation offset.
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Generating Conf igur at ion Typ e 0 Cycles
The Universe II asserts one of AD[31:11] on the PCI bus to select a device during a
configuration Type 0 access. To perform a configuration Type 0 cycle on the PCI b us:
• Program the LAS field of VSIx_CTL for Configuration Space,
• Program the VSIx_BS, VSIx_BD regis ters to some suitable value ,
• Program the VSIx_TO register to 0, and
• Program the BUS_NO field of the MAST_CTL register to some value.
Perfor m a VMEbus access where:
• VA[7:2] identifies the PCI Re gis te r Number and will be mapped directly to AD[ 7:2],
• VA[10:8] identifies the PCI Function Num ber and will be mapped directly to
AD[10:8],
• VA[15:11] selects the device on the PCI bus and will be ma pped to AD[31:12]
according to Table 2.2,
• VA[23:16] matches the BUS_NO in MAST_CTL register, and
• Other address bits are irrelevant—they are not mapped to the PCI bus.
Table 2.2 : PCI Addres s Line Asserted as a Function of VA[15:11]
VA[15:11]aPC I Ad d ress L in e A sse rted b
00000 11
00001 12
00010 13
00011 14
00100 15
00101 16
00110 17
00111 18
01000 19
01001 20
01010 21
01011 22
01100 23
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Generating Conf igur at ion Typ e 1 Cycles
To generate a conf iguration Type 1 cycle on the VMEbus:
• Program LAS field of VSIx_CTL to Configuration Space,
• Program the VSIx_BS, VSIx_BD regis ters to some suitable value ,
• Program the VSIx_TO register to 0 and
• Program the BUS_NO field of the MAST_CTL register to some value.
Perfor m a VMEbus access where:
• VMEb us Address[7:2] identif ies the PCI Register Number,
• VMEb us Address[10:8] identif ies the PCI Function Number,
• VMEb us Address[15:11] identif ies the PCI Device Number,
• VMEb us Address[23:16] does not match the BUS_NO in MAST_CTL register, and
• VMEb us Address[31:24] are mapped directly through to the PCI bus.
01101 24
01110 25
01111 26
10000 27
10001 28
10010 29
10011 30
10100 31
a. The othe r value s of VA[1 5:11] are not defined and m ust not be
used.
b. Only one of AD[31:11] is asserted; the other address lines in
AD[31:11] are negated.
Table 2.2 : PCI Addres s Line Asserted as a Function of VA[15:11]
VA[15:11]aPCI Address Line Assertedb
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2.2.4 VMEbus Configu ration
The Universe II provides the following functions to assist in the initial configuration of the
VME bus sy st em:
• First Slot Detector,
• Re gister Access at Po wer - up, and
• Auto Slot ID (two methods).
These are described separately below.
2.2.4.1 First Slot Detector
As specified by the VME64 specification the First Slot Detector module on the Universe II
sample s BG3IN* immediately after re set to determine whether the Univer se II’s host board
resides in slot 1. The VMEb us specif ication requires that BG[3:0]* lines be driven high aft er
reset. This means that if a card is preceded b y another card in the VMEbus system, it will
always sample BG3IN* high after reset. BG3IN* can only be sampled low af ter reset by the
first card in the system (ther e is no preceding card to drive BG 3IN* high). If BG3IN* is
sample d at logic lo w immediately a fter reset (due to the Universe II’s internal pull-do wn),
then the Univer se II’s host board is in slot 1 and the Uni verse II becomes SYSCON:
otherwise, the SYSCON module is d isabled. This mechanism may be ove rridden b y software
through clearing or setting the S YSCON bit i n the MISC_CTL register (Table A.82).
The Universe II monitor s IACK* ( rathe r than IACKI N*) when it is configured as SYSCON.
This permits it to operate as SYSCON in a VMEbus chassis slot other than slot 1, provided
there are only empty slots to its left. The slot with SYSCON in it be comes a virtual slot 1.
2.2.4.2 VMEbus Register Access at Power- up
The Universe II provides a VMEbus slave image that allows access to all Universe II Control
and Status Registers (UCSR). The base address for this slave image is programmed through
the VRAI_BS register (Ta ble A.104). At power-up, the Universe II can program the
VRAI_BS and VRAI_CTL (Table A.103) registers with information specifying the UCSR
sla ve image (see “Power-Up Options” on page 2-115).
Regist er access at power-up would be used in s ystems where the Universe II’s card has no
CPU, or where register access for that card needs to be independent of the local CPU.
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2.2.5 Automatic Slot Identif ication
The Univ er se II supports two types of Auto-ID functionality. One type uses the Auto S lot ID
technique as described in the VME64 specification. The other type uses a proprietary method
de veloped b y DY4 Systems and implemented in the Tundra SCV64. Neither system identifies
geographical addressing, only the relati ve posi tion amongst the boards present in the system
(i.e. fourth board versus fourth slot).
Auto-ID prevents the need for jumpers to uniquely identify cards in a system. This can:
• increase th e speed of syst em level repairs in the field,
• reduce the possibili ty of incorrect configurations, and
• reduce the number of unique spare cards that must be stocked.
Both methods of Auto ID employed by the Universe II are described belo w.
2.2.5.1 Au to Sl ot ID : VME64 Specified
The VME64 auto ID cycle (described in the VME64 Specification) requires at power - up that
the Auto ID slave
• generate IRQ2*, and
• negate SYSFAIL*.
When the Auto ID slave responds to the Monarch’s IACK cycle, it will
• enable acces ses to its CR/CS R space,
• provide a Status/ID to the Monarc h indicating the interrupt is an Auto-ID request,
• assert DTA CK*, and
• release IRQ2*.
The Universe II pa rtici pates in the VME64 auto ID cycle in either an automatic or
semi-a utoma tic mode . In its fully automatic mode, it holds SYSFAIL* asserted until
SYSRST* is negated. When SYSRST* is ne gated, the Univ erse II asserts IRQ2* and releases
SYSFAIL*. In its semi- automa tic mode, the Universe II still holds SYSFAIL* asse rted until
SYSRST* is negated. However, when SYSRST* is negated, the local CPU performs
diagnostics and l ocal logic sets the AUTOI D bit in the MISC_CTL register (Table A.82). This
asserts IRQ2* and releases SYSFAIL*.
After SYSFAIL* is released and the Univer se II detects a le v el 2 IACK cycle, it responds with
the STATUS/ID stored in its level 2 STATID regist er (which defaults to 0xFE).
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The Univer se II can be progra mmed so that it wi ll not release SYSFAIL* until the SYSFAIL
bit in the VCSR _CLR register (Ta ble A.125) is cleared by local logic (SYSFAIL* is asserted
if the SYSFAIL bit in the VCSR_SET register, Tab le A.126, is set at po wer-up). Since the
system Monarch does not service the Auto-ID sla ve until after SYSFAIL* is negated, not
clearing the SYSFAIL bit allo ws the Auto-ID process to be delayed until the CPU completes
local diagnostics. Once local diagnostics are complete, the CPU clears the SYSFAIL bit and
the Auto-ID c ycle proceeds.
The Monarch can perform CR/CSR reads and writes at A[23:19]= 0x00 in CR/CSR space and
re-locate the Unive rse II ’s CR/ CSR base addr ess .
Univ erse II and the Auto-I D Monarch
At po wer -up an Auto-ID Monar ch waits to run a le ve l 2 IACK cycle until after SYSFAIL*
goes high. After the IACK cycle is pe rforme d and it has received a Status/ID indicati ng an
Auto-ID request, the monarch softw a re
• mas ks IRQ2* (s o that it will not service other interrupters at that interrupt level until
current Auto-ID cycle is comple ted),
• performs an access at 0x00 in CR/CSR space to get information about Auto-ID sla ve,
• moves the CR/CSR base address to a ne w location, and
• unmasks IRQ2* (to allow it to service the next Auto-ID slave).
The Universe II supports monarch activity through its capability to be a level 2 interrupt
handler. All other activity mus t be handled through software residing on the board.
2.2.5.2 Au to- I D: A Proprietary Tun dra Meth od
The Univ er se II uses a proprietary Auto-ID scheme if this is selected as a power-up option
(see “A uto-ID” on page 2-118). The Tundr a proprietary Auto-ID function identifies the
relative position of each board in the syst em, without using jumpers or on-board information.
The ID number generated by Auto-ID can then be used to determine the board’s base address.
After any system reset (assertion of SYSRST*), the Auto-ID logic responds to the first level
one IACK cycle on the VMEbus.
After the level one IACK* signal has been asserte d (either through IRQ1* or with a
synthesized version), the Univ erse II in slot 1 counts f i ve clocks from the start of the cycle and
then asserts IACK OUT* to the second board in the system (see Figure 2.4). All other boards
continue counting until they receive IACKIN*, then count four more clocks and assert
IACKOUT* to the next board. Finally, the last board asserts IA C KOUT* and the b us pauses
until the data transfer time-out c irc uit ends the bus c yc le b y asser ting BERR*.
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Because all boards are four clocks “wide”, the v alue in the clock count er is divi ded b y four to
identify the slot in which the board is i nstalled; any re mainder is dis car ded. Note that since the
start of the IACK cycle is not synchronized to SYSCLK, a one count variation from the
theoretical value of the board can oc cur. However, in all cases the ID value of a board is
greater than that of a board in a lower slot number. The result is placed in the DY4AUTOID
[7:0] field and the DY4DONE bit is set (both are located in the MISC_STAT register,
Table A.83).
2.2.6 System Controller Functions
When located in Slot 1 of the VMEb us system (see “First Slot Detector” on page 2-23), the
Universe II assumes the role of SYSCON and sets the SYSC ON status bit in the MIS C_CTL
register (Table A.82). In accordance with the VME64 specification, as SYSCON the Uni verse
II provides:
• a system clock driver,
• an arbitration module,
• an IACK Daisy Chain Dri ver (DCD), and
• a bus timer.
2.2.6.1 System Clock Dri ver
The Uni verse II provides a 16 MHz SYS CLK signal deriv ed from CLK64 when configured as
SYSCON.
Figure 2.4 : Timing f or Auto-ID Cycle
SYSCLK
AS*
DS0✴
IACK✴
IACKOUT✴
(CARD 1)
IACKOUT✴
(CARD 2)
IACKOUT✴
(CARD 3)
ID COUNTER
VALUE
D
CBA
00123456789101112131415
ID = 5
ID = 9
ID = 13
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2.2.6.2 VMEbus Arbit er
When the Universe II is SYSCON, the Arbitration Module is enabled. The Arbitration
Module supports the following arbitration modes:
• Fi xed Prior ity Arbitra tion M ode (PRI),
• Single Level Arbitration (SGL) (a subset of PRI), or
• Round Robin Arbitration Mode (RRS) (default setting).
These are set with the VARB bit in the MISC_CTL register (Table A.82).
Fixe d Priori ty Arbi tr ation Mo de (PRI )
In this mode, the order of priority is VRBR#[3], VRBR#[2], VRBR#[1] , and VRBR#[0] as
defined by the VME64 specification. The Arbitration Module issues a Bus Grant (VBGO
[3:0]#) to the highest requesting level.
If a Bus R eques t of higher priority than the current bus ow ner becomes as ser t ed, the
Arbitration Module asserts VBCLR# until the own er releases the b us (VRBBSY# is negated).
Single Level Arbitration Mode (SGL)
In this mode, a subset of priority mode, all requests and grants are made exclusively on
level 3. Set the Universe II in PRI mode to use this mode.
Round Robin Arbitration Mode (RRS)
This mode arbitrates all le vels in a round robin mode, repeatedly scanning from le vels 3 to 0.
Only one grant is issued per level and one owner is ne ver forced from the bus in fa vor of
another requester (VBCLR# is never asserted).
Since only one grant is issued per level on each round robin cycle, several scans will be
required to service a queue of re quests at one level.
VMEbus Arbiter Time-out
The Universe II’s VMEbus arbiter can be programmed to time-out if the requester does not
assert BB SY* within a specified period. This allows BGOUT to be negate d so that the arbiter
may continue with other re ques te rs. The timer is progra mmed using the VARBT O field in the
MISC_CTL regis ter (Table A.82), and can be set to 16 µs, 256 µs, or disabled. The default
setting for the timer is 16 µs. The arbitra tion time-out time r ha s a granularity of 8 µs; setting
the timer for 16 µs means the timer may timeout in as little as 8 µs.
2.2.6.3 IACK Dais y-Chain Driver Module
The IACK Daisy-Chain Dri ver module i s enabled when the Universe II becomes system
controller. This module guarantees that IACKIN* will stay high for at least 30 ns as specified
in rule 40 of the VME64 specification.
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2.2.6.4 VMEbus Time-out
A programmable bus timer allo ws users to select a VMEbus time-out period. The time-out
period is programmed through the VBTO field in the MISC_CTL register (Table A.82) a nd
can be set to 16µs, 32µs, 64µs, 128 µs, 256 µs, 512 µs, 1024 µs, or disabled. The default setting
for the timer is 64 µs. The VMEb us T imer module asserts VXBERR# if a VMEb us transaction
times out (indicated by one of the VMEbus data strobes remaining asserted beyond the
time-out period).
2.2.7 BI-Mode
BI-Mode® (Bus Isolation Mode) is a mechanism for logically isolating the Uni verse II from
the VMEbus. This mechanism is useful for the following purposes:
• impleme nting hot-standby systems. A system may have two identically configured
boards, one in BI-Mode. If the board that is not in BI-Mode fails, it can be put in
BI-Mode while the spare board is removed fr om BI-Mode.
• system diagnostics for routine maintenance, or
• fa ult isolation in the e vent of a card failur e, even if a spa re board is not provide d, at
least the faulty board can be isolated.
While in BI-Mode, the Universe II data channels cannot be used to communicate between
VMEbus and PCI ( Unive rse II mailboxes do provide a means of communication). The only
traf f ic permitted is to Uni verse II registers either t hrough configuration c ycles, the PCI re gister
image, the VME bus register image, or CR/CSR space. No IACK c ycles will be generated or
responded to. No DMA activity will occur. Any access to othe r PCI images will result in a
Target-Retry. Access to other VMEbus imag es will be ignored.
Entering BI-Mode has the following effects.
• The VMEbus Master Interface becomes inactive. PC I Target Channel coupled
accesses will thereafter be retried. The PCI Target Channel Posted Writes FIFO will
continue to accept transactions but will eventually fill and no further posted writes
will be accepted. The DMA FIFO will eventually empty or fill and no further DMA
activi ty will take place on the PCI bu s. The Uni verse II VMEb us Master will not
service interrupts while in BI-Mode.
• The Universe II will not respond as a VMEbus slave, except for accesses to the
register image and CR/CSR image.
• The Universe II will not r espond to any interrupt it had outstanding. All VMEbus
outputs from the Univ erse II will be tri -stat ed, so that the Universe II will not be
driving any VMEbus signals. The only exception to this is the IACK and BG daisy
chains which must remain in operation as before.
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There are four ways to cause the Universe II to enter BI-Mode . The Universe II is put into
BI-Mode:
1. if the BI-Mode power-up option is selected (Se e “Power-up Option Descriptions”
on page 2-117 and Table 2.22 on page 2-116),
2. when SYSRS T * or RST# is asserted any time after the Universe II has been
powered-up in BI-Mode,
3. when VRIR Q# [1] is asserte d, prov ided tha t the ENGBI bit in the MISC_C TL
regis ter has been set, or
4. when the BI bit in the MISC_CTL register is set.
Note that when the Universe II is put in BI-Mode, the BI bit in the MISC_CTL register
(Ta ble A.82) is set. Clearing this bit ends Bi-Mode.
There are two ways to rem ove the U n iverse II from BI-Mode:
1. powe r-up the Universe II with the BI-Mode option off (see “BI-Mode” on
page 2-118), or
2. clear the BI bit in the MISC_CTL register, which will be effective only if the
source of the BI-Mode is no longer active . That is, if VRIRQ# [1] is still being
asserted while the ENGBI b it in the MISC_CTL register is set, then attempting to
clear the BI bit in the MISC_CTL registe r will not be effecti ve.
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2.3 PCI Bus Interface
The PCI Bus Interface is organized as follo ws:
• “PCI Cycles—Overview” below,
• “Universe II as PCI Master” on page 2-35, and
• “Universe II as PCI Target” on page 2-38.
The Universe II PCI Bus Interfa ce is electrically and logically directly connec ted to the PCI
bus. For information concerning the diffe rent types of PCI accesses available, see “PCI Bus
Tar get Images” on page 2-53.
2.3.1 PCI Cycles—Overview
The PCI b us port of the Uni v erse II operates as a PCI complia nt port with a 64-bit mu ltiplexe d
address/data bus. The Univ erse II PCI bus Interface is configured as li ttle-endian using
address in var iant translation when mapping between the VMEbus and the PCI b us. Address
invariant tra ns la tion preserv e s the byte orde ring of a data structure in a little-endian memory
map and a big-endian memory map (see Appendix-E).
The Univ erse II has all the PCI signals described in the PCI specification with the exception of
SBO# and SDONE (since the Uni verse II does not provide cache support).
Univ erse II PCI cycles are synchronous, meaning that bus and control input signals are
e xternally synchronized to t he PCI clock (CLK) . PCI cycles are divided into four phases:
1. re quest,
2. address phase,
3. data transfer, and
4. cycle termination.
2.3.1.1 32-Bit Vers us 64-Bit PCI
The Univ erse II is configur ed with a 32-bit or 64-bit PCI data b us at power - up (see “PCI Bus
Width” on page 2- 119 for directions on how to configure the PCI bus width.)
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Each of the Universe II’s VMEbus slave images can be programmed so that VMEb us
transactions are mapped to a 64- bit data bus on the PCI Interface (with the LD64EN bit, e.g.
see Table A.85). If the VMEbus slave image is programmed with a 64-bit PCI bus data width
and if the Uni verse II powered up in a 64-bit PCI en vironment, then the Universe II asserts
REQ64# during the address phase of the PCI transaction. If the PCI target is 64-bit capable,
then it will respond with ACK64# and the Uni verse II will pack data to the full width (64 bits)
of the PCI bus. If the PCI ta rget is not 64-bit capa ble, then it does not assert ACK64# and the
Universe II will pack data to a 32-bit PCI b us.
Note that REQ64# will be asserted if LD64EN is set in a 64-bit PCI system
independent of whether the Universe II has a f ull 64 bits to transfer. This may
result in a performance degr adation because of the ex tr a clocks r equired to
assert REQ64# and to sample ACK64#. Also, there can be some performance
de gr adation w hen acces sing 32-bit tar g ets with L D64EN set. Do not se t this bit
unless ther e are 64-bit targets in the slave imag e window.
If the VMEbus slave images are not programmed for a 64-bit wide PCI data bus, then the
Univ erse operates transpar ently in a 32-bit PCI environment.
Independent of the setting of the LD64EN bit, the Uni v erse II will ne ver attempt a 64-bit cycle
on the PCI bus if it is powered up as 32-bit.
2.3.1.2 PCI Bus Request and Parking
The Universe II supports bus parking. If the Universe II requires the PCI bus it will assert
REQ# only i f its GNT# is not currently asserted. When the PCI Master Module is ready to
be gin a transaction and its GNT # is as serted, the trans fer begins immediately. This e liminate s
a possible one clock cycle delay before be ginning a transaction on the PCI b us which would
exist if the Universe II did not implement bus parking. Bus parking is described in Section
3.4.3 of the PCI Specification (Rev. 2.1).
2.3.1.3 Address Phase
PCI transactions are initiated b y asserting FRAME# and driving address and command
information onto the b us . In t he VMEbus Sla ve Channel, the Universe II calculates the
address for the PCI transaction by adding a translation offset to the VMEb us address (see
“Universe as VMEbus Slave” on page 2-13).
The command signals (on the C/BE# lines ) contain informa tion about Memory spa ce, cycle
type and whether the transaction is read or write. Table 2.3 below gi ves PCI the command
type encoding implemented with the Universe II.
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Memory Read Multiple and Memory Read Line transactions are alia sed to Memory Read
transactions when the Universe II is accessed as a PCI target with these commands. Lik ewise,
Memory Write and Inv alida te is aliased to Memory Write. As a P CI initiat or, the Univ e rs e II
may generate Memory Read Multiple but never Me mory Read Line.
PCI targets are expected to assert DEVSEL# if they have decoded the access. During a
Configuration c ycle, the tar get is s elected by its particular IDSE L. If a target does not respond
with DEVSEL# within 6 clocks, a Master-Abor t is generated. The role of configuration c ycles
is described in the PCI 2.1 Specification.
Table 2.3 : Command Type Enco ding f o r Transfer Type
C/ B E # [3:0] for PCI,
C/ B E # [7 :4 ] for
non-multiplexed Com m and Type Universe II Capability
0000 Interrupt Acknowledge N/A
0001 Special C ycle N/A
00 10 I/O R ead T arget/Master
0011 I/O Write T arget /M aste r
0100 Reserved N/A
0101 Reserved N/A
01 10 Memory Read T arget/Master
0111 Memory Write Target/Master
1000 Reserved N/A
1001 Reserved N/A
1010 Configuration Read Target/Master
1011 Configur atio n Wr ite T arget /M aste r
1100 Memory Read Multiple (See Text)
1101 Dual Address Cycle N/A
1110 Memory Read Line (See Tex t)
11 11 Memory Write an d Invalidate (S ee Text)
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2.3.1.4 Data Transfer
Acknowledgment of a data phase occurs on the first rising clock edge after both IRDY# and
TRDY# are asserted b y the master and target, respectiv ely. REQ64# may be driven during the
address phase to indic ate that the mas te r wishe s to initiate a 64-bit transaction. The P CI ta r ge t
asserts ACK64# if it i s able to respond to the 64-bit transaction.
Wait cycles are introduced by either the master or the target by deasserting IRD Y# or TRDY#.
For write cycle s, data is valid on the first rising edge afte r IRDY# is asserted. Data is
acknowledged b y t he target on t he first ris ing edge with TRD Y# asserted. For read c ycles, data
is transferred and acknowledged on first rising edge with both IRDY# and TRDY# asserted.
A single data transfer c y cle is repeated every time IR DY# and TRDY# are both asserted . The
transaction only enters the termination phase when FRAME# is deasserted (master-initiated
ter mination) or if ST OP# is asse rted (target-i nitia te d). When both FRAME# and IRDY# are
deasserte d (fi nal data phase is complete), the b us is define d a s idle.
2.3.1.5 Terminat io n P hase
The PCI Bus Interface permi ts all four types of PCI termina tions:
1. Master-Abort: the PCI bus master nega tes FRAME# when no target re sponds
(DEVSEL# not asser t ed) after 6 clock cycles.
2. Target-Disconnect: a termination is requested by the target (STOP# is asserted)
because it is unable to respond within the latency requirements of the PCI
specification or it requires a ne w address phase. Target-disconnect means that the
transaction is terminated after data is transferred. The Universe II will deassert
REQ# for at least two clock cycles if it receives STOP# from the PCI target.
3. Target-Retry: termination is requested (STOP# is asserted) b y the target because it
cannot currently process the transaction. Retry means that the transaction is
terminated after the address phase without any data transfer.
4. Target- Abort: is a modif ied version of tar get-dis connect where the target requests a
termination (asserts ST OP#) of a transaction whi ch it will ne v er be able to respond
to, or during which a fatal error occurred. Although there may be a fatal error for
the initiating application, the transaction completes gracefully, ensuring normal
PCI op e ra tio n fo r ot he r PCI resou rces.
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2.3.1.6 Parity Checking
The Universe II both monitors and generates parity information us ing the PAR signal. The
Univ erse II monitors PAR when it accepts data as a master during a read or a target during a
write. The Universe II drives PAR when it provides data as a target during a read or a ma ster
during a write. The Universe II also drives PAR during the address phase of a transaction
when it is a master and monitors PAR during an address phase when it is the PCI target. In
both address and data phases, the PAR signal pro vides even parity for C/BE#[7:0] and
AD[63:0]. The Uni verse II continues with a transaction i ndependent of an y parity error
reported during the transaction.
The Univ er se II can also be programmed to report address parity errors. It does this by
asserting the SERR# signal and setting a status bit in its registers. No inte rrupt is generated,
and regardless of whether assertion of SERR# is enabled, the Universe II does not respond to
the errored access. I f po wered up in a 64-bit PCI environment, the Universe II uses PAR64 in
the same way as PAR, except for AD[63:32] and C/BE[7:4].
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2.3.2 Un i verse II as PCI Master
The Universe II requests PCI bus mastership through its PCI Master Interface. The PCI
Master Interf ace is a v ailable to either the VMEbus Sla ve Channel (access from a remote
VMEbus master) or the DMA Channel.
The VMEbus Slave Channel makes an interna l request for the PCI Master Inter face when:
• the RXFIFO contains a complete transac tion,
• suf f icient data exis ts in the RXFIFO to generate a transaction of length def ined b y the
programmable aligned burst size (PABS), or
• there is a coupled cycle request.
The DMA Channel makes an internal request for the PCI Master Interface when:
• the DMAFIFO has room for 128 bytes to be read from PCI,
• the DMAFIFO has queued 128 b ytes to be written to PCI, or
• the DMA block is completely queued during a write to the PCI b us.
Arbitration be tween the two channels for the PCI Master Interface follows a round robin
protocol. Each channel is giv en access to the PCI bus for a single transaction. Once that
tra nsaction completes, o wne rship of the PCI M aster Interf ace is gran ted to the other cha nnel if
it requires the b us. The VMEb us Sla ve Channel and the DMA C hannel each ha ve a set of rules
that determine when it is ‘done’ with the PCI Master Interface. The VMEbus Slav e Channel is
done under the following conditions:
• an entire transaction (no greater in length than the programmed aligned b urst s ize) is
emptied from the RXFIFO, or
• the coupled c ycle is complete.
The DMA Cha nnel is done when:
• the boundary programmed into the PCI aligned b urst size is emptied from the
DMAFIFO during writes to the PCI bus , or
• the boundary pr ogrammed into the PCI aligned b urst size is queued to the DMAFIFO
during re ads from the PCI bus.
As discussed el sewhere (“Universe as VMEbus Slave” on pa ge 2-13) , acces s from the
VMEbus may be either coupled or decoupled. For a full description of the operation of these
data paths, see “Universe as VMEb us Sla ve” on page 2-13.
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The PCI Master Interf a c e can generate the following command types:
• I/O Read,
• I/O Write,
• Memory Read,
• Me mory Read Multiple,
• Memory Write,
• Conf iguration Read (Type 0 and 1), and
• Configuration Write (Type 0 and 1).
The type of cycle the Universe II generates on the PCI bus depends on which VMEbus slave
image is accessed and how it is programmed. For example, one slave image might be
programmed as an I/O space, another as Memory space and another for Configuration space
(see “VME S lav e Images” on page 2-50). When generating a m em ory transaction, the implied
addressing is either 32-bit or 64-bi t aligned, depending upon the PCI target. When generating
an I/O transaction, the implied addressing is 32-bit aligned and all incoming transactions are
coupled.
2.3.2.1 PCI Burst Transfers
The Univer se II generates aligned burs t transfers of some maximum alignment, according to
the programmed PCI aligned burs t size ( PABS field in the MAST _CTL regist er, Table A.81).
The PCI aligned burst size can be programmed at 32, 64 or 128 bytes. Burst transfers will not
cross the programmed boundaries. For example, when programmed for 32-b yte boundaries, a
ne w b urst will be gin at XXXX_XX20, XXXX_XX40, etc. If necessary, a ne w burst will be gin
at an address with the programmed alignment. To opt imize PCI bus usage, the Universe II
al ways attempts to transfer data in aligned bursts at the full negotiated width of the PCI bus.
The Universe II can perform a 64-bit data transfer ove r the AD [63:0] lines, if operated in a
64-bit PCI en vironment or against a 64-bit capable target or initiator . The LD64EN bit must be
set if the access is being made through a VMEbus sla ve image; the LD64EN bit must be set if
the access is being performed with the DMA.
Th e Universe II gen e rate s burs t cy cl es on th e PCI bus if it is:
• emptying the RXFI FO (the RXFE status bit in the MISC_STAT register is set when
the RXFIFO empt ies),
• filling the RDFIFO (r eceives a block read reque st from a VMEbus maste r to an
appropriately programmed VMEbus s lave image), or
• performing DMA transfers
All other accesses are treated as single data beat transactions on the PCI b us.
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During PCI burst transactions, the Universe II dynamically enables b yte lanes on the PCI bus
by changing the BE# signals during each data phase.
2.3.2.2 Termination
The Uni verse II performs a Master-Abort if the tar get does not respond within 6 clock c ycles.
Coupled PCI t ransactions terminated with Tar get -Abort or Master- Abort are terminated on the
VMEbus with BERR*. The R_TA or R_MA bits in the PCI_CS register (Table A.3) are set
when the Uni verse II receiv es a Target-Abort or generates a Master-Abort independent of
whether the tra nsaction was coupled, decoupled, prefetched, or initia ted by the DMA.
If the Univ erse II r eceives a retry from the PCI target, then it relinquishes the PCI bus and
re-requests within 2-3 PCI clock cycles. No other trans actions are processed by the PCI
Master Inter f ace unt il the retry condition is cleared . The Universe II can be programmed to
perform a maximum number of retries using the MAXRTRY fi eld in the MAST_CTL register
(Ta ble A.81). When this number of retries has been rea ched, the Universe II responds in the
same w ay as it does to a Target-Abort on the PCI bu s . That is, the Univ ers e II may issue a
BERR* signal on the VMEbus. Target-Abor ts are discussed in the ne xt two paragraphs. All
VMEbus slave coupled trans actions and decoupled transactions will encounter a delayed
DTACK once the FI FO f ills until the condition clears either due to success or a retry time-out.
If the error occurs during a posted write to the PCI bus (see also “ Bus Error Handling” on
page 2-58), the Universe II uses the L_CMDERR re gis ter (Table A.32) to log the command
information for the trans action (CMDERR [3:0]) and the address of the errored tra nsaction is
latched in the LAERR regist er (Table A.33) . The L_CMDERR register also records if
multiple errors occur (with the M_ERR bit) although the number of errors is not given. The
error log is qualif ie d with the L_STAT bit. The rest of the transaction will be purged from the
RXFIFO if some portion of the write encounters an error. An interrupt is generated on the
VMEbus and/or PCI b us depending upon whether the VERR and LER R i nterrupts are enabled
(see “Interrupt Handling” on page 2-68).
If an err or occurs on the PCI bus, the Universe II does not translate the error condition into a
BERR* on the VMEbus. Indeed, the Universe II does not directly map the error. By doing
nothing, the Univ erse II forces the external VMEbus error ti mer to expire.
2.3.2.3 Parity
The Univ er se II monitors PAR when it accepts data as a master during a read and drives PAR
when it provides data as a master during a write. The Universe II also drives PAR during the
address phase of a transaction when it is a master. In both addres s and data phases, the PAR
signal provides ev en parity for C/BE#[3:0] and AD[31:0]. If the Univ erse II is po wered up in a
64-bit PCI environment, then PAR64 provides even parity for C/BE#[7:4] and AD[63:32].
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The PERESP bit in the PCI_CS regi ster (Table A.3) determines whether or not the Uni verse II
responds to parity errors as PCI m aster. Data parity errors are r eported through the assertion of
PER R# if the PERESP bit is set. Rega rdles s of the setting of these two bits, the D_PE
(Detected Parity Error) bit in the PCI_CS register is set if the Uni verse II encounters a parity
error as a master. The DP_D (Data Parity Detected) bit in the same register is only set if parity
checking is enabled through th e PERES P bit and t he Univ erse II detects a parity error while it
is PCI master (i.e. it asserts P ERR # during a read transaction or receives PERR# during a
write).
No interrupts are generated by the Universe II in response to parity errors reported during a
transaction. Parity errors are reported by the Universe II through assertion of PERR# and by
setting th e appropri at e bits in the PCI_CS re gis t er. If PERR# is asserted to the Uni verse II
while it is PCI mas ter, the only action it takes is to set the DP_D. The Universe II continues
with a transaction independent of an y parity errors reported during the transaction.
As a master, the Univ erse II does not monitor SERR#. It is expected that a central resource on
the PCI bus will monitor SERR# and take appropriate action.
2.3.3 Un i verse II as PCI Target
This section covers the follo wing aspects of the Universe as PCI bus target:
• “Ov ervie w” on page 2-38,
• “Data Trans fer” on page 2-39,
• “Coupled Transfers ” on page 2-42,
• “Posted Writes” on page 2- 44,
• “The Special Cycle Generator ” on page 2-45,
• “Using the VOW N bit” on page 2- 48,
• “Terminations” on page 2-49.
2.3.3.1 Overview
The Uni verse II becomes PCI bu s target when one of its eight programmed PCI target images
or one of its registers is accessed by a PCI b us master (the Uni verse II cannot be that PCI bus
master). Register accesses are discussed else where (see “Registers” on page 2-100); this
section describes only those accesses destined for the VMEbus.
When one of its PCI target im ages is accessed, the Universe II responds with DEVS EL#
within two clocks of FRAME# (making the Uni verse II a medium speed de vice, as reflected
b y the DEVSEL field in the PCI_C S register).
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As PCI target, the Universe II re sponds to the following command types:
•I/O Read,
• I/O Write,
• Memory Read,
• Memory Write,
• Conf iguration Read (Type 0),
• Conf iguration Write (Type 0),
• Me mory Read Multiple (alia s ed to Memory Read),
• Memory Li ne Read (aliased to Me mory Read),
• Me mory Write and Inv a lidate (alias e d to Memory Write).
Type 0 Configuration accesse s can only be made to the Universe II’s PCI configuration
registers. The PCI target images do not accept Type 0 ac cess es.
Address parity errors are reported if both PER ESP and SERR_EN are set in the PCI_CS
regis ter (Table A.3). Address parity errors are reported by the Universe II by asserting the
SERR# signal and se tting the S_SERR (Signalled SERR#) bit in the PCI_CS regis ter.
Assertion of SERR# can be disabled by clearing t he SERR_EN bit in the PCI_CS regis ter. No
interrupt is gener ated, and regardless of whether assertion of SERR# is enabled or not, the
Univ erse II does not respond to the access with DEVSEL#. Typically the master of the
transaction times out with a Master-Abort.
If the Uni v erse II is accessed v alidly with REQ64# in Memory space as a 64-bit target, then it
responds with ACK 64# if it is powered up as a 64-bit device.
2.3.3.2 Data Transfer
Read transactions are always coupled (as opposed to VMEbus slave reads, which may be
pre-fetched; see “Universe as VMEbus Slave” on page 2-13). Write transactions can be
coupled or posted (see Figure 2.5 below and “ PCI Bus Target Images” on page 2-53). To
ensure sequential consis ten cy, coupled operations (reads or writes) ar e only processed once all
previously posted wri te operations hav e completed (i.e. the TXFIFO is empty).
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The data trans fer between the PCI bus a nd VMEbus is perhaps best explained by Figure 2. 6
below. The Universe II can be s een as a funnel where the m outh of the funnel is the data width
of the PCI transaction. The end of the funnel is the maximum VM Ebus data width
progra mmed into the PCI tar get image (VD W bit in the PCI tar get image contr ol r egister) . For
exampl e, consider a 32-bit PCI transaction accessing a PCI target im age with VDW set to 16
bits. A data beat with all byte lanes enabled will be broken into two 16-bit cycles on the
VMEbus . If the PCI target image is also programmed with block transfers enabled, the 32-bit
PCI dat a beat will result in a D16 block transfer on the VMEb us. Write data is unpacked to the
VMEbus and read data is packed to the PCI bus data width.
If the data width of the PCI data be at is the same as the maximum data width of the PC I tar get
image, then the Universe II maps the data beat to an equivalent VMEb us cycle. For example,
conside r a 32-bit PCI transaction acces sing a PCI tar ge t image with VD W set to 32 bits. A
data beat with all byte lanes enabl ed is transl ated to a single 32-bit cycle on the V MEbus.
As the gene ral rule, if the PC I b us dat a width is le ss than the VM Ebus data width then there is
no packing or unpacking between the two buses. The only exception to this is during 32-bit
PCI multi- data beat transactions to a PCI target ima ge program med with maximum VMEbus
data width of 64 bits. In this cas e, packing/unpacking occurs to make maximum use of the full
bandwidth on both buse s.
Only aligned VMEbus transactions are generated, so if the requested PCI da ta beat has
unaligned or non-contiguous b yte enables, then it is broken into multiple aligned VMEbus
transactions no wider than the programmed VMEbus data width. F or exampl e, consider a
thre e-byte PCI data beat (on a 32-bit PCI bus ) acces sing a PCI tar ge t image with VDW set to
16 bits. The three-byte PCI data beat will be broken into two aligned VMEbus cycles: a
single-byte cycle and a double-byte cycle (the ordering of the two cycles depends on the
arrangement of the byte enables in the PCI data beat). If in the above example the PCI target
image has a VDW set to 8 bits , then the t hree -b y te PCI data beat will be broken into three
single-byte VMEb us cycles.
Figure 2.5 : PCI Bus Target Channel Dataflow
TXFIFO
PCI BUS
SLAVE
INTERFACE
VMEbus
MASTER
INTERFACE
COUPLED WRITE DATA
POSTED WRITE DATA
COUPLED READ DATA
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Figure 2.6 : Influence of Transaction Data W idth and Target Image Data
Width on Data Packing/Unpacking
Data width of PCI
transaction
Maximum data width
programmed into PCI
target image
PCI BUS SIDE VMEBUS SIDE
Data wi dth exceeds
max imum data width of t he
PCI target image
Data width fits wi th maximum
data width of the PCI target
image
WRITE (UNPACKING)
READ (PACKING)
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2.3.3.3 Coup led Transfers
The PCI Target C hannel supports “coupled transfers”. In a nutshell, a coupled t ransfer thr ough
the PCI Target Channel is a transfer between PCI and VME where the Universe II maintains
ownership of the VMEbus from the beginning to the end of the transfer on the PCI bus (and
possibly longer), and where the term ination of the cycle on the VMEbus is relayed directly to
the PCI initiator in the normal manne r (i.e., Target-Abort, or Target Completion), rather than
through error-logging and interrupts.
By default, all PCI target images are set for coupled transfers. Coupled transfers typically
cause the Universe II to go through three phases: The Coupled Request Phase, the Coupled
Data-Tr ans fer Phase, and then the Coupled Wa it Phase. When an external PCI Ma ster
attempts a data transfer through a slave image programmed for coupled cycles, then:
• If the Univ erse II currently o wns the VMEbus, the PCI Target Channel mov es
directly to the Coupled Data-Trans fer Phase; otherwise,
• the Universe II moves to the Coupled Request Phase. These three phases are
described below.
Note that once the Coupl ed Request phase has begun, posted writes may traverse the PCI
Tar get Channel without affecting coupled transfers.
Coup le d Reques t Phas e
During the Coupled Request Phase, the Universe II will attempt to a cquire the VMEbus . But
first it must empty any posted wri tes pending in the TXFIFO, and obtai n owner ship of the
internal VMEbus Master Interfa ce (see “VMEbus Releas e” on page 2-8 for more details on
how the Universe II shares the VMEbus between channels.) The PCI Target Channel retries
the PCI master until the PCI Target Channel obtains ownershi p of the VMEbus. Eve r y time it
issues such a retry, the Universe II restarts the Coupled Request Timer , which counts down a
period of 215 PC I clock cycles . The Coupled Reques t Timer co-determines how long the
Univ erse II mainta ins the VMEbus since the last time the Univ e rse II issued a Target-Retr y
during a Coupled Request Phase: the Universe II will release (or terminate its attempt to
obtain) the VMEbus if a coupled transfer is not attempted before the Coupled Request Timer
expires.
Usually, an external PCI Master will attempt a coupled cycle once the Universe II has
acquired the VMEb us during its Coupled Request Phase. In this case the Universe will
proceed to the “Coupled Data-Transfer Phase”. No addresss matching is performed to ve rify
whether the current coupled cycle ma tches the initiating coupled cyc l e. If an external PCI
Master reque s ts a PCI I/O or RMW transfer with an illegal byte lane combination, the
Univ erse II will exit the “Coupled Request Phase.”
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Coupled Data-Transfer Phase
At the beginning of the Coupled Data-Transfer Phase, the Universe II latches the PCI
command, byte enable, address and (in the case of a write) data. Regardles s of the state of
FRAM E#, the Uni verse II retries1 the master, and then perf orms the transaction on the
VMEb us. The Uni v erse II conti nues to signal Targe t-Retry to the e xterna l PCI master until t he
transfer completes (normally or abnormally) on the VMEbus .
If the transfer completes normally on the VMEbus, then in the case of a read, the data is
transmitted to t he PCI bus master. If a data phase of a coupled transfer requires packing or
unpacking on the VMEbus, ackno wledgment of the transfer is not given to the PCI bus master
until all data has been packed or unpacked on the VMEbus. Successful termination is
signalled on the PCI b us—the data beat is ackno wledged with a Tar get-Disconnect, forcing all
multi-beat transfe rs into single beat. At this point, the Universe II enters the Coupled Wait
Phase.
If a b us error is signalled on the VMEbus or an error occurs during packing or unpacking, then
the transaction is terminated on the PCI bus with Target-Abort.
See also “Data Transfer” on page 2-39.
Coup le d Wait Ph ase
The Coupled Wait Phase is entered after the succes sful completion of a Coupled
Data-Transfer phase. The Coupled Wait Phase allo ws consecutiv e coupled transactions to
occur without releasing the VMEbus . If a ne w coupled transaction i s attempted while t he
Unive rse II is in the Coupled Wait Phase, the Universe II will move direc tly to the Coupled
Data-Tr ans fer Phase without re-e ntering the Coupled Request Phase.
The Coupled Window Timer determines the maximum duration of the Coupled Wait Phase.
When the Universe II enters the Coupled Wait Phase , the Couple d Window Timer starts. The
period of this timer is specified in PCI clocks and is programmable through the CW T field of
the LMISC re gister (Table A.30). If this field is programmed to 0000, the Universe II will do
an early release of BBSY* during the coupled transfer on the VMEb us and will not enter the
“Coupled Wait Phase.” In this case, VMEbus ownership is relinquished immediately by the
PCI Target Channel after each coupled cycle.
Once the timer associated with the Coupled Wait Phase expires, the Univ erse II will release
the VMEbus if rele as e mode is set f or RWD, or the relea se mode is set for ROR and the re is a
pending (external) request on the VMEbus.
1. PCI latency requirements (as described in revision 2.1 of the PCI Specification) require that only 16 clock cy-
cle s can ela pse betwe en the fi rst an d second da ta beat of a tran sact ion. Sinc e the Uni ver se II cannot guarant ee tha t
data a cknowle dgment wil l b e rece iv ed from the VME bus i n ti me t o mee t t hese P CI late ncy requ ire ments, t he Un i-
vers e II performs a target-disconnect after the first data beat of every co upled write transaction.
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2.3.3.4 P osted Writes
Posted writes are enabled for a PCI target ima ge by setting the PWEN bit in the control
register of the PCI target i mage (see “PCI Bus Target Images” on page 2-53). Writ e
transactions are relayed from the PCI bus to the VMEbus through a 32-ent ry deep TXFIFO.
The TXFIFO allows each entry to contain 32 address bits (with extra bits provided for
command information), or up to 64 data bits. For each posted write transaction recei ved from
the PCI bus, the PC I Target I nterf ace queues an addr ess entry in the FIFO. This entry contains
the translated address space and mapped VMEbus attrib ut es information relevant to the
particular PCI target image that has been accessed (see “PCI Bus Tar get Images” on
page 2-53). For this rea son, any re-programming of PCI bus target image attributes will only
be reflected in TXFIFO entries queued after the re-programming. Transactions queued before
the re-pr ogramming are deli v ered to the VMEb us with the PCI b us targe t i mage attrib utes that
were in use before the re-programming.
Caution: Care should be taken before reprogramming target images from one
bus while that image is being accessed from the opposite bus . If there is a
chance the image may be accessed while be ing reprogrammed, disable the
image firs t before changing image attributes.
Once the address phase is queued in one TXFIFO entry, the PCI Tar get Interface may pack the
subsequent data beats to a full 64-byte width before queuing the data into new entries in the
TX FIFO .
For 32-bit PC I transfers in the U niverse II, the TXFIFO will accept a single burst of one
addres s phas e and 59 data pha s es when it is em pty. F or 64-bit PCI, the TXFI FO will a ccept a
single burst of one address phase and 31 data phases when it is empty. To im pro ve PCI bus
utilization, the TXFIFO does not accept a ne w address phase if it does not have room for a
burst of one address phase and 128 bytes of data. If the TXFI FO does not have enough space
for an aligned burst, then the posted write transaction is terminated with a Target-Retry
immedi ately after the address phase.
When an external PCI Master posts writes to the PCI Target Channel of the Uni verse II, the
Univ erse II will issue a disconnect if the implied address will cross a 256-byte boundary.
Before a transac tion can be delivered to the VMEbus from the TXFIFO, the PCI Target
Channel must obtain ownership of the VMEbus Mas ter Interfa ce. Ownership of the VMEbus
Master Inter f ace i s granted to the diff erent channels on a round robin basis (see “VMEbus
Release” on page 2- 8). Once the PCI Target Channel obtains the VMEbus through the
VMEbus Master Interf ace, the manner in which the TXFIFO entries are delivered depends on
the programming of the VMEbus attributes in the PCI targe t image (see “PCI Bus Target
Images” on page 2-53). For e xampl e, if the VMEb us data width is programmed to 16 bi ts, and
block transfers are disabled, then each data entry in the TXFIFO corresponds to four
transactions on the VMEbus.
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If block transfers are enabled in the PCI target image, then each transaction queued in the
TXFIFO, independent of its length, is deliv ered to the VMEbus as a block transfer. This
means that if a single data beat transaction is queued in the TXFIFO, it appears on the
VMEbus as a single data phase block transfer.
Any PCI master attempti ng coupled tr ansactions is retr ied while the TXFIFO contains data. If
posted writes are continually writ ten to the P CI Target Channel, and the FIFO does not empty,
coupled transactions in the PCI Target Channel will not proceed and will be continually
retried. This presents a potential star vation scenario.
2.3.3.5 The Speci al Cycle Generator
The Special Cycle Gener at or in the PCI Target Channel of the Universe II can be used in
conjunction with one of the PCI Target Images to generate read-modify-write (RMW) and
Address Only With Handsha ke (ADOH) cycles.
The address programmed into the SCYC_ADDR register (Table A.26), in the address space
specified by the LAS field of the SCYC_CTL register (Memory or I/O), must appear on the
PCI bus during the address phase of a transfer for the Specia l Cycle Generator to perform its
function. Whene ver this address on the PCI bus matches the address in the SCYC_ADDR
register, the Universe II does not respond with ACK64# (since the Special Cycle Generator
only processes up to 32-bit cycles).
The c ycle that is produced on the VMEbus (if any) will use attributes programmed into the
Image Control Re gis ter of the image that contains the address programmed in the
SCYC_ADDR register.
The Special Cycle Generator is configured through the register fields shown in Table 2.4 and
described below.
Table 2.4 : Register Fields for the Special Cycle G enerator
Fiel d Regis ter Bits Descr iption
32-bit ad dress ADDR in Tab le A.26 specifi es PCI bus target imag e address
PCI Address Spa ce LAS in Table A.25 specifi es whether the addr ess specified in the ADDR field
lies in PCI memory or I/O space
Special cycle SCYC[1:0] in Table A.25 disabled, RMW or ADOH
32-bit en able EN [31 :0] in Ta ble A.27 a bit m ask to select the bits to be mo difi ed in the VMEbus
read data during a R M W cycle
32-bit co mpare CMP [31:0] in Table A. 28 dat a w hich i s com pared to the VMEbus read data duri ng a
RMW cycle
32-bit swap SWP [31: 0] in Tab le A.29 data w hich i s swapped with the VMEbus read data and
written to the original address
during a RMW cyc le
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The following sections descr ibe the specific properties for each of t he transfer types: RMW
and ADOH.
Read-Modify-Write
When the SCYC field is set t o RMW, any PCI b us read access to the specif ied PCI bus address
(SCYC_ADDR register) will result in a RMW cycle on the VMEbus (pro vided the constraints
listed belo w are satisfied). RMW c ycles on the VMEb us consist of a single read followed by a
single write operation. The data from the read portion of the RMW on the VMEb us is returned
as the read data on the PCI bus.
RMW cycles make use of three 32-bit re gisters (see Table 2.5 above) . The bit enable f ield is a
bit mask which lets the user specify which bits in the read data are compared and mod ified in
the RMW cycle. This bit enable setting is completely independent of the RMW cycle data
width, which is determined by the data width of the initiating PCI transaction. Dur ing a RMW,
the VMEb us read data is bitwise compared with the SCYC_C MP and SCYC_EN register s.
The valid compared and enabled bits are then swapped using the SCYC_SWP register.
Each enable d bit that compares true is swapped with the corres ponding bit in the 32-bit swap
field. A false comparison results in the original bit being written back.
Once the RMW cycle completes, the VME bus read data is returned to the waiting PCI bus
master and the PCI c ycle terminates.
Certain restrictions apply to the use of RMW cycles. If a write transaction is initiated to the
VMEbus address when the speci al cycle field (SCYC in Table A.25) is set for RMW, then a
standa rd write occurs with the attributes programme d in the PCI target image (in other words,
the special cycle generator is not used). The Universe II performs no packing and unpacking
of data on the VMEbus during a RMW operation. The following constraints must also be met.
1. The Special Cycle Generator will only generate a RMW if it is accessed with an
8-bit, aligned 16-bit, or aligned 32-bit read cycle.
2. The Special Cycle Generator will only generate a RMW if the size of the requ est is
less than or equal to the programmed VMEbus Maximum Datawid th.
3. The destina tion VMEbus address space must be one of A16, A24 or A32.
In the eve nt that the Special Cycle Gener ato r is acce sse d with a read cycle that does not meet
the three crite ria desc ribed above, the Universe II generates a Target- Abor t. Thus it is the
user’s responsibility to ensure that the Uni verse II is correctly programmed and accessed with
correct byte-lane information.
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VME Lock Cycles—Exclusive Access to VMEbus Resources
The VME Lock cycle is used in combination w ith the VOW N bit in the MAST_CTL register
to lock resources on the VMEbus. The VME Lock cycle ca n be used by the Universe II to
inform the resource that a locked cycle is intended (so that the VMEb us slav e can prevent
accesses from other mast er s on a different bus). The VOWN bi t in the MAST _CT L register
can be set to ensure that when the Uni verse II acquires the VMEbus, it is the only master giv en
access to the bus (until the VOWN bit is cleared). It m ay also be necessary for the PCI master
to ha ve locked the Uni verse II using the P CI LOCK# signal.
When the SCYC field i s set to VME Lock, any write access to the specified VMEbus address
will result in a VME Lock cycle on the VMEbus. A VME Lock c ycle is coupled: the cycle
does not complete on the PCI bus until it c ompletes on the VMEbus. Rea ds to the specified
address translate to VMEbus reads in the standard fashi on. The data during writes is ignored.
The AM code generated on the VMEbus is determined by the PCI target image definition for
the specified VMEbus address (see Ta ble 2.12 on page 56).
Ho we v er , after t he VME Lock c ycle is complete, there is no gua rantee that t he Uni v erse II will
remain VMEb us master unless it has set the VO WN bit. If the Univer se II loses VMEbus
ownership, then the VMEbus resouce will no longer remain locked.
The following procedur e is required to lock the VMEbus via a n ADOH cycle :
• (If there is more than one master on the PCI bus, it may be necessar y to use PCI
LOCK# to ensure t hat the PCI master driving the ADOH c ycle has sole PCI access to
the Universe II registers and the VME bus,)
• program the V OWN bit in the MAST_CTL regis ter to a value of 1 (see “Using the
VOWN bit” below),
• wait until the VOWN_ACK bit in the MAST_CTL register is a value of 1,
• generate an ADOH cycle with the Special Cycle Generator,
• perform transactions to be lock ed on the VMEbus,
• release the VMEb us by programming the V O W N bit in the MAST_CTL re gister to a
value of 0, and
• wait until the VOWN_ACK bit in the MAST_CTL register is a value of 0.
In the event that BERR* is asserted on the VMEbus once the Universe II has locked and owns
the VMEbus, it is the responsibility of the user to release ownership of the VMEbus by
programming the V OWN bit in the MAST_CTL register to a value of 0.
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The following restrictions apply to the use of VME Lock cycles:
1. All byte lane information is ignored for VME Lock cycles,
2. The Universe II will generate a n VME Lock cycle on the VMEbus only if the PCI
Tar get Image which subsumes the special cycle has posted writes disabled,
3. T he Universe II Spec ial C yc le Gene rator will not gener ate VME L oc k cycles if the
address space is not one of A16, A24 or A32. Instead it produces regular cyc les.
2.3.3.6 Using the VOWN bit
The Universe II provides a VMEbus ownership bit (VOWN bit in the MAST_CTL register,
Table A.81) to ensure that the Universe II has access to the locked VMEbus resource for an
indeterminate period. The Uni v erse II can be programmed to assert an interrupt on the P CI bus
when it acquires the VMEbus and the VO WN bit is set (VOWN enable bit in the LINT_EN
regis te r, Table A.57). While the VMEbus is held us ing the VOWN bit, the Universe II sets the
VOWN_ACK bit in the MAST_CTL register. The VMEbus Master Inte rface maintains bus
tenure while the o wnership bit is s et, and only releases the VMEbus when the ownership bit is
cleared. Thi s function is important for the follo wing two reasons.
If the VMEbus Master Interface is programmed for RWD (VREL bit in MAST_CTL register),
it may release the VMEbus when the P CI Tar ge t Channel has completed a transaction
(def inition of ‘done’ for the PCI Target Channel, see “VMEbus Release” on page 2-8).
Therefore, if exclusive access to the VMEbus resource is required for multiple transactions,
then the VMEbus o w nership bit will hol d the bus until the exclusiv e access is no l onger
required.
Alternativ ely, if the VMEbus Master Interface is programmed for ROR, the VMEb us
ownership bit will ensure VMEbus tenure e ven if other VMEbus requesters re quire the
VMEbus.
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2.3.3.7 Terminations
The Universe II performs the following terminations as PCI target:
1. Target-Disconnect
- when registers are accessed with FRAME# asserted (no bursts allowed to
registers),
- after the first data beat of e very coupled c ycle, or
- after the f irs t da ta phase of a PCI Me mory comma nd (with FR AME# ass erte d) if
AD[1:0] is not equal to 00, as recommended in Revision 2.1 of the PCI
Specification (page 28).
2. Ta rget -Re t ry
- for 64- bit PCI, when a new pos ted write is attempted and the TXFIFO does not
have room for a burst of one address phase and sixteen 64-bit data phases,
- when a coupled transaction is attempted and the U niverse II does not own the
VMEbus,
- when a cou pled transact ion is attempted while the TXFIFO ha s entri es to proce ss,
or
- when a mas ter attemp ts to access the Univer se II’s registers while a VME bus
master owns the Re gis ter Channel (e.g., through a RMW access or another type of
access).
3. Target-Abort
- when the Universe II rec eives BER R* on the VMEbus during a coupled cycle
(BERR* tra nsl ated as Target-Abort on the PCI side and the S_TA bit is set in the
PCI_CS regis ter, Table A.3).
Whether to terminate a trans acti on or for retry purposes, the Universe II kee ps STOP#
asserted until FRAME# is deasserted, independent of the logic levels of IRDY# and TRDY#.
If ST OP# is asser ted while T RDY# is deasserted, it means that the Uni verse II wil l not transfer
any more data to the ma ster.
If an err or occurs during a posted wri te to the VMEbus, the Universe II uses the V_AMERR
register (Table A.107) to log the AM code of the transaction (AMERR [5:0]), and the state of
the IACK* signal (IACK bi t, to indicate whether the error occurred during an IACK cycle).
The FIFO entries for the offending cycle are purged. The V_AMERR register also records
whether multiple error s ha ve occurred (with the M_ER R bit) although t he number is not
giv en. The error log is qualif ied with the V_STAT bit ( logs are v a lid if the V_STAT bit is set).
The address of the errored transaction is latched in the VAERR re gister (Table A.108). When
the Uni v erse II receives a VMEbus error during a p osted write, it generates an interrupt on the
VMEbus and/or PCI bus depending upon whether the VERR and VERR interrupts are
enabled (see “Interrupt Handling” on page 2-68).
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2.4 Slave Image Programming
The Univ er se II recognizes two types of accesses on its bus interfaces: accesses destined for
the other b us, and accesses decoded for its o wn register space. Address decoding for the
Univ erse II’s re gist er space is described in “Re gisters” on page 2-100. This section describes
the slave images used to map transacti ons between t he PCI bus and VM Ebus.
2.4.1 VME Slave Images
The Univ erse II accepts accesses from the VMEbus within specifi c programmed slav e images.
Each VMEbus slave image opens a window to the resources of the PCI bus and, through its
specific attributes, allows the user to control the type of access to those resources. The table s
below describe programming for the VMEbus slave images by dividing them into VM Ebus,
PCI b us and Control fields.
Table 2.5 : VMEb us Field s f o r V MEbus Sla ve Image
Field Register Bits Description
base BS[31:12 ] or BS[31 :16] in VSI x _BS m ultiples of 4 or 64 K bytes (base to bound:
maxi m um of 4 GB ytes)
bound BD[ 31:12 ] o r BD[31: 16 ] i n VS Ix_B D
addr ess space VAS in VSIx_CTL A16, A24, A32, User 1, User 2
mode SUPER in VSIx_CTL supervisor and/or non-privileged
type PGM in VSIx_CTL program and/or data
Table 2.6 : PCI Bus Fiel ds for VMEbus Slave Image
Field Register Bits Description
trans lation offs et TO[31: 12] or TO[31:16] i n VSIx_T O offset s V MEbus slave add ress to a selected PCI
address
addres s space LAS i n VS Ix_CTL Memory, I/O, Configuration
RMW LLRMW in VSIx_CTL RMW enable bit
Table 2.7 : Control Fie lds for VMEbu s Slave Image
Field Register Bits Description
im age enable EN in VSIx_CTL enable bi t
posted write PWEN in VSIx_CTL posted write enable bi t
prefetched read PREN in VSIx_CTL prefetched read enable bit
enable PCI D64 LD64EN in VSIx_CTL enables 64-bit PCI bus transactions
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Note that the Bus Master Enable (BM) bit of the PCI_CS re gis te r must be set in order for the
image to accept posted wri tes from an external VMEbus master. If this bit is cleared while
there is data in the VMEbus Slave Posted Write FIFO, the data will be written to the PCI bus
but no further data will be accepted into this FIFO until the bit is set.
T undr a recommends that the attrib utes in a slav e image not be changed while data is en queued
in the Posted Writes FIFO. To ensure data is dequeued from the FIFO, check the RX FE status
bit in the MISC_STAT register (Table A.83) or perform a read from that image. If the
programming for an image is changed after the transaction is queued in the FIFO, the
transaction’s attributes are not changed. Only subsequent transactions are affected by the
change in attributes.
2.4.1.1 VMEbus Fields
Decoding for VMEbus accesses is base d on the address, and address modifier s produced by
the VMEbus m aster. Before responding to an external VMEbus master , the address must lie in
the window defined by the base and bound addresses, and the Address Modifier must match
one of those specified by the address spa ce, mode, and type fields.
The Uni verse II’s eight VMEb us slave images (images 0 to 7) are bounded by A32 space. The
first and fif th of these i mages (VMEbus sla ve image 0 and 5) ha v e a 4 Kbyte resolution while
VMEbus sla ve images 1 to 3 and 6 to 8 hav e 64-Kbyte resolution (maximum image size of 4
GBytes). Typically, image 0 or 5 would be used as an A16 image since they provide the finest
granularity of the eight images.
The address space of a VMEb us slave image must not overlap with the address
space for the Universe II’s control and status registers.
2.4.1.2 PCI Bus Fields
The PCI bus fields specify how the VMEbus tr ansaction is mapped to the appropr iate PCI bus
transaction. The tr anslat ion offset field allows the user to transl ate t he VMEbus address to a
different address on the PCI bus. The translation of VMEbus transactions beyond 4 Gbytes
results in wrap-around to the low portion of the address range.
The PAS field controls ge nera tion of the PCI transaction command. The LLRMW bit allows
indivisible mapping of incoming VMEbus RMW cyc les to the PCI bus via the PCI LOCK#
mechanism (see “VMEb us Read-Modify-Write Cycles (RMW Cycles)” on page 2-19). When
the LLRMW bit is set , single cycle re ads will always be mapped to single dat a beat locked
PCI transac tions. Setting this bit has no effect on non-block writes: they can be coupled or
decoupled. Ho wev er , note that only accesses to PCI Memory Space are decoupled, accesses to
I/O or Configuration Space are always coupled.
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2.4.1.3 Contr ol Fields
The control fields allow the user to enable a VMEbus slave image (using the EN bit), as well
as spe cify how re ads and w rites will be process ed. At power-up, all images are disabled and
are configured for coupled rea ds and writes.
If the PREN bit is set, the Uni v erse II will prefetch for incoming VMEb us block read cycles. It
is the user's responsibili ty to ensure that prefetched reads are not destructiv e and that the entire
image contains prefetchable resources.
If the PWEN bit is s et , i ncoming write data fr om the VM Eb us is loaded into the RXFIFO ( see
“Posted Writes” on page 2- 15). Note that posted write transactions can only be mapped to
Memory space on the PCI bus. Setting the PAS bit in the PCI f ields to I/O o r Conf iguration
Space will force all incoming cycles to be couple d independent of this bit.
If the LD64EN bit is set, the Univ e r se II will attempt to gener ate 64-bit trans actions on the
PCI bus by asserting REQ64#. The REQ64# line is ass erted during the address phase in a
64-bit PCI system, and is the means of determining whether the PCI target is a 64-bit port. If
the target asserts A C K64# with DEVSEL#, then t he Uni v erse II uses the 64-bit data b us. If the
target does not assert ACK64# with DEVSEL#, then the Universe II uses a 32-bit data bus.
However, note that use of REQ64# requires extra clocks internally. Therefore, if no 64-bit
targets are expected on the PCI bus then performance can be improved by disabling LD64EN
on the VMEbus slave images.
In order for a VMEb us slave image to res pond to an incoming cycle, the PCI
Master Interface must be e nabled (bit BM in the PCI_CSR register, Table A.3 ).
Figure 2.7 : Address Translation Mechanism for VMEbus to PCI Bus Trans fers
Offset [31..12] VME [31..12] VME [11..0]
PCI [31..12] PCI [11..0]
A32 Image
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2.4.2 PCI Bus Target Images
The Univer se II accepts accesses from the PCI bus with specific programmed PCI target
images. Each image opens a window to the resources of the VMEbus and allows the user to
control the type of access to those resources. The tables below desc ribe programming for the
eight standard PCI bus target images (numbered 0 to 7) by dividing them into VMEbus, PCI
bus and Control f ields. One special PCI tar get image separate from the four discussed belo w is
described in “Specia l PCI Target Image” on page 2-55.
Tundra recommends that the attributes in a target image not be changed while data is
enqueued in the Posted Writes FIFO. To ensure data is dequeued from the FIFO, check the
TXFE status bit in the MISC_STAT register (Table A.83) or perform a read from that image.
If the programming for an image is changed after the transaction is queued in the FIFO, the
transaction’s attributes are not changed. Only subsequent transactions are affected by the
change in attributes.
Ta b le 2. 8 : PC I Bu s Fi el d s fo r the PC I Bu s Target Im a g e
Field Register Bits Description
base BS[31:12] or BS[31:16] in LSIx_BS mul tiples of 4 or 64 Kbytes (b ase to bound:
maximum of 4 GBytes)
bound BD[31:12] or BD[31:16] in LSIx _BD
addres s space L A S in LSIx_CTL Memory or I/O
Tabl e 2.9 : VMEb us Fields for the PCI Bus Target Image
Field Register Bits Description
trans lation offs et TO[3 1:12] or TO [31:16] in LSIx_TO trans late s address supplie d by PCI master to a
specified VMEbus address
max im um data width VDW in LSIx_CTL 8 , 16, 32, or 64 bits
addres s space VAS in LSIx_CTL A16 , A24, A32, CR/CSR, User1, User2
mode S UP ER in LSIx_CTL supervi sor or non-pri vileg ed
type PGM in LSIx_CTL program or data
cycle VC T in LSIx_CTL single or block
Tabl e 2.10 : Control Fields for PCI Bus Target Image
Field Register Bits Description
im age enable EN in LSIx_CTL enable bi t
posted write PWEN in LSIx_CTL enable bit
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2.4.2.1 PCI Bus Fields
All decoding for VMEbus accesses are based on the address and command information
produced by a PCI bus ma ster. The PCI Target Interfac e claims a cycle if there is an address
match and if the command matches certai n criteria .
All of the Universe II’s eight PCI target images a re A32-capable only. The first and fifth of
them ( i.e., PCI tar get images 0 and 4) ha ve a 4 Kbyte resolution while PC I tar get ima ges 1 to 3
and 5 to 8 have 64 Kbyte resolution. Typically, image 0 or image 4 would be used for an A16
image since they hav e the finest granularity.
The address space of a VMEb us slave image must not overlap with the address
space for the Universe II’s control and status registers.
2.4.2.2 VMEbus Fields
The VMEbus f ields map PCI transactions to a VMEbus transaction, causing the Uni v erse II to
generate the appropriate VMEbus address, AM code, and cycle type. Some invalid
combinations exist within the PCI targe t image definition fields. For example, A16 and
CR/CSR spaces do not support block transfers, and A16 space does not support 64-bit
transactions. Note that the Universe II does not attempt to detect or prevent these invalid
programme d combination s, and that use of these combinat ions may cause illega l activity on
the VMEbus.
The 21-bit translation offset allows the user to translate the PCI address to a dif f erent address
on the VMEbus. The f igur e belo w illus trate s the translation process:.
Trans lat ions beyond the 4 Gbyte limit will wrap around to the low address range.
!
Figure 2.8 : Address Translation Mechanism for PCI Bus to VMEb us Transfers
Offset [31..12] PCI [31..12] PCI [11..0]
VME [31..12] VME [11..0]
A32 Image
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The AM code generated by the Universe II is a function of: the VMEbus fields, and the data
width and alignment generated by the PCI b us master. For RMW and ADOH cycles, the AM
code also depends on the settings for the Special Cycle Generator (s ee “The Special Cycle
Generator” on page 2-45).
The address space, mode, type, and cycle fields control the VMEbus AM code for most
transactions. Setting the cycle field to BLT enables the BLT cycle generation. MBLT cycles
are generated when the maximum width is set to 64, the BLT bit is set, and the PCI master
queues a transaction with at least 64 bits (aligned) of data.
The Univ er se II provides support for user defined AM codes. The USER_AM register
(Table A.84) contains AM codes identified as User1 and User2. The USER_AM regis ter can
only be used to generate and accept AM codes 0x10 through 0x1F. These AM codes are
designated as USERAM codes in the VMEbus specification. If the user selects one of these
two, then the corresponding AM code from the global register is generated on the VMEbus.
This approach re sults in sta ndard single cycle transfer s to A32 VMEbus addres s space
independent of other settings in the VMEbus fi elds .
The VCT bits in the LSIx_CTL registers determine whether or not the VMEbus Master
Inte rf a ce will generate BLT transfers. The VCT bit will only be used if the VAS fie ld is
programmed for A24 or A32 space and the VD W bits are program med for 8, 16, or 32 bits. If
VAS bits of the control register are programmed to A24 or A32 and the VDW bits are
programmed for 64-bit, the Universe II may perform MBLT transfers independent of the state
of the VCT bit.
2.4.2.3 Contr ol Fields
The control fields allo w the user to enable a PCI targe t image (the EN bit), as well as sp ec ify
how writes are processed. If the PWEN bit is set, then the Universe II will perform posted
writes when that particular PCI target image is accessed. Posted write transactions are only
decoded within PCI Memory space. Accesses from other spaces will re sult in coupled cycles
independent of the setting of the PWEN bit.
2.4.3 Special PCI Target Im age
The Univer se II provides a special PCI target image located in Memory or I/O space. Its base
address is aligned to 64-Mbyte boundaries and its size is fixed at 64 M bytes (decoded using
PCI address lines [31:26]). The Special PCI Tar get Image is divided into four 16Mbyte
regions numbered 0 to 3 (see Figure 2.9 on page 2-57). These separate re gions are sel ected
with PCI address bits AD [25:24]. For example, if AD[25:24] = 01, then region 1 is decoded.
Within each region, the upper 64Kbytes map to VMEbus A16 space, while the remaining
portion of the 16 Mbytes maps to VME bus A24 s pace. Note that no off sets are provided, so
address information from the PCI transaction is mapped directly to the VMEbus.
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The general attributes of each region are programmed according to the tables below.
The special PCI target image pro vides acces s to all of A16 and most of A24 space (all except
the upper 64 Kb ytes). By using the special PCI target image for A16 and A24 transactions, it
is possible to free the eight standar d PCI target images (see “P CI Bus Target Images” on
page 2-53), which are typically programmed to access A32 space.
Note that some address space redundancy is provided in A16 space. The VMEbus
specification requires only two A16 spaces, whil e the special PCI tar get image allows for four
A16 address spaces.
Table 2.11 : PCI Bus Fields f or the Special PCI Target Image
Field Register Bits Description
base BS[5 :0] in Table A.31 64 Mby te ali gne d bas e addres s fo r th e
image
address spa ce LAS [1:0] in Table A.31 Places image in Memory or I/ O
Table 2.12 : VMEbus Fields for the Special PCI Bus Target Image
Field Register Bits Description
maxi m um data width VDW in Table A. 3 1 separat ely sets each regi on for 16 or 32
bits
mode SUPER in Table A.31 separately sets each region as
supervis or or non- privileged
type PGM in Table A.31 separ ately sets each regi on as program
or data
Table 2.13 : Control Fields f or the Special PCI Bus Target Image
Field Register Bits Description
image enable EN in Table A.31 enable bit for the image
posted write PWEN i n T able A.31 en able bi t for posted writ es for t he
image
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A16
A16
A16
A16
A24
A24
A24
A24
16 Mbytes
64 Kbytes
Figur e 2.9 : Mem ory Mapping in th e Special PCI Tar get Image
0
1
2
3
BASE+400 0000
BASE+3FF 0000
BASE+300 0000
BASE+2F F 0000
BASE+200 0000
BASE+1F F 0000
BASE+100 0000
BASE+0F F 0000
BASE+000 0000
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2.5 Bus Error Handling
There are two fundamentally diffe rent conditions under which bus errors may occur with the
Univ erse II: during coupled cycles or during decoupled cycles. In a coupled transaction, the
completion status is returned to the transaction master, which may then tak e some action.
Ho we v er, in a decoupled transaction, the master is not in v olv ed in the dat a ackno wledgment at
the destination bus and higher level protocols are required.
The error handling provided by the U niverse II is described for both coupled and decoupled
transactions below.
2.5.1 Coupled Cycles
During coupled cycles, the Universe II provides immediate indication of an errored cycle to
the originating bus. VMEbus to P CI transac tions terminate d with Tar ge t-Abort or
Master-Abort are termina ted on the VMEb us with BERR*. Th e R_TA or R_MA bits in the
PCI_CS R register (Table A.3 on page A-8) are set when the Universe II receives a
Tar get- Abort or Master-Abort. For PCI to VMEb us transactions, a VMEbus BERR* received
by the Univer se II is communicated to the PCI master as a Target-Abort and the S_TA bit is
set (Table A.3). No information is logged in either direction nor is an interrupt generated.
2.5 .2 D e co upled Trans ac tions
2.5.2.1 P osted Writes
The Univ er se II provides the option of performing posted writes in both the PCI Target
Channel and the VMEbus Slave Channel. Once data is written into the RXFIFO or TXFIFO
b y the initiati ng master (VME bus or PCI b u s respec tively), the Universe II pro v ides
immediate ackno wledgment of the cycle's termination. When the data in the FIFO is written to
the destination slav e by the Uni verse II, the Univ erse II may subsequently receiv e a bus error
instead of a normal termination. The Universe II handles this situation by logging the errored
transactions in one of two error logs and generating an interrupt. Each error log (one for
VMEbus errors and one for PCI bus errors) is comprised of two registers: one for address and
one for command or address space logging.
If the error occurs during a posted write to the VMEbus , the Universe II uses the V_AMERR
regis ter (Table A.107) to log the AM code of the transaction (AMERR [5:0]). The state of the
IACK* signal is logged in the IA C K bit, to indicate whether the error occurred during an
IACK c ycle. The address of the errored transaction is latched in the V_AERR register
(Table A.108). An interrupt i s generated on th e VMEbus and/or PCI b us depending upon
whether the VERR and VERR i nterrupts are enabled (see “Interrupt Handling” on page 2-68).
The remaining entries of the offending transaction are purged from the FIFO.
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If the error occur s during a posted write to the PCI b u s, the Universe II uses the L_CMDERR
regis ter (Table A.32) to log the command information for the transaction (CM DERR [3:0]).
The address of the errored transaction is latched in the L_AERR register (Table A.33). An
interrupt i s generated on the VMEbus and/or PCI bus depending upon whether the VERR and
LERR interrupts are enabled (see “Interrupt Handling” on page 2- 68).
Under either of the abo ve conditions (VMEbus to PCI, or PCI to VMEb us), the address that is
stored in the log represents the most recent address t he Universe II generated befo re the bus
error was encountered. F or single c ycle transactions, the address represents the address for the
actual errored transaction. However, for multi-data beat transactions (block transfers on the
VMEbus or burst transact ions on the PCI bus ) the log only indicates tha t an error occ urred
some where after the latched address. For a VMEbus block transfer, the logged ad dress will
represent the start of the block transfer. In the PCI Target Channel, the Uni verse II generates
block transfers that do not cross 256-byte boundaries, the error will have occurred from the
logged address up to the ne xt 256- byte boundary. In the VMEb us Sla ve Channel, the error will
have occurred anywhere from the logged address up to the next burst aligned address .
In the case of PCI-initiated transactions, all data from the errored address up to the end of the
initiating transaction is flushed from the TXFIFO. Since the Universe II breaks PCI
transactions at 256-byte boundaries (or earlier if the TXFIFO is full), the data is not flushed
past this point. If the PCI master is generating bur sts that do not cross the 256-byte boundary,
then (again) only dat a up t o the end of that transaction is flushed.
In a posted write from the VMEbus, all data subsequent to the error in the transaction is
flushed from the RXFIFO. However, the length of a VMEbus transaction differs fr om the
length of the errored PCI bus transaction. For non-block transfer s, the length always
corresponds to one so only the errored data beat is flushed. Ho wever, if an error occurs on the
PCI bus during a transaction initiated by a VMEbus block transfer, all data subsequent to the
errored data beat in the block t ransfer is flushed from the RXFIFO. In the case of BLTs, this
implies that potentially all data up to the next 256-b yte boundary may be flushed. F or MBLTs,
all data up to the next 2-KByte boundary may be flushed.
Once an error is captured in a log, that set of re gis ters is frozen ag ainst further errors until the
error is ac knowledged. The log is acknowledged and made available to latch another error by
clearing the corresponding status bit in the VINT_STAT or LINT_STAT re gisters. Should a
second error occur before the CPU has the opportunity to ackno wledge the first error, another
bit in the logs is set to indicate this situation (M_ERR bit).
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2.5.2.2 Prefetched Reads
In response to a block read from the VMEbus, the Uni verse II initiates prefetching on the PCI
b us (if the VMEb us sla ve image is programmed with this option, see “Slav e Image
Programming” on page 2-50). The transactio n generated on the PCI bus i s an aligned memory
read transaction with multiple data beats extending to the aligned burst boundary (as
programmed by PABS in the MAST_CTL register, Table A.82). Once an acknowledgment is
giv en for the fir st data beat, an acknowle dgment is sent to the VMEbus initiator by the
assertion of DTACK*. Therefore , the first data beat of a prefetched read is coupled while all
subsequent reads in the transaction are decoupled.
If an err or occurs on the PCI bus, the Universe II does not translate the error condition into a
BERR* on the VMEbus. Indeed, the Universe II does not directly map the error. By doing
nothin g, the Universe II force s the exte rnal VME bus error timer to e xpire.
2.5.2.3 DMA Errors
How the Uni verse II responds to a bus err or during a transfer controlled b y the DM A Channel
is described in “DMA Error Handling” on pa ge 2-96.
2.5.2.4 Parity Errors
The Universe II both monitors and generates parity information using the PAR signal. The
Univ erse II monitors PAR when it accepts data as a master during a read or as a target during
a write. The Uni ver se II dri ves PAR when it provides data as a target during a read or a master
during a write. The Universe II also drives PAR during the address phase of a transaction
when it is a master and monitors PAR during an address phase when it is the PCI target. In
both address and data phases, the PAR signal pro vides even parity for C/BE#[3:0] and
AD[31:0]. If the Univ erse II is powered up in a 64-bit PCI environment, then PAR64 provides
e ven parity for C/BE#[7:4] and AD[63:32].
The PERESP and S ERR_EN bits in the P CI_CS regis ter (Table A.3) determine whether or not
the Universe II responds to parity errors. Data parity errors are reported through the assertion
of PE RR# i f the PERES P bit is set. Addr ess parity errors, repor ted through the SERR# signal,
are reported if both PERESP and SERR_EN are set. Regardless of the setting of these two
bits, the D_PE (Detected Parity Error) bit in the PCI_CS register is set if the Universe II
encounters a parity error as a master or as a target. The DP_D (Data Parity Detected) bit in the
same register is only set if parity checking is enabled through the PER ESP bit and the
Universe II detects a parity error while it is PCI master (i. e. it asserts PERR# during a read
transaction or rec eives PERR# during a write).
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No interrupts are generated by the Universe II either as a master or as a target in response to
parity errors reported during a transaction. Parity errors are reported by the Universe II
through assertion of PERR# and by setting the appropri ate bits in the PCI_CS regis ter. If
PER R# is asser ted to the Univ erse II while it is PCI master, the only action it tak es is to set the
DP_D. Regardless of whether the Universe II is the master or target of the transaction, and
regardless which agent asserted PERR#, the Universe II does not t ake any action other than to
set bits in the PCI_CS regis ter. The Univ erse II continues with a transaction independent of
any parity errors reported during the transaction.
Simila rly, address par ity errors are report ed b y the Uni verse II (if the SERR_EN bit and the
PERESP bit are set) by asserting the SERR# signal and setting the S_SERR (Signalled
SERR#) bit in the PCI_CS register. Assertion of SERR# can be disabled by clearing the
SERR_EN bit in the PCI_CS re gister. No interrupt is generated, and regardless of whet her
assertion of SERR# is enabled or not, the Uni verse II does not respond to the access wi th
DEVSEL#. Typicall y the master of the tr ansaction times out with a Ma ster-Abort. As a
master, the Universe II does not monitor SERR#. It is expected that a central resource on the
PCI bus will monitor SERR# and take appropri ate action.
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2.6 Interr upt Ge ne ratio n
This is the firs t of tw o sections in this chapter which describe the Univ erse II’s interru pt
capab ilities . This section describe s the Univer se II as a generator of interrupts. The following
section, “Interrupt Handling” on page 2-68, describes the U niverse II as an interrupt handler.
Each of these sections has subsections which detail interrupt events on the PCI b us and
VMEbus (i.e., ho w the Universe II can generate interrupts on t he PCI bus and the VMEbus,
and how the Universe II can respond to interr upt sources on the PCI bus and the VMEbus).
The Interrupt Channel handles the prior itization and routing of interrupt sources to interrupt
outputs on the PCI bus and VMEbus. The interrupt sources are:
• the PCI LINT#[7:0] lines,
• the VMEb us IRQ*[7:1] lines,
• ACFAI L* an d SYSFAIL*
• va rious internal events
These sources can be routed to either the PCI LINT# [7:0] lines or the VMEbus IRQ* [7:1]
lines. Each interrupt source is indi vidually maskable and can be mapped to vari ous interrupt
outputs. Most interrupt sources can be mapped to one particular destination bus. The PCI
sources, LINT#[7:0], can only be mapped to the VMEbus interrupt outputs, while the
VMEbus s ources, VI RQ[7:1], can only be mapped to the PC I interrup t outputs . Some internal
sources (for example, error conditions or DMA activity) can be mapped to either bus.
LINT [7:0]
VRIQ#[7:1]
VXIRQ#[7:1]
VRACFAIL#
VRSYSFAIL#
and Enabling
Mapping
and Enabling
Mapping
Internal
Interrupt
Handler
Internal
Sources
Figure 2.10 : Universe Interrupt Circuit r y
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Tundra Semiconduc tor Corporation 2-63
Figure 2.10 above illustra tes the circuitry inside the Universe II Interrupt Channel. The PCI
hardware interrupts are listed on the left, and the VMEbus interrupt inputs and outputs are on
the right. Inte rnal interrupts are also illustrate d. The f igur e shows that the interrupt sources
may be mapped and enabled. The Internal Interrupt Ha ndler is a block within the Universe II
that detects assertion of the VRIRQ#[7:1] pins and generates the VME IA CK through the
VME Master. Upon completion of the I ACK cycle, the Internal Interrupt Handler notifies the
Mapping Block which in turn asserts the local LINT#, if e nabled. (Whereas the Internal
Interrupt Handler implies a delay between assertion of an interrupt condition to the U niverse
II and the Unive rse’s mapping of the interrupt, all other interrupt sources get mapped
immediately to their destination—assertion of LINT# immediately causes an IRQ, assertion
of ACFAIL immediately causes an LINT#, etc .) Thi s is described in further detail in the
following sections.
2.6.1 PCI Interrupt Generation
The Univer se II expands on the basic PCI specifi cation which permits “single function”
devices to assert only a single interrupt line. Eight PCI interrupt outputs provide maximum
flexibi lity, although if ful l PCI com pliancy is required, the user may route all interrupt sources
to a single PCI interrupt output.
Only one of the PCI interrupt outputs, LINT#[0], has the drive strength to be
fully compliant with the PCI specification. The other seven may require
b uffering if they are to be routed to PCI compliant interrupt lines. For most
applications, however, the drive strength provided should be suff icient.
PCI interrupts may be generated from mul tiple sources:
• VMEbus sources of PCI interrupts
- IRQ*[7:1]
- SYSFAIL*
- ACFAIL*
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• internal sources of PCI interrupts
- DMA
- VMEbus bus error encountered
- PCI Target-Abor t or Master-Abort encountered
-VMEbus ownership has been grante d while the VOWN bit is set (see “ VME Lock
Cycles—Exclusi ve Access to VMEbus Resources” on page 2-47)
- software i n ter ru pt
- mailbox access
- location monitor acces s
- VMEbus IAC K cycle performed in response to a software inte rrupt
Each of these sources may be individually enabled in the LINT_EN re gis ter (Table A.57) and
mapped to a single LINT# signal through the LINT_MAP0, LINT_MAP1, and LINT_MAP2
registers (Table A.59, Table A.60, Table A.73). When an interrupt is receiv ed on any of the
enabled sources, the Universe II asserts the appropriate LINT # pin and s ets a matching bit in
the LINT_STAT register (Tab le A.62). See Table 2.15 below for a list of the enable, mapping
and status bits for PCI interrupt sources.
Table 2.14 : Source , Enabling, Mapp ing, and Stat us of PCI Interr upt Output
Interrupt Sour ce Enable Bit in LINT_EN
(Table A.57)
Mapping Field in LINT_MAPx
(Table A.59, Table A.60,
Table A.73)
Status Bit in LINT_STAT
(Table A.58)
ACFAIL* ACFAIL ACFAIL ACFAIL
SYSFAIL* SYSFAIL SYSFAIL SYSFAIL
PC I So ftware In te rr up t S W_ INT SW_I N T SW_ I N T
VMEbus Softwa re IA CK S W_IACK SW_IACK SW_IACK
VMEbus Error VERR VERR VERR
PC I T ar get -A b or t or
Master-Abort LERR LERR LERR
DMA Event DMA DMA DMA
VMEbus Interrupt Input VIRQ7-1 VIRQ7-1 VIRQ7-1
Location Monitor LM3-0 LM3-0 LM3-0
Mailbox Access MBOX3-0 MBOX3-0 MBOX3- 0
VMEbus Ownership VOWN VOWN VOWN
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The LINT_STAT register sho ws the status of all sources of PCI interrupts, independen t of
whether that source has been enabled. This implies that an interrupt handling routine must
mask out those bits in the re gister that do not correspond to enabled sources on the activ e
LINT# pin.
Except for SYSFAIL* and ACFAIL*, all sources of PCI interrupts are edge-sensitiv e .
Enabling of the A CFAIL* or SYSFAIL* sources (ACFAIL and SYSFAIL bits in the
LINT_EN re gister) causes the status bit and mapped PCI interrupt pin to assert synchronously
with the assertion of the ACFAIL* or SYSFA IL* source. The PCI interrupt is negated once
the ACFAIL or SYSFAIL status bit is cleare d. The status bit cannot be cleared if t he source is
still ac ti ve. Therefore, if SYSFAIL* or ACFAIL* is stil l asserted while the interrupt is enabled
the interrupt will continue to be asserted. Both of the se sources are synchronized and filtere d
with multiple edges of the 64 MHz clock at their inputs.
All other sources of PCI interrupts are edge-sensitive. Note that the VMEbus source for PCI
interrupts actually comes out of the VMEbus Interrupt Handler block and reflects acquisition
of a VMEbus STATUS/ID. Therefore, even though VMEbus interrupts externally are
level-sensitive as required by the VMEbus specification, they are internally mapped to
edge-sensiti ve interrupts (see “VMEbus Interrupt Handling” on page 2-68).
The interrupt s ource status bit (in the LI NT_STAT re gister) and the mapped LINT# pin remain
asserted with all interrupts. The status bit and the PCI interrupt output pin are only released
when the interrupt is cleared by writing a “one” to the appropriate s t atus bit.
2.6.2 VMEbus Interrupt Generation
This section details the conditions under which the Universe II genera tes interrupts to the
VMEbus.
Interrupts may be generated on any combination of VMEbus interrupt lines (IRQ*[7:1]) from
multiple sources:
• PCI sources of VMEb us interrupts
- LINT #[7:0]
• Internal sources of VMEbus interrupts
- DMA
- VMEbus bus error encountered
- PCI Target-Abor t or Master-Abort encountered
- Mailbox register access
- software i n ter ru pt
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Each of these sources may be indi vidually enabled through the VINT_ EN register
(Ta ble A.61) and mapped to a particular VMEbus Interrupt leve l using the VINT_MAPx
registers (Table A.63, Table A.64, and Table A.74). Multiple sources may be mapped to any
VMEbus level. Mapping interrupt sources to level 0 effectively disables the interrupt.
Once an interrupt has been recei ved from any of the sources, the Universe II sets the
corresponding status bit in the VINT_STAT re gis ter (Table A.62), and asserts the appropriate
VMEbus interrupt output signal (if enabled). When a VMEbus interrupt handler receives the
interrupt, it will perform an IACK cycle at that interrupt level. When the Universe II decodes
that IACK cycle together with IACKIN* asserted, it provides the STATUS/ID previously
stored in the S TATID register (Table A.65), unless it is configur ed as SYSCON in which case
it does not monitor IACKIN*. See Table 2.15 belo w for a list of the enable, mapping and
status bits for VMEb us interrupt sources.
Table 2.15: Sour c e , Enabling, Mappi ng, and Stat us of VMEbus
In te rrupt Outputs
Interrupt Sour ce En able Bit in VINT_EN
(Table A.61)
Mapping Field in
VINT_MAPx
(Table A.63, Table A.64,
Table A.74)
Status Bit in VINT_STAT
(Table A.62)
VMEbus Software
Interrupt SW_INT7-1 N/Aa
a. This set of softwar e interrupts cannot be mapped. That is, setting the SW_INT1 bit triggers VXIRQ1, setting the SW_INT2 bit
triggers VXIRQ2 etc.
SW_INT7-1
VMEbus Error VERR VERR (Table A.64) VERR
PC I T ar get -A b or t or
Master-Abort LERR LERR (Table A.64) LERR
DMA Event DMA DMA (Table A.64) DMA
Mailbox Register MBOX3-0 MBOX3-0 (Table A.74) MBOX3-0
PCI bus Int errup t Input LIN T7-0 LIN T7-0 (Table A.74) LIN T7-0
VMEbus Software
Interrupt
(mappable)
SW_INT SW_INT(Table A.64) SW_INT
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For all VMEbus interrupts, the Universe II interrupter supplies a pre-programmed 8-bit
STATUS/ID: a common v alue for al l interrupt lev els. The upper sev en bits ar e programmed in
the STAT ID register. The lowest bit is cleared if the source of the interrupt was the software
interrupt, and i s set for all other interrupt sources . If a softwa re interrupt source and another
interrupt source are active and mapped to the same VMEbus interrupt lev el, the Univer se II
gives priority to the software source.
Once the Universe II has provided the STATUS/ID to an interrupt handler during a software
initiat ed VMEb us interrupt, it genera tes an internal interrupt, SW_IACK. If enabled, this
interrupt feeds back to the P CI b us (through one of t he LINT# pins ) to signal a process that the
interrupt started through software has been completed.
All VMEbus interrupts generated by the Universe II are RORA, except for the software
interrupts which are R OAK. This means that if the inter rupt source was a softw are interrupt,
then the VMEb us interrupt output i s automatically negated when the Univ erse II receiv es the
IAC K cycle. However, for any other interrupt, the VMEbus interrupt output remains asser ted
until cleared by a register access. Writing a “one” to the relevant bit in the VINT_STAT
re gis ter clear s that interrupt source. However, since PCI inte rrupts are le vel-sensitiv e, if an
attempt is made to clear the VMEbus interrupt while the LINT# pin is still asserted, the
VMEbus interrupt remains as serted. This causes a sec ond interrupt to be generated to the
VMEbus. For this reason, a VMEbus interrupt handler should clear the source of the PCI
interrupt be fore clearing the VMEbus interrupt.
Since software interrupts are RO AK, the respective bits in the VINT_STAT register are
cleared automatically on completion of the IACK cycle, simultaneously with the negation of
the IRQ.
Figure 2.11 : STATUS/ID Provided by Universe II
Programmed from
VME_STATUS/ID
Registers
0 if S/W Interrupt Source
1 if Internal or LINT
Interrupt Source
STATUS/ID
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2.7 Interr upt Ha ndling
This is the second of two sec tions in this chapter which describe the Universe II’s interrupt
capabilities. The previous section, “ Interrupt Generation” on page 2-62, described the
interrupt outputs of the Univ erse II on the PCI bus and the VMEbus. The curr ent section
describes how the Uni ver se II responds to interrupt sources. In other words, this section
describes the Univ erse II as an interrupt handler.
This section is broken down as follows :
• “PCI Interrupt Handling” on page 2-68 explains how the Universe II can respond to
hardware interrupts on the PCI bus,
• “VMEbus Interrupt Handling” on page 2-68 expla ins how the Universe II can
respond to hardware interrupts (or SYSFAI L* and ACFAIL*) on the VMEbus,
• “Internal Interrupt Handling” on page 2-71 explains how internal states of the
Univ erse II can trigger interrupts.
2.7.1 PCI Interrupt Handling
This section explains how the Univ erse II can respond to hardware interrupts on the PCI bus.
All eight PCI interrupt lines, LINT#[7:0], can act as interrupt inputs to the Univ erse II. They
are lev el-s e nsitive and, if enabled in the VINT_EN register (Table A.61), immediately
generate an interrupt to the VMEbus. It is expected that when a VMEbus interrupt handler
receives the Uni v erse II ’s STATUS/ID from the Univ erse II, the int errupt handler will c lear the
VMEbus interrupt by first clearing the source of the interrupt on the PCI bus, and then
clearing the VMEbus inte rrupt itself (by writing a “one” to the a ppropriate bit in the
VINT_STAT re gis ter, Table A.62).
Note that since PCI interrupt s are le vel- sens itiv e, if an attempt is made to clear the VMEbus
interrupt while the LINT# pin is still asserted, the VMEbus interrupt rema ins asserted. This
causes a second interrupt to be generated to the VMEbus. F or this reason, a VMEbus interrupt
handler should clear the source of the PCI interrupt before clearing the VMEbus inte rrupt.
2.7.2 VMEbus Interrupt Handling
This section explains how the Univ erse II can respond to hardware ev ents on the VMEb us as
an interrupt handler.
As a V MEbus interrupt handler, the Universe II can monitor any or all of the VM Ebus
interrupt le vels. It can also monitor SYSFAIL* and ACFAIL*, although IACK cycles are not
generated for these inputs. Each interrupt is enabled through the LINT_EN register
(Table A.57).
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Once enabled, asserti on of an y of the VMEbus interrupt lev els , IRQ[7:1]*, causes the internal
interrupt handler circuitry to request ownership of the Universe II's VMEbus Master Interface
on the level programmed in the MAST_CTL re gis ter (see “VMEb us R equester” on page 2- 6).
This interface is shared betw een several channel s in the Universe II: the PCI Target Channel,
the DMA Channel, and the Interrupt Channel. The Interrupt Channel has the highest priority
over all other channe ls and, if an interrupt is pending, assumes owne rship of the VMEbus
Master Inter f ace when the pre vious owner has relinquished ownership.
The Uni verse II latches the f ir st interrupt that appears on the VMEb us and begins to pr ocess it
immedia tely. Thus if an interrupt at a higher priority is asserted on the VMEbus before
BBSY* is asserted the Uni v erse II will perform a n interrupt a cknowle dge for the f irst interr upt
it detected. Upon completion of that IACK cycle, the Universe II will then perform IACK
cycles for the higher of any remaining active interrupt s.
There may be some latency between reception of a VMEb us interrupt and generat ion of the
IACK cycle. This arises because of the latency involved in the Interrupt Channel gaining
control of the VMEbus Master Interface, and because of possible latency in gaining ownership
of the VME b us if the VMEb us Master Interf ace is programmed for release-when-done. In
addition, the Universe II only generates an interrupt on the PCI bus once the IACK cycle ha s
completed on the VMEbus. Because of thes e combined latencies (time to acquire VMEbus
and time to run the IACK cycle), systems should be designed to accommodate a certain worst
case latency from VMEbus interrupt genera tion to its translation to the PCI bus .
When the Univer se II receiv es a STATUS/ID in response to an IACK cycle, it stores that v alue
in one of seven registers. These registers, V1_STATID through V7_STATID (Table A.66 to
Table A.72), stor e the STATUS/ID corres ponding to ea ch IACK level (in the STATID field).
Once an IACK cycle has been generated and the re sulting STATUS/ID is latched, another
IACK cycle will not be run on that level until the le v el has been r e-armed b y writing a “one” to
the corresponding status bit in the VINT_STAT register (Table A.62). If other interrupts (at
dif ferent le vels) are pending while the inter rupt is waiting to be re-armed, IACK c ycles are run
on those levels in order of priority and the STATUS/IDs stored in their respectiv e regis ters.
Once the IACK cycle is complete and the STATUS/ID stored, an interrupt is gene rated to the
PCI bus on one of LINT#[7:0] depending on the mapping for that VMEb us level in the
LINT_MAP0 register. The interrupt is cleared and the VMEbus interrupt level is re-armed by
clearing the correct bit in the LINT_STAT register.
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2.7.2.1 Bus Erro r During VMEbus IACK Cycle
A bus error encountered on the VMEbus while the Univ erse II is performing an IA CK cycle is
handled by the Universe II in two ways. The first is through the error logs in the VMEb us
Master Interf ace. These logs store address and command information whenever the Uni v erse
II encounters a b us error on the VMEbus (see “Bus Error Handling” on page 2-58). If the err or
occurs during an IACK cycle, the IACK# bit is set in the V_AMERR register (Table A.107).
The VMEbus Master Interface al so gener ates an internal in terrupt to the Interrupt Channel
indicating a VMEbus error occu rred. This internal inte rrupt can be enabled and mapped to
either the VMEbus or PCI bus .
As well as generating an interrupt indicating an error during the IACK cycle, the Universe II
also generates an inte rrupt as though the I ACK cycle completed succes sfully. If an e rror
occurs during the fetching of the STATUS/ID, the Universe II sets the ERR bit in the
Vx_STATID re gister (Table A.66 to Table A.72), and generates an interrupt on t he appropriate
LINT# pin (as mapped in the LINT_MAP0 re gister, Table A.62). The PCI resource, upon
receiving the PCI interrupt, is expected to read the STATUS/ID register, and take appropriate
actions if the ERR bit is set. Note that the STATUS/ID cannot be considered va lid if the ERR
bit is set in the STATUS/ID register.
It is important to recognize that the IACK cycle error may gene rate two PCI interrupts: one
through the VM Ebus mas ter b us err or interrupt and another through the standard PCI interr upt
translation. Should an error occur during acquisition of a STAT US/ID, the VINT_STAT
regis ter (Table A.62) wi ll show that both VIRQx, and VERR are acti v e.
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2.7.3 Internal Interrupt Handling
The Univ er se II's internal interrupts are routed from sev eral processes in the device. There is
an interrupt from the VMEbus Master Interface to indicate a VMEbus error, anot her from the
PCI Master Interface to indicate an error on that bus, another from the DMA to indicate
various conditions in that channel, along with se veral others as indicated in Table 2.16 below.
Table 2.16 shows to which bus each interrupt source may be routed (some sources may be
mapped to both buses, but we recommend that you map interrupts to a single bus).
Figure 2.12 shows the sources of interrupts, and the interfaces from which they originate.
Interrupt handling for each one of these sources is d escribed in the following subsections.
Table 2.16 : Internal Interrupt Routing
Interrupt Sourc e May be Routed to:
VMEb us PCI Bus
PCI s/w interrupt √
VMEbus s/w interrupt √
IACK cycl e complete
for s/w int er rup t √
DMA event √√
Mailbox access √√
Location monitor √
P C I Target-Abort or
Master-Abort √√
VMEbus bus error √√
VMEbus bus
ow nership grant ed √
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PCI
Slave
DMA Channel
PCI
Master
VME
Master
VME
Slave
VMEbus Slave Channel
Interrupt Channel
PCI Bus Slave Channel
PCI Bus
Interface VMEbus
Interface
DMA bidirectional FIFO
coupled read logic
DMA
PCI error
PCI software interrupt
VME error
VME ownership bit
software IACK
VME software interrupt
Interrupt Handler
prefetch read FIFO
posted writes FIFO
coupled path
posted writes FIFO
Figure 2.12 : Sources of Inter nal Interrupts
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2.7.3.1 VMEb u s and PCI Softwar e Interru pts
It is possible to interrupt the VMEb us and the PCI b us through software. These interrupts may
be triggered by writing a “one” to the res pective enable bits.
Interrupting the VMEbus through software
There are two methods of triggering software interrupts on the VMEbus. The second method
is provided for compatibility with the Universe I.
1. The first method for interrupting the VMEbus through software involve s writing
“one” to one of the SW_INT7-1 bits in the V INT_EN register (Table A.61) while
the mask bit is zero.1 This causes an interrupt to be generated on the corresponding
IRQ7-1 line. That is, setting the SW_INT1 bit triggers VXIRQ1, setting the
SW_INT2 bit triggers VXIRQ2, etc.
2. The second method for interrupting the V MEbus through software involves an
e xtra step. Writing a “one” to the SW_INT bit in the VINT_EN regis ter when this
bit is “zero” (Table A.61) triggers one (and only one) interrupt on the VMEbus on
the level programmed in the VINT_MAP1 register (Table A.64). Notice that this
method requires that the user specify in the VINT_MAP1 re gister to which line the
interrupt i s t o be generated. When the SW_INT interrupt (method 2) i s acti ve at the
same level as one of SW_INT7-1 interrupts (method 1), the SW_INT interrupt
(method 2) takes priority. While this interrupt source is active, the SW_INT st atus
bit in the VINT_STAT register is set.
With both methods, the mask bit (SW_INTx or SW_INT) in the VINT_EN regis ter must be
zero in order for writing “one” to the bit to have any effect.
Re gardless of t he software interrupt method used, when an IA CK cycle is serviced on the
VMEbus, the Universe II can be programmed to generate an interrupt on the PCI bus by
setting the SW_IACK enable bit in t he LINT_EN re gis ter (see “Software IACK Interrupt” on
page 2-74).
Interrupting the PCI bus through software
On the PCI bus, there is only one method of directly triggeri ng a software interrupt. (This
method is analogous to the second method described in the previous section.) Causing a
“zero” to “one” transition in the SW_INT in the LINT_EN (Table A.57) re gis ter generates an
interrupt to the PCI bus. While this interrupt source is active, the SW_INT status bit in
LINT_STAT is set. The SW_INT fi eld in the LINT_MAP1 register (Table A. 60) determines
which interrupt line is asserted on the PCI interface.
1. The term “enable” is more meaningful with respect to the other fields in this register, i.e., excluding the software
in terrupts. Writing t o the sof tware interrupt fie lds of this register does not ena b le an in terrupt, it triggers an inter-
rupt.
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Termination of sof tware interrup ts
Any software interrupt may be cleared by clearing the respectiv e bit in the VINT_EN or
LINT_EN register. However, this method is not recommend for software VME bus inte rrupts
because it may result in a spurious inte rrupt on that bus. That is, the Universe II will then not
respond to the interrupt handler’s IA CK c ycle, and the handler will be left without a
STATUS/ID for the interrupt.
Since the software interrupt is edge-sensitiv e , the so ftware interrupt bit in the VINT_EN or
LINT_EN register should be cleared any time between the last interrupt finishing ant the
generation of another inter rupt. It is recommended that the appropriate interrupt handler clear
this bit once it has completed its operations. Alte rnatively, the process generating a software
inter rupt could clear this bit before re-asserting it.
Softwar e interrupts on the VMEb us ha ve priority over other interrupts mapped internally to
the same level on the VMEbus. When a VMEbus interrupt handler generates an IACK cycle
on a lev el mapped to both a software interrupt and another interrupt, the Universe II alw a ys
provides the STATUS/ID for the softwa re interrupt (bit zero of the Sta tus/ID is cleared). If
there are no other active interrupts on that level, the interrupt is automatically cleare d upon
completion of the IACK cycle (since software interrupts are ROAK).
While the software i nter rupt STATUS/ID has priori ty ov er other interrupt s ources, the user can
giv e other interrupt sources priority ov er the software interrupt. This is done by reading the
LINT_STAT register (Table A.62) when handling a Uni verse II interrupt. This re gis ter
indicates all active interrupt sources. Using this information, the inte rrupt handler can then
handle the interrupt sources in any system-defined order.
2.7.3.2 Software IACK Interrupt
The Univer se II generates an internal interrupt whe n it provide s the software STATUS/ID to
the VMEbus. This interrupt can only be routed to a PCI interrupt output. A PCI interrupt will
be generated upon completion of an IACK cy cle that had been initiated b y the Uni verse II’s
software interrupt if:
• the SW_IACK bit in the LINT_EN register (Table A.57) is set, and
• the SW_IACK field in the LINT_MAP1 registe r (Table A.60) is mapped to a
corresponding PCI interrupt line.
This interrupt could be used by a PCI process to indicate that the software interrupt generated
to the VMEbus has been received by the sl ave device and acknowledged.
Like other i nterrupt sources, this interrupt source can be independently enabled through the
LINT_EN regis ter (Table A.57) and mapped to a particular LINT# pin using the LINT_MAP1
regis ter (Table A.60). A status bit in the LINT_STAT register (Table A.62) indicates when the
interrupt source is acti ve, and is used to clear the interrupt once it has been serviced.
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2.7.3.3 VMEbus Ownership Interrupt
The VMEbus ownership interrupt is generated when the Universe II acquires the VMEbus in
response to programming of the V OWN bit in the MAST _CTL re gister (Table A.81). This
interrupt source can be used to indicate that ownership of the VME bus is ensured during an
exclusive access (see “VME Lock Cycle s—Exc l usive Access to VME bus Resources ” on
page 2-47). The interrupt is cleared by wri ting a one to the matching bit in the LINT_ STAT
regis ter (Table A.62).
2.7.3.4 DMA Interrupt
The DMA module provides six possible interrupt sources:
• if the DMA is stopped (INT_STOP),
• if the DMA is halted (INT_HALT),
• if the DMA is done (INT_DONE),
• for PCI Target-Abort or Master-Abort (INT_LERR ),
• for VMEb us errors (INT_VERR), or
• if there is a PCI protocol error or if the Universe II is not enabled as PCI mas ter
(INT_P_ERR).
All of these interrupt sourc e s are ORed to a single DMA interrupt output line. When an
interrupt come s from the DMA mod ule, s oftware must rea d the DMA sta tus bits (Table A.55)
to discover the originating interrupt source. The DMA interrupt can be mapped to either the
VMEbus or one of the PCI interrupt output lines. See “DMA Interrupts” on page 2-95.
2.7.3.5 Mailbox Register Access Interrupts
The Univ erse II can be programmed to genera te an i nterrupt on the PCI bus and/or the
VMEbus when any one of its mailbox registers is accessed (see “Mailbox Registers” on
page 2-108). The user may enable or disable an interrupt respons e to the access of any
mailbox regis ter (Table A.57). Each register access may be indi vidually mapped to a specific
interrupt on the PCI bus (LINT_MAP2, Table A.73) and/or the VMEbus (VINT_MAP2,
Table A.74). The status of the PCI interrupt and the VMEb us are recorded in the LINT_STAT
(Ta ble A.58) and VINT_STAT registers (Table A.62), respectively.
2.7.3.6 Location Monitors
The Universe II can be programmed to generate an interrupt on the PCI bus whe n one of its
four location monitors is accessed (see “Location Monitors” on page 2-19).
In order for an incoming VMEbus transaction to a ctivate the location monitor of the Universe
II, the location monitor must be enabled, the access must be within 4 kbytes of the location
monitor base address (LM_BS, Table A.102), and it must be in the specified address space.
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When an access to a location monitor is detected, an inte rrupt may be generated on the PCI
bus (if the location monitor is enabled). There are four loca tion monitors:
• VA[4:3] = 00 selects Location M onitor 1,
• VA[4:3] = 01 selects Location M onitor 2,
• VA[4:3] = 10 selects Location M onitor 3, and
• VA[4:3] = 11 selects Location M onitor 4.
The user may enable or disable an interrupt response to the access of any location m onitor
with bits in the LINT _EN register (Table A.57). Access to each location monitor may be
indi vidually mapped to a specif ic interrupt on th e P CI bus (LIN T_MAP2, Table A.73)—not to
the VMEbus b us . The status of the P CI interrupt is logged in (LMn bit of the LINT_STAT,
Table A.58).
2.7.3.7 PCI and VMEbus Error Interrupts
Interrupts from VMEbus errors, PCI Target-Aborts or Master-Aborts are generated only when
bus errors ar ise during decoupled writes. The bus error interrupt (from either a PCI or
VMEbus error) can be mapped to either a VME bus or PCI interrupt output line.
2.7.4 VME64 Au to-ID
The Universe II includes a power-up option for participation in the VME64 Auto-ID process.
When this option is enabled, the Universe II generates a level 2 interrupt on the VMEbus
before release of SYSFAIL*. When the lev el 2 IACK cycle is run b y the system Monarch, the
Univ erse II responds with the Auto-ID Status/ID, 0xFE, and enables access to a CR/CSR
image at base address 0x00_0000.
When the Monarch detects an Auto-ID STATUS/ID on le vel 2, it is expected to access the
enabled CR/C SR space of the interr upter. From there it completes id enti fication and
configuration of the card. The Monarch functionality is typically implemented in software on
one card in the VMEbus system. See “Automatic Slot Identification” on page 2-24.
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2.8 DMA Controller
The Uni verse II has a DMA controller for high performance data transfer between the PCI b us
and VMEbus. It is operated through a series of registers that control the source and
destination for the data, length of the tr ansfer and the transfer protocol to be used. There are
two modes of operation for the DMA: Direct Mode, and Linked List Mode. In direct mode,
the DMA registers a re programmed directly by the external PCI master. In linked list mode,
the registers are loaded from PCI memory by the Uni verse II, and the transfer described by
these registers is e xecuted. A block of DMA registers stored in PCI memory is called a
command packet. A command packet may be linked to another command packet, such that
when the DMA has completed the o perations described b y one comm and packet, it
automatica lly mov es on to the ne xt command packe d in the linked-list of command packets .
This section is brok en into the following ma jor sub-sections
1. “DMA Registers Outline” on page 2-77 describes in de tail how the DMA is
programmed from a regis ter perspective.
2. “Direct M ode Operation” on pa ge 2-83 describes how to operate the DMA when
directly programming the DMA re gis ters.
3. “Linked-List Operation” on page 2-86 describes how to operate the DMA when a
linked-list of comma nd packets describing DMA transfers is stored in PCI
memory.
4. “FIFO Oper ation and Bus Ownership” on page 2-92 describes internally how the
DMA makes use of its FIFO and how this affects ownership of the VMEb us and
PCI bus .
5. “DMA Interrupts” on page 2-95 describes the interrupts generated by the DMA
6. “Interactions with Other Channels” on page 2-96 discusses the relations between
the DMA Channel and the other data channels.
7. “DMA Error Handling” on page 2-96 describes how to handle errors encountered
by the DMA
2.8.1 DMA Registers Ou tline
The DMA re gis ters reside in a block starting at of f set 0x200. They describe a single DMA
transfer : where to t ransfer da ta from ; where to tra nsfer da ta to; how muc h data to transfer; and
the transfer attributes to use on the PCI bus and VMEbus. A final regis ter contains status and
control information for the transfer. While the DMA is active, the registers are locked against
any changes so that a ny writes to the registers will have no impact.
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In dire ct-mode operation, these registers would be programmed directly by the user. In
link ed-lis t opera tion, they are repeatedly loaded by the Univer se II from command packet s
residing in PCI memory until the end of the link e d-lis t is reached (see “Linked-List
Operation” on page 2-86).
2.8.1.1 Source and Desti nat ion Address es
The source and destination addresses for the DMA reside in two registers: the DMA PCI bus
Address Regis ter (DLA re gister, Table A.52), and the DMA VMEbus Address Register (DVA
regis ter in Table A.53). The determination of which is the source address, and which is t he
destination is made by the L2V bit in the DCTL re gister (Table A.50). When set, the DMA
transfers data from the PCI to the VMEbus. Hence DLA becomes the PCI source regi ster and
DVA becomes the VMEbus de sti nat ion register. When cleared, the DMA transfers data from
the VMEb us to PCI bus and DLA becomes the PCI destina tion register; DVA becomes the
VMEbus source register.
The PCI addres s may be programmed to any byte address in PCI Memory s pace. It cannot
transfer to or from PCI I/O or Configuration spaces.
The VMEbus address may also be programmed to any byte address, and can access any
VMEbus address space from A16 to A32 in supervisory or non-privileged space, and data or
program space. The setting of address space, A16, A24 or A32, is program med in the VAS
field of the D CTL register (Table A.50). The sub-spaces are programmed in the PGM and
SUPER f ields of the same register.
Although the PCI and VMEbus addresses may be programmed to any byte
aligned address, they must be 8-byte aligned to each other (i.e. the low three
bits of each must be identical). If not programmed with aligned source and
destination addresses and an attempt to start the DMA is made, the DMA will
not start, it will set the protocol error bit (P_ERR) in the DCSR register
(Table A.55), and if enabled to, generate an interrupt. Linked-list operations
will cease.
In dire ct mode the user must reprogram the source and destination a ddress registers (DMA,
DLA) before each transfer. These regis ters are not updated in direct mode. In linked-list mo de,
these registers are updated by the DMA when (and onl y when) the DMA is stopped, halted, or
at the completion of processing a co mma nd packet. If r ead during DMA acti vity, the y will
return the number of bytes remaining to transfer on the PCI side. All of the DMA registers are
locked against any changes b y the user while the DMA is active. When stopped due to an
error situation, the DLA and DVA registers should not be used, but the DTBC is valid (see
“DMA Error Handling” on page 2-96 for details). At the end of a successful linked-list
transfer, the DVA and DLA register s will point to the next addre ss at the end of the trans fer
block, and the DTBC regis ter will be zero.
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2.8.1.2 Transfer Size
The DMA may be programmed through the DMA Transfer Byte Count register (DTBC
register in Table A .51) to trans fe r any number of bytes from 1 byte to 16 MBytes. There are
no alignment requirements to the source or destination addresses. Should the width of the
data turnov ers (8- through 64-bit on VM Eb us and 32- or 64-bit on PC I) not align to t he length
of the tr ans fer or the source/ dest inat ion addres ses , the DMA will inser t transfer s of smaller
width on the appropr iate bus. For example, if a 15-byte transfer is progr ammed to start at
address 0x1000 on the VMEbus, and the width is set for D32, the DMA will perform three
D32 transfers, foll owe d by a D16 transf er, followe d by a D08 transfer. The Universe II does
not generate unaligned transfers. On a 32-bit PCI bus, if the start address was 0x2000, the
DMA would generate three data beat s with all byte l anes enabled, and a fourth with three by te
lanes enabled.
The DTBC register is not updat ed while the DMA is acti ve (indicat ed by the ACT bit in the
DGCS register). At the end of a transfer it will contain zero. Howev er, if stopped by the user
(via the ST OP bit in the DGCS re gis ter) or the DMA encounters an error, th e DTBC re gis ter
contains the number of bytes remaining to transfer on the source side. See “DMA Error
Handling” on page 2-96.
Starting the DMA while DTBC=0 will result in one of two situations . If the CHAIN bit in the
DGCS re giste r (Table A.55) is not set, the DMA will not start ; it will perf orm no action. If the
CHAIN bit is set, then the DMA loads the DMA registers with the contents of the command
packet pointed to by the DCPP re gister (Table A.54), and starts the transfers described by that
packet. Note that t he DCPP[31:5] fie ld of the DCPP register implies that the command
packets be 32-byte aligned (bits 4:0 of this register must be 0).
2.8.1.3 Transfer Data Width
The VMEbus and PC I bus data widths are determined by three fields in the DCTL register
(Ta ble A.50). These fields affect the speed of the transfer. They should be set for the
maximum allowable width that the destination device is capable of accepting.
On the VMEbus, the DMA supports the following data widths:
D08(EO), D16, D16BLT, D32, D64, D32BLT, and D64BLT (MBLT).
The width of the transfer is set with the VD W field in the DCTL regis ter. The VCT bit
determines whether or not the Universe II VMEbus Master will generate BLT transfers. The
value of this bit only has meaning if the address space is A24 or A32 and the d ata width is not
64 bits. If the data width is 64 bits the U niverse II may perform MBLT transfer s independent
of the st ate of the VCT bit.
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The Univ erse II may pe rform data tra nsfers s maller than tha t programmed in the VD W field in
order to bring itself into alignment with t he programmed width. For example if the width is
set for D32 and the s tarting VMEbus address is 0x101, the DMA will perform a D08 cycle
followed by a D16 cycle. O nly once it has achieved the alignment se t in the VDW field does
it start D32 transfers. At the end of the transfer, the DMA will al so have to perform more
low-width transfers if the last address is not aligned to VDW. Similarly, if the VCT bit is set
to enable block transfers, the DMA may perf orm non-block transfers to bring itself into
alignment.
On the PCI bus, the DMA provides the option of performing 32- or 64-bit PCI transactions
through the LD64EN bit in the DCTL register (Ta ble A. 50). If the Universe II has
powered-up on a 32-bit bus (see “Power-up Option Descriptions” on p age 2-117), this bit will
have no effect. If powe red-up on a 64-bit bus, this bit can provide some performance
improv ements when accessing 32-bit targe ts on that b us . Fo llowing the PCI specification,
befor e a 64-bit PCI initiator starts a 64-bit transa ction, it eng ages in a protocol with the
intended target to determine if it is 6 4-bit capable. This protocol typically consumes one
clock period. To sav e bandwidth, the LD64EN bit can be cleared to bypass this protocol when
it is known that the target is only 32-bit capable
2.8.1.4 DMA Comm an d Packet Po inter
The DMA Command Packet Pointer (DCPP in Table A.54) points to a 32-byte aligned
address location in PCI Memory space that contains the next command packet to be loaded
once th e transfer currently programmed into the DMA re gisters has been successfully
completed. When it has been co mpleted (or t he DTBC regis ter is zero when the GO bit is set)
the DMA reads the 32-b yte command packet from PCI memory and e xecutes the transfer it
describes.
2.8.1.5 DMA Cont rol and Status
The DMA General Control/Status Register (DGCS in Table A.55) cont ains a number of fields
that control initiation and operation of the DMA as well as actions to be taken on completion.
DMA Initiation
Once all the parameters associated with the transfer have been programmed
(source/destination addresses, transfer length and data widths, and if desired, linked lists
enabled), the DMA tra nsfer is started b y s etting the GO bit i n the DGCS register. This causes
the DMA first to e xamine the DTBC re gis ter. If it is non-zero, it latches the v a lues
programmed into the DCTL, DTBC, DLA, and DVA regis ters and initiates the transfer
programmed into those registers. If DTBC=0, it checks the CHAIN bit in the DGCS register
and if tha t bit is cleare d it as sumes the transfer to hav e c omple ted a nd s tops. Otherwise, if the
CHAIN bit is set, it loads into the DMA regi sters the command packet pointed to by the DCPP
register and initiates the transfer describe there.
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If the GO bi t is set, but the Uni v erse II has not been enabled as a PCI master with the BM (b us
maste r enable) bit in the PCI_CSR regis te r, or if the DVA and DLA contents are not 64-bit
aligned to each other , the transfer does not start, a protocol error is indicated by the P_ERR bit
in the DGCS register and, if enabled, an interrupt is generated.
If the DMA has been terminated for some reason (stopped, halted, or error), all DMA regi sters
contain values indicating where the DMA terminated. Once all status bits hav e been cleared,
the DMA may be restarted from where it left off by simply setting the GO bit. The GO bit
will only ha ve a n effect if all status bi ts ha ve been cleared. These bits include STOP, HALT,
DONE, LERR, VERR , and P_ERR; all in the D GCS registe r. These bits are all cleared by
writing "one" to the m, eithe r before or while setting the GO bit.
The GO bit alw ays returns a zero when read independent of the DMA’s current state. Clearing
the bit has no impact at any time. The ACT bit in the DGCS regis ter indicates whether the
DMA is cur rently activ e. It is set by the DMA once the GO bit is set, and cleared when the
DMA is idle. Generally, when the A CT bit is cleared, one of the other status bits in the DGCS
regis ter is set (DONE, STOP, HALT, LERR, VERR, or P _ERR), indicating wh y the DMA is
no longer active.
DMA VMEbus Ow ner sh ip
Two fields in the DGCS register determine how the DMA will share the V MEbus with the
other two potential mas ters in the Universe II (PCI Target Cha nnel, and Interrupt Channel),
and with other VMEbus masters on the bus. These fields are: VON and VOFF.
VON affe cts how much data the DMA will tra nsfer before giving the opportunity to another
master (either the Univ erse II or an external master) to assume ownership of the bus. The
VON counter is used to temporarily s top the DMA fr om tr ansferring data once a programmed
number of byt es ha ve been transferred (256 b ytes, 512 bytes , 1K, 2K, 4K, 8K, or 16K). When
performing MBLT transfers on the VMEb us , the DMA will stop performing tra ns fers within
2048 bytes after the programmed V ON limit has been reached. When not performing MBLT
transfers, the DMA will stop performing transfers within 256 b ytes once the programmed
limit has been reached. When programmed for R elease-When-Done operation, the Uni ver se II
will perform a n early r elease of BBSY* when the VON counter reaches its programme d li mit.
VON may be disabled by setting the field to zero. When set as such, the DMA will continue
transferring dat a as long as it is able.
There are other conditions under which the DMA may relinquish bus ownership. See“FIFO
Operation and Bus Ownership” on page 2-92 for details on the VMEbus request and release
conditions for the DMA.
VOFF affects how long the DMA will wait before re-requesting the bus after the V ON limit
has been reached. By setting VOFF to zero, the DMA will immediately re-request the bus
once the VON boundary has been reached. Since the DMA operates in a round-robin fashion
with the PCI Target Channel, and in a priority f a shion with the Interrupt Channel, if either of
these channels require ownership of the VMEbus, they will receive it at this time.
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VOFF is only invoked when VMEbus tenure is relinquished due to encountering the VON
boundary. When the VMEbus is released due to other conditions (e.g., the DMAFIFO has
gone full while reading from the VMEbus), it will be re-requested as soon as that condi tion is
cleared. The VOFF timer can be programmed to various time intervals from 0µs to 1024µs.
See “FIFO Ope ration and Bus Ownership” on page 2-92 for details on the VMEbus request
and release conditions for the DMA.
See “Interactions with Other Channels” on page 2-96 for information on other mechanisms
which may delay the DMA Channel fr om acquiring the VMEbus or the PCI bus.
DMA Completion and Term in ation
Normally, the DMA will continue processing its transfers and c ommand pa cke ts until either it
completes everything has been requested to, or it encounters an error. There are also two
methods for the user to interrupt this process and cause the DMA to termina te prematurely:
Stop and Halt. S top causes th e DMA to terminate immediate ly, while halt causes the DMA to
terminate when it has completed processing the current command pac ket in a linked list.
When the STOP_REQ bit in the DGCS register is set by the user, it tells the DMA to cease its
operations on the source b us immediate ly. Remai ning data in the FIFO continues to be
written to the destination bus until the FIFO is empty. Once the FIFO is empty, the STOP bit
in the same regis te r is set and, if enable d, an interrupt gene ra ted. The DMA registers will
contain the values that the DMA stopped at: the DTBC register contains the number of bytes
remaining in the tr ansfer, the source and destination address re gis ters contain the next address
to be read/written, the DCPP r egister contains the next command packe t in the linked-lis t, and
the DCTL regis te r contains the trans fer at tributes.
If read transac tions are occurring on the VMEbus, then setting a stop request can be affected
b y the V OFF timer. If the ST OP_REQ bit is set while the DMA is lying idl e waiting for V OFF
to expire before recommencing reads, then the request remains pending until the VO FF timer
has expired and the bus has been granted.
Halt provides a mechanism to interrupt the D MA at command packet boundaries during a
link ed-lis t tr a nsfer. In contr ast, a st op re quests the DM A to be interrupted immediately, while
halt takes eff ect only when the current command packet is complete. A ha lt is requested of
the DMA by setting the HALT_REQ bit in the DGCS register. This causes t he DMA to
complete the transfers defined b y the current contents of the DMA re gisters and, if the CHAIN
bit is set, load in the next command pack et. The DMA then terminat es, the HALT bit in the
DGCS register is set, and, if enabled, an interrupt generate d.
After a stop or halt, the DMA can be rest arted from the point it left off by setting the GO bit;
but before it can be re-started, the STOP and HALT bits must both be cleared.
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Re gardless of ho w the DMA stops—whether normal , bus err or or user interrupted—the DMA
will indicate in the DGCS register why it stopped. The STOP a nd HALT bits get set in
response to a stop or halt request. The DONE bit gets set when the DMA has successfully
completed the DMA transfer, including all entries in the linked-list if operating in that mode.
There are also three bits that are set in response to error conditions: LERR in the case of
Tar get- Abort encountered on the PCI bus; VERR in t he case of a bus error encountered on the
VMEbus ; and P_ERR in the case that the DMA has not been properly programmed (the DMA
w as started with the BM bit i n the P CI_CSR regist er not enabled, or the DLA and DVA
registers were not 64-bit aligned, (see “Source and Destination Addresse s” on page 2- 78).
Befor e the DMA can be restarted, each of th ese stat us bits must be cleare d.
When the DMA terminates, an interrupt may be generated to VMEbus or PCI bus. The user
has control over which DMA termination conditions will cause the interrupt through the
INT_ST OP, INT_HALT, INT_DONE, INT_LERR, INT_VERR, and INT_P_ERR bits in the
DGCS register.
2.8.2 Direct Mode Operation
When operated in direct mode, the Universe II DMA is set through manual regis ter
programming. Once the transfer described by the DVA, DLA, DTBC and DCTL r e gis ters has
been completed, the DMA sits idle awaiting the next manual programming of the registers.
Figure 2.13 describes the steps inv olved in operatin g the DMA in direct mode.
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Figure 2.13 : Direct Mode DMA transf ers
Step 1: Program DGCS
with tenure and interrupt
requirements
Step 2: Program
source/destination
addresses, & transfer
size/attributes
Step 4: Set GO bit
Step 5: Await termination
of DMA
Normal
Termination?
More
transfers
required?
No
Yes
Handle error
No
Yes
Done
Step 3: Ensure status bits are clear
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In Step 1, the DGCS register is set up: the CHAIN bit is cleared, VON a nd VOF F are
programmed with the appropriate values for controlling DMA VMEbus tenure, and the
interrupt b its (INT_STOP, INT_ H A LT, INT_DONE, INT_LE RR , IN T _ V ER R, and
INT_P_ERR) are programmed to enable generation of interrupts based on DMA termination
e vents. DMA interrupt enable bits in the LINT_EN or VINT_EN bits should also be enabled
as necessary (see “PCI Interrupt Generation” on page 2- 63 and “VMEbus Int errupt
Generation” on page 2-65 for details on generating interrupts).
In Step 2, the actual trans fe r is programmed into the DM A: source and destination start
addresses int o the DLA and D VA regis ters, transfer count into the DTBC register, and transfer
width, direction and VMEbus address space into the DCTL register. These should be
reprogrammed after each transfer.
In Step 3, ensure that if any status bits (DONE, STOP, HALT, LERR , VERR, or P_ERR)
remain set from a previous transfer the y are cleared. P_ERR must not be updated at the same
time as Step 4, otherwise the P_ERR that may be generated b y sett ing GO may be missed (see
Step 4). These bits may be cleared as part of Step 1.
In Step 4, with t he transfer programm ed, the GO bit in DGCS must be set. If the DMA has
been improperly programmed, either because the BM bit in the PC I_CSR has not been set to
enable PCI bus mastership, or the source and destinati on star t addresses ar e not aligned, then
P_ERR will be asserted. Otherwise, the ACT bit will be set, and the DMA will then start
transferring dat a, sharing ownership of the VMEb us with the PCI Tar get and Interrupt
channels and the PCI bus with the VMEb us Sla ve Channel.
In Step 5, one w ai ts for termination of the DMA transfers. The DMA will continue with the
tra nsfer s until it:
• completes al l trans fers,
• is terminated early with the STOP_REQ bit, or
• encounters an error on the PCI bus or VMEbus.
Each of these conditions will cause the AC T bit to clear, and a corresponding status bit to be
set in the DGCS register. If enabled in Step 1, an interrupt will also be generated. Once the
software has set the GO bit, the soft wa re can monitor for DMA completion b y either waiting
for generation of an interrupt, or by polling the status bits. It is recommended that a
background timer also be initiated to time-out the transfer. This will ensure that the DMA has
not been hung up by a busy VMEbus, or other such system issues.
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If an ea rly termination is desir ed, perhaps because a higher priority opera tion is required, the
STOP_REQ bit in the DGCS register can be set. This will stop all DMA operations on th e
source bus immediately, and set the STOP bit in the same register when the last piece of
queued data in the DMA FIFO has been written to t he destination b us . Attempting to
termina te the transfer with the HALT_REQ bit will ha ve no ef fe ct in direct mode operation
since this bit only reques ts the DMA to stop betw een command packets in linked-list mode
operation.
When the softwar e has detected completion, it should verify the status bits in the DGCS
register to see the reason for completion. If one of the error bits hav e been set it proceeds into
an error handling routine (see “DMA Error Handling” on page 2-96). If the ST OP bit was set,
the software should take whatever actions were desired when it set the ST OP_R EQ bit. F or
e xample, if it w as stopped for a higher priority transfer, it might record the DLA, DVA and
DTBC register s, and then reprogram them with the higher priority transfer. When that has
completed it can restore the DVA, DLA and DTBC registers to complete the remaining
transfers.
If the DONE bit was set, it indicates that the DMA completed its requested transfer
successfully, and if more transfers are required, the software can proceed to Step 2 to start a
ne w transfer.
2.8.3 Linked-List Operation
Unlike direct mode, in w hich the DMA performs a single block of data at a time, linked-list
mode allows the DMA to tra nsfer a series of non-contiguous blocks of data without software
interve ntion. Each entry in the linke d-lis t is described by a command packet which parallels
the DMA register layout. The data structure for each command packet is the same (see
Figure 2.14 below), and contains all the necessary infor mat ion to program the DMA address
and control registers. It could be described in software as a record of eight 32-bit data
elements. Four of the elements represent the four core regis ters required to define a DMA
transfer: DCTL, DTBC, DVA, and DLA. A fifth element represents the DCPP register whi ch
points to the next command pack et in the list. The least two significant bits of the DCPP
element (the PROCESSED and NULL bits) provide status and control information for linked
list processing.
The PROCESSED bit indicates whether a command packe t has been PROCESSED or not.
When the DMA processes the command packet and has successfully completed all transfers
described by this pack et, it sets the PROCESSED bit to “1” before reading in the ne xt
command pac ket in the list. This implies that the P R OCE SSED bit must be initia lly set for “0”
by the use r for it to be of use . This bit, when set to 1, indicates that this command packet has
been disposed of by the DMA and its memory can be de-allocated or reused for another
transfer description.
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The NULL bit indicates the termination of the entire linked list. If the NULL bit is set to “0”,
the DMA processes the ne xt command packet pointed to by the command pack et pointer. If
the NULL bit is set to “1” then the address in the command packet pointer is considered
inv alid and the DMA stops at the completion of t he trans fer described b y the current command
packet.
Figure 2.15 outlines the steps in programming the DMA for linked-list operation.
Linked-List Start
Address in
Command Packet
Pointer Register
First Command Packet
in Linked-List
Register information
copied to DMA Control
and Address Registers
DCPP points
to next command
packet
in Linked-List Second Command Packet
in Linked-List
Last Command Packet
in Linked-List
DCTL Register
DTBC Register
DLA Register
reserved
DVA Register
reserved
DCPP Register
reserved
rPN
DCTL Register
DTBC Register
DLA Register
reserved
DVA Register
reserved
DCPP Register
reserved
rPN
DCTL Register
DTBC Register
DLA Register
reserved
DVA Register
reserved
DCPP Register
reserved
rPN
r = reserved
P = processed bit
N = null bit
N = 1 for last command packet
Figu re 2. 14 : Command Packet Structu re and Linked List Operation
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In Step 1, the DGC S register is se t up: the CHAIN bit is set, VON and VOFF a r e programmed
with the appropriate values for controlling DMA VMEbus tenure, and the interrupt bits
(INT_STOP, INT_HALT, INT_DONE , INT_L ERR , INT_VE RR, and INT_P_ERR) are
programmed to enable generation of interrupts based on DMA termination ev ents. DMA
interrupt enable bits in the LINT_EN or VINT_EN bits should also be enabled as necessary
(“PCI Interrupt Generation” on page 2-63 and “VMEbus Inter rupt Generation” on page 2-65).
In Step 2, the linked-lis t struct ure is programmed with the required transf e rs. The actual
structur e may be set up at any time with command packet pointers pre-progra mmed and then
only the remaining DMA transfer elements nee d be programmed la ter. One common way is
to set up the command packets as a circular queue: each packet points to th e next in the list,
and the last points to the first. This allows continuous programming of the packets without
having to set-up or tear down packets later.
Step 1: Program DGCS
with tenure and interrupt
requirements
Step 4 : Set GO bit
Step 5 : Await termination
of DMA
Normal
Termination?
Yes
Step 2 : Set up linked-list
in PCI memory space
Step 3 : Clear DTBC
register, program DCPP
Done
handle error
No
Figure 2.15 : DMA Linked List Operation
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Once the structure for the linke d-list is established, the individual packets are progr ammed
with the appropriate source and destination addres ses, transfer sizes and attributes.
In Step 3, Clear the DTB C re gister and program the DCPP register to point to the fir st
command pack et in the list.
When using the DMA to perform linked-list transfers, it is important to ensure
that the DTBC register contains a value of zero before setting the GO bit of the
DGCS register. Otherwise, the DMA may not read the first command pac ket but
instead perform a direct mode transfer based on the contents of the DCTL,
DTBC, DLA, DVA and DGCS registers. After this direct mode transfer is
completed, the PROCESSED bit of the first command packet is programmed
with a value of 1 even though the packet was not actuall y processed. The DMA
continues as expected with the next command packet.
In Step 4, to start the linked-list transfer, set the GO bit in the DGCS register. The DMA will
first perform the transfe rs defined by the current contents of the DCTL, DTBC, DVA and
DLA regis te rs. Once that is complete it will then start the trans fers defined by the linked-lis t
pointed to in the D CPP register.
In Step 5, awa it and deal with termination of the DMA. Once the DMA channel is enabled, it
processes the first command packet as specifi ed by the DCPP register. The DMA transfer
regis ters are programmed by information in the command packets and the DMA transfer steps
along each command packet in sequence (see Figure 2.14 above). The DMA will terminate
when it:
• processes a command packet with the NULL bit set indicating the last pack e t of the
list,
• is stopped wit h the STOP_REQ bit in the DGCS regis ter,
• is halted with the HALT_REQ bit in the DGCS register, or
• encounters an error on either the PCI bus or VMEbus.
Each of these conditions will cause the AC T bit to clear, and a corresponding status bit to be
set in the DGCS register. If enabled in step 1, an interrupt will also be generated. Once the
software has set the GO bit, the soft wa re can monitor for DMA completion b y either waiting
for generation of an interrupt, by polling the status bits in the DGCS re gister , or by polling the
PROCESSED bits of the command pac kets. It is recommended tha t a background timer also
be initiated to time-out the transfer. This will ensure that the DMA has not been hung up by a
bus y VMEbus, or other such system issues.
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Linked- list operation can be halted by setting the HALT_REQ bit in the DGCS re gis ter
(Table A.55). When the HALT_REQ bit is set, the DM A ter minates when all transfers def ined
b y the curr ent command packet is complete. It then loads the ne xt c omma nd packet into its
registers. The HALT bit in the DGCS register is asserted, and the ACT bit in the DG CS
regis te r is cleared. The P ROCESSED bit in the linked-list is set to “1” approximately 1 µs
after the HA LT bit is se t: therefore after a DMA halt the user should wait at least 1 µs before
checking the status of the PROC ESSED bit.
The DMA can be restar ted by clearing the HALT status bit and setting the GO bit if desired
during the same re gister write. If the DMA is restarted, the ACT bit is set by the Universe II
and execution continue s as if no HALT had occurred: i.e., the Universe II processes the
current command packet (see Figure 2.14 above).
In contrast t o a halt, the DMA can also be immediately terminated through the ST OP_R EQ
bit. This will stop all DMA operation s on t he source bus imme diately, and set the ST OP bi t in
the same r e gis ter when the last piece of que ued da ta in the DMA FIFO has be en written to the
destination bus .
Once stopped, the D VA, DLA and DTBC registers contain values indicating the next
addres ses to rea d/write and the num ber of bytes rema ining in the transfer. Clearing the STOP
bit and setting the GO bit will cause the DMA to start up again fr om where it lef t of f,
including continuing with subsequent command packets in the list.
If the DMA is being stopped to insert a high priority DMA transfer, the remaining portion of
the DMA transfer may be stored as a new command packet inserted at the top of the linked
list. A new command packet with the attributes of the high priority transfer is then placed
before that one in the list. Now the linked list is set up with the high priority packet f irst,
followed be the rem ainder of the inte rrupted pack et, followed in turn b y the rest of the linked
list. Finally, the DTBC register is cleared and the DCPP programmed with a pointer to the top
of the lis t where the high priority command packe t has been placed. When the GO bit is set
(afte r clearing the STOP status bit in the DGCS register), the DMA will perf orm the transf ers
in the order set in the linked list. F or more details on updating the linked list see “Linked List
Updating” on page 2-91.
DMA transfers continue until the DMA encounters a command packet with the NULL bit set
to “1”, indicati ng that the last packet has been reached. At this point , the DMA stops, the
DONE bit is set, and the ACT flag is cleared. As it completes the transfers indicated by each
command packet, the DMA sets t he PROCESSED bit in that command packet before reading
in the next command packet and processing its contents.
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2.8 .3.1 L inke d L is t U pd a tin g
The Universe II provides a mechanism which allows the linked list to be updated with
additional linked list entries without halti ng or stopping the DMA. This takes place through
the use of a semaphore in the device: the UPDATE bit in the D_LLUE register (Table A.56).
This bit is meant to ensure that the DMA does not read a command packet into the DMA
registers while the command packet (outside the Universe II) is being updated. This
semaphore does not prevent external masters from updating the DMA registers.
Adding to a linked list begins by writing a “1” to the UPDATE bit . The DMA checks this bit
before proceeding to the next command packet. If the UPD ATE bit is “0”, then the DMA
locks the UPDATE bit against writes and proceeds to the next comma nd packet. If the
UPDATE bit is “1”, then the DMA waits until the bit is cleared before proceeding to the next
command packet. Therefore, setting the UPDATE bit is a me ans of stalling the DMA at
command packet boundaries while local logic updates the linked list.
In order to ensure that the DMA is not currently reading a command packet during updates,
the update logic must write a “1” to the UPDATE bit and read a value back. If a “0” is read
back from the UPDAT E bit, then the DMA is currently reading a command pac ket and has
locked the UPDAT E bit against writes. If a “1” is read back from the UPDATE bit, then the
DMA is idle or processing a transaction and command pac kets can be updated. If the DMA
attempts to proceed to the ne xt command packet during the update, it will encounter the set
UPDATE bit and wait until the bit is cleared.
If a set of linked command packets has already been created with empty packets at the end of
ne w transfers, adding to the end of the current linked list tak e s the following procedure:
1. Get UPDATE valid (write “1”, read back “1”),
2. Program a ttributes for new transfer in next available packet in list.
3. Change “null” pointer (on previous tail of linked list),
4. Release update (clear the UPDATE bit).
After updating the linked list, the DMA controller will be in three possibl e conditions:
1. It may be activ e and w orking its way through the l inked list. In this case, no further
steps are required.
2. The DMA may be idle (done) because it rea ched the final command packet. If a
full set of linked command packets had alre ady been created ahead of time, then
the DCPP re gister would point to the most recently programmed command packet,
and the DTBC re gis ter w ould be zero. The DMA can be started on the new packet
b y s imply cle aring the DONE bit and setting t he GO bit in the DGC S r egis te r. If a
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set of command packets had not been created ahea d of time, the DCPP register
may not be programmed to any v a lid pack et, and will need programming to the
ne wly programmed packet.
3. The DMA has encountered an error. In this circums tance, see “DMA Error Han-
dling” on page 2-96 for how to handle DMA errors.
Operation may be considerably simplified by ens uring that sufficient command pac kets have
been create d during system initia lization, probably in a ci rcular queue. In this fashion, when a
ne w en try is added to the list, it is simply a matter of progra mming the ne xt available entry in
the list with the new transfer attributes and changing the prev ious ly last packet's NULL bit to
zero. The DCPP re gis ter will be guaranteed to point to a v alid command pack et, so upon
updating the list, both ca ses 1 and 2 above can be covered by clearing the DONE bit and
setting the GO bit. T his will have no effect for case 1 since the DMA is still active, and w ill
restart the DMA for case 2.
If an err or has been encountered by the DMA (c ase 3) , se tting the GO bit and clearing the
DONE bit will not be sufficient to restart the DMA—the error bits in the DGCS regis ter will
also have to be clear ed before operation can continue.
2.8.4 FIFO Operation and Bus Ownership
The DMA uses a 256-byte FIFO. (The DMA FIFO is 64 bits wide). This supports high
performance DMA transfers. In general, the DM A r eads data from the s ource, and s tor es i t as
transactions in the FIFO. On the destination side, the DMA requests ownership of the master
and once granted begins transfers. T rans fers stop on the source side when the FIFO fills , and
on the destination side when the FIFO empties.
2.8.4.1 PCI to VMEbus Transfers
PCI to VMEbus transfers involv e the Uni verse II read ing from the PCI b us and writing to the
VMEbus.
The PCI bus is requested for th e current read once 128 bytes are a vai lable in the DMAFIFO.
The DMA Channel fills the DMAFIFO using PCI read transactions with each transaction
broken at address boundaries determined by the programmed PCI aligned burst size (PABS
field in the MAST_CTL register, Table A.81). This ensures that the DMA makes optimal use
of the PCI bus by always generating bursts of 32, 64 or 128 bytes with ze ro wait states.
The DMA packs read data into the DMAFIFO to the full 64-bit width of the FIFO,
independent of the width of the PCI bus , or the data width of the ensuing VMEb us trans action.
The PCI read transactions continue until either the DMA has completed the full programmed
tra nsfer, or there is insuffi cient room av aila ble in the DMAFIFO for a full transa ction. The
a vailable space required for anot her burst read transaction is again 128 b ytes. Since the
VMEb us is typically much s lower tha n the PCI b u s , the DM AFIFO may f ill frequently during
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PCI to VMEbus transfers, though th e depth of the FIFO helps to minimize this. When the
DMAFIFO fi lls, the PCI b us is free for other transactions (for example, between other devices
on the bus or possibly for use by the Universe II’s VMEbus Slave Channel). The DM A only
resumes read transactions on the PCI bus when the DMAFIFO has space for another aligned
b ur st si ze trans action.
Caution: The DMA may prefetch extr a read data from the external PCI target.
This implies that the DMA should only be used with memory on the PCI bus
which has no adve rse side-effects when prefe tched. The Univ erse II will
prefetch up to the aligned address boundary defined in the PA BS field of the
MASC_CTL register. On the VMEb us , the actual programmed number of bytes
in the DTBC register will be written. Prefetching can be avoided by
programming the DMA for transfers that terminate at the PABS boundary. If
further data is r equir ed be yond the boundary, but befor e the next boundar y , the
DTBC re gister may be programmed to eight byte trans fer s. The DMA will
fetc h the full eight bytes, and nothing more. Pro gr amming the DTBC to less
than eight bytes will still result in eight bytes fetc hed from PCI.
The DMA requests o wnership of the Universe II's VMEbus Master Interface once 64 bytes of
data hav e been queued in the DMAFIFO (see “VMEb us Request er” on page 2-6 on how the
VMEbus Master Interface is shared between the DMA, the PCI Target Channel, and the
Inte rrupt C hannel) . The Uni verse II maintains ownership of the Master Inter f ace until:
• the DMAFIFO is empty,
• the DMA block is complete,
• the DMA is stopped,
• a linked list is halted,
• the DMA encounters an error, or
• the DMA VMEb us tenure limit (VON in the DGCS register ).
The DMA can be programmed to limit its VMEbus tenure to fixe d block sizes using the VON
field in the DGCS register (Table A.55). With VON enabled, the DMA will relinquish
ownership of the Master Interf ace at defined address boundaries. See “DMA VMEb us
Ownership” on page 2- 81.
To further control the DMA’s VMEbus o wners hip, the VOFF timer in the DGCS regist er can
be used to program the DMA to remain off the VM Eb us for a specified period when VMEbus
tenure is relinquished. See “DMA VMEbus Ownership” on page 2- 81.
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The DMA Channel unpacks the 64-bit data queued in the DMAFIFO to whatever the
programmed transfer width is on the VMEbus (e.g. D16, D32, or D64). The VMEbus Master
Interf ace deli v ers the data in the DMAFIF O according to th e VMEb us c ycle type pr ogrammed
into the DCTL regi ster (Table A.50, see ““DMA Controller” on page 2-77). The DMA
provides data to the VMEbus until:
• the DMAFIFO empties, or
• the DMA VMEbus Tenure Byte Count (VON in the DMA_GCSR register,
Table A.55) expi res.
If the DMAFIFO empties, transfers on the VMEb us s top and, if th e cycle being generated is a
block transfer , then the block is terminated (AS* negated) and VMEbus ownership is
relinquished by the DMA. The DMA does not r e-request VMEb us owner ship until another
eight entries are queued in the DMAFIFO, or the DMA Channel has completed the current
Trans fer Block on the PCI bus (see “VMEbus Release” on page 2-8).
PCI b us trans acti ons are the full width of the PC I data b us with appropriate b yte lanes enabled.
The maximum VMEbus data width is programmable to 8, 16, 32, or 64 bits. Byte transfers
can be only of type DO8 (EO). Because the PCI bus has a more flexible byte lane enabling
scheme than the VMEbus, the Universe II may be required to generate a variety of VMEbus
transaction types to handle the byte resolution of the starting and ending addresses (see “Data
Trans fer” on page 2-39).
2.8.4.2 VMEbus to PCI Transfers
VMEb us to PCI transfe rs inv olve the Universe I I re ading from th e VMEbus a nd writing to the
PCI bus .
With DMA transfers i n this direction, the DMA Channel begins to queue data in the
DMAFIFO as soon as there is room f or 64 bytes in the DMAFIFO. When this watermark is
reached, the DMA will request the VMEbus (through the VMEb us Master Interface) and
begin reading data from the VMEbus. The Universe II maintains VMEbus ownership until:
• the DMAFIFO is full,
• the DMA block is complete,
• the DMA is stopped,
• a linked list is halted,
• the DMA encounters an error, or
• the VMEbus tenure limit is reached (VON in the DGCS regis te r).
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The DMA can be programmed to limit its VMEbus tenure to fixe d block sizes using the VON
field in the DGCS register (Table A.55). With VON enabled, the DMA will relinquish
ownership of the Master Interf ace at defined address boundaries. See “DMA VMEb us
Ownership” on page 2- 81.
To further control the DMA’s VMEbus o wners hip, the VOFF timer in the DGCS regist er can
be used to program the DMA to remain off the VM Eb us for a specified period when VMEbus
tenure is relinquished. See “DMA VMEbus Ownership” on page 2- 81.
Entries in the DMAFIFO are delivered to the PCI bus as PCI write transactions as soon as
there are 128 bytes a vailable in the DMAFIFO. If the PCI bus responds too slowly, the
DMAFIFO runs the risk of filling before write transactions can begin at the PCI Master
Interface. Once the DMAFIFO reaches a “nearly full” s tate (corresponding to three entries
remaining) the DMA requests tha t the VMEbus Master Interface complete its pending
operations and stop. The pending read oper ati ons typically f ill the DMAFIFO. Once the
pending VMEbus reads are completed (or the VON timer expires), the DMA relinquishes
VMEbus owner ship and only re-reques t s th e VMEbus Master Inter face once 64 bytes again
become available in the DMAFIFO. If the bus was released due to encountering a VON
boundary, the bus is not re-requested until the VOF F timer expires.
PCI b us trans acti ons are the full width of the PC I data b us with appropriate b yte lanes enabled.
The maximum VMEbus data width is programmable to 8, 16, 32, or 64 bits. Byte transfers
can be only of type DO8 (EO). Because the PCI bus has a more flexible byte lane enabling
scheme than the VMEbus, the Universe II may be required to generate a var iety of VMEbus
transaction types to handle the byte resolution of the starting and ending addresses (see
“Universe II as PCI Target” on page 2-38).
2.8.5 DMA In terrupts
The Interrupt C hannel in the Universe II handles a single interrupt sourced from the DMA
Channel which it routes to either the VMEbus or PCI bus via the DMA bits in the LINT_EN
and VINT_EN registers. There are six internal DMA sources of interrupts and the se are all
routed to this single interrupt. Each of these six sources may be individually enabled, and are
listed in Table 2.17 below. Setting the enable bit enables the corresponding interrupt source.
Table 2.17 : DMA Inte r rupt Sources and Enable Bits
In terrup t Source Enabl e Bit
Stop Request INT _STOP
Halt Request INT_HALT
DMA Completion INT_DONE
PCI Target -A bort or Master-A bort I N T _LERR
VMEb us Error INT_VERR
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Once an enabled DM A interrupt has occurred, regardless of whether the LINT_EN or
VINT_EN enabl e bits hav e been set, the corresponding DMA bit in the LINT_STAT
(Table A.58) and VINT_STAT (Table A.62) registers are set. Each one must be cleared
independently. Clearing one does not clear the oth er. See “Interrupt Handling” on page 2-68.
2.8.6 Interactions with Other Channels
This section describes the impact that the PCI Bus Target Channel and the VMEbus Slave
Channel may have on the DMA Channel.
The Universe II does not apply PCI 2.1 transaction ordering requirements to the DMA
Controller. That is, reads and writes through the DMA Controller can occur independently of
the other channels.
ADOH cycles and RMW cycles through the VMEbus Slave Channel do impact on the DMA
Channel. Once an external VMEbus master locks the PCI bus, the DMA Controlle r will not
perform transfers on the PCI bus until the Universe II is unlocked (see “VMEbus Lock
Commands (ADOH Cycles)” on page 2-18). When an external VMEbus Master be gins a
RMW cycle , at some point a read cycle will appear on the PCI bus. During the time betwee n
when the read cycle occur s on the PCI bus and when the associat ed write cycle occurs on the
PCI bus , no DMA trans fe rs will occ ur o n the PC I bus (see “V MEb u s Rea d-Modify -Write
Cycles (RMW Cycles)” on page 2-19).
If the PCI Target Channel locks the VMEbus us ing VOWN, no DMA transfers will take place
on the VMEbus (see “Using the VOWN bit” on page 2-48).
2.8.7 DM A Error Handlin g
This section describes ho w the Uni v erse II responds to errors in v olving the DM A, and ho w the
user can recov er from them. As described below, the software source of a DMA error is a
protocol, and the hardware source of a DMA error is a VMEbus error , or PCI bus Target-Abort
or Ma ster-Abort.
P rotocol Erro r INT _M_ERR
Table 2.17 : DMA Inte r rupt Sources and Enable Bits
In terrup t Source Enabl e Bit
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2.8.7.1 DMA Software Response to Err or
While the DMA is operating norma lly, the ACT bit in the DGCS re gis ter will be set
(Table A.55). Once the DMA has termin ated, it will clear this bit, and se t one of six status bits
in the same register. The DONE bit will be set if the DMA completed all its programmed
operations normally. If the user interrupted the DMA, either the STOP or HALT bits will be
set. If an error has occurred, one of the remaining three bits, LERR, VERR, or P_ERR, will
be set. All six forms of DMA terminations can be optionally set to generate a DMA interrupt
b y setting the appropria te enable bit in the DGCS regis te r (s ee “DMA Interr upts” on
page 2-95).
• LERR is set if the DMA encounters an error on the PCI b us: either a Master-Abort or
Target-Abort. Bits in the PCI_CSR register will indicate which of these conditions
caused the error.
• VERR is set if the DMA encounters a bus error on the VMEbus. This will be
exclus ively through a detected assertion of BERR* during a DMA cycle.
• P_ERR is set if the GO bit in the DGCS register is set to sta rt the DMA, and the
DMA has been improperly program med either because the BM bit in th e PCI_CSR
disables PCI bus mastership, or the source and destinatio n start addresses are not
aligned (see “Source and Destination Addresses” on page 2-78).
Whether the error occurs on the destination or source bus, the DMA_CTL register contains
the a ttributes relevant to the particular DMA transaction. The DTBC register provides the
number of bytes remaining to transfer on the PCI side. The DTBC regi ster contains valid
values after an error. The DLA and DVA registers should not be used for error recovery.
2.8.7.2 DMA Hardwa re Respons e to Error
This section describes ho w transfers proceed following a b us error, and how interrupts can be
generated following DMA error conditions.
When the err or condition (VMEbus Error, Target-Abort, or Master-Abort) occurs on the
source bus while the DMA is reading from the source bus, the DMA stops reading from the
source b us . An y data pre vious ly queued within the DMAFIFO i s written to the destination
b us . Once the DMAFIFO empties, the err or status bit is set and the DMA generates an
interrupt (if enabled by INT_LERR or INT_VERR in the DGCS re gis ter—see “DMA
Interrupts” on page 2-95).
When the err or condition (VMEbus Error, Target-Abort, or Master-Abort) occurs on the
destination bus while the DMA is writing data to the destinat ion bus , the DMA stops writing
to the destination b us, and it also stops reading from the source b us. The error bit in the DGCS
register is set and an interrupt asserted (if enabled).
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Interru p t Generation During Bus Errors
To generate an interrupt from a DMA error, th ere are two bits in the DGCS register (and one
bit each in the VINT_EN and LINT_EN re gis ters). In the DGCS register the INT_LERR bit
enables the DMA to generate an interrupt to the In terrupt Channel after encount ering an error
on the PCI bus. The INT_VERR enables the DMA to generate an interrupt to the Interrupt
Channel upon encountering an error on the VMEbus. Upon reaching the Interrupt Channel, all
DMA interrupts can be r outed to either the PCI bus or VMEbus by setting the appropriate bit
in the enable registers. All DMA sources of interrupts (Done, Stopped, Halted, VMEbus
Error, and PCI Error) constitute a single interrupt into the Interrupt Channel.
2.8.7.3 Resuming DMA Transfers
When a DMA error occurs (on the source or destination bus), the user should r ead the status
bits and determine the source of the error. If it is poss ible to resume the transfer, the transfer
should be resumed at the addr ess that was in place up to 256 b ytes from the current byte count.
The original addresses (i.e., DLA and DVA) are required in order to resume the transfer at the
appropriate location. However, the value s in the DLA and the DVA registers should not be
used to reprogram the DMA, because they are not v alid once the DMA begins. In di rect mode,
it is the user’s responsibility to record the ori ginal state of the DVA and DLA registers for
error recov ery. In Link ed-List mode, the user can refer to the current Command P a cket stored
on the PCI bus (whos e location is specif ied by the DC PP register) for the location of the DVA
and DLA in formation.
The DTBC reg ister contains the number of bytes remaining to transfer on the source si d e . The
Univ erse II does not store a count of bytes to transfer on the destination side. If the error
occurred on t he source side, then the location of the error is simply the latest source address
plus the byte count. If the err or occured on the destination si de, then one cannot infer
specifically where the error occurred, because the b yte count only refers to t he number of data
queued from the source, not what has been written to th e destination. In this case, the error
will have occurred up to 256 bytes before: the original address plus the byte count.
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Give n this background, the following procedure may be implemented to recover from errors.
1. Read the value contained in the DTBC register.
2. Read the record of the DVA and DLA that is stored on the PCI bus or elsewhere
(not the value stor ed in the Universe I I registers of the same na me, see above).
3. If the difference between the v alue contained in the DTBC register and the original
value is less than 256 bytes (the FIFO depth of the Uni verse II), reprogram all the
DMA regis te rs with their original values.
4. If the difference between the v alue contained in the DTBC register and the original
value is greater than 256 bytes (the FIFO depth of the Uni verse II), add 256 (the
FIFO depth of the Universe II) to the v alue contained in the DTBC register.
5. Add the dif fer ence between the original value in the DTBC and the ne w value in
the DTBC regis te r to the original value in the DLA register.
6. Add the dif fer ence between the original value in the DTBC and the ne w value in
the DTBC register to the original value in the DVA register.
7. Clear the status flags.
8. Restart the DMA (see “ DMA Initiation” on page 2-80).
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2.9 Registers
This section is or ganized as follows:
• “Ov ervie w of Uni verse II Registers” on page 2-100,
• “Regis ter Access from the PCI Bus” on page 2-101,
• “Regis ter Access from the VMEbus” on page 2-104,
• “Mailbox Registers” on page 2-108, and
• “Semaphores” on pa ge 2-109
2.9.1 Overview of Universe II Registers
The Universe II Control and Status Registers (UCSR) occupy 4 Kbytes of internal memory.
This 4 Kbytes is logi cally di vi ded into three groups (see Figure 2.16 below) :
• PCI Configuration Space (PCICS) ,
• Universe II Device Sp ecific Registers (UDSR), and
• VMEb us Control and Status Re gis ters (VCSR).
The Universe II regis ters are little-endian.
The access mechanisms for the UCSR are diff erent depending upon whether the re gister space
is accessed f rom the PCI bus or VMEbus . Register access f rom the PCI bus and VMEbus is
discussed below.
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2.9.2 Register Access from the PCI Bus
There are two mechanisms to access the UCSR space from the PCI bus: through
Configuration space or through PCI Memory or I/O space (Table A.6).
Figure 2.16 : Uni vers e II Con trol and Status Register Space
PCI CONFIGURATION
SPACE
(PCICS)
UNIVERSE DEVICE
SPECIFIC REGISTERS
(UDSR) 4 Kbytes
VMEbus Configuration
and Status Registers
(VCSR)
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2.9.2.1 PCI Configu ration Access
When the UCSR space is accessed as Configuration spac e, it means that the access is
e xternally decoded and the Uni v erse II is notified via IDSEL (much like a standard chip select
signal). Since the re gister locat ion is encoded by a 6-bit register number (a v alue used to index
a 32-bit chunk of Configuration space), only the lower 256 b ytes of the UCSR can be accessed
as Configur ation space (this corresponds to the PCICS in the UCSR space, see Figure 2.17 on
page 2-102). Thus, only the PCI configuration registers are accessible through PCI
Configur ation cycles.
PCI CONFIGURATION
SPACE
(PCICS)
UNIVERSE DEVICE
SPECIFIC REGISTERS
(UDSR) All 4 Kbytes
Accessible as
Memory or I/O
Space
4 Gbytes
of Memory
or I/O Space
PCI_BS
Accessible
through PCI
Configuration
Cycle
VMEbus Configuration
and Status Registers
(VCSR)
Figure 2.17 : PCI Bus Access to UCSR as Memory or I/O Space
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2.9.2.2 Memory or I/O Access
Exactly two 4-Kbyte ranges of addresses in PCI Memory space and/or PCI I/O space can be
dedicated to the Uni verse II regis ters. The Universe II has two programmable regis ters
(PCI_BS0 and PCI_BS1) that each specify the base address and address space for PCI access
to the Universe II’s registers. The PCI_BSx registe rs can be programmed through PCI
Configuration space or through a VMEbus access, to make the Universe II registers available
anywhere in the 32-bit Memor y space and in I/O space (as offsets of the BS[31:12] field i n
PCIBSx).
The SPACE bit of the PCI_BSx register s specifies whether the address lies in Memory space
or I/O space. The SPACE bit of these two re gisters are read-only. There is a power- up option
that determines the value of the SPACE bit of the PC I_BSx r egis ters. At power- up the SPACE
bit of the PCI _BS1 regis ter is the ne gation of the SPACE bit of the PCI_BS0 register.
• When the VA[1] pin is sampled low at power-up, the PCI_BS0 register’s SPACE bit
is set to “1”, which signifies I/O space, and the PCI_BS1 register’s SPACE bit is set
to “0”, which signifies Memory space.
• When VA[1] is sampled high at power-up, the PCI_BS0 register’s SPACE register’s
bit is set to “0”, which signifies Memory space, and the PCI_BS1 register’s SPACE
bit is set to “1”, which signifies I/O space.
Universe II registers are not prefetchable. The Universe II does not accept b urst writes to its
registers.
Eliciting Conditions of Target-Retry
Attempts to acce ss UCSR spa ce from the PCI bus will be retried by the Universe II under the
following conditions:
• While UC SR space is being access ed by a VMEbus master, PCI maste rs will be
retried.
• If a VMEb us maste r is perf orming a RMW access to the UCSRs then P CI attempts to
access the USCR space will resu lt in a Target-Retry until AS* is neg ated.
• If the Universe II registers a re accessed through an ADOH cycle from the VMEbus,
any PCI attempt to access the UCSRs will be retried until BBSY* is negated.
2.9.2.3 Lockin g the Register Block from the PCI bus
The Universe II regist ers can be locked by a PCI master by using a PC I locked transaction.
When an external PCI master locks t he register block of the Universe II, an access to the
regis te r block from the VMEbus will not terminate with the assert ion of DTACK* until the
regis ter block is unlocked. Hence a prolonged lock of the re gister block b y a PCI resou rce may
cause the VMEbus to timeout with a BER R*.
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2.9.3 Register Access from the VMEbus
There are two mechan isms to ac cess the UCSR spac e from the VMEbus. One method uses a
VMEbus Regis ter Acces s Ima ge (VRAI) which allows the use r to put the UCS R in an A16,
A24 or A32 address space. The VRAI approach is useful in systems not implementi ng
CR/C SR space as defined in the VME64 specification. The other way to acce ss th e UCSR is
as CR/CSR space, where each slot in the VMEbus system is assigned 512 Kbytes of CR/CSR
space.
Each method i s discussed belo w.
2.9.3.1 VMEbus Register Access Image (V RAI)
The VMEbus register access image is defined by the following register fields:
The VMEb us Regi ster Access Image occupies 4 Kbytes in A16, A24 or A32 space (depending
upon the programming of the address space described in Tab le 2.18 abov e, see Figure 2.18
belo w). All registers are accessed as address of fsets from the VRAI base address programmed
in the VRAI_BS register (Table A.104). The image c an be enabled or disabled using the EN
bit in the VRAI _CTL register (Table A. 103).
Note that the VRAI base address can be configured as a power-up option (see “Power-up
Option Descriptions” on page 2-117).
Table 2.18 : Programming the VMEbus Register Access Image
Field Register Bits Description
address space VAS in Table A.103 one of A16, A24, A32
base address BS[31: 12] in Tab le A.104 l ow est ad dress in the 4Kbyte slave image
slave image en able EN in Table A.103 enables VMEbus register access im age
mod e SUPER in Table A.103 Supervisor and/or Non-Privileg ed
type PGM in Table A.103 Progr am and/o r Data
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Figure 2.18 : UCSR Access from the VMEbus Register Access Image
PCI CONFIGURATION
SPACE
(PCICS)
VMEbus Configuration
and Status Registers
(VCSR)
UNIVERSE DEVICE
SPECIFIC REGISTERS
(UDSR) 4 Kbytes
of UCSR
Total Memory
in A16, A24 or A32
Address Space
VRAI_BS
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2.9.3.2 CR/CSR Accesses
The VME64 specification assigns a total of 16 Mbytes of CR/CSR space for the entire
VMEbus syste m. The CR/CSR image is enabled with the EN bit in the VCSR_CTL register
(Ta ble A.105). This 16 Mbytes is broken up into 512 Kbytes per slot for a total of 32 slots.
The first 512 Kbyte block is reserved for use by the Auto-ID mechanism. The UCSR space
occupies the upper 4 Kbytes of the 512 Kbytes a vailable for its slot position (see Figure 2.19
below ). The base addre ss of the CR/CSR space all ocat ed to the Universe II’s slot i s
programmed in the VCSR_BS register (Table A.127). F or CSRs not supported in the Universe
II and for CR accesses, the LAS field in the VCSR_C TL registe r spec ifies the PCI bus
command that is generated when the cycle is mapped to the PCI bus. There is also a
translation offset added to the 24-bit VMEbus address to produce a 32 -bit PCI bus address
(programmed in the VCSR_TO register, Table A.106).
Note that the re gisters in the UCSR space are locat ed as address of fsets from VCSR_BS.
These offsets are different from those used in the VRAI mechanisms, where the first register
in the UCSR has address offset of zero (see Table A.1 in Appendix A). When accessing the
UCSR in CR/CSR space, the first register will have an address offset of 508 Kbytes (512
Kbytes minus 4 Kbytes). A simple approach for determining the register offset when
accessing the UCSR in CR/CSR space is t o add 508 Kbytes (0x7F000) to the address offsets
giv en in Table A.1.
2.9.3.3 RMW and ADOH Regis ter Access Cycles
The Univ er se II supports RMW and ADOH accesses to its re gis ters.
A read-modify-write (RMW) c ycle allows a VMEbus master to read from a VMEbus slav e
and then write to the same resource without relinquishing VMEb us tenure between the two
operations. The Universe II accepts RMW c ycles to any of its registers. This prevents an
e xternal PCI Master from accessing the re gis ters of the Univ erse II until VMEb us AS* is
asserted. This is useful if a s ingle RMW access to the ADHO is required.
If a sequence of accesses to the Univ erse regi sters must be performed without interv ening PCI
access to UCSR is re quired, then the VMEb us master should lock the Uni verse II through the
use of ADOH. This prevents an e xternal PCI Master from accessing the re gisters of the
Universe II until VMEb us BBSY* is ne gate d. It also prev ents other VMEbus masters from
acce ssing t he Universe I I register s.
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Figure 2.19 : UCSR Access in VMEbus CR/CSR S pace
PCI CONFIGURATION
SPACE
(PCICS)
UNIVERSE DEVICE
SPECIFIC REGISTERS
(UDSR) 4 Kbytes
of UCSR
Mapped
to
PCI
512 Kbytes
of VMEbus
CR/CSR Space
(Portion of 16 Mbyte
Total for Entire
VMEbus System)
VCSR_BS
VMEbus Configuration
and Status Registers
(VCSR)
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2.9.4 Mailb ox Registers
The Uni verse II has four 32-bit m ailbox re gis ters which provide an additional communication
path between the VMEbus and the PCI bus (see Table A.75 to Table A.78). The mailbox es
support read and write accesses from either b us, and may be enabled to generate interrupts on
either bus when they are wr itten to . The mailboxes are accessibl e from the same address
spaces and in the same manner as the other Unive rse II registers, as described above.
Mailbox registers are useful for the communication of concise command, status, and
parameter data. The specif ic uses of mailbox es depend on the application. For example, they
can be used when a mas ter on one bus needs to pass inf ormation (a mes sage) on the other bus,
without knowing where the information should be stored in the other bus’s address space. Or
the y can be used to store the address of a longer message written by the processor on one bus
to the address space on the other bus , thro ugh t he Uni v erse II . They can also be used to initiate
larger transfers through the FIFO, in a user-defined manner.
Often users will enable and map mailbox interrupts, so that when the processor writes to a
mailbox from one bus, the Universe II will interrupt the opposite bus. The interrupt service
routine on the opposite bus would then cause a read from this same mailbox.
Reading a mailbox cannot automatically trigger an interrupt. Ho wev er, a similar effect can be
achieved by reading the mailbox and then triggering an interrupt through hardware or
software. Or one may use a “polling” approach, where one designates a bit in a mailbox
regis ter to indicate whether one has read from the mailbox.
For details on how the mailbox interrupts a re enabled and mappe d, see “Interrupt Handling”
on page 2-68 and “Mailbox Register Access Interrupts” on page 2-75.
Applications will sometimes designate two mailboxes on one interface as being read/write
from the PCI b us, and read-only from the VMEb us, and the two other mailboxes as read/write
from the VMEbus and read-only from the PCI bus. This eliminates the need to implement
locking. The Universe II provides semaphores w hich can be also be used to synchronise
access to the mailboxes. Semaphores are described in the next section.
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2.9.5 Semaphores
The Universe II has two general-purpose semaphore registers each containing four
semaphores. The registers are SEMA0 (Tab le A.79) and SEMA1 (Table A.80). To gain
ownership of a semaphore, a process writes a logic one to the semaphore bit and a unique
pattern to the associated tag field. If a subsequent read of the tag field returns the same
pattern, the process can consider itself t he owner of the semaphore. A process writes a value
of 0 to the semaphore to release it.
When a semaphore bit is a va lue of 1, t he associated tag f ield cannot be updated. Only when a
semaphore is a value of 0 ca n the associated tag field be updated.
These semaphores allow the user to share resources in the system. While the Universe II
provi des the semaphor es, it is up to the user to determine access to which part of the system
will be controlled by semaphores, and to design the system to enforce these rules.
An example of a use of the semaphore inv olves g ating access to the Sp ecial Cycle Generator
(page 2-45). It may be necessary to ensure th at while one process uses the Special Cycle
Generator on an address, no other process accesses this address. Before performing a Special
Cycle, a process would be required to obtain the semaphore. This process w ould hold the
semaphore until the Special Cyc le completes. A separate process that intends to modify the
same address would need to obtain the semaphore before proceeding (it need not v erify the
state of the SCYC[1:0] bit). This mechanism requires that processes know which addresses
might be accessed through the Special Cycle Generator.
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2.10 Uti lity Functions
This section discusses miscellane ous utility functions that are prov ided by the Uni verse II,
including:
• “Resets” on page 2-110,
• “Power-Up Options” on page 2-115,
• “Hardwa re Initialization (N ormal Operating Mode)” on page 2-121,
• “Test Modes” on page 2-122, and
• “Clocks” on page 2-123.
2.10.1 Resets
This section is divided in three sections. The fi rst section lists the pins and re gis ters that are
involved in the reset circ uitry. The second section presents and explains the reset c ircuitry
diagram. The thir d section pro vides important s uggestions and w arnings about conf iguring the
Univ er se II re s et ci rc uitry.
2.10.1.1 Overview of Reset Support
The Univ erse II pro vides a number of pins and registers for reset support. Pin support is
summarized in Table 2.19.
Table 2.19 : Hardware Reset Mechanism
Interfac e and
Direction Pi n Name Long Name Effec tsa
a. A m ore detailed account of the effects of r eset signals is provided in “R eset Implementat ion Caut ions” on pag e 2-114
VMEbus Inpu t VRSYSRST# VMEbus Reset Input Asserts LRST# on t he local bus , reset s the Univer se II,
and reconfigures pow er-up options.
VMEbus Outp ut VXS YS RST VMEbus System Reset Univ erse II out put for SYSRST* (resets the VMEbus)
PCI Input PWRRST# Power -up Rese t Resets the Universe II a nd reconfigures pow er-up
options.
RST# PCI Reset Input Resets the Universe II fr om the PCI bus.
VME_RESET# VMEbu s Reset
Initiator Causes Universe II to assert VXSYSRST
PCI Outpu t LRST# PCI Bus Reset Output Resets PCI resources
JTAG Input T RST# JTAG Test Rese t Provides asynchronous init ializati on of th e TA P
controller in the Universe II.
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The Uni verse II is only r e set through hardware. Sof twar e can only make the Universe II asser t
its reset outputs. In order to reset the Universe II through software, the Universe II reset
outputs must be connected to the Universe II reset inputs. For example, the SW_LRST bit in
the MISC_CTL register, which asserts t he LRST# output, wi ll not reset the Univ erse II itself
unless LRST# is looped back to RST#. As descri bed in “Reset Implementation Cautions” on
page 2-114, there are potential loopback configurations resulting in permanent reset.
Table 2.20 : Software Reset Mechanism
More detailed information about the effects of vario us reset events is provided in the next
section.
Register and
Table Name Type Function
MISC_CTL
Table A.82 SW_LRST W Softw are PCI Reset
0=No effect, 1=Initiate LRST #
A read always returns 0.
SW_S Y SR ST W Software VMEbus SYS RESET
0=No effect, 1=Initiate SYSR ST*
A read always returns 0.
VCSR_SET
Table A.126 RESET R/W Board Reset
Reads: 0=LRST# not ass erted, 1=LRST# ass e r ted
Write s: 0=n o effect, 1=assert LRST#
SYSFAIL R / W VMEbus SYSFAIL
Reads: 0=VXSYSFAIL not asserted, 1=VXSYSFAIL asserted
Writes:0=no effect, 1=assert VXSYSFAIL
VCSR_CLR
Table A.125 RESET R/W Board Reset
Reads: 0=LRST# not ass erted, 1=LRST# ass e r ted
Wr ites : 0=n o effect, 1=negate LRST #
SYSFAIL R / W VMEbus SYSFAIL
Reads: 0=VXSYSFAIL not asserted, 1=VXSYSFAIL asserted
Writes:0=no effect, 1=negate VXSYSFAIL
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2.10.1.2 Univ erse II Reset Circ uitry
Table 2.21 below shows how to res et various aspects of the Uni verse II. F or example, it shows
that in order to reset the clock se rvices (SYSCLK, CLK64 enables, and PLL divide r),
PWRRST# should be asserted. If the table is read from left to right, it indicates the effects of
various reset s ource s. Not ice that PWR R ST# r esets all aspects of Universe II listed in co lumn
1 of Table 2.21. Table 2.21 also indicates the reset effects that are extended in ti me. F or
e xample, VXSYSRST# remains asserted for 256 ms after all initiators are removed—this
satisfies VMEbus rule 5.2 (mini mum of 200 ms SYSRST *). The external 64 MHz clock
controls this assertion time. LRST# is asserted for 5 ms or more from all sources except
VRSYSRST #. The same information is present ed in pictorial format in Figure 2.20.
Table 2.21 : Functions Affected by Reset Initiatiors
Effect of Reseta,b
a. On PW RRST #, opti on s ar e l oad ed from pins . On SY SRST a nd RST#, o pti on s ar e l oaded f rom valu es t hat were lat c hed at t he
pre vious PW RRST#.
b. Refer to Appe ndix- A to find the effects of various re set events
Reset Source
Clock Services
SYSCLK
CLK64 enables
PLL Divider
PWRRST#
VMEbus Services
VMEbus Arbiter
VMEbus Time r
VCSR Registers
PWRRST#, or
VRSYSRST#
Genera l Servi ces
Most registers
Intern a l stat e m ac h in es
PWRRST#,
RST# or
VRSYSRST#
Power-Up and Reset State Machi ne
Power-up the device
Reset Register s
PWRRST#, or
VRSYSRST#
VMEbus Reset Output
VXSYSRST# (asserted for more than 200 ms ) PWRRST#, or
VME_RESET# , or
SW_SYSRST bit in MISC_CTL register
PCI Bus Reset Ou tput
LRS T# (asserted for at least 5 ms ) PWRRST#, or
SW_LRST bi t in MI SC_CTL register, or
RESET bit i n VCSR_SET registerc
c. LRST# may be cl eared by writing 1 to the RESET bit in the CSR_CLR register.
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VME Services
Clock Services
General Services
Power-Up and Reset State Machine
> 200ms
>= 5ms
PWRRST#
VRSYSRST#
RST#
VME_RESET#
MISC_CTL Register
SW_SYSRST
SW_LRST
VCSR_CLR and
VCSR_SET Registers
RESET LRST#
VXSYSRST#
VOE#
(Power-up, reset registers, assert VOE#)
(VME Arbiter, VMEbus timer, VCSR registers)
(SYSCLK, CLK64 enables, PLL divider)
(Most Registers, internal state machines)
hold for
hold for
Figure 2.20 : Reset Circuitry
Note 1: On PWRRST#, options are loaded f rom pins. On SYSR ST and R ST#, opt ions
are loaded from values that were latched at the previous PWRRST#.
Note 2: R efer to Appendix-A to find the effects of various reset events.
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2.10.1.3 Reset Implementation Cautions
To pre vent the Univ erse II from reset ting the PCI bus, the LRST# output may be left
unconnected. Otherwise, LRST# should be grouped with other PCI reset generators to assert
the RST# signal such that :
RST# = LRST# & reset_source1 & reset_source2 &...
If the Univ erse II is the only initiator of PCI reset, LRST# may be dir e ctly connected to R ST #.
Assertion of VME_RESET# causes the Uni verse II to assert VXSYSRST#.
Caution: Since VME_RESET# causes assertion of SYSRST*, and since
SYSRST* causes assertion of LRST#, tying both VME_RESET# and LRST# to
RST# will put the Universe II into permanent reset. If VME_RESET# is to be
driven by PCI reset logic, ensure that the logic is designed to break this
feedback path.
The PWRRST# inpu t keeps the Uni v erse II in r eset unti l the po wer supply has r eached a stable
level (see Table 2.21). It should be h eld asserted for over 100 milliseconds after po wer is
stable. Typica lly this can be achieved through a resistor/capacitor combination (see
Figure 2.21); ho wever, a more reliable solution usi ng under voltage sensing circuits (e.g.
MC34064) is common.
The Universe II supports the VMEbus CSR Bit Clear and Bit Set registers (Table A.125 and
Table A.126). The VCSR_SET registers allows the user to assert LRST# or SYSFAIL by
writing to the RESET or SYSFAIL bits, respectively. LR ST# or SYSFAIL remains asserted
until the corr esponding bit is cleared in the VCSR_CLR re gister. The FAIL bit in each of these
registers is a status bit and is set by the software to indicate board failure.
!
Figure 2.21 : Resistor-Capacitor Circuit Ensuring Power -Up Reset Duration
PWRRST#
47 K
10µF
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2.10.2 P ower-Up Options
The Universe II may be automatically configure d at power-up to ope rate in different
functional modes. These power -up options allow t he Uni verse II to be set in a particular mode
independent of any local intelligenc e. The Uni verse II power -up options are listed in
Table 2.22 and described below.
The majority of the Universe II power- up options (listed below) are loaded from the VMEb us
address and data l ines after an y PWRRST#. There are two po wer-up options that are not
initiated by PWRRST#. The f ir st of these is PC I bus width ( a power- up option required by the
PCI bus specif ication), and this is loaded on an y RST# event from the REQ64# pin. The
second special power - up option is VMEbus SYSCON enabling, required by the VMEbus
specif ication. The SYSCON option is loaded during a SYSRST* e vent from the BG3IN*
signal.
All power-up options are latched from the state of a particular pin or group of pins on the
rising edge of PWRST#. Each of these pins except REQ64# has a weak internal pull-down to
put the Universe II into a default conf iguration. (REQ64# has an internal pull-up). If a
non-default configuration is required, a pull-up of approximately 10k Ω (or activ e drive) is
required on the signal. See “PCI Bus Width” on page 2-119 and the VMEbus Specification
concerning Auto-Syscon Detect for the exc eptions to the rule described in this paragraph.
The Univer se II may be restored to the state it was in immediately f ollowing the pre vious
power -up without re-asserting PWRRST#: after SYSRST* or RST# ( with PWRRST #
ne gated), the values that were origi nally latched at the rising edge of PWRRST# will be
reloaded into t he Universe II (except for PCI bus width and VMEb us SYSCON enabling,
which are loaded from their pins).
Table 2.22 li sts the power-up options of the Universe II, the pins which determine the options,
and the regis ter settings that are set by this option. Each option is described in more detail in
“Power-up Option Descriptions” on page 2-117.
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Table 2.22 : Po wer-Up Optionsa
a. All power -up o ptions are latched only at the rising-edg e of PW RRST#. They a re loaded when PWRRST#, SYSRST*
and RST# are negated.
Option Register Field Default Pins
VMEbus Regi ster Ac cess Sl ave Image VRAI_CTL EN disabled VA[31]
VAS A16 VA[30:29]
VRAI_BS BS 0x00 VA[28:21]
VMEb us CR/ CSR sla ve image VCSR_CTL LAS[0]b
b. The LAS fiel d w ill enable the PC I_CSR register’s MS or IO S f ield if the EN FIELD of the LS IO_CTL register is set.
memory VA[20]
VCSR_TO TO 0x00 VA[19:15]
Auto-ID MISC_STAT DY4AUTO disabled VD[30]
MISC_CTL V64AUTO disabled VD[29]
VINT_EN SW_INT 0
VINT_STAT SW_INT 0
VINT_MAP1 SW_INT 000
BI-ModeMISC_CTL BI disabled VD[28]
Auto-Syscon Detect MISC_CTL SYSCON enabled VBGIN[3]*
SYSFAIL* Asserti on VCSR_SET SYSFAIL asserted VD[27]
VCSR_CLR SYSFAIL
PC I Ta rg e t Im a g e LSI0_CTL EN disabled VA[13]
LAS[0] memory VA[12]
VAS A16 VA[11:10]
LSI0_BS BS 0x0 VA[9:6]
LSI0_BD BD 0x0 VA[5:2]
PCI Register Access PCI_BS0,
PCI_BS1 SPACE See Table A.6 and
Table A.7 VA[1]
PCI Bus Sizec
c. The PCI Bus Size is loaded on any RST# event, as per the PCI 2.1 Specification.
MISC_STAT LCLSIZE 32-bit REQ64#
PCI CSR Image Space PCI_CSR BM disabled VA[14]
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2.10.2.1 Power-up Option Descriptions
This section describes each of the groups of power-up options that were lis ted in Table 2.22.
VMEbus Register Acces s Im age
The Univer se II has se veral VMEb us slav e images, each of which may provide a different
mapping of VMEb us cycles to PCI c ycles. All VMEb us sla v e images are conf igurable through
a set of VMEbus slave regis ters: VSIxCTL, VSIx_BS, VSIx_BA, and VSIx_IO. No VMEb us
to PCI transaction is pos sible until these regis ters are program med .
The VMEbus Re gister Access Image (VRAI) po wer - up option permits access from the
VMEbus to the Universe II internal registers at power-up. The pow er-up option allows
programming of the VMEb us register slave image address space and the upper fi ve bits of its
base address ; all othe r bits will be z ero (s ee Table 2.23 below). Once access is provided to the
registers, then all other Universe II feature s (such as fur ther VMEbus slave images) can be
configured from the VMEbus.
Table 2.23 above shows how the upper bits in the VRAI base address are programmed for
A16, A24, and A32 VMEbus register acces s ima g es.
VMEbus CR/CSR Slave Image
CR/CS R space is an address space introd uced in the VME64 specif ication. The CR/CSR
space on any VMEbus device is 512 Kbytes in size: the upper region of the 512 Kbytes
dedicated to register space, and the lower region is dedicated to configuration ROM. The
Univ erse II m aps its internal re gisters to the upper region of t he CR/CSR s pace, and passes all
other accesses through to the PCI bus (s ee “Registers” on page 2- 100).
The VMEbus CR/CS R Slav e Image po wer - up option maps CR/CSR accesses to the PCI bus.
CR/CSR space can be mapped to memory or I/O space with a 5-bit offset. This allo ws
mapping to an y 128Mb yte page on the P CI b us. As part of t his implementation, ensure that the
PCI Ma ster Interface is enabled through the MAST_EN bit power-up option (see below) or
configured through a register access before accessing configuration ROM.
Table 2.23 : VRAI Base Address Power-up Options
VRAI_CTL: VAS BS [31:24] BS [23:16] BS [15:12]
A16 0 0 Power-up Option VA [28:25]
A24 0 Pow e r-up Option VA [28:21] 0
A3 2 Powe r-u p O ption VA [2 8 : 21 ] 0 0
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Auto-ID
There are two Auto-ID mechanisms pro vided b y the Universe II. One is the VME64 specified
ve rsion which relies upon use of the CR/CSR space for configur ation of the VMEbus system,
and a Tundra proprietary system which uses the IACK daisy chain for identifying cards in a
system . Either of these mechanisms can be enabled at power-up (see “Aut omat ic Slot
Identification” on page 2-24).
Because VME64 Auto-ID relies upon SYSFAIL to operate correctly, this power-up option
over rides the SYSFAIL power-up option described below.
BI-Mode
BI-Mode (Bus Isolation Mode) is a mechan ism for logi cally isolating the Uni verse II from the
VMEbus for diagnostic, maintenance and failure recov ery purposes. BI-Mode may be enabled
as a power-up option (see “BI-Mode” on page 2-28). When the Universe II has been
powered-up in BI-Mode, then any subsequent SYSRST* or RST # restores the Universe II to
to BI-Mode,
Auto-Syscon Det ect
The VMEbus SYSCON enabling, required by the VME bus specification, is a special
power -up option in that it does not return to its after -po wer-up state following RST# or
SYSRST#.The SYSCON option is loaded during a SYSRST* event from the VBG3IN*
signal.
SYSFAIL* Assertion
This power-up option caus es t he Univ erse I I to as sert SYSFAIL* immediately upon entry int o
reset. The SYSFAIL* pin is released through a register access. Note that this power-up option
is ov e r - ridden if VME64 Auto-ID has been enabled. This option w ould be used when
e xtensiv e on-board diagnostics need to be performed before release of SYSFAIL*. After
completion of diagnostics, SYSFAIL* may be released through software or through initiation
of the VME64 Auto-ID sequence if that mechanism is to be used (see “Auto Slot ID: VME64
Specified” on page 2-24).
PCI Target Image
The PCI Target Image power-up option provides for default enabling of a PCI targe t image
(automatically mapping PCI cycles to the VMEb us ). The default tar get image can be mapped
with base and bounds at 256MB resol ution in Memory or I/O space, and map PCI transactions
to different VMEb us address spaces. Beyond the settings provided for in this po wer- up option,
the target image will possess its other defa ult conditions: the tr anslation offset will be zero,
posted writes will be disabled, and only 32-bit (maximum) non-block VMEbus cycles in the
non-privileged data space will be generated. This option would typically be used to access
permits the use of Boot ROM on another car d in the VMEbus system.
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PCI Register Access
A power-up option determines if the registers are mapped into Memory or I/O space.
P C I Bus Wi d th
The PCI Interface can be used as a 32-bit bus or 64-bit bus. The PCI b us width is determined
during a PCI reset (see Secti on 4.3.2 of the PCI Specification, Re v. 2.1). The Universe II is
configured as 32-bit PCI if REQ64# is high on RST#; it is configured as 64-bit if REQ64# is
low. The Universe II has a n internal pull-up on REQ 64#, so the Universe II defaults to 32-bit
PCI. On a 32-bit PCI bus, the Universe II drive s all its 64-bit extension bi-direct signals at all
times; these signals include: C/BE [7:4]#, AD[63:32], REQ64#, PAR64 and ACK64# to
unknown va lues. If used as a 32-bit inte rface, the 64-bit pins, AD[63:32], C/BE[7:4], PAR64
and ACK64# may be left unter minated.
PCI CSR Image Space
There is a power-up option (using the VA[1] pin) that determines the value of the SPACE bit
of the PCI_BSx regis ters. At po wer - up the SPACE bit of the PCI_BS1 reg ister is the negation
of the SPACE bit of the PCI_BS0 re gister.
• When the VA[1] pin is sampled low at power-up, the PCI_BS0 register’s SPACE bit
is set to “1”, which signifies I/O space, and the PCI_BS1 register’s SPACE bit is set
to “0”, which signifies Memory space.
• When VA[1] is sampled high at power-up, the PCI_BS0 register’s SPACE register’s
bit is set to “0”, which signifies Memory space, and the PCI_BS1 register’s SPACE
bit is set to “1”, which signifies I/O space.
Once set, this mapping persists until the next power-up sequence.
See “Memory or I/O Access” on page 2-103, Table A.6 and Table A.7.
2.10.2.2 P owe r-Up Option Implementation
This section describes pull-up requirements and timing relevant to the power-up options.
The pull-ups for the general po wer - up options (if other than default v alues are required) must
be placed on the VA[31:1] and VD[31:27] lines . During reset, the Universe II will ne gate
VOE#, putting these signals into a high-impedance state. While VOE# is ne gated the pull- ups
(or internal pull-downs) will bring the option pins (on A[31:1] and D[31:27]) to their appro-
priate state.
Caution: The internal pul l-downs are very weak. The leakag e current on many
transceivers may be sufficient to override these pull-downs. To ensure proper
operation designers should ensure power-up option pins will go to the correct
state.
!
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Within two CLK64 periods after PWRRST# is negated, the Uni verse II latches the lev e ls on
the option pins, and then neg ates V OE# one clock later. This enables the VMEb us transceiv ers
inwards.
The po wer- up options are subs equentl y loaded into their respecti ve re gisters se veral PCI clock
periods after PWRRST #, SYSRST* and RST# have all been negated.
Because of the power-up configuration, the VM Ebus buffers are not enabled
until several CLK64 periods after releas e of SYSRST* (approximately 45 ns).
Allowing for worst case backplane skew of 25 ns, the Universe II will not be
prepar ed to receive a slave access until 70 ns after release of SYSRST*.
power-up options
CLK64
VOE#
VA, VD
PWRRST#
Figure 2.22 : Power-up Options T imi ng
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2.10.3 Hardware Initialization (Normal Operating Mode)
The Universe II has I/O capabilities that are specific to manufacturing test functions. These
pins are not required in a non-manufacturing test setting. Table 2.24 below shows how these
pins should be termin ated.
Table 2.24 : Manufacturing Pin Requir ements f or Normal Operating Mode
Pin Name Pin Value
TMODE[2] VSS (or pulled-down i f board tests wi ll occ asion ally be perfor m ed, se e “A uxiliary Tes t
Mo des ” on page 2-12 2 )
TMODE[1]
TMODE[0]
PLL_TESTSEL VSS
ENID VSS
PLL_TESTOUT N/C
VCOCTL VSS
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2.10.4 Test Mod es
The Univ er se II provides two types of test modes: auxiliary modes (NAND tree simulation
and High Impedance) and JTA G (I EEE 1149.1).
2.10.4.1 Auxiliary Test Modes
Tw o auxiliary test m odes are supported: NAND tree and high impedance. The Universe II has
three test mode input pins (TMODE[2:0]). F or normal operations these inputs should be tied
to ground (or pulled to ground through resistors). Table 2.25 below indicates the 3 operating
modes of the Uni verse II. At reset the TMODE[2:0] inputs are latched by the Universe II to
determine the mode of opera tion. The Uni verse II remains in this mode unt il the
TMODE[2:0] inputs have changed and a reset event has oc curred. PLL_TESTSEL must be
high for any test mode.
For NAND Tree Simulation, the values of the TMODE pins are latched during the active part
of PWRRST#. The se pins c an change state during the NAND Tree tests. The timers are
always accelera ted in this mode. All outputs are tristated in this mode, except for the
VXSYSFAIL output pin.
For High Impedance mode, the values of the TMODE pins are also latched during the active
part of PWRRST#. All outputs are tris tated in this mode, except for the VXSYSFAIL output
pin.
Table 2.25 : Test Mode Operation
Operation Mode TMODE[2:0] PLL_TESTSEL
Nor ma l Mode 000 0
Accelerate 001 0
Reserved 010 1
Reserved 011 1
NAND Tree Simula ti on 100 1
Reserved 101 1
High Impedance 110 0/1
Reserved 111 1
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2.10.4.2 JTAG support
The Univer se II includes dedicated user-accessible test logic that is fully compatible with the
IEEE 1149.1 Standard Test Access Port (TAP) and Boundary Scan Architecture. This
standard was developed by the Test Technology Technical Comm ittee of IEEE Computer
Society and the Joint Test Action Group (JTA G) . The Universe II’s JTAG support includes:
• A five-pin JTAG inter face (TCK, TDI, TDO, TMS, and TRST#),
• a JTAG TAP cont roller,
• a three -bit instruc tion register,
• a boundary scan regis ter,
• a bypass re gister,
• and an IDCODE register.
The follow ing required public instructions are supported: BYPASS (3'b111),
SAMPLE(3'b100), and EXTEST(3'b000). The optional public instruction IDCODE(3'b011)
selects the IDCODE regist er which returns 32'b01e201d. The follo wing exter nal pins are not
part of the boundary scan register: LCLK, PLL_TESTOUT, PLL_TESTSEL, TMODE[3:0],
and VCOCTL.
A BSDL file is available upon request from Tundra Semiconductor Corporation.
2.10.5 Clocks
CLK64 is a 64 MHz clock that i s required by the Univ erse II in order to synchronize internal
Unive rse II state machines and to produce the VMEbus system clock (VSYSCLK) when the
Uni v erse II is system cont roller (SYSCON). This clock is spec ified to ha v e a minimum 60-40
duty c ycle with a maximum rise time of 5 ns. Using a diff erent frequency is not recommended
as it will alter v a rious internal timers and change some VME timing.
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VMEbus Interface Components—Universe II User Manual
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3 Description of Signals
The following detailed description of the Universe II signals is organized according to
these functional groups:
• VMEbus Sign al s
• PCI Signals
3.1 VMEbus S ignals
CLK64 Input
Refe re nce Clock – th is 64 MHz cloc k is us ed to gener at e fixed timi ng par amet ers. It r equir es a 50- 50 duty cyc le (±2 0% )
with a 5ns maximum rise time. CLK64 is required to synchronize the internal state machines of the VME side of the
Univ erse II.
VA [31: 1] Bidirectional
VMEbus Addr ess Lines 31 to 01 – duri ng M B LT trans fers, V A 31-01 ser ve as data bits D63-D33.
VA03-0 1 are used to indicat e int errupt level on th e V MEbus.
VA_DIR Output
VMEbus Address Transceiver Dir ecti on C ontrol – the U niver se II controls th e direction of the address (VA31-01,
VLWORD#) transceivers as required for master, slave and bus isolation modes. When the Universe II is driving lines on
the VMEbus, this signal is driven high; when the VMEbus is driving the Universe II, this signal is driven low.
VAM [5:0] Bidirectional
VMEbu s Addre ss Modi fier Codes – thes e codes i ndic ate the addr ess space being acces sed (A1 6, A24, A32), the privile ge
level (user, supervisor), the cycle type (standard, BLT, MBLT) and the data type (program, data).
VAM_DI R Output
VMEbus AM Code D irec tion Contro l – controls the di rect ion of the AM code trans ceive rs as required for master, slave
and bus isola tion modes. When the U niverse II is driving l ines on t he V MEbus, this signa l is dri ven high; when the
VMEbus is driving the Universe II, this signal is driven low.
VAS# Bidirectional
VMEbu s Add res s Str obe – the fall in g edg e of V AS# in dicat es a va lid ad dre ss on th e bus. By con tinui ng to a ssert VA S#,
ow nership of the bus is maintain ed during a RMW cycle .
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VAS_DIR Output
VMEbus Addr ess Strobe D irection Cont rol – controls the dire ction o f the addr ess st robe transcei ver as re quire d for
master, slave and bus isolation modes. When the Un iverse II is driving line s on the VMEbus, this si gnal is driven hi gh;
when the VMEbus is driving the Universe II, this signal is driven low.
VBCLR# Output
VMEbus Bus Clear – reques ts tha t the cu rrent ow ner rel ease t he bus.
Asserted by the Universe II when configured as SYSCON and the arbiter detects a higher level pending request.
VB G I # [3 :0 ] Input
VMEbus Bus Grant Inp u ts – The VM E arbiter awards use of the data tra nsfer bus by dri ving these bus grant lines low .
T he signa l propa gates do w n the bus grant daisy chain an d is either:
• acc epted b y a reque ster if it re quest ing at t h e appropriate level, or
• passed on as a VBG O [3:0] # to the ne xt boa rd in the bus grant daisy chain.
VBGO# [3:0] Output
VMEbus Bus Grant Outputs – On ly one out put is asser ted at an y time, a ccording to the level at which the V MEbus is
being gr anted.
VD [31:0] Bidirectional
VMEbus Data Lines 31 throug h 00
VD_DIR Output
VMEbu s Dat a T ran scei ver Di re ction Co ntr ol – the Un iver se I I con tr ols the di r ectio n o f th e data (VD [31 :0] ) tra nsc ei vers
as required for master, slave and bus isolation mode s. When the Universe II is dri ving lines o n the VMEbus, this s ignal
is driven high; when t he VMEbus is dri ving the Universe II, this si gnal i s driven low.
VDS# [1:0] Bidirectional
VMEbus Dat a Strob es – the level of these signa ls are used to indicate active by te lanes:
• During w rite cycles, the f alling edge i ndicates valid data on the bus.
• Duri ng read cycles, assertion indicates a request to a slave to pro vide data.
VDS_DIR Output
VMEbus Data Strobe Direction Control – contr ols th e direction of the data stro be tran sceivers as requ ired f o r m aster,
sla ve and bus isol at ion m ode s. W hen th e Uni ve rs e II i s dri ving li nes on th e VM Ebus, thi s si gna l i s dri ve n hi gh; whe n t he
VMEbus is driving the Universe II, this signal is driven low.
VDTACK# Bidirectional
VMEbus Dat a Transfer A cknowledge – VDTACK # driven low indic ates t hat the addres sed sla ve has re sponded to the
transf er . T he Un iv ers e II alw a ys re sc in d s D T A C K *. It is tri st ate d on c e the in it ia ting m as te r neg at es AS * .
3.1 VMEbus S ignals (Continued)
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VIACK# Bidirectional
VMEbus In terr upt Acknowled ge – indicates that the cycle j ust be ginni ng is an interrupt acknowledge cycle.
VIACKI# Input
VMEbus In terr upt Acknowled ge In – Inpu t for IACK dais y chain driver. If in terr upt ackn ow ledge is at same l evel as
inter rupt cu rrent ly generate d by the U niverse II , t hen t he cycle is accepted. I f in terrupt acknowle dge i s not at s am e le vel
as current interrupt or Universe II is not generating an interrupt, then the Universe II propagates VIACKO#.
VIACKO# Output
VMEbus In terr upt Acknowled ge O ut– gen erat ed by the Universe II if it receive s V IA CK I# and i s not cur rently
generating an int errup t at the level being acknowl edged.
VLWORD# Bidirectional
VMEbus Longword Data Transfer Size Indicator – this signal is used in conjunction with the two data strobes
VDS [1:0 ]# and VA 01 to indicate the numb er of byt es (1 – 4) in the current transfer . Du ring MBLT transfers
VLWO RD # serves as data bit D 32.
VOE# Output
VMEbus Transcei ver Output Enabl e – u sed to c ontro l transceivers to i sola te the Universe II from the VMEbus during a
reset or BI-mode. On power-up, VOE# is high (to disable the buffers).
VRACFAIL# Input
VMEbus ACFAIL Input signal – war n s the VMEbus sys tem of imminent pow er fai lure . This gives th e modules in the
system time to shut down in an orderl y fashion befor e pow erdown. ACFAIL is ma pped to a PCI inter rupt.
VRBBSY# Input
VMEbus Rec eive Bus Busy – allo w s the Univers e II to monitor wheth er the VMEbus is owned by another VMEbus
master
VRBERR# Input
VMEbus Receive Bus Err or – a low level s ignal indicates that the add resse d slave has n ot r esponded, or is signalling an
error.
VRBR# [3:0] Input
VMEbus Receive Bus Request Lines – if the Universe II is the Syscon, the Arbiter logic monitors these signals and
generates the appropriate Bus Grant signals. Also monitored by requester in ROR mode.
VRIRQ# [7:1] Input
VMEbus Rec eive In terr upts 7 through 1 – these interrupts can be mapped to any of t he U niver se II’s PCI interru pt
ou tputs.
VRIRQ7-1# are indi vidually ma skable, but cannot be read.
3.1 VMEbus S ignals (Continued)
VMEbus Signals Universe II User Manual
3-4 Tundra Semiconductor Corporation
VRSYSFAIL# Input
VMEbu s Rec eive SYSFA IL – ass er ted by a VMEb us s ystem to indi cate some sy st em fai lure . VRSYSFAI L# i s mappe d
to a PCI interrupt.
VRSYSRST# Input
VMEbus Rec eive Sys tem Reset – causes ass ertion of LRST# on the local bus and re sets the U nive rse II.
VSLAVE_DIR Output
VMEbus Sl ave Direction Control – transceiver co ntrol that al low the Univers e II to dr ive DTA C K * o n the VMEb us.
When the Un iverse II is dri ving li nes on the VMEbus, this signal is driv en high; w hen the VM Ebus is dr iving the
Universe II, this signal is driven low.
VSYSCLK Bidirectional
VMEbus System Clock – generated by the Universe II when it is the Syscon and monitored during DY4 Auto ID
sequence
VSCON_DIR Output
Syscon Direction Control – transceiver control that allows the Universe II to drive VBCLR# and SYSCLK. When the
Universe II is driving lines on the VMEbus, this signal is driven high; when the VMEbus is driving the Universe II, this
si gn a l is driv e n low.
VWRITE# Bidirectional
VMEbus Write signal – indicates the direction of data tr ansf er.
VXBBSY Output
VMEbus Tra nsmit Bu s Busy Signal – generated by the Uni vers e II when it is VMEbus mast er
VXBERR Output
VMEbus Tra nsmit Bu s Error Signal – generated by the Universe II wh en PCI target gene rates target abort on co upled
P C I acces s from VMEbus.
VXBR [3:0] Output
VMEbus Transmit Bus Request – the Universe II requests the VMEbus when it needs to become VMEbus master.
VXIRQ [7:1] Output
VM E b us Tr an smit Inte rr upt s – th e VM E b u s in te rrup t outpu t s ar e indi v idua l ly ma sk a ble.
VXSYSFAIL Output
VMEbus Sys tem Fail ure – asserted by th e U n iverse II dur ing re set and plays a role in VME64 Auto ID .
VXSYSRST Output
VMEbus System Reset – the Universe II output f or SYSRST*.
3.1 VMEbus S ignals (Continued)
Universe II Use r Manual P CI Bu s Signal s
Tundra Semiconduc tor Corporation 3-5
3.2 PCI B us S ignal s
ACK64# Bidirectional
Acknow ledge 64-bit Transfer – when dri ven by the PCI sl ave (target), it indicates slave can perf orm a 64-bit trans fer.
AD [31:0] Bidirectional
P C I A ddres s/Dat a Bus – address and data are m ultiplexe d over these pins pro vidin g a 32-bi t address/data bus.
AD [63:32] Bidirectional
P C I A ddres s/Dat a Bus – address and data are multiplexed over these pi ns prov iding 64-bit address and data capab ility.
C/ B E # [7 :0 ] Bidirectional
P C I Bu s Comma nd and Byte Enab le Line s – com m and and byte enable information is m ultiplex ed over al l eig ht C /BE
lines. C/B E [7 :4 ]# are on l y us ed in a 64 -b it PC I bu s
DEVSEL# Bidirectional
PCI Device Select – is driven by the Universe II when it is accessed as PCI slave.
ENID Input
E nable I D D Te sts – re quire d for ASIC manufac turi ng test, tie to groun d for nor ma l opera tion .
FRAME# Bidirectional
Cycle Frame – is driven by the Universe II wh en it is PCI initiato r, and is moni tored by the Unive rse II when i t is PCI
target
GNT# Input
P C I G rant – indica tes to the Univ erse II that it has be en granted ownership of the PCI bus.
IDSEL Input
P C I Initializa tion Devic e Select – is used as a chip select during co nfiguration read and write transactions
LINT# [7:0] Bidirectional (Open Drain)
P C I Inte rrupt Inputs – these PCI interrupt i nputs ca n be m apped to any PCI bus or VMEbus inte rrupt output.
IRDY# Bidirectional
Initiator Ready – is used by the Universe II as PCI master to indicate that is ready to complete a current data phase.
LCLK Input
P CI Clock – prov id es tim ing f or a ll tr ans act ions on th e PCI b us. PCI s ign al s are sa mpl ed on t he ris in g edg e of CLK , and
all timing parameters are d efined rela tive to this signal. The PCI clock freq uency of the U niver se II II m ust be between
2 5 and 33MHz. Lower frequencies will result in inval id VME timing.
PCI Bus Signals Universe II User Manual
3-6 Tundra Semiconductor Corporation
LOCK# Bidirectional
L ock – used by t he U nive rse II to indicate an exclusiv e oper atio n wi th a PCI de vice. Whi le the U niverse II driv es
L OCK#, other PCI masters are exclude d from accessing that partic ular PCI device. Likewi se, when the Universe II
sam ples LOCK# , it may be exclude d from a particular PCI device.
LRST# Output
P C I Reset Output – used to reset PCI resour ces.
PAR Bidirectional
P arity – parity i s even across A D [31:0] and C/BE [3 :0] ( the num ber of 1s summed across t hese lines and PAR equal an
even number).
PAR64 Bidirectional
P arity U p per DWOR D – par ity is even ac ross AD [63:32] and C/BE [7:4] (th e number of 1s summed across thes e lines
and PA R equal an even number).
PERR# Bidirectional
P arity Error – report s pari ty erro rs duri ng all trans actio ns. The Uni vers e II drives PE RR# high wit hin two cl ocks of
recei ving a par ity error on i ncoming data , and holds PERR# for at least one clock fo r each er rored data phase.
PLL_TESTOUT Output
Manufacturing Test Output—No connect
PLL_TESTSEL Input
Manufacturing Test Select—tie to ground for normal operation
PWRRST# Input
P ower-up Reset – al l Universe I I cir c uitr y is reset by this inpu t.
REQ# Output
Bu s Reques t – used by the Universe II to indicate that it requi res the use of the PCI bus.
REQ64# Bidirectional
6 4-B it Bus Request – used t o reques t a 64-bi t PCI tr ansact ion. If the t arget do es not r e spond wi th ACK64#, 32-bit
operation is assumed.
RST# Input
PCI Reset Input—resets the Universe II from the PCI bus.
SERR# Bidirectional
System Error – reports address parity errors or any other system error.
3.2 PCI B us S ignal s (Continued)
Universe II Use r Manual P CI Bu s Signal s
Tundra Semiconduc tor Corporation 3-7
STOP# Bidirectional
St o p – us ed by th e U ni ver se II as PC I sl ave wh en it w ishe s to sign a l the PCI master t o st op the cu r r e nt t ra ns act io n. As
P C I m aster , the Unive rse II will terminat e the transaction if it receives STOP# from th e PC I slave.
TCK Input
JT A G Test Clock I nput – used to clock the U niver se II TA P controller. Tie to any lo gic level if JTAG is n ot use d in the
system.
TDI Input
JTAG Test Data Input – used to serially shift test data and test instructions into the Universe II. Tie to any logic level if
JTAG is not used in the system.
TDO Output
JTAG Test Data Output – used to serially shift test data and test instructions out of the Universe II
TMODE [2 :0] Input
T est Mode Enable – used for chip tes ting , tie to ground f or normal operati on.
TMS Input
JTAG Test Mode Select – controls the state of the Test Access Port (TAP) controller in the Universe II. Tie to any logic
level if JTAG is not used in the system.
TRDY# Bidirectional
Target Ready – used by the Universe II as PCI slave to indicate that it is ready to complete the current data phase. During
a read with Universe II as PCI mast er, t he slave asserts T R DY# to in dicate to the Unive rse II that valid data is present
on the data bus.
TRST# Input
JT AG Test Reset – pr ovi de s asynch ron ous initi al izat io n of t he TAP co ntrol le r in the Unive rs e II . Tie to grou nd if JTA G
is not used in the system.
VCOCTL Input
Manufactur ing testing, tie to ground for normal ope rati on
VME_RESET# Input
VMEbus Res et Input — generates a VME bus system reset.
3.2 PCI B us S ignal s (Continued)
PCI Bus Signals Universe II User Manual
3-8 Tundra Semiconductor Corporation
VMEbus Interface Components—Universe II User Manual
Tundra Semiconduc tor Corporation 4-1
4 Signals and DC Characteristics
4.1 Terminology
The I/O type abbreviations used in the pin list in Table 4. 2 on page 4-3 are defined below.
A numbered suffix indicates the current rating of the output (in mA).
Analog Analog input signal
I Input only
I/O Input and output
O Output only
OD Open drain output
PD Pulled- down interna lly
PU Pulled-up internally
TP Totem pole output
TTL Input with TTL thresholds
TTL SCH Schmitt trigger input with TTL
thresholds
3S Tri–state output
DC Characteristics and Pin Assignments Universe II User Manual
4-2 Tundra Semiconductor Corporation
4.2 DC Ch aracteris tic s and Pin Assignments
Table 4.1 : DC Electrical Characteristics (VDD = 5 V ± 10%)
Symbol Parameter Signal
Type Test Conditions Tested at
0°C to 70°C
Min Max
VIH Min. high–
level inpu t
CTTL VOUT = 0. 1V or VDD – 0.1V; [IOUT] = 20 µA 2.2 V VDD + 0.3V
CMOS VOUT = 0.1V or VDD – 0.1V; [I OUT] = 20 µA 0.7VDD VDD + 0.3V
VIL Max. low–
level inpu t
CTTL VOUT = 0. 1V or VDD – 0.1V; [IOUT] = 20 µA –0.3 V 0.8V
CMOS VOUT = 0.1V or VDD – 0.1V; [I OUT] = 20 µA –0.3 V 0.3VDD
VT+
Positive
going
Schmitt
trigger
voltage
CTTL/
SCH VOUT = 0.1V or VDD – 0.1V; [IOUT] = 20 µA – 2.4 V
CMOS/
SCH VOUT = 0.1V or VDD – 0.1V; [IOUT] = 20 µA – 0.7VDD
VT–
Negative
going
Schmitt
trigger
voltage
CTTL/
SCH VOUT = 0.1V or VDD – 0.1V; [IOUT] = 20 µA 0.8 V –
CMOS/
SCH VOUT = 0.1V or VDD – 0.1V; [IOUT] = 20 µA 0.25VDD –
VHysteresis
Schmitt
trigger
hysteresis
voltage
CTTL/
SCH VT+ to VT– 0.05VDD –
CMOS/
SCH VT+ to VT– 0.12VDD –
IIN
Maximum
input
leakage
current
CMOS
and
CTTL With no pull– up resistor (VIN = VSS or V DD) –5.0 µA 5.0 µA
IOZ
Maximum
output
leakage
current
3S (VOUT = VSS or VDD) –10.0 µA 10.0 µA
OD (VOUT = VDD) –10.0 µA 10.0 µA
Universe II User Manual DC Characteristi cs and Pin Assignments
Tundra Semiconduc tor Corporation 4-3
Table 4.2 : Pin List and DC Characteristics for Univ erse II Signals
Pin Nam e PBGA
Pin
Number
CBGA
Pin
Number Type Input Type Output
Type IOL
(mA) IOH
(mA) Sign al D escr iption1
ACK64# W 11 W8 I/O TTL 3S 6 –2 PCI Acknowledge 64 Bit
Transfer
AD [63:0] TABLE 4.3 I/O TTL 3S 6 –2 PCI Address/ Data Pins
C/BE# [0] Y14 T11 I/O TTL 3S 6 –2 PCI Command and Byte
Enables
C/BE# [1] V14 Y11
C/BE# [2] T14 U11
C/BE# [3] W13 W10
C/BE# [4] AE15 Y12
C/BE# [5] AD14 V11
C/BE# [6] T12 V10
C/BE# [7] AD12 Y9
CLK64 C23 D16 I TTL – – – VME Clock 64 MHz—60-40
duty, 5 ns rise time
DEVSEL# AC7 V6 I/O – 3S 6 –2 PCI Devic e Sel ect
ENID AE21 Y16 I CMOS – – – En able IDD Tests
FRAME# W17 T12 I/O TTL 3S 6 –2 PCI Cycle Frame
GNT# AE17 Y14 I TTL – – – PCI Grant
IDSEL AB16 Y15 I TTL – – – PCI Initialization Device Select
LIN T# [0] K20 H15 I/O TTL OD 12 –12 PCI Interrupt
LINT# [1] AA5 U3 I/O TTL OD 4 –4
LINT# [2] L9 J3
LINT# [3] V6 R4
LINT# [4] M 4 J4
LINT# [5] L3 J6
LINT# [6] M 8 J5
LINT# [7] L1 K4
IRDY# AC15 V12 I/O TTL 3S 6 –2 PCI Initiat or Ready
LCLK AA3 W3 I TTL – – – PCI Clock Signal
LOCK# AA23 T18 I/ O TTL 3S 6 –2 PCI Loc k
LRST# R1 M1 O – 3S 6 –2 PCI Reset Output
PAR P8L1I/OTTL 3S 6 –2PCI parity
PAR64 AE5 W4 I/O TTL 3S 6 –2 PCI Parity Upper DWORD
PERR# AB4 W5 I/O TTL 3S 6 –2 PCI Parity Error
PLL_TESTOUT AB2 V1 FOR FACTORY TESTING
DC Characteristics and Pin Assignments Universe II User Manual
4-4 Tundra Semiconductor Corporation
PLL_TESTSEL AC1 T2 FOR FACTORY TESTING
PWRRST# T4 R1 I TTL/
SCHM – – – Power–up Reset
REQ# K22 F20 O – 3S 6 –2 PCI Req uest
REQ64# AD18 T13 I/O TTL 3S 6 –2 PCI Req uest 64 Bit Trans fer
RST# AA19 W17 I TTL – – – PCI Reset
SERR# AA7 R7 O TTL OD 12 –12 PCI Sy stem E rror
STOP# AB18 W15 I/ O TTL 3S 6 –2 PCI Stop
TCK H12 A10 I TTL – – – JTAG Test Clock Input
TDI A13 F10 I TTL
(PU) – – – JTAG Test Data In put
TDO C13 E11 O – 3S – – JTAG Tes t Data OUTput
TMODE [0] AA13 W11 I TTL – – – Tes t Mode Enable
TMODE [1] AA21 V17
TMODE [2] W23 R18
TMS C11 C9 I TTL
(PU) – – – JTAG Test Mode Sele ct
TRDY# AD8 W7 I/O TTL 3S 6 –2 PCI Ta rge t Ready
TRST# E13 B10 I TTL
(PU) – – – JTAG Test Reset
VA [31:1] TABLE 4.4 I/O TTL
(PD) 3S 3 –3 VMEbus A ddress Pins
VAM [0 ] E11 D8 I/O TTL 3S 3 –3 VMEbus Address Modifier
Signals
VAM [1 ] D10 A6
VAM [2 ] G9 E9
VAM [3 ] B10 B8
VAM [4 ] H10 D9
VAM [5 ] A9 A7
VAM_DIR B8 E8 O – 3S 6 –6 VMEbus AM Signal Direction
Control
VAS# B14 A12 I/O TTL/
SCHM
(PU)
3S 3 –3 VMEbus Address Stro be
VAS_DIR K12 D10 O – 3S 6 –6 VMEbus AS Directi on Con tr ol
VA_DIR G13 B11 O – 3S 12 –12 VMEbus Add re ss Di rec ti on
Control
Table 4.2 : Pin List and DC Characteristics for Univ erse II Signals (Continued)
Pin Nam e PBGA
Pin
Number
CBGA
Pin
Number Type Input Type Output
Type IOL
(mA) IOH
(mA) Sign al D escr iption1
Universe II User Manual DC Characteristi cs and Pin Assignments
Tundra Semiconduc tor Corporation 4-5
VBCLR# N3 K5 O – 3S 3 – 3 VMEbus BCLR* Signal
VBGI# [0] N21 K19 I TT – – – VMEbus Bus Gran t In
VBGI# [1] M16 K17
VBGI# [2] N25 K15
VBGI# [3] N23 L16 TT (PD)
VBGO# [0] M20 K16 O – 3S 1 2 –12 VM Ebus Bus Grant Out
VBGO# [1] L25 J20
VBGO# [2] M18 K20
VBGO# [3] M24 K18
VCOCTL AE3 T5 I – – – – Fac tor y te sting
VD [31:0] TABLE 4.4 I/O TTL 3S 3 –3 VMEbus Data Pins
VD_DIR F10 F8 O – 3S 12 – 12 VMEbus Data Dire ction Con trol
VDS# [0] F12 E10 I/O TTL
(PU) 3S 3 –3 VMEbus D ata St robes
VDS# [1] A11 A9
VDS_DIR J11 F9 O – 3S 6 –6 VMEbus Data Strobe Dir ection
Control
VDTACK# G15 B13 I/O TTL/
SCHM
(PU)
3S 3 –3 VMEbus DTACK* Si gnal
VIACK# E7 E6 I/O TTL 3S 3 –3 VMEbus IACK* Signal
VIACKI# AE23 W16 I TTL – – – VMEbus IACKIN* Signal
VIACKO# L21 H17 O – 3S 12 –12 VMEbus IACKOUT* Sig nal
VLWORD# K14 C11 I/O TTL
(PD) 3S 3 –3 VMEbus LWORD* Signal
VME_RESE T# V22 T19 I TTL VMEbus Reset Input
VOE# B12 C10 O – 3S 24 –24 VMEbus Tr ansce iver Out put
Enable
VRACFAIL# P18 M16 I TTL/
SCHM – – – VMEbus ACFAI L * Signal
VRBBSY# M6 J2 I TTL/
SCHM – – – VMEbus Received BBSY*
Signal
VRBERR# A7 B7 I TTL/
SCHM – – – VMEbus Receive Bus Error
Table 4.2 : Pin List and DC Characteristics for Univ erse II Signals (Continued)
Pin Nam e PBGA
Pin
Number
CBGA
Pin
Number Type Input Type Output
Type IOL
(mA) IOH
(mA) Sign al D escr iption1
DC Characteristics and Pin Assignments Universe II User Manual
4-6 Tundra Semiconductor Corporation
VRBR# [0] W5 U2 I TTL/
SCHM – – – VMEbus Recei ve Bus Request
VRBR# [1] U1 P1
VRBR# [2] R3 M3
VRBR# [3] L7 H2
VRIRQ# [1] H22 F19 I TTL/
SCHM – – – VMEbus Rec eive I nterrupts
VRIRQ# [2] H20 F17
VRIRQ# [3] E25 E20
VRIRQ# [4] J2 1 G18
VRIRQ# [5] V16 U12
VRIRQ# [6] P20 M19
VRIRQ# [7] R17 M18
VRSYSFAIL# AC13 T10 I TTL – – – VMEbus Rec eive SYSFAIL
Signal
VRSYSRST# C21 C16 I TTL/
SCHM – – – VMEbus Receive SYSRESET*
Signal
VSCON_DIR M2 J 1 O – 3S 6 –6 SYSCON signals direction
control
VSLAVE_DIR C15 F12 O – 3S 6 –6 DTACK/BERR dir ectio n
control
VSYSCLK N7 K2 I/O TTL 3S 3 –3 VMEbus SYSCLK Signal
VWRITE# D8 B6 I/O TTL 3S 3 –3 VMEbus Wri te
VXBBSY P2 L3 O – 3S 3 –3 VMEbus Tr ansmit B BSY *
Signal
VXBERR D12 B9 O – 3S 3 –3 VMEbus Transmit Bus Error
(BERR*)
VXBR [0] G25 G19 O – 3S 3 –3 VMEbus Transmit Bus Request
VXBR [1] H24 H16
VXBR [2] P24 M2 0
VXBR [3] G23 C19
Table 4.2 : Pin List and DC Characteristics for Univ erse II Signals (Continued)
Pin Nam e PBGA
Pin
Number
CBGA
Pin
Number Type Input Type Output
Type IOL
(mA) IOH
(mA) Sign al D escr iption1
VMEbus Interface Components—Universe II User Manual
Tundra Semiconduc tor Corporation 4-7
Note 1: All PCI pins meet PCI’s AC current specifications.
VX IR Q [1 ] J 19 J1 6 O – 3S 3 –3 V ME bu s Tra n sm i t In terr up ts
VXIRQ [2] K24 H19
VXIRQ [3] K18 J17
VXIRQ [4] J25 G20
VXIRQ [5] L23 J18
VXIRQ [6] M22 J19
VXIRQ [7] R25 L17
VXSYSFAIL M10 K3 O – 3S 3 –3 VMEbus Transm it SYSFAIL
Signal
VXSYSRST A23 E16 O – 3S 3 –3 VMEbus Transmit
SYSRESET* Si gnal
Table 4.3 : PCI Bus Address/Data Pins
Signal PBGA CBGA Signal PBGA CBGA
AD [0] P16 L18 AD [32] L17 J 15
AD [1] P22 M17 AD [33] N19 L 19
AD [2] R19 N19 AD [34] R23 M15
AD [3] T18 U20 AD [35] U1 9 N18
AD [4] T22 N15 AD [36] U2 3 R2 0
AD [5] T20 T20 AD [37] W25 P16
AD [6] AA25 U19 AD [38] U21 P1 7
AD [7] AB2 4 R17 AD [39] V20 R19
AD [8] AB2 2 R16 AD [40] Y22 U18
AD [9] AE25 T17 AD [41] W21 P15
AD [10] AC21 V19 AD [42] AD22 Y1 8
AD [11] AB20 V15 AD [43] Y20 T15
AD [12] AC19 W18 AD [44] AD20 T14
AD [13] AA17 V14 AD [45] Y18 U15
AD [14] AA15 U13 AD [46] AE19 W14
AD [15] U1 5 R12 AD [47] AD16 W13
AD [16] AE11 U1 0 AD [48] V12 T9
Table 4.2 : Pin List and DC Characteristics for Univ erse II Signals (Continued)
Pin Nam e PBGA
Pin
Number
CBGA
Pin
Number Type Input Type Output
Type IOL
(mA) IOH
(mA) Sign al D escr iption1
DC Characteristics and Pin Assignments Universe II User Manual
4-8 Tundra Semiconductor Corporation
AD [17] AB12 U9 AD [49] Y12 W9
AD [18] W 9 V8 AD [50] AC11 R9
AD [19] AD10 U8 AD [51] V10 Y4
AD [20] AE7 T7 AD [52] AB10 R8
AD [21] Y8 W 6 AD [53] AA9 U7
AD [22] AD4 U6 AD [54] AB8 T6
AD [23] Y6 R5 AD [55] AB6 V4
AD [24] Y2 P5 AD [56] Y4 R3
AD [25] V4 R2 AD [57] W3 V2
AD [26] U5 P3 AD [58] AA1 T1
AD [27] W 1 P2 AD [59] V2 N5
AD [28] U7 M5 AD [60] R5 N4
AD [29] T8 M4 AD [61] T2 N2
AD [30] P6 L5 AD [62] R9 M6
AD [31] P10 L4 AD [63] N5 L2
Table 4.3 : PCI Bus Address/Data Pins
Signal PBGA CBGA Signal PBGA CBGA
VMEbus Interface Components—Universe II User Manual
Tundra Semiconduc tor Corporation 4-9
Table 4.4 : VMEbus Address Pinsa
Signal PBGA CBGA Signal PBGA CBGA
VA [1] H14 E12 VA [17] D18 B1 6
VA [2] A15 D11 VA [18] C19 C15
VA [3] F14 B12 VA [19] B20 D17
VA [4] J15 C12 VA [20] B22 D15
VA [5] D14 D12 VA [21] D2 0 C1 7
VA [6] G17 C13 VA [22] F20 E15
VA [7] H16 A17 VA [23] E19 F14
VA [8] B16 D13 VA [24] A25 C20
VA [9] C17 A15 VA [25] E23 B18
VA [10] D1 6 F13 VA [26] C25 E19
VA [11] A1 9 E14 VA [27] G21 F16
VA [12] B18 B14 VA [28] E21 D18
VA [13] F16 A16 VA [29] F22 F18
VA [14] E17 D14 VA [30] D24 D19
VA [15] A2 1 B17 VA [31] F24 G16
VA [16] F18 B15
a. All VA pins have an internal pull-down.
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4-10 Tundra Semiconductor Corporation
Tabl e 4.5 : VMEbus Data Pinsa
Signal PBGA CBGA Signal PBGA CBGA
VD [0] J7 H3 VD [16] F6 E2
VD [1] K8 D1 VD [17] G5 G6
VD [2] K2 H4 VD [18] B2 E5
VD [3] J3 F1 VD [19] C1 E3
VD [4] K4 H6 VD [ 2 0] E3 E4
VD [5] G1 G5 VD [21] C3 A3
VD [6] H2 G2 VD [22] A1 C2
VD [7] K6 E1 VD [23] A3 B5
VD [8] J5 G4 VD [24] C5 C4
VD [9] E1 D2 VD [25] D6 C6
VD [10] H6 F2 VD [26] B4 B4
VD [11] H4 F5 VD [27] B6 E7
VD [12] G3 F3 VD [28] C7 B3
VD [13] F2 D4 VD [29] F8 D6
VD [14] D2 F4 VD [30] A5 A5
VD [15] F4 D3 VD [31] E9 C7
a. VD [30:27] have inte rnal pu ll-downs.
Universe II User Manual DC Characteristi cs and Pin Assignments
Tundra Semiconduc tor Corporation 4-11
*AVDD and AVSS are power pins specifically used for powering the analog circuitry in the
Universe II. Extra care should be taken to avoid noise and ground shifting on these pins
through the use of decoupling capacitors or isolated ground and power planes.
Table 4.7 and Table 4.8 below are tables that map pi n numbers to signal
names. These tables should not be read as f igures. For layout purposes, please
see Appendix-G.
Table 4.6 : Pin Assignm e nts f o r Po wer and Ground
VSS Pins VDD Pins
PBGA CBGA PBGA CBGA
AB14 N15 A14 R10 A17 H8 W15 A4 G17 U1
AC9 N17 A18 R11 AA11 H18 W19 A8 H1 U14
AC25 P4 B2 R13 AC3 J1 Y24 A11 H5 U16
AD6 P12 B19 R14 *AC5 J9 A13 H18 U17
*AE1 P14 C1 T16 AC17 J17 C3 H20 V3
AE13 R11 F7 U4 AC23 J23 C5 K1 *V5
J13 R13 F11 *U5 AD2 L5 C8 L20 V7
K10 R15 G1 V9 AD24L19 C14N1V13
K16T6G15V20 AE9 R7 C18 N3 V16
L11 T16 K6 W2 B24 R21 D5 N16 V18
L13 T24 L6 W12 C9 T10 D7 N20 Y8
L15 U11 L15 W19 D4 U3 D20 P4 Y10
M12 U13 M2 Y3 D22 U9 E13 P18 Y13
M14 V24 N6 Y5 E5 U17 E17 R6 Y17
N1 Y10 N17 Y6 E15 U25 E18 R15
N9 Y16 P6 Y7 G7 V8 F6 T3
N11 P19 G11 V18 F15 T4
N13 P20 G19 W7 G3 T8
!
Table 4.7 : Pinout for 313-pin Plastic BGA Package
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE
1VD[22] VD[19] VD[9] VD[5] VDD INT#[7] VSS LRST# VRBR#[1] AD[27] AD[58] PLL_
TESTSEL AVSS 1
2VD[18] VD[14] VD[13] VD[6] VD[2] VSCON_
DIR VXBBSY AD[61] AD[59] AD[24] PLL_
TESTOUT VDD 2
3VD[23] VD[21] VD[20] VD[12] VD[3] INT#[5] VBCLR# VRBR#[2] VDD AD[57] LCLK VDD VCOCTL 3
4VD[26] VDD VD[15] VD[11] VD[4] INT#[4] VSS PWRRST# AD[25] AD[56] PERR# AD[22] 4
5VD[30] VD[24] VDD VD[17] VD[8] VDD AD[63] AD[60] AD[26] VRBR#[0] INT#[1] AVDD PAR64 5
6VD[27] VD[25] VD[16] VD[10] VD[7] VRBBSY# AD[30] VSS INT#[3] AD[23] AD[55] VSS 6
7VRBERR# VD[28] VIACK# VDD VD[0] VRBR#[3] VSYSCLK VDD AD[28] VDD SERR# DEVSEL# AD[20] 7
8VAM_DIR VWRITE# VD[29] VDD VD[1] INT#[6] PAR AD[29] VDD AD[21] AD[54] TRDY# 8
9VAM[5] VDD VD[31] VAM[2] VDD INT#[2] VSS AD[62] VDD AD[18] AD[53] VSS VDD 9
10 VAM[3] VAM[1] VD_DIR VAM[4] VSS VXSYSFAIL AD[31] VDD AD[51] VSS AD[52] AD[19] 10
11 VDS#[1] TMS VAM[0] VDD VDS_DIR VSS VSS VSS VSS ACK64# VDD AD[50] AD[16] 11
12 VOE# VXBERR VDS#[0] TCK VAS_DIR VSS VSS CBE[6] AD[48] AD[49] AD[17] CBE[7] 12
13 TDI TDO TRST# VA_DIR VSS VSS VSS VSS VSS CBE[3] TMODE[0] VRSYS-
FAIL# VSS 13
14 VAS# VA[5] VA[3] VA[1] VLWORD# VSS VSS CBE[2] CBE[1] CBE[0] VSS CBE[5] 14
15 VA[2] VSLAVE_DIR VDD VDTACK# VA[4] VSS VSS VSS AD[15] VDD AD[14] IRDY# CBE[4] 15
16 VA[8] VA[10] VA[13] VA[7] VSS VBGI#[1] AD[0] VSS VRIRQ#[5] VSS IDSEL AD[47] 16
17 VDD VA[9] VA[14] VA[6] VDD AD[32] VSS VRIRQ#[7] VDD FRAME# AD[13] VDD GNT# 17
18 VA[12] VA[17] VA[16] VDD VXIRQ[3] VBGO#[2] VRACFAIL# AD[3] VDD AD[45] STOP# REQ64# 18
19 VA[11] VA[18] VA[23] VDD VXIRQ[1] VDD AD[33] AD[2] AD[35] VDD RST# AD[12] AD[46] 19
20 VA[19] VA[21] VA[22] VRIRQ#[2] INT#[0] VBGO#[0] VRIRQ#[6] AD[5] AD[39] AD[43] AD[11] AD[44] 20
21 VA[15] VRSYSRST# VA[28] VA[27] VRIRQ#[4] VIACKO# VBGI#[0] VDD AD[38] AD[41] TMODE[1] AD[10] ENID 21
22 VA[20] VDD VA[29] VRIRQ#[1] REQ# VXIRQ[6] AD[1] AD[4] VME_RST# AD[40] AD[8] AD[42] 22
23 VXSYSRST CLK64 VA[25] VXBR[3] VDD VXIRQ[5] VBGI#[3] AD[34] AD[36] TMODE[2] LOCK# VDD VIACKI# 23
24 VDD VA[30] VA[31] VXBR[1] VXIRQ[2] VBGO#[3] VXBR[2] VSS VSS VDD AD[7] VDD 24
25 VA[24] VA[26] VRIRQ#[3] VXBR[0] VXIRQ[4] VBGO#[1] VBGI#[2] VXIRQ[7] VDD AD[37] AD[6] VSS AD[9] 25
Table 4.8 : Pinout for 324–pin Ceramic BGA Package
Table 4.7 and Table 4.8 map pin numbers to signal names. These tables should not be read as figures. For layout
purposes, please see Appendix-G.
A B C D E F G H J K L M N P R T U V W Y
1VSS VD[1] VD[7] VD[3] VSS VDD VSCON_DIR VDD PAR LRST# VDD VRBR#[1] PWRRST# AD[58] VDD PLL_TESTOUT 1
2VSS VD[22] VD[9] VD[16] VD[10] VD[6] VRBR#[3] VRBBSY# VSYSCLK AD[63] VSS AD[61] AD[27] AD[25] PLL_TESTSEL VRBR#[0] AD[57] VSS 2
3VD[21] VD[28] VDD VD[15] VD[19] VD[12] VDD VD[0] INT#[2] VXSYSFAIL VXBBSY VRBR#[2] VDD AD[26] AD[56] VDD INT#[1] VDD LCLK VSS 3
4VDD VD[26] VD[24] VD[13] VD[20] VD[14] VD[8] VD[2] INT#[4] INT#[7] AD[31] AD[29] AD[60] VDD INT#[3] VDD VSS AD[55] PAR64 AD[51] 4
5VD[30] VD[23] VDD VDD VD[18] VD[11] VD[5] VDD INT#[6] VBCLR# AD[30] AD[28] AD[59] AD[24] AD[23] VCOCTL AVSS AVDD PERR# VSS 5
6VAM[1] VWRITE# VD[25] VD[29] VIACK# VDD VD[17] VD[4] INT#[5] VSS VSS AD[62] VSS VSS VDD AD[54] AD[22] DEVSEL# AD[21] VSS 6
7VAM[5] VRBERR# VD[31] VDD VD[27] VSS SERR# AD[20] AD[53] VDD TRDY# VSS 7
8VDD VAM[3] VDD VAM[0] VAM_DIR VD_DIR AD[52] VDD AD[19] AD[18] ACK64# VDD 8
9 VDS#[1] VXBERR TMS VAM[4] VAM[2] VDS_DIR AD[50] AD[48] AD[17] VSS AD[49] CBE[7] 9
10 TCK TRST# VOE# VAS_DIR VDS#[0] TDI VSS VRSYSFAIL# AD[16] CBE[6] CBE[3] VDD 10
11 VDD VA_DIR VLWORD# VA[2] TDO VSS VSS CBE[0] CBE[2] CBE[5] TMODE[0] CBE[1] 11
12 VAS# VA[3] VA[4] VA[5] VA[1] VSLAVE_DIR AD[15] FRAME# VRIRQ#[5] IRDY# VSS CBE[4] 12
13 VDD VDTACK# VA[6] VA[8] VDD VA[10] VSS REQ64# AD[14] VDD AD[47] VDD 13
14 VSS VA[12] VDD VA[14] VA[11] VA[23] VSS AD[44] VDD AD[13] AD[46] GNT# 14
15 VA[9] VA[16] VA[18] VA[20] VA[22] VDD VSS INT#[0] AD[32] VBGI#[2] VSS AD[34] AD[4] AD[41] VDD AD[43] AD[45] AD[11] STOP# IDSEL 15
16 VA[13] VA[17] VRSYSRST# CLK64 VXSYSRST VA[27] VA[31] VXBR[1] VXIRQ[1] VBGO#[0] VBGI#[3] VRACFAIL# VDD AD[37] AD[8] VSS VDD VDD VIACKI# ENID 16
17 VA[7] VA[15] VA[21] VA[19] VDD VRIRQ#[2] VDD VIACKO# VXIRQ[3] VBGI#[1] VXIRQ[7] AD[1] VSS AD[38] AD[7] AD[9] VDD TMODE[1] RST# VDD 17
18 VSS VA[25] VDD VA[28] VDD VA[29] VRIRQ#[4] VDD VXIRQ[5] VBGO#[3] AD[0] VRIRQ#[7] AD[35] VDD TMODE[2] LOCK# AD[40] VDD AD[12] AD[42] 18
19 VSS VXBR[3] VA[30] VA[26] VRIRQ#[1] VXBR[0] VXIRQ[2] VXIRQ[6] VBGI#[0] AD[33] VRIRQ#[6] AD[2] VSS AD[39] VME_RESET# AD[6] AD[10] VSS 19
20 VA[24] VDD VRIRQ#[3] REQ# VXIRQ[4] VDD VBGO#[1] VBGO#[2] VDD VXBR[2] VDD VSS AD[36] AD[5] AD[3] VSS 20
!
DC Characteristics and Pin Assignments Universe II User Manual
4-14 Tundra Semiconductor Corporation
VMEbus Interface Components —Univ erse II User Manua l
Tundra Semiconductor Corporation App A-1
Appendix A Registers
The Universe II Control and Status Registers facilitate host system configuration and allow the
user to control Universe II operational charact er istics. The registers are divided into three
groups:
• PCI Configuration Space,
• VMEbus Configur ation and Status Registers, and
• Universe II Device Specific Status Registers.
The Univer se II re gister s have little-e ndian byte-ordering.
Figure A.1 belo w summarizes the supported register access mechanisms.
The bit combinations listed as "Reserv ed" must not be progr amme d. All bits listed as
"Reserv ed" must read back a value of zero.
PCI CONFIGURATION
SPACE
(PCICS)
UNIVERSE DEVICE
SPECIFIC REGISTERS
(UDSR)
4 Kbytes
VMEbus Configuration
and Status Registers
(VCSR)
Figu re A.1 : UCSR Access Mechanisms
Registers Universe II User Manual
App A-2 Tundra Semiconductor Corporation
Table A.1 below lists the Universe II registers by addre ss offset. The tables following the
regis ter map (Table A.2 to Table A.127) provide detailed descriptions of each re gister.
Table A.1 : Universe II Register Map
Offset Register Name
000 PCI Configuration Space ID Register PCI_ID
004 PCI Configuration Space Control and Status Regis-
ter PCI_CSR
008 PCI Configuration Class Register PCI_CLASS
00C PCI Config urati on Miscellaneous 0 Regist er PCI_MISC 0
010 PCI Configuration Base Address Re gister PCI_BS0
014 PCI Configurati on B a s e A ddres s 1 Register PCI_BS1
018-024 PCI U nimplemented
028 PCI Reserved
02C PCI Reserved
030 PCI Unimplemented
034 PCI Reserved
038 PCI Reserved
03C PCI Configuration Miscellaneous 1 Register PCI_MISC1
040-0FF PCI U nimplemented
100 PCI Target Image 0 Control Register LSI0_CTL
104 PCI Tar get Image 0 Base Address Regist er LSI0_BS
108 PCI Tar get Image 0 Bound Addr ess Register LSI0_BD
10C PCI Target Image 0 Translati on O ffset Re gister LSI0_TO
110 Reserved
114 PCI Target Image 1 Control Register LSI1_CTL
118 PCI Tar get Image 1 Base Address Regist er LSI1_BS
11C PCI Tar get Image 1 Bound Addr ess Register LSI1_BD
120 PCI Target Image 1 Transl ation Offset Re gister LSI1_TO
124 Reserved
128 PCI Target Image 2 Control Register LSI2_CTL
12C PCI Tar get Image 2 Ba s e A ddres s Regis ter LSI2_BS
130 PCI Tar get Image 2 Bound Addr ess Register LSI2_BD
134 PCI Target Image 2 Transl ation Offset Re gister LSI2_TO
138 Reserved
13C PCI Tar get Image 3 Control R e gister LSI3_CTL
140 PCI Tar get Image 3 Base Address Regist er LSI3_BS
144 PCI Tar get Image 3 Bound Addr ess Register LSI3_BD
148 PCI Target Image 3 Transl ation Offset Re gister LSI3_TO
Univer se II User Manual Regis ters
Tundra Semiconductor Corporation App A-3
14C-16C Reserved
170 Special Cycle Control Re gister SCYC_CTL
174 Special Cycle PCI Bus Address Register SCYC_ADDR
178 Special Cycle Swap/Compare Enable Register SCYC_EN
17C Spec ial C ycle Compare Data Register SCYC_CMP
180 Special Cycle Sw ap D ata Register SCYC_SWP
184 PCI Miscellaneous Register LMISC
188 Special PCI T arget Image Register SLSI
18C PCI Command Error Log Register L_CMDERR
190 PCI Address Error Log Register LAERR
194-19C Reserved
1A0 PCI Tar get Image 4 Control Register LSI4_CTL
1A4 PCI Target Ima ge 4 Base Address Regis ter LSI4_BS
1A8 PCI Target Ima ge 4 Bound Addres s Register LSI4_BD
1AC PCI Target Image 4 Transl ation Offset Re gister LSI4_TO
1B0 Reserved
1B4 PCI Target Image 5 Control Register LSI5_CTL
1B8 PCI Tar get Image 5 Base Address Register LSI 5_BS
1BC P CI Target Ima ge 5 Bound Addres s Register LSI5_BD
1C0 PCI Slave I mage 5 Trans lation O ffset Re gister LSI5 _TO
1C4 Reserved
1C8 PCI Target Image 6 Control Register LSI6_CTL
1CC P CI Target Ima ge 6 Base Address Regis ter LSI6_BS
1D0 PCI Target Ima ge 6 Bound Addres s Register LSI6_BD
1D4 PC I Target Image 6 Translation Offset Register LSI6_TO
1D8 Reserved
1DC PCI Target Image 7 Control Register LSI7_CTL
1E0 PCI Target Ima ge 7 B a s e A ddres s Register LSI7_BS
1E4 PCI Target Ima ge 7 B ound Addr ess Register LSI7_BD
1E8 PCI Tar get Image 7 Translati on O ffset Re gister LSI7_TO
1EC-1FC Reserved
200 DMA Transfer Control Register DCTL
204 D MA Transfer Byt e Count Register DTBC
208 DMA PCI Bus Address Register DL A
20C Reserved
210 DMA VMEbus Address Regist er DVA
214 Reserved
Table A.1 : Universe II Register Map (Continued)
Offset Register Name
Registers Universe II User Manual
App A-4 Tundra Semiconductor Corporation
218 DMA Co mmand Packet Pointer Register DCPP
21C Reserved
220 DMA General Control and S tatus Register DGCS
2 24 DMA Linked List U p date Enable Registe r D_LLUE
228-2FC Reserved
300 PCI Interrupt Enable Register LINT_EN
304 PCI Interrupt Status Regis ter LINT_STAT
308 PCI Interrupt Map 0 Re gister LINT_MAP0
30C PCI Interrupt Map 1 Register LINT_MAP1
310 VMEbus Interrupt Enable Register VINT_EN
314 VMEbus Interrupt Status Register VINT_STAT
318 VMEbus Interrupt Map 0 Register VINT_MAP0
31C VMEb us Inter rup t Map 1 Register VINT_MAP1
320 Interrupt Status/ID Out Register STATID
324 VIR Q1 STATUS/ID Register V1_STATID
328 VIR Q2 STATUS/ID Register V2_STATID
32C VIR Q3 STATUS /ID Register V3_STATID
330 VIR Q4 STATUS/ID Register V4_STATID
334 VIR Q5 STATUS/ID Register V5_STATID
338 VIR Q6 STATUS/ID Register V6_STATID
33C VIR Q7 STATUS /ID Register V7_STATID
340 PCI Interrupt Map 2 Re gister LINT_MAP2
344 VME Int errupt Map 1 Register VINT_MAP2
348 Mailbox 0 Register MBOX0
34C Mailbox 1 Register MBOX1
350 Mailbox 2 Register MBOX2
354 Mailbox 3 Register MBOX3
358 Semaphore 0 Regis ter SEMA0
35C Semaphor e 1 Register SEMA1
360-3FC Reserved
400 Master Control Register MAST_CTL
404 Miscell a neous Control Register MISC_CTL
408 Miscell a neous Status R egister MISC_STAT
40C User AM Codes Register USER_AM
410-EFC Reserved
F00 VMEbus Slave Image 0 Control Register VSI0 _CTL
F04 VMEbus Slave Image 0 Base Address Register VSI0_BS
Table A.1 : Universe II Register Map (Continued)
Offset Register Name
Univer se II User Manual Regis ters
Tundra Semiconductor Corporation App A-5
F08 VM Ebus Slave Ima ge 0 Bound Address Register VSI0_BD
F0C VMEbus Slave Image 0 Translation Offset Register VSI0_TO
F10 Reserved
F14 VMEbus Slave Image 1 Control Register VSI1 _CTL
F18 VMEbus Sla ve Image 1 Base Address Register VSI1_BS
F1C VMEbus Slave Image 1 Bound A ddress Register VS I1_BD
F20 VMEbus Slave Image 1 Translation Offset Register VSI1_TO
F24 Reserved
F28 VMEbus Slave Image 2 Control Register VSI2 _CTL
F2C VMEbus Slave Image 2 Base Address Register VSI2_BS
F30 VM Ebus Slave Ima ge 2 Bound Address Register VSI2_BD
F34 VMEbus Slave Image 2 Translation Offset Register VSI2_TO
F38 Reserved
F3C VME bus Slave Image 3 Control Register VSI3 _CTL
F40 VMEbus Sla ve Image 3 Base Address Register VSI3_BS
F44 VM Ebus Slave Ima ge 3 Bound Address Register VSI3_BD
F48 VMEbus Slave Image 3 Translation Offset Register VSI3_TO
F4C-F60 Reserved
F64 Location Monitor Control Regis ter LM_CTL
F68 Loc ation Monitor Base Address Register L M_BS
F6C Reserved
F70 V MEbus Register Access Image Control Register VRAI_ CT L
F74 VMEbus Register Access Image Base Address Register VRAI_BS
F78 Reserved
F7C Reserved
F80 VMEbus CSR Control Register VCSR_ CTL
F84 VME bus CSR Trans l ation O ffse t Regis te r V CSR_T O
F88 VMEbus AM Code Error Log Register V_AMERR
F8C V MEbus Address Error Log Register VAERR
F90 VMEbus Slave Image 4 Control Register VSI4 _CTL
F94 VMEbus Sla ve Image 4 Base Address Register VSI4_BS
F98 VM Ebus Slave Ima ge 4 Bound Address Register VSI4_BD
F9C VMEbus Slave Image 4 Translation Offset Register VSI4_TO
FA0 Reserved
FA4 VME bus Slave Image 5 Control Register VSI5 _C TL
FA8 VMEbus Slave Image 5 Base Address Register VSI5_BS
FA C VMEbus Slave Image 5 Bound Address Register VS I5_BD
Table A.1 : Universe II Register Map (Continued)
Offset Register Name
Registers Universe II User Manual
App A-6 Tundra Semiconductor Corporation
FB0 VMEbus Slave Image 5 Translation Offset Register VSI5_TO
FB4 Reserved
FB8 VME bus Slave Image 6 Control Register VSI6 _CTL
FBC VMEbus Slave Image 6 Base Address Register VSI6_BS
FC0 VMEbus Slave Image 6 Bound A ddress Register VS I6_BD
FC4 VMEbus Slave Image 6 Translation Offset Register VSI6_TO
FC8 Reserved
FCC VME bus Slave Image 7 Control Register VSI7 _CTL
FD0 VMEbus Slave Image 7 Base Address Register VSI7_BS
FD4 VMEbus Sla ve Ima ge 7 Bound A ddress R egister VSI7_BD
FD8 VMEbus Slave Image 7 Translation Offset Register VSI7_TO
FDC-FEC Reserved
FF0 VME CR/ CSR Reserv e d
FF4 VMEbu s CSR Bit Clear Register VCSR_CLR
FF8 VMEbu s CSR Bit Set Register VCSR_SET
FFC VMEbus CSR Base Address Register VCSR_BS
Table A.1 : Universe II Register Map (Continued)
Offset Register Name
Univer se II User Manual Regis ters
Tundra Semiconductor Corporation App A-7
Table A.2 : PCI Configurat ion Space ID Register (PCI_ID)
Register Name: PCI_ID Offset:000
Bits Function
31-24 DID
23-16 DID
15-08 VID
07-00 VID
PCI_ID Description
Name Type Reset By Reset State Functio n
DID[15:0] R all 0 Device ID - Tundra allocated device identifier
VID [ 15:0] R all 10E3 Ven dor ID - PCI SIG allocat ed ven dor identifier
Registers Universe II User Manual
App A-8 Tundra Semiconductor Corporation
Table A.3 : PCI Configurat ion Spac e Cont ro l and St atus Register
(PCI_CSR)
Register Name: PCI_CSR Offset:004
Bits Function
31-24 D_PE S_SERR R_MA R_TA S_TA DEVSEL DP_D
23-16 TFB BC PCI Reserved
15-08 PCI Reserved MFBBC SERR_EN
07-00 WAIT PERESP VGAPS MWI_EN SC BM MS IOS
PCI_CSR Description
Name Type Re set By Reset S tat e Functio n
D_PE R/Write 1
to Clear all 0 Detected Parity Error
0=N o parity err or, 1=Parity error
This bit is always set by the Universe II when the PCI master
interface detects a data parity error or the PCI target interface
de tects address or data pa ri ty error s .
S_SERR R/Write 1
to Clear all 0 Si gnalled SERR#
0=SERR# not a sserted, 1=SERR# asserted.
The Universe II PCI target interf ace s ets this bit when it asserts
SERR# to signal an address parity error. SERR_EN must be set
be fo re SERR# can be asser ted.
R_MA R/Write 1
to Clear all 0 Receiv ed Master - A bort
0= Mas ter di d not gene rate Master-Abort, 1=Master generated
Master-Abort
The Universe II PCI master interface sets this bit when a
transaction it initiated had to be terminated with a Master-Abort.
R_TA R/Write 1
to Clear all 0 Receive d Target- A bort
0= Mas ter did not detect Target-Abor t, 1=Mas ter detected Tar get-
Abort.
The Universe II PCI master interface sets this bit when a
transaction it initiated was terminated with a Target-Abort.
S_TA R/Write 1
to Clear all 0 Signalled Target-Abort
0=Target did not terminate transaction with T arget-
Abort,1=Target terminated transaction with Target-Abort.
DEVSEL R all 01 Device Select Timing
The Universe II is a medium speed dev ice
DP_D R/Write 1
to Clear all Data Parity Detected
0= Mas ter did not detect/ge nerate data parit y error, 1=Mast er
de tected/ generat ed data pa rity error.
The Universe II PCI master interface sets this bit if the Parity
Error Response bit is set, it is the master of transaction in which
it asserts PERR#, or the addressed target asserts PERR#.
TFBBC R all 0 Target Fast Back to Back Capab le
Universe II cannot accept Back to B ack cycles from a different
agent.
Univer se II User Manual Regis ters
Tundra Semiconductor Corporation App A-9
If the VCSR or LSI0 powe r-up options are e nabled, these bits are not diabled after reset.
The Univer se II only rejects PCI addresses with parity errors in the e vent that both the
PERESP and SERR_EN bits are programmed to a value of 1.
MFBBC R all 0 Master Fast B ack to Back Enable
0= no f a s t bac k- to-back tran s actions
The Universe II master never gener a tes fast ba ck to back
transactions.
SERR_ EN R/W all 0 SE RR# Enable
0= Disa ble SE RR# driver, 1=E nable SERR# driver.
Setting this and PERESP allows the Universe II PCI target
interfa ce to report addre ss parity errors with SERR# .
WAIT R all 0 Wait Cycle Control
0=N o address/data stepping
PERESP R/W all 0 Parity Error Response
0= Disa ble, 1=Enabl e
Controls t he U nivers e II respons e to data and address pari ty
errors. When enabled, it allows the assertion of PERR# to report
da ta parity errors. When this bit and SER R_ EN are asserted, the
Univ erse II can report address parity errors on SERR#. Universe
II parity gene ratio n is unaffec ted by this bi t.
VGAPS R all 0 VGA Palette Snoop
0=Disable
The Universe I I treats palet te accesses lik e all other acc es s es .
MWI_EN R all 0 Memory Write and Invalidate Enable
0=Disable
The Universe II PCI master interface never generates a Memory
Wr ite and Invalid at e comma n d.
SC R all 0 Sp ecial Cycl es
0=Disable
The Universe I I PCI t arget interface never responds to special
cycles.
BM R/W PWR VME see note 1 Maste r Enable
0= Disa ble, 1=Enabl e
For a VMEbus slave image to respond to an incoming cycle, this
bit must be set. If this bit is cleared while there is data in the
VMEbus Slav e Posted Write FIFO, the data will be written to the
PCI bus but no fur the r data wil l be accep ted into thi s FI FO until
the bit is set.
MS R/W PWR VME see note 1 Target Memory Enable
0= Disa ble, 1=Enabl e
IOS R/W PWR VME see note 1 Targ et IO En able
0= Disa ble, 1=Enabl e
PCI_CSR Description
Name Type Re set By Reset S tat e Functio n
Registers Universe II User Manual
App A-10 Tundra Semiconductor Corporation
Table A.4 : PCI Configurat ion Class Regis ter (PCI_CL A SS)
Register Name: PCI_CLASS Offset:008
Bits Function
31-24 BASE
23-16 SUB
15-08 PROG
07-00 RID
PCI_CLASS Description
Name Type Re set By Reset S tat e Functio n
BASE [7:0] R all 06 Base Class Code
The Universe II is defined as a PCI bridge de vice
SUB [7:0] R all 80 Sub Class Co de
The Universe II sub-class i s "ot her bridge device"
PROG [7:0] R all 00 Pr ogr amming Interface
The Universe I I does not have a st andardized register-level
programming interface
RID [7:0] R all 01 Revision ID
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-11
Table A.5 : PCI Configurat ion Miscellaneous 0 Register (PCI_MISC0)
The Universe II is not a multi-function device .
Register Name: PCI_MISC0 Offset:00C
Bits Function
31-24 BISTC SBIST PCI Reserved CCODE
23-16 MFUNCT LAYOUT
15-08 LTIMER 0 0 0
07-00 PCI Unimplemented
PCI_MIS C0 Descrip tio n
Name Type Reset By Reset State Functio n
BISTC R all 0 The Univ erse II is not BIST Capable
SBIST R all 0 Start BIST
The Universe II is not BIST capable
CC OD E R all 0 Co m pletion C o de
The Universe II is not BIST capable
MFU N CT R all 0 Multifunction Device
0=No, 1=Yes
The Universe II is not a multi-function device.
LAYOUT R all 0 Configura tion Space Layout
LTIMER [7:3] R/W all 0 Latency Timer: The latency timer has a resolution of 8 clocks
Registers Universe II User Manual
App A-12 Tundra Semiconductor Corporation
Table A.6 : PCI Configurat ion Bas e Address Register (PCI_BS0)
This register specifies the 4 Kbyte aligned base addre ss of the 4 Kbyte Universe II register
space on PCI.
A power-up option determines if the registers are mapped into Memory or I/O space in
relation to this base address. (See “Power-Up Options” on page 2-115 ). If mapped into
Memory space, the user is free to locate the re gisters anywhere in the 32-bit address space.
• When the VA[1] pin is sampled low at power-up, the PCI_BS0 register’s SPACE bit
is set to “1”, which signifies I/O space, and the PCI_BS1 register’s SPACE bit is set
to “0”, which signifies memory space.
• When VA[1] is sampled high at power-up, the PCI_BS0 register’s SPACE register’s
bit is set to “0”, which signifies Memory space, and the PCI_BS1 register’s SPACE
bit is set to “1”, which signifies I/O space.
A write must occur to this register before the Universe II De vice Specific Registers can be
accessed. This write can be performed with a PCI configuration transaction or a VMEbus
register access.
Register Name: PCI_BS0 Offset:010
Bits Function
31-24 BS
23-16 BS
15-08 BS 0000
07-000000000SPACE
PCI_BS0 Description
Name Type Reset By Reset State Function
BS[31:12] R/W all 0 Base Addr ess
SPACE R all Power-up
Option PCI Bus Address Space
0=Me mo ry, 1=I/O
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-13
Table A.7 : PCI Configurat ion Bas e Address 1 Register (PCI_BS1)
This register specifies the 4 KByte aligned base address of the 4 KByte Universe II register
space in PCI .
A power-up option determines the value of the SPACE bit. This determines whether the
re gis ters are mapped into Memory or I/O space i n relation to this base address. (See “Power-
Up Options” on page 2-115). If mapped into Memory space, the user is free to locate the
Univ erse registers anywhere in the 32-bit address space. If PCI_BS0 is mapped to Memory
space, PCI_BS1 is mapped to I/O space; if PCI_BS0 is mapped to I/O space, t hen PCI_BS1 is
mapped to Memory space.
• When the VA[1] pin is sampled low at power-up, the PCI_BS0 register’s SPACE bit
is set to “1”, which signifies I/O space, and the PCI_BS1 register’s SPACE bit is set
to “0”, which signifies memory space.
• When VA[1] is sampled high at power-up, the PCI_BS0 register’s SPACE register’s
bit is set to “0”, which signifies Memory space, and the PCI_BS1 register’s SPACE
bit is set to “1”, which signifies I/O space.
A write must occur to this register before the Universe II De vice Specific Registers can be
accessed. This write can be performed with a PCI configuration transaction or a VMEbus
register access.
The SPACE bit in this registe r is an in version of the SPACE fie ld in PCI_BS0.
Register Name: PCI_BS1 Offset:014
Bits Function
31-24 BS
23-16 BS
15-08 BS 0000
07-000000000SPACE
PCI_BS1 Description
Name Type Reset By Reset State Function
BS[31:12] R/W all 0 Base Addr ess
SPACE R all Power-up
Option PCI Bus Address Space
0=Me mo ry, 1=I/O
Registers Universe II User Manual
App A-14 Tundra Semiconductor Corporation
Table A.8 : PCI Configurat ion Miscellaneous 1 Register (PCI_MISC1)
The MIN_GNT parameter assumes the Univ erse II master is transferring an aligned bur st size
of 64 byte s to a 32-bit target with no wait states. This would require roughly 20 clocks (at a
clock frequency of 33 MHz, this is about 600 ns). MIN_GNT is set to three, or 750 ns.
Register Name: PCI_MISC1 Offset:03C
Bits Function
31 -24 MA X_ LAT [7 :0}
23-16 MIN_GNT [7:0}
15-08 INT_PIN [7:0}
07-00 INT_LINE [7:0}
PCI_MIS C1 Descrip tio n
Name Type Reset By Reset State Function
MAX_LAT[7:0] Rall 0 Maximum Latency: This device has no special latency
requirements
MIN_GNT[7:0} Rall 0000 0011 Minimum Grant:.250 ns units
INT_PIN[7:0]Rall 00000001 Inter ru pt Pin: Universe II pin INT # [0] has a PC I compli a nt
I/O buf fer
INT_LINE[7:0]R/W all 0 Interrupt Line: used by some PCI systems to record interrupt
routing information
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-15
Table A.9 : PCI Target Image 0 Contr ol (LSI 0_CTL)
In the PCI Target Image Control register, setting the VCT bit will only have effect if the VAS
bits are programmed for A24 or A32 space and the VDW bits are programmed for 8-bit, 16-
bit, or 32-bit.
If VAS bits are programmed to A24 or A32 and the VDW bits are programmed for 64-bit, the
Univ erse II may perform MBLT transfers independent of the state of the VCT bi t.
The setting of the PWEN bit is ignored if the LAS bit is programmed for PCI Bus I/O Space,
forcing all transactions through this image to be coupled.
Register Name: LSI0_CTL Offset:100
Bits Function
31-24 EN PWEN Reserved
23-16 VDW Reserved VAS
15-08 Reserved PGM Reserved SUPER Reserved VCT
07-00 Reserved LAS
LSI0_CTL Description
Name Type Re set By Reset S tat e Functio n
EN R/W all Power-up
Option Image Enable
0= Disa ble, 1=Enabl e
PWEN R/W all 0 Posted Write Enable
0= Disa ble, 1=Enabl e
VDW R/W all 10 VME bus Maximum D ata width
00=8-bit data width, 01=16 b it data wi dth, 10=32 - bit data width,
11=64-bit data wi dth
VAS R/W all Power-up
Option VMEbus Address Space
000=A16, 001=A24, 010=A32, 011= Reserved, 100=Reserved
101=CR/CS R, 110=Us er1, 111=User2
PGM R/W all 0 Progr am/Data AM C ode
0= Data, 1=Program
SUPER R/W all 0 Supervisor/User AM Code
0= No n- Privileged, 1=Supervi s or
VCT R/W all 0 VMEbus Cycle Type
0= No BLTs on VMEbus , 1=Single BLTs on VMEbus
LAS R/W all Power-up
Option PCI Bus Memory Space
0=PCI Bus Memory Space, 1=PCI Bus I/O Space
Registers Universe II User Manual
App A-16 Tundra Semiconductor Corporation
Table A.10 : P CI Target Image 0 Base A ddress Register (LSI0_BS)
The base address specifies the lowest address in the address ra nge that will be decoded.
The base address for PCI Target Im age 0 and PCI Target Image 4 have a 4Kbyte resolut ion.
PCI Tar get Images 1, 2, 3, 5, 6, and 7 ha ve a 64Kbyte resolution.
Register Name: LSI0_BS Offset:104
Bits Function
31-24 BS
23-16 BS
15-08 BS Reserved
07-00 Reserved
LSI0_BS Description
Name Type Rese t By Reset State Function
BS[31:28] R/W all Power-up
Option Base Address
BS[27:12] R/W all 0 Base Add re s s
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-17
Table A.11 : PCI Targ et Image 0 Bound Address Register (LS I0_BD)
The addresses decoded in a slave image are those which are greater than or equal to the base
address and less than the bound re gister. If the bound address is 0, then the addresses decoded
are those greater than or equal to the base address.
The bound address for PCI Target Image 0 and PCI Target Image 4 have a 4Kbyte resolution.
PCI Tar get Images 1, 2, 3, 5, 6, and 7 ha ve a 64Kbyte resolution.
Register Name: LSI0_BD Offset:108
Bits Function
31-24 BD
23-16 BD
15-08 BD Reserved
07-00 Reserved
LSI0_BD Description
Name Type Rese t By Reset State Function
BD[31:28] R/W all Power-up
Option Bound A ddress
BD[27:12] R/W all 0 Bound Address
Registers Universe II User Manual
App A-18 Tundra Semiconductor Corporation
Table A.12 : PCI Target Image 0 Translation Offset (LSI0_TO)
The translation offset for PCI Target Image 0 and PCI Target Image 4 ha v e a 4Kbyte
resolution. PCI Target Images 1, 2, 3, 5, 6, and 7 have a 64Kbyte resolution.
Address bits [31:12] generated on the VMEbus in res ponse to an image decode are a two’s
complement addition of address bits [31:12] on the PCI Bus and bits [31:12] of the image’s
translation offset.
Register Name: LSI0_TO Offset:10C
Bits Function
31-24 TO
23-16 TO
15-08 TO Reserved
07-00 Reserved
LSI0_TO Description
Name Type Reset By Reset State Function
TO[31:12] R/W all 0 Tran sla tion Offset
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-19
Table A.13 : PCI Tar get Image 1 Cont rol (LSI1_CTL)
In the PCI Target Image Control register, setting the VCT bit will only have effect if the VAS
bits are programmed for A24 or A32 space and the VDW bits are programmed for 8-bit, 16-
bit, or 32-bit.
If VAS bits are programmed to A24 or A32 and the VDW bits are programmed for 64-bit, the
Univ erse II may perform MBLT transfers independent of the state of the VCT bi t.
The setting of the PWEN bit is ignored if the LAS bit is programmed for PCI Bus I/O Space,
forcing all transactions through this image to be coupled.
Register Name: LSI1_CTL Offset:114
Bits Function
31-24 EN PWEN Reserved
23-16 VDW Reserved VAS
15-08 Reserved PGM Reserved SUPER Reserved VCT
07-00 Reserved LAS
LSI1_CTL Description
Name Type Re set By Reset S tat e Functio n
EN R/W all 0 Im age Enab le
0= Disa ble, 1=Enabl e
PWEN R/W all 0 Posted Write Enable
0= Disa ble, 1=Enabl e
VDW R/W all 10 VMEb us Maximum Dat awidth
00=8-bit data width, 01=16 b it data wi dth, 10=32 - bit data width,
11=64-bit data wi dth
VAS R/W all 0 VMEbus Address Space
000=A 16, 001=A24, 0 10=A32, 011= Reserved, 100=Res e r ved,
101=CR/CS R, 110=Us er1, 111=User2
PGM R/W all 0 Program/ D ata AM Code
0= Data, 1=Program
SUPER R/W all 0 Supervisor/User AM Code
0= No n- Privileged, 1=Supervi s or
VCT R/W all 0 VMEbus C ycle Type
0= no BLTs on VMEb us, 1 = BLTs on VMEb us
LAS R/W all 0 PCI Bus Memory Space
0=PCI Bus Memory Space, 1=PCI Bus I/O Space
Registers Universe II User Manual
App A-20 Tundra Semiconductor Corporation
Table A.14 : P CI Target Image 1 Base A ddress Register (LSI1_BS)
The base address specifies the lowest address in the address ra nge that will be decoded.
Register Name: LSI1_BS Offset:118
Bits Function
31-24 BS
23-16 BS
15-08 Reserved
07-00 Reserved
LSI1_BS Description
Name Type Rese t By Reset State Function
BS[31:1 6] R/W all 0 Base Address
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-21
Table A.15 : PCI Targ et Image 1 Bound Address Register (LS I1_BD)
The addresses decoded in a slave image are those which are greater than or equal to the base
address and less than the bound re gister. If the bound address is 0, then the addresses decoded
are those greater than or equal to the base address.
The bound address for PCI Target Image 0 and PCI Target Image 4 have a 4Kbyte resolution.
PCI Tar get Images 1, 2, 3, 5, 6, and 7 ha ve a 64Kbyte resolution.
Register Name: LSI1_BD Offset:11C
Bits Function
31-24 BD
23-16 BD
15-08 Reserved
07-00 Reserved
LSI1_BD Description
Name Type Rese t By Reset State Function
BD[ 31:16] R/W all 0 Boun d A ddres s
Registers Universe II User Manual
App A-22 Tundra Semiconductor Corporation
Table A.16 : PCI Target Image 1 Translation Offset (LSI1_TO)
Address bits [31:16] ge nera ted on the VMEbus in res ponse to an image decode are a two’s
complement addition of address bits [31:16] on the PCI Bus and bits [31:16] of the image’s
translation offset.
Register Name: LSI1_TO Offset:120
Bits Function
31-24 TO
23-16 TO
15-08 Reserved
07-00 Reserved
LSI1_TO Description
Name Type Reset By Reset State Function
TO[31:16] R/W all 0 Translation offset
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-23
Table A.17 : PCI Tar get Image 2 Cont rol (LSI2_CTL)
In the PCI Target Image Control register, setting the VCT bit will only have effect if the VAS
bits are programmed for A24 or A32 space and the VDW bits are programmed for 8-bit, 16-
bit, or 32-bit.
If VAS bits are programmed to A24 or A32 and the VDW bits are programmed for 64-bit, the
Univ erse II may perform MBLT transfers independant of the state of the VCT bi t.
The setting of the PWEN bit is ignored if the LAS bit is programmed for PCI Bus I/O Space,
forcing all transactions through this image to be coupled.
Register Name: LSI2_CTL Offset:128
Bits Function
31-24 EN PWEN Reserved
23-16 VDW Reserved VAS
15-08 Reserved PGM Reserved SUPER Reserved VCT
07-00 Reserved LAS
LSI2_CTL Description
Name Type Re set By Reset S tat e Functio n
EN R/ W a ll 0 Image Enab le
0= Disa ble, 1=Enabl e
PWEN R/W all 0 Posted Write Enable
0= Disa ble, 1=Enabl e
VDW R/W all 10 VME bus Maximum D ata width
00=8-bit data width, 01=16 b it data wi dth, 10=32 - bit data width,
11=64-bit data wi dth
VAS R/W all 0 VMEbus Address Space
000=A 16, 001=A24, 0 10=A32, 011= Reserved, 100=Res e r ved,
101=CR/CS R, 110=Us er1, 111=User2
PGM R/W all 0 Progr am/Data AM C ode
0= Data, 1=Program
SUPER R/W all 0 Supervisor/User AM Code
0= No n- Privileged, 1=Supervi s or
VCT R/W all 0 VMEbus Cycle Type
0= no BLTson VME bus, 1=BLTs on V MEbus
LAS R/W all 0 PCI Bus Memory Space
0=PCI Bus Memory Space, 1=PCI Bus I/O Space
Registers Universe II User Manual
App A-24 Tundra Semiconductor Corporation
Table A.18 : P CI Target Image 2 Base A ddress Register (LSI2_BS)
The base address specifies the lowest address in the address ra nge that will be decoded.
Register Name: LSI2_BS Offset:12C
Bits Function
31-24 BS
23-16 BS
15-08 Reserved
07-00 Reserved
LSI2_BS Description
Name Type Rese t By Reset State Function
BS[31:1 6] R/W all 0 Base Address
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-25
Table A.19 : PCI Targ et Image 2 Bound Address Register (LS I2_BD)
The addresses decoded in a slave image are those which are greater than or equal to the base
address and less than the bound re gister. If the bound address is 0, then the addresses decoded
are those greater than or equal to the base address.
Register Name: LSI2_BD Offset:130
Bits Function
31-24 BD
23-16 BD
15-08 Reserved
07-00 Reserved
LSI2_BD Description
Name Type Rese t By Reset State Function
BD[ 31:16] R/W all 0 Boun d A ddres s
Registers Universe II User Manual
App A-26 Tundra Semiconductor Corporation
Table A.20 : PCI Target Image 2 Translation Offset (LSI2_TO)
Address bits [31:16] generated on the VMEbus in res ponse to an image decode are a two’s
complement addition of address bits [31:16] on the PCI Bus and bits [31:16] of the image’s
translation offset.
Register Name: LSI2_TO Offset:134
Bits Function
31-24 TO
23-16 TO
15-08 Reserved
07-00 Reserved
LSI2_TO Description
Name Type Reset By Reset State Function
TO[31:16] R/W all 0 Translation offset
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-27
Table A.21 : PCI Tar get Image 3 Cont rol (LSI3_CTL)
In the PCI Target Image Control register, setting the VCT bit will only have effect if the VAS
bits are programmed for A24 or A32 space and the VDW bits are programmed for 8-bit, 16-
bit, or 32-bit.
If VAS bits are programmed to A24 or A32 and the VDW bits are programmed for 64-bit, the
Univ erse II may perform MBLT transfers independent of the state of the VCT bi t.
The setting of the PWEN bit is ignored if the LAS bit is programmed for PCI Bus I/O Space,
forcing all transactions through this image to be coupled.
Register Name: LSI3_CTL Offset:13C
Bits Function
31-24 EN PWEN Reserved
23-16 VDW Reserved VAS
15-08 Reserved PGM Reserved SUPER Reserved VCT
07-00 Reserved LAS
LSI3_CTL Description
Name Type Re set By Reset S tat e Functio n
EN R/ W a ll 0 Image Enab le
0= Disa ble, 1=Enabl e
PWEN R/W all 0 Posted Write Enable
0= Disa ble, 1=Enabl e
VDW R/W all 10 VME bus Maximum D ata width
00=8-bit data width, 01=16 b it data wi dth, 10=32 - bit data width,
11=64-bit data wi dth
VAS R/W all 0 VMEbus Address Space
000=A 16, 001=A24, 0 10=A32, 011= Reserved, 100=Res e r ved,
101=CR/CS R, 110=Us er1, 111=User2
PGM R/W all 0 Progr am/Data AM C ode
0= Data, 1=Program
SUPER R/W all 0 Supervisor/User AM Code
0= No n- Privileged, 1=Supervi s or
VCT R/W all 0 VMEbus Cycle Type
0= no BLTs on VMEb us, 1 = BLTs on VMEb us
LAS R/W all 0 PCI Bus Memory Space
0=PCI Bus Memory Space, 1=PCI Bus I/O Space
Registers Universe II User Manual
App A-28 Tundra Semiconductor Corporation
Table A.22 : P CI Target Image 3 Base A ddress Register (LSI3_BS)
The base address specifies the lowest address in the address ra nge that will be decoded.
Register Name: LSI3_BS Offset:140
Bits Function
31-24 BS
23-16 BS
15-08 Reserved
07-00 Reserved
LSI3_BS Description
Name Type Rese t By Reset State Function
BS[31:1 6] R/W all 0 Base Address
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-29
Table A.23 : PCI Targ et Image 3 Bound Address Register (LS I3_BD)
The addresses decoded in a slave image are those which are greater than or equal to the base
address and less than the bound re gister. If the bound address is 0, then the addresses decoded
are those greater than or equal to the base address.
Register Name: LSI3_BD Offset:144
Bits Function
31-24 BD
23-16 BD
15-08 Reserved
07-00 Reserved
LSI3_BD Description
Name Type Rese t By Reset State Function
BD[ 31:16] R/W all 0 Boun d A ddres s
Registers Universe II User Manual
App A-30 Tundra Semiconductor Corporation
Table A.24 : PCI Target Image 3 Translation Offset (LSI3_TO)
Address bits [31:16] generated on the VMEbus in res ponse to an image decode are a two’s
complement addition of address bits [31:16] on the PCI Bus and bits [31:16] of the image’s
translation offset.
Register Name: LSI3_TO Offset:148
Bits Function
31-24 TO
23-16 TO
15-08 Reserved
07-00 Reserved
LSI3_TO Description
Name Type Reset By Reset State Function
TO[31:16] R/W all 0 Translation offset
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-31
Table A.25 : Special Cycle Control Register (SCYC_CTL)
The special cycle generator will generate an ADOH or RMW cycle for the 32-bit PCI Bus
address which matches the programmed address in SCYC_ADDR, in the address space
specif ied in the LAS f ield of the SCYC_CTL register. A Read-Modify-Write command is
initiat ed by a rea d to the s pecified address. Address-Only c ycle s are initia ted by either read or
write cycles.
Register Name: SCYC_CTL Offset: 170
Bits Function
31-24 Reserved
23-16 Reserved
15-08 Reserved
07-00 Reserved LAS SCYC
SCYC_CTL Description
Name Type Rese t By Reset State Function
LAS R/W all 0 PCI Bus Address Space
0=PCI Bus Memory Space, 1=PCI Bus I/O Space
SCYC R/W all 0 Sp ecial Cycle
00=Disable, 01=RMW, 10=ADOH, 11=Re served
Registers Universe II User Manual
App A-32 Tundra Semiconductor Corporation
Table A.26 : Special Cycle PCI Bus Address Register (SCYC_ADDR)
This re gister designates the special cycle address. This address must appear on the PCI Bus
during the address phase of a transfer for the Special Cycle Generator to perform its function.
Whene ver the addresses match, the Universe II does not respond with ACK64#
Register Name: SCYC_ADDR Offset: 174
Bits Function
31-24 ADDR
23-16 ADDR
15-08 ADDR
07-00 ADDR Reserved
SCYC_ADDR Description
Name Type Reset By Reset State Function
ADDR[31:2] R/W all 0 Address
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-33
Table A.27 : Special Cycle Swap/Compare Enable Register (SCYC_EN)
The bits enabled in this register determine the bits that will be involved in the compare and
swap operations for VME RMW cycles.
Register Name: SCYC_EN Offset: 178
Bits Function
31-24 EN
23-16 EN
15-08 EN
07-00 EN
SCYC_EN Description
Name Type Reset By Reset State Function
EN[31:0] R/W all 0 Bit Enable
0=Disable, 1=Enable
Registers Universe II User Manual
App A-34 Tundra Semiconductor Corporation
Table A.28 : Special Cycle Compare Data Register (SCYC_CMP)
The data returned from the read portion of a VMEb us RMW is compared with the contents of
this register. SCYC_EN is used to cont rol which bits are compared.
Register Name: SCYC_CMP Offset: 17C
Bits Function
31-24 CMP
23-16 CMP
15-08 CMP
07-00 CMP
SCYC_CMP Description
Name Type Rese t By Reset State Function
CMP[31:0] R/W all 0 The data returned from the VMEbus is compared with the
contents of this re gister.
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-35
Table A.29 : Special Cycle Swap Data Register (SCYC_SWP)
If enabled bits matched with the value in the compare register, then the contents of the s wap
data re gister is written back to VME. SCYC_EN is used to control which bits are written back
to VME.
Register Name: SCYC_SWP Offset: 180
Bits Function
31-24 SWP
23-16 SWP
15-08 SWP
07-00 SWP
SCYC_SWP Description
Name Type Reset By Reset State Function
SW P[3 1:0] R/W a l l 0 Sw a p da ta
Registers Universe II User Manual
App A-36 Tundra Semiconductor Corporation
Table A.30 : PCI Miscellane ous Register (LMISC)
The Univ er se II uses CWT to determine how long to hold ownership of the VMEbus after
processing a coupled trans action. The timer is restarted each time the Universe II processes a
coupled transaction. If this timer expi res, the PCI Slave Channel releases the VMEbus.
De vice beha viour is unpredictable if CWT is changed during coupled c ycle acti vity.
This register can only be set at configuration or after disabling all PCI Slave Images.
Regis ter Name: L MISC Offset:184
Bits Function
31-24 CRT[3:0] Reserved CWT
23-16 Reserved
15-08 Reserved
07-00 Reserved
SLSI Descr iption
Name Type Re set By Reset S tat e Functio n
CRT[3:0] R/W all 0000 CRT
This field is provided for backwa rd comp atib ilit y with the
Univ erse I. It has no effect on the operation of the U niverse I I.
CWT [2 :0] R/W all 000 Coupled Window Timer
000=D isabl e - r elea se af ter firs t co upled tran sacti on, 00 1=1 6 P CI
Clo cks , 010=32 PCI Clocks, 011=64 PCI Clock s , 100=128 PCI
Clo cks, 101=246 PCI Clocks, 110=512 PCI Clocks,
others=Reserved
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-37
Table A.31 : Special PC I Target Image (SLSI)
This re gister fully specifies an A32 capable special PCI Target Image. The base is
programmable to a 64 Mbyte alignment, and the size is fixed at 64 Mbytes. Incoming address
lines [31:26] (in Memory or I/O) must match this field for the Universe II to decode the
access. This special PCI Target Image has lower prior i ty than any other PC I Target I mage.
The 64 Mb yte s of the SLSI is partitioned into four 16 M byte regions, number ed 0 to 3 (0 is at
the lowest address). PCI address bits [25:24] are used to sele ct regions. The top 64 Kbyte of
each region is mapped to VMEbus A16 space, and the rest of each 16 Mbyte re gion is mapped
to A24 space.
Regist er Name: SLSI Offset:188
Bits Function
31-24 EN PWEN Reserved
23-16 VDW Reserved
15-08 PGM SUPER
07-00 BS Reserved LAS
SLSI Description
Name Type Re set By Reset S tat e Functio n
EN R/W all 0 Im age Enab le
0= Disa ble, 1=Enabl e
PWEN R/W all 0 Posted Write Enable
0= Disa ble, 1=Enabl e
VDW [3:0] R/W all 0 VMEbus Maximum Datawidth
Each of the four bits s pecif ies a data w idth for the corresponding
16 MB yte r e gion. Lo w or der b its co rr espon d to t he lo wer addr ess
regions.
0=16-bit, 1=32- bit
PGM [3:0] R/W all 0 Program/ D ata AM Code
Each of the four bits specifies Prog ra m/Data AM code f or the
corresponding 16 MByt e region. Lo w or der bit s corres pond to
the lower address re gions.
0= Data, 1=Program
SUPER [3:0] R/W all 0 Supervisor/User AM Code
Each of the fou r bits speci fies Super visor/ U s er AM code fo r the
corresponding 16 MByt e region. Lo w or der bit s corres pond to
the lower address re gions.
0= No n- Privileged, 1=Supervi s or
BS [5:0] R/W all 0 Base Add ress
Specifies a 64 MByte aligned base address for this 64 MByte
image.
LAS R/W all 0 PCI Bus Address Space
0=PCI Bus Memory Space, 1=PCI Bus I/O Space
Registers Universe II User Manual
App A-38 Tundra Semiconductor Corporation
The user can use the PGM, SUPER and VDW fields t o specif y the AM code a nd the
maximum port size for each region. The PGM field is ignored for the portion of each region
mapped to A16 space.
No block transf er AM codes are generated.
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-39
Table A.32 : PCI Command Error Log Register (L_CMDERR)
The Univ er se II PCI Master Int erf ace is responsible for logging errors under the following
conditions:
• a posted write transaction re sult s in a targe t abort,
• a posted write transaction re sult s in a master abort, or
• a ma ximum retry counter expires during re try of posted write transaction.
This register logs the command information.
Regist er Name: L_CMDERR Offset: 18C
Bits Function
31-24 CMDERR M_ERR Reserved
23-16 L_STAT Reserved
15-08 Reserved
07-00 Reserved
L_CMDERR Description
Name Type Reset By Reset State Functio n
CMDERR
[3:0] Rall 0111 PCI Command Error Log
M_ERR R all 0 Multiple Error Occurred
0= Si ngle error, 1 =A t l eas t one error has occurred s ince the logs
were frozen.
L_STAT R/W all 0 PCI Error Log Status
Reads:
0= logs invalid, 1= logs are valid and error log ging halt ed
Writes:
0=no effect, 1=clears L _STAT and enable s error loggi ng
Registers Universe II User Manual
App A-40 Tundra Semiconductor Corporation
Table A.33 : PCI Addr es s Error Log (LAERR)
The starting address of an errored PCI transaction is logged in this register under the following
conditions:
• a posted write transaction re sult s in a targe t abort,
• a posted write transaction re sult s in a master abort, or
• a ma ximum retry counter expires during re try of posted write transaction.
Contents are qualified by bit L_STAT of the L_CMDERR register.
Regis ter Name: L AERR Offset: 190
Bits Function
31-24 LAERR
23-16 LAERR
15-08 LAERR
07-00 LAERR
LAERR Description
Name Type Reset By Reset State Functio n
LAER R [31:0] R all 0 PCI address error log
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-41
Table A.34 : PCI Tar get Image 4 Cont rol Register (LSI4_CTL)
In the PCI Target Image Control register, setting the VCT bit will only have effect if the VAS
bits are programmed for A24 or A32 space and the VDW bits are programmed for 8-bit, 16-
bit, or 32-bit.
If VAS bits are programmed to A24 or A32 and the VDW bits are programmed for 64-bit, the
Univ erse II may perform MBLT transfers independent of the state of the VCT bi t.
The setting of the PWEN bit is ignored if the LAS bit is programmed for PCI Bus I/O Space,
forcing all transactions through this image to be coupled.
Register Name: LSI4_CTL Offset:1A0
Bits Function
31-24 EN PWEN Reserved
23-16 VDW Reserved VAS
15-08 Reserved PGM Reserved SUPER Reserved VCT
07-00 Reserved LAS
LSI4_CTL Description
Name Type Re set By Reset S tat e Functio n
EN R/W all 0 Im age Enab le
0= Disa ble, 1=Enabl e
PWEN R/W all 0 Posted Write Enable
0= Disa ble, 1=Enabl e
VDW R/W all 10 VMEb us Maximum Dat awidth
00=8-bit data width, 01=16 b it data wi dth, 10=32 - bit data width,
11=64-bit data wi dth
VAS R/W all 0 VMEbus Address Space
000=A 16, 001=A24, 0 10=A32, 011= Reserved, 100=Res e r ved,
101=CR/CS R, 110=Us er1, 111=User2
PGM R/W all 0 Program/ D ata AM Code
0= Data, 1=Program
SUPER R/W all 0 Supervisor/User AM Code
0= No n- Privileged, 1=Supervi s or
VCT R/W all 0 VMEbus C ycle Type
0= no BLTs on VMEb us, 1 = BLTs on VMEb us
LAS R/W all 0 PCI Bus Memory Space
0=PCI Bus Memory Space, 1=PCI Bus I/O Space
Registers Universe II User Manual
App A-42 Tundra Semiconductor Corporation
Table A.35 : P CI Target Image 4 Base A ddress Register (LSI4_BS)
The base address specifies the lowest address in the address ra nge that will be decoded.
Register Name: LSI4_BS Offset:1A4
Bits Function
31-24 BS
23-16 BS
15-08 BS Reserved
07-00 Reserved
LSI4_BS Description
Name Type Rese t By Reset State Function
BS[31:1 2] R/W all 0 Base Address
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-43
Table A.36 : PCI Targ et Image 4 Bound Address Register (LS I4_BD)
The addresses decoded in a slave image are those which are greater than or equal to the base
address and less than the bound re gister. If the bound address is 0, then the addresses decoded
are those greater than or equal to the base address.
The bound address for PCI Target Image 0 and PCI Target Image 4 have a 4Kbyte resolution.
PCI Tar get Images 1, 2, 3, 5, 6, and 7 ha ve a 64Kbyte resolution.
Register Name: LSI4_BD Offset:1A8
Bits Function
31-24 BD
23-16 BD
15-08 BD Reserved
07-00 Reserved
LSI4_BD Description
Name Type Rese t By Reset State Function
BD[ 31:12] R/W all 0 Boun d A ddres s
Registers Universe II User Manual
App A-44 Tundra Semiconductor Corporation
Table A.37 : PCI Target Image 4 Translation Offset (LSI4_TO)
Address bits [31:12] generated on the VMEbus in res ponse to an image decode are a two’s
complement addition of address bits [31:12] on the PCI Bus and bits [31:12] of the image’s
translation offset.
Register Name: LSI4_TO Offset:1B0
Bits Function
31-24 TO
23-16 TO
15-08 TO Reserved
07-00 Reserved
LSI4_TO Description
Name Type Reset By Reset State Function
TO[31:12] R/W all 0 Translation offset
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-45
Table A.38 : PCI Tar get Image 5 Cont rol Register (LSI5_CTL)
In the PCI Target Image Control register, setting the VCT bit will only have effect if the VAS
bits are programmed for A24 or A32 space and the VDW bits are programmed for 8-bit, 16-
bit, or 32-bit.
If VAS bits are programmed to A24 or A32 and the VDW bits are programmed for 64-bit, the
Univ erse II may perform MBLT transfers independent of the state of the VCT bi t.
The setting of the PWEN bit is ignored if the LAS bit is programmed for PCI Bus I/O Space,
forcing all transactions through this image to be coupled.
Register Name: LSI5_CTL Offset:1B4
Bits Function
31-24 EN PWEN Reserved
23-16 VDW Reserved VAS
15-08 Reserved PGM Reserved SUPER Reserved VCT
07-00 Reserved LAS
LSI5_CTL Description
Name Type Re set By Reset S tat e Functio n
EN R/W all 0 Im age Enab le
0= Disa ble, 1=Enabl e
PWEN R/W all 0 Posted Write Enable
0= Disa ble, 1=Enabl e
VDW R/W all 10 VMEb us Maximum Dat awidth
00=8-bit data width, 01=16 b it data wi dth, 10=32 - bit data width,
11=64-bit data wi dth
VAS R/W all 0 VMEbus Address Space
000=A 16, 001=A24, 0 10=A32, 011= Reserved, 100=Res e r ved,
101=CR/CS R, 110=Us er1, 111=User2
PGM R/W all 0 Program/ D ata AM Code
0= Data, 1=Program
SUPER R/W all 0 Supervisor/User AM Code
0= No n- Privileged, 1=Supervi s or
VCT R/W all 0 VMEbus C ycle Type
0= no BLTs on VMEb us, 1 = BLTs on VMEb us
LAS R/W all 0 PCI Bus Memory Space
0=PCI Bus Memory Space, 1=PCI Bus I/O Space
Registers Universe II User Manual
App A-46 Tundra Semiconductor Corporation
Table A.39 : P CI Target Image 5 Base A ddress Register (LSI5_BS)
The base address specifies the lowest address in the address ra nge that will be decoded.
Register Name: LSI5_BS Offset:1B8
Bits Function
31-24 BS
23-16 BS
15-08 Reserved
07-00 Reserved
LSI5_BS Description
Name Type Rese t By Reset State Function
BS[31:1 6] R/W all 0 Base Address
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-47
Table A.40 : PCI Targ et Image 5 Bound Address Register (LS I5_BD)
The addresses decoded in a slave image are those which are greater than or equal to the base
address and less than the bound re gister. If the bound address is 0, then the addresses decoded
are those greater than or equal to the base address.
The bound address for PCI Target Image 0 and PCI Target Image 4 have a 4Kbyte resolution.
PCI Tar get Images 1, 2, 3, 5, 6, and 7 ha ve a 64Kbyte resolution.
Register Name: LSI5_BD Offset:1BC
Bits Function
31-24 BD
23-16 BD
15-08 Reserved
07-00 Reserved
LSI5_BD Description
Name Type Rese t By Reset State Function
BD[ 31:16] R/W all 0 Boun d A ddres s
Registers Universe II User Manual
App A-48 Tundra Semiconductor Corporation
Table A.41 : PCI Target Image 5 Translation Offset (LSI5_TO)
Address bits [31:16] generated on the VMEbus in res ponse to an image decode are a two’s
complement addition of address bits [31:16] on the PCI Bus and bits [31:16] of the image’s
translation offset.
Register Name: LSI5_TO Offset:1C0
Bits Function
31-24 TO
23-16 TO
15-08 Reserved
07-00 Reserved
LSI5_TO Description
Name Type Reset By Reset State Function
TO[31:16] R/W all 0 Translation offset
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-49
Table A.42 : PCI Tar get Image 6 Cont rol Register (LSI6_CTL)
In the PCI Target Image Control register, setting the VCT bit will only have effect if the VAS
bits are programmed for A24 or A32 space and the VDW bits are programmed for 8-bit, 16-
bit, or 32-bit.
If VAS bits are programmed to A24 or A32 and the VDW bits are programmed for 64-bit, the
Univ erse II may perform MBLT transfers independent of the state of the VCT bi t.
The setting of the PWEN bit is ignored if the LAS bit is programmed for PCI Bus I/O Space,
forcing all transactions through this image to be coupled.
Register Name: LSI6_CTL Offset:1C8
Bits Function
31-24 EN PWEN Reserved
23-16 VDW Reserved VAS
15-08 Reserved PGM Reserved SUPER Reserved VCT
07-00 Reserved LAS
LSI6_CTL Description
Name Type Re set By Reset S tat e Functio n
EN R/W all 0 Im age Enab le
0= Disa ble, 1=Enabl e
PWEN R/W all 0 Posted Write Enable
0= Disa ble, 1=Enabl e
VDW R/W all 10 VMEb us Maximum Dat awidth
00=8-bit data width, 01=16 b it data wi dth, 10=32 - bit data width,
11=64-bit data wi dth
VAS R/W all 0 VMEbus Address Space
000=A 16, 001=A24, 0 10=A32, 011= Reserved, 100=Res e r ved,
101=CR/CS R, 110=Us er1, 111=User2
PGM R/W all 0 Program/ D ata AM Code
0= Data, 1=Program
SUPER R/W all 0 Supervisor/User AM Code
0= No n- Privileged, 1=Supervi s or
VCT R/W all 0 VMEbus C ycle Type
0= no BLTs on VMEb us, 1 = BLTs on VMEb us
LAS R/W all 0 PCI Bus Memory Space
0=PCI Bus Memory Space, 1=PCI Bus I/O Space
Registers Universe II User Manual
App A-50 Tundra Semiconductor Corporation
Table A.43 : P CI Target Image 6 Base A ddress Register (LSI6_BS)
The base address specifies the lowest address in the address ra nge that will be decoded.
Register Name: LSI6_BS Offset:1CC
Bits Function
31-24 BS
23-16 BS
15-08 Reserved
07-00 Reserved
LSI1_BS Description
Name Type Rese t By Reset State Function
BS[31:1 6] R/W all 0 Base Address
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-51
Table A.44 : PCI Targ et Image 6 Bound Address Register (LS I6_BD)
The addresses decoded in a slave image are those which are greater than or equal to the base
address and less than the bound re gister. If the bound address is 0, then the addresses decoded
are those greater than or equal to the base address.
The bound address for PCI Target Image 0 and PCI Target Image 4 have a 4Kbyte resolution.
PCI Tar get Images 1, 2, 3, 5, 6, and 7 ha ve a 64Kbyte resolution.
Register Name: LSI6_BD Offset:1D0
Bits Function
31-24 BD
23-16 BD
15-08 Reserved
07-00 Reserved
LSI6_BD Description
Name Type Rese t By Reset State Function
BD[ 31:16] R/W all 0 Boun d A ddres s
Registers Universe II User Manual
App A-52 Tundra Semiconductor Corporation
Table A.45 : PCI Target Image 6 Translation Offset (LSI6_TO)
Address bits [31:16] generated on the VMEbus in res ponse to an image decode are a two’s
complement addition of address bits [31:16] on the PCI Bus and bits [31:16] of the image’s
translation offset.
Register Name: LSI6_TO Offset:1D4
Bits Function
31-24 TO
23-16 TO
15-08 Reserved
07-00 Reserved
LSI6_TO Description
Name Type Reset By Reset State Function
TO[31:16] R/W all 0 Translation offset
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-53
Table A.46 : PCI Tar get Image 7 Cont rol Register (LSI7_CTL)
In the PCI Target Image Control register, setting the VCT bit will only have effect if the VAS
bits are programmed for A24 or A32 space and the VDW bits are programmed for 8-bit, 16-
bit, or 32-bit.
If VAS bits are programmed to A24 or A32 and the VDW bits are programmed for 64-bit, the
Univ erse II may perform MBLT transfers independent of the state of the VCT bi t.
The setting of the PWEN bit is ignored if the LAS bit is programmed for PCI Bus I/O Space,
forcing all transactions through this image to be coupled.
Register Name: LSI7_CTL Offset:1DC
Bits Function
31-24 EN PWEN Reserved
23-16 VDW Reserved VAS
15-08 Reserved PGM Reserved SUPER Reserved VCT
07-00 Reserved LAS
LSI7_CTL Description
Name Type Re set By Reset S tat e Functio n
EN R/W all 0 Im age Enab le
0= Disa ble, 1=Enabl e
PWEN R/W all 0 Posted Write Enable
0= Disa ble, 1=Enabl e
VDW R/W all 10 VMEb us Maximum Dat awidth
00=8-bit data width, 01=16 b it data wi dth, 10=32 - bit data width,
11=64-bit data wi dth
VAS R/W all 0 VMEbus Address Space
000=A 16, 001=A24, 0 10=A32, 011= Reserved, 100=Res e r ved,
101=CR/CS R, 110=Us er1, 111=User2
PGM R/W all 0 Program/ D ata AM Code
0= Data, 1=Program
SUPER R/W all 0 Supervisor/User AM Code
0= No n- Privileged, 1=Supervi s or
VCT R/W all 0 VMEbus C ycle Type
0= no BLTs on VMEb us, 1 = BLTs on VMEb us
LAS R/W all 0 PCI Bus Memory Space
0=PCI Bus Memory Space, 1=PCI Bus I/O Space
Registers Universe II User Manual
App A-54 Tundra Semiconductor Corporation
Table A.47 : P CI Target Image 7 Base A ddress Register (LSI7_BS)
The base address specifies the lowest address in the address ra nge that will be decoded.
Register Name: LSI7_BS Offset:1E0
Bits Function
31-24 BS
23-16 BS
15-08 Reserved
07-00 Reserved
LSI7_BS Description
Name Type Rese t By Reset State Function
BS[31:1 6] R/W all 0 Base Address
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-55
Table A.48 : PCI Targ et Image 7 Bound Address Register (LS I7_BD)
The addresses decoded in a slave image are those which are greater than or equal to the base
address and less than the bound re gister. If the bound address is 0, then the addresses decoded
are those greater than or equal to the base address.
The bound address for PCI Target Image 0 and PCI Target Image 4 have a 4Kbyte resolution.
PCI Tar get Images 1, 2, 3, 5, 6, and 7 ha ve a 64Kbyte resolution.
Register Name: LSI7_BD Offset:1E4
Bits Function
31-24 BD
23-16 BD
15-08 Reserved
07-00 Reserved
LSI7_BD Description
Name Type Rese t By Reset State Function
BD[ 31:16] R/W all 0 Boun d A ddres s
Registers Universe II User Manual
App A-56 Tundra Semiconductor Corporation
Table A.49 : PCI Target Image 7 Translation Offset (LSI7_TO)
Address bits [31:16] generated on the VMEbus in res ponse to an image decode are a two’s
complement addition of address bits [31:16] on the PCI Bus and bits [31:16] of the image’s
translation offset.
Register Name: LSI7_TO Offset:1E8
Bits Function
31-24 TO
23-16 TO
15-08 Reserved
07-00 Reserved
LSI7_TO Description
Name Type Reset By Reset State Function
TO[31:16] R/W all 0 Translation offset
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-57
Table A.50 : DMA Transfer Contr ol Register (DCTL)
This register is programmed from either bus or is programme d by the DMAC when it loads
the command packet. The DMA only accesses PCI Bus Memory space.
The VCT bit determines whether or not the Uni verse II VME Master will gener ate BLT
transfers. The value of this bit only has meaning if the address space is A24 or A32 and the
data width is not 64 bits. If the data width is 64 bits the Univ erse II may perform MBLT
transfers independent of the state of the VCT bit.
Register Name: DCTL Offset:200
Bits Function
31-24 L2V Reserved
23-16 VDW Reserved VAS
15-08 PGM SUPER Reserved VCT
07-00 LD64EN Reserved
DCTL Description
Name Type Rese t By Reset State Function
L2V R/W all 0 Direction
0=Transfer from VMEbus to PCI Bus, 1=Transfer from PCI Bus
to VMEbus
VDW R/W all 0 VMEbus Ma xi mum Datawidth
00=8-bit data width, 01=16 b it data wi dth, 10=32 - bit data width,
11=64-bit data wi dth
VAS R /W all 0 VMEb us Address Space
000=A 16, 001=A24, 0 10=A32, 011= Reserved, 100=Res e r ved,
101=Reserved , 110=User1, 1 11=U s er2
PGM R/W all 0 Pro gr am/Data A M C ode
00=D ata, 01=P rogram, others=Reserved
SUPER R/W all 0 Supervisor/User AM Code
00=N on-Pr ivileged, 01=Supe rvisor, others =Rese rved
VCT R/W all 0 VMEbus C ycle Type
0= no BLTs on VMEb us, 1 = BLTs on VMEb us
LD64EN R/W all 1 Enable 64-bit PCI Bus Transactions
0= Disa ble, 1=Enabl e
Registers Universe II User Manual
App A-58 Tundra Semiconductor Corporation
Table A.51 : DMA Transfer Byte Count Register (DTBC)
This register specifies the number of bytes to be moved by the DMA before the start of the
DMA trans fer, or the number of rema ining bytes in the trans fer while the DMA is a ctiv e . This
register is programmed from either bus or is programmed by the DMA Controller when it
loads a command packet from a linked-list.
In direct mode the user must reprogram the DTBC register before each transfer.
When using the DMA to perform linked-list transfers, it is essential that the DTBC register
contains a v alue of zero before setting the GO bit of the DGCS register or undefined beha viors
may occur.
Register Name: DTBC Offset:204
Bits Function
31-24 Reserved
23-16 DTBC
15-08 DTBC
07-00 DTBC
DTBC Description
Name Type Rese t By Reset State Function
DTBC[23:0] R/W all 0 DMA T ransfer Byte Count
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-59
Table A.52 : DMA PCI Bus Address Register (DLA)
This register is programmed from either bus or b y the DMA Controller when it loads a
command pack et. In direct mod e the user must reprogram the DLA register before each
transfer. In linke d-list mode, this r egister is only updated when the DMA is stopped, halted, or
at the completion of processing a command packet.
After a Bus Error, a Target-Abort, or a Maste r-Abort, the value in the DLA regist er must not
be used to reprogram the DMA because it has no useable information. Some off set from its
original va lue must be used.
Address bits [2:0] must be pr ogramme d the same as those in the DVA.
Register Name: DLA Offset:208
Bits Function
31-24 LA
23-16 LA
15-08 LA
07-00 LA
DLA Description
Name Type Rese t By Reset State Function
LA[31:3] R/W all 0 PCI Bus Addres s
LA[2:0] R/W all 0 PCI Bus Address
Registers Universe II User Manual
App A-60 Tundra Semiconductor Corporation
Table A.53 : DMA VMEbus Address Register (DVA)
This re gister is progr ammed from either b us or i s programmed by the DMA Controller when it
loads a command packet. In direct mode the user must reprogram the D VA regis ter before
each transfer. In linked-l ist operation, this re gi ster is only updated when the DMA is stopped,
halted, or at the completion of processing a command packet.
After a Bus Error, a Target-Abort, or a Maste r-Abort, the value in the DLA regist er must not
be used to reprogram the DMA because it has no useable information. Some off set from its
original va lue must be used.
Address bits [2:0] must be pr ogramme d the same as those in the DLA.
Register Name: DVA Offset:210
Bits Function
31-24 VA
23-16 VA
15-08 VA
07-00 VA
DVA Description
Name Type Rese t By Reset State Function
VA[31:0] R/W all 0 VMEb us Addr ess
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-61
Table A.54 : DMA Command P acket Pointer (DCPP)
This re gis te r contains the pointer into the cur rent comma nd packet. Initially it is progr amme d
to the starting packet of the linked-list, and is updated with the address to a new command
packet at the completi on of a packet. The packets must be aligned to a 32-byte address .
Register Name: DCPP Offset:218
Bits Function
31-24 DCPP
23-16 DCPP
15-08 DCPP
07-00 DCPP Reserved
DCPP Descri ption
Name Type Reset By Reset State Function
DCPP[31:5] R/W all 0 DMA Command Pack et Pointer
Registers Universe II User Manual
App A-62 Tundra Semiconductor Corporation
Table A.55 : DMA General Control/Status Register (DGCS)
Register Name: DGCS Offset: 220
Bits Function
31-24 GO STOP_REQ HALT_REQ 0 CHAIN 0 0 0
23-16 Reserved VON VOFF
15-08 ACT STOP HALT 0 DONE LERR VERR P_ERR
07-00 0 INT_STOP INT_HALT 0 INT_DONE INT_LERR INT_VERR INT_P_ERR
DGCS Description
Name Type Reset By Reset State Function
GO W/Read 0
always all 0 DMA Go Bit
0 =No effect, 1=Enab l e DMA Trans f e r s
STOP_ REQ W/Read 0
always all 0 DMA Stop Req ue st
0=N o effect, 1=Stop DMA transfer when all buffered data has
been written
HALT_REQ W/Read 0
always all 0 DMA Halt Request
0= No effect, 1=Halt the DMA transfer at the completi on of the
current comman d packet
CHAIN R/W all 0 DMA Chai ning
0=DMA Direct Mode, 1=DMA Linked List mode
VON [2:0] R/W all 0 VMEbus "On" counter
000= U ntil do n e, 001= 25 6 bytes , 010 =51 2 bytes,
011=1024 bytes, 100=2048 bytes, 1 01=4096 b ytes, 110=8192
bytes, 111=163 84 bytes , other s =Re s erved
VOFF [3:0] R/W all 0 VMEbus "Off" Counter
0000=0µs, 000 1=16µs, 0010=32µs, 0011=64µs, 0100=128µs ,
0101=256µs, 0110=51 2µs, 0111=1024µs, 1000=2µs, 10 01=4µs,
1010=8µs, other s =Rese rved
The DMA will not re-request the VME Master until this timer
expires.
ACT R all 0 D MA Ac t ive S t atus B i t
0=N ot Ac tive, 1=Ac tive
STOP R/Write 1 to
Clear all 0 DMA Stopped Status Bi t
0=N ot Stopped, 1=Stopped
HALT R/Write 1 to
Clear all 0 DMA Halted Stat us Bit
0=Not Halted, 1=Halted
DONE R/Write 1 to
Clear all 0DMA Done Status Bit
0=N ot Com plet e, 1=Comp le te
LERR R/Write 1 to
Clear all 0 DMA PCI Bus Error Status Bit
0=N o Error, 1=Erro r
VERR R/Write 1 to
Clear all 0 DMA VMEbus Error Status Bit
0=N o Error, 1=Erro r
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-63
ST OP, HALT, DONE, LERR, VERR, and P_ERR must be cleared before the GO bit is
enabled.
P_ERR R/Write 1 to
Clear all 0 DMA Programmi ng Prot ocol Er ror Status Bit
Asserted if PCI master interface disabled or lower three bits of
PCI and VME addresses differ
0=N o Error, 1=Erro r
INT_STOP R/W all 0 Interr upt when Stopped
0= Disa ble, 1=Enabl e
INT_HALT R/W all 0 Interrupt when Halted
0= Disa ble, 1=Enabl e
INT_DONE R/W all 0 Int errup t when Done
0= Disa ble, 1=Enabl e
INT_LERR R/W all 0 Inter rupt on LE RR
0= Disa ble, 1=Enabl e
INT_VERR R/W all 0 Interrupt on VERR
0= Disa ble, 1=Enabl e
INT_P_ERR R/W all 0 Interrupt on Master Enable Error
0= Disa ble, 1=Enabl e
DGCS Description
Name Type Reset By Reset State Function
Registers Universe II User Manual
App A-64 Tundra Semiconductor Corporation
Table A.56 : DMA Linked List Update Enable Register (D_LLUE)
The PCI Resource must r ead back a logic 1 in t he UPDATE field bef ore proceeding to modif y
the linked list. After the Linked List has been modif ied the PCI Resource must cl ear the
UPDAT E fie ld by writing a logic 0. the Universe II does not prevent an ex tern al master, f r om
the PCI bus or the VMEbus, from writing to the other DMA regis ters. See “Linked List
Updating” on page 2-91.
Register Name: D_LLUE Offset:224
Bits Function
31-24 UPDATE Reserved
23-16 Reserved
15-08 Reserved
07-00 Reserved
D_LLUE Description
Name Type Reset By Reset State Function
UPDATE R/W all 0 DMA Linked List Update Enable
0= PC I Res ource not Up dating L inked Li s t
1=PCI Resource Updating Linked List
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-65
Table A.57 : PCI Interrupt Enable Register (LINT_EN)
Regis ter Name: L INT _EN Offset:300
Bits Function
31-24 Reserved
23-16 LM3 LM2 LM1 LM0 MBOX3 MBOX2 MBOX1 MBOX0
15-08 ACFAIL SYSFAIL SW_INT SW_IACK Reserved VERR LERR DMA
07-00 VIRQ7 VIRQ6 VIRQ5 VIRQ4 VIRQ3 VIRQ2 VIRQ1 VOWN
LINT_EN Description
Name Type Reset By Reset State Functio n
LM3 R/W all 0 Location Monitor 3 Mask
0= LM 3 Interrupt Masked , 1=LM3 Interrupt Enabled
LM2 R/W all 0 Location Monitor 2 Mask
0= LM 2 Interrupt Masked , 1=LM2 Interrupt Enabled
LM1 R/W all 0 Location Monitor 1 Mask
0= LM 1 Interrupt Masked , 1=LM1 Interrupt Enabled
LM0 R/W all 0 Location Monitor 0 Mask
0= LM 0 Interrupt Masked , 1=LM0 Interrupt Enabled
MBOX3 R/W all 0Mailbox 3 Mask
0= MBO X 3 Interrupt Masked, 1=MBOX3 Inte rrupt Enabled
MBOX2 R/W all 0Mailbox 2 Mask
0= MBO X 2 Interrupt Masked, 1=MBOX2 Inte rrupt Enabled
MBOX1 R/W all 0Mailbox 1 Mask
0= MBO X 1 Interrupt Masked, 1=MBOX1 Inte rrupt Enabled
MBOX0 R/W all 0Mailbox 0 Mask
0= MBO X 0 Interrupt Masked, 1=MBOX0 Inte rrupt Enabled
ACFAIL R/W all 0 ACFAIL Interrupt Mask
0=ACFAIL In te rrupt masked
1=ACFAIL Inte rrupt enab le d
SYSFAIL R/W all 0 SY SFAIL Int er rupt Mask
0=SYSFAIL Interrupt masked
1=SYSFAIL Interrupt enabled
SW_INT R/W all 0 Local Software Interrupt Mask
0=PCI Software Inte rrupt masked
1=PCI Softwa re Interrupt enab le d
A zero-to-one transition will cause the PCI software interrupt to
be as s er ted. Subsequent zeroing of this bit w il l cause the
interrupt to be masked, but will not clear the PCI Software
Interrupt Status bit.
SW_IACK R/W all 0 “VME Software IACK” Mask
0 =“VME Software IACK” Interrupt masked
1 =“VME Software IA CK” Interrupt enabled
VERR R/W all 0 PCI VERR Interrupt Mask
0 =PCI VERR Interrupt masked
1=PCI VERR In terrupt enab le d
Registers Universe II User Manual
App A-66 Tundra Semiconductor Corporation
Bits VIRQ7-VIRQ1 enable the Universe II to respond as a VME Interrupt Handler to
interrupts on the VIRQ[x] lines. When a VIRQx interrupt is enabled, and the corresponding
VIRQ[x] pin is asserted, the Uni verse II requests the VMEbus and performs a VME IACK
cycle for that interrupt level. When the interrupt acknowledge cycle completes, the
STATUS/ID is stored in the corresponding VINT_ID register, the VIRQx bit of the
LINT_STAT regi ster is set, and a PCI interrupt is generated. The Univ erse II does not acquire
further interrupt STATUS/ID vectors at the same inte rrupt level until the VIRQx bit in the
LINT_STAT register is cleared.
The other bits enable the respective internal or external sources to interrupt the PCI side.
LERR R/W all 0 PCI LERR Interrupt Mask
0 =PCI LERR Interrupt masked
1 =PCI LERR Interrupt enabled
DMA R/W all 0 PCI DMA Interrupt Mask
0=PCI DMA Interrupt masked
1=PCI DMA Interrupt enabled
VIRQ7-VIRQ1 R/W all 0 VIRQx Interrupt Mask
0=VIRQx Interrupt masked
1 =VIRQx Interrupt enabled
VOWN R/W all 0 VOWN Interrupt Mask
0=VOWN Int errupt masked
1=VOWN Interrupt Enable d
LINT_EN Description
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-67
Tabl e A.58 : PCI Interr upt Status Regis ter (LIN T_S TAT)
Regist er Name: LINT_STAT Offset: 304
Bits Function
31-24 Reserved
23-16 LM3 LM2 LM1 LM0 MBOX3 MBOX2 MBOX1 MBOX0
15-08 ACFAIL SYSFAIL SW_INT SW_IACK Reserved VERR LERR DMA
07-00 VIRQ7 VIRQ6 VIRQ5 VIRQ4 VIRQ3 VIRQ2 VIRQ1 VOWN
LINT_STAT Description
Name Type Reset By Reset State Functio n
LM3 R/Write 1
to Cl ear all 0 Location Monitor 3 Status/Clear
0= no Locati on Monit or 3 Interrupt,
1=Location Monitor 3 Interrupt active
LM2 R/Write 1
to Cl ear all 0 Location Monitor 2 Status/Clear
0= no Locati on Monit or 2 Interrupt,
1=Location Monitor 2 Interrupt active
LM1 R/Write 1
to Cl ear all 0 Location Monitor 1 Status/Clear
0= no Locati on Monit or 1 Interrupt,
1=Location Monitor 1 Interrupt active
LM0 R/Write 1
to Cl ear all 0 Location Monitor 0 Status/Clear
0= no Locati on Monit or 0 Interrupt,
1=Location Monitor 0 Interrupt active
MBO X3 R/Write 1
to Cl ear all 0 Mailbox 3 Status/Clear
0= no Mailbox 3 Interrupt,
1=Ma ilb o x 3 Interrup t active
MBO X2 R/Write 1
to Cl ear all 0 Mailbox 2 Status/Clear
0= no Mailbox 2 Interrupt,
1=Ma ilb o x 2 Interrup t active
MBO X1 R/Write 1
to Cl ear all 0 Mailbox 1 Status/Clear
0= no Mailbox 1 Interrupt,
1=Ma ilb o x 1 Interrup t active
MBO X0 R/Write 1
to Cl ear all 0 Mailbox 0 Status/Clear
0= no Mailbox 0 Interrupt,
1=Ma ilb o x 0 Interrup t active
ACFAIL R/Write 1
to Cl ear all 0 ACFAIL Interrupt Status/Clear
0= no ACFAIL Inter rupt,
1=ACFAIL Inte rrupt act ive
SYSFAIL R/Write 1
to Cl ear all 0 SYSFAIL Inter rupt Statu s /Cl ear
0=no SYSFAIL Interrupt,
1=SYSFAIL Interrupt active
SW_INT R/Write 1
to Cl ear all 0 Local Software Interrupt Status/Clear
0=no PCI Software Interrupt,
1=PCI Software Inte rrupt active
Registers Universe II User Manual
App A-68 Tundra Semiconductor Corporation
Status bits indicated as “R/Write 1 to Clear” are edge sensitive: the status i s latched when the
interrupt event occurs. These status bit s can be cleared independently of the state of the
interrupt source by writing a “1” to the status register. Clearing the status bi t does not imply
the source of the interrupt i s cleared.
Howev er, A CFAIL and SYSFAIL are level-sensitive. Clearing ACFAIL or SYSFAIL while
their respective pins are sill asserted will have no effect.
SW_IA CK R/Write 1
to Cl ear all 0 “VME Software IA CK” Status/Clear
0=no “VME Software IACK” Interrupt,
1=“VM E Software IACK” Inte rrupt active
VERR R/Write 1
to Cl ear all 0 Local VERR Interr upt Status /Clear
0=Local VERR In terrupt masked,
1=Loca l VERR Inte rrupt enab led
LERR R/Write 1
to Cl ear all 0 Local LERR Interrupt Status/Clear
0=Loca l LER R Interrupt masked,
1=Local LERR Interrupt enabled
DMA R/Write 1
to Cl ear all 0 Local DMA Interrupt Status/Cl ear
0=Local DMA Inter rupt masked,
1=Local DMA Interrupt enabled
VIRQ7-VIRQ1 R/Write 1
to Cl ear all 0 VIRQx Interrupt Stat us/C le ar
0=VIRQx Interrupt masked,
1=VIRQx Interrupt enabled
VO WN R /Wr i t e 1
to Cl ear all 0 VO WN Interrupt Status/Clear
0= no VOWN Interrup t masked,
1=VOWN Interrupt enabled
LINT_STAT Description
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-69
Tabl e A.59 : PCI Interrupt Map 0 Register (LINT_MAP0)
This regis ter maps various interrupt sources to one of the eight PCI interrupt pins. A value of
000 maps the corresponding interrupt source to L INT# [0] , a value of 001 m aps to LINT# [1],
etc.
Regist er Name: LINT_MAP0 Offset: 308
Bits Function
31-24 Reserved VIRQ7 Reserved VIRQ6
23-16 Reserved VIRQ5 Reserved VIRQ4
15-08 Reserved VIRQ3 Reserved VIRQ2
07-00 Reserved VIRQ1 Reserved VOWN
LINT_MAP0 Description
Name Type Reset By Reset State Functio n
VIRQ7-VIRQ1 R/W all 0 PCI interrupt destination (LINT[7:0]) for VIRQx
VOWN R/W all 0 VM Ebus ownersh ip bit interrup t map to PCI interrupt
Registers Universe II User Manual
App A-70 Tundra Semiconductor Corporation
Tabl e A.60 : PCI Interrupt Map 1 Register (LINT_MAP1)
This regis ter maps various interrupt sources to one of the eight PCI interrupt pins. A value of
000 maps the corresponding interrupt source to L INT# [0] , a value of 001 m aps to LINT# [1],
etc.
Regist er Name: LINT_MAP1 Of fs et: 30C
Bits Function
31-24 Reserved ACFAIL Reserved SYSFAIL
23-16 Reserved SW_INT Reserved SW_IACK
15-08 Reserved VERR
07-00 Reserved LERR Reserved DMA
LINT_MAP1 Descriptio n
Name Type Reset By Reset State Functio n
ACFAIL R/W all 0 ACFAIL interrupt destination
SYSFAIL R/W all 0 SY SFA IL inte rrupt desti nati on
SW_INT R/W all 0 PCI software interrupt destination
SW_IACK R/W all 0 VMEbus Software IA CK interrupt destination
VERR R/W all 0 VMEbus Error interrupt destination
LERR R/W all 0 PCI Bus Error interrupt destination
DMA R/W all 0 DMA interrupt destination
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-71
Table A.61 : VMEbu s Interrupt Enable Reg ister (VIN T_EN)
Regist er Name: VINT_ EN Offset:310
Bits Function
31-24 SW_INT7 SW_INT6 SW_INT5 SW_INT4 SW_INT3 SW_INT2 SW_INT1 Reserved
23-16 Reserved MBOX3 MBOX2 MBOX1 MBOX0
15-08 Reserved SW_INT Reserved VERR LERR DMA
07-00 LINT7 LINT6 LINT5 LINT4 LINT3 LINT2 LINT1 LINT0
VINT_EN Descri ption
Name Type Reset By Reset State Functio n
SW_INT7 R/W all 0 VM E Software 7 Interr upt Mask
0=VME Software 7 Interrupt masked,
1=VME Software 7 Interrupt enabled
A zero-to-one transition will cause a VME level 7 interrupt to be
ge nerated. Subsequent zeroing of this bit will caus e th e inter rupt
to be masked, but will not clear the VME Software 7 Interrupt
St a tus bit.
SW_INT6 R/W all 0 VM E Software 6 Interr upt Mask
0=VME Software 6 Interrupt masked,
1=VME Software 6 Interrupt enabled
A zero-to-one transition will cause a VME level 6 interrupt to be
ge nerated. Subsequent zeroing of this bit will caus e th e inter rupt
to be masked, but will not clear the VME Software 6 Interrupt
St a tus bit.
SW_INT5 R/W all 0 VM E Software 5 Interr upt Mask
0=VME Software 5 Interrupt masked,
1=VME Software 5 Interrupt enabled
A zero-to-one transition will cause a VME level 5 interrupt to be
ge nerated. Subsequent zeroing of this bit will caus e th e inter rupt
to be masked, but will not clear the VME Software 5 Interrupt
St a tus bit.
SW_INT4 R/W all 0 VM E Software 4 Interr upt Mask
0=VME Software 4 Interrupt masked,
1=VME Software 4 Interrupt enabled
A zero-to-one transition will cause a VME level 4 interrupt to be
ge nerated. Subsequent zeroing of this bit will caus e th e inter rupt
to be masked, but will not clear the VME Software 4 Interrupt
St a tus bit.
SW_INT3 R/W all 0 VM E Software 3 Interr upt Mask
0=VME Software 3 Interrupt masked,
1=VME Software 3 Interrupt enabled
A zero-to-one transition will cause a VME level 3 interrupt to be
ge nerated. Subsequent zeroing of this bit will caus e th e inter rupt
to be masked, but will not clear the VME Software 3 Interrupt
St a tus bit.
Registers Universe II User Manual
App A-72 Tundra Semiconductor Corporation
This register enables the various s ources of VMEb us i nterrupts. SW_INT can be enabled with
the VME64AUTO po wer -up option.
SW_INT2 R/W all 0 VM E Software 2 Interr upt Mask
0=VME Software 2 Interrupt masked,
1=VME Software 2 Interrupt enabled
A zero-to-one transition will cause a VME level 2 interrupt to be
ge nerated. Subsequent zeroing of this bit will caus e th e inter rupt
to be masked, but will not clear the VME Software 2 Interrupt
St a tus bit.
SW_INT1 R/W all 0 VM E Software 1 Interr upt Mask
0=VME Software 1 Interrupt masked,
1=VME Software 1 Interrupt enabled
A zero-to-one transition will cause a VME level 1 interrupt to be
ge nerated. Subsequent zeroing of this bit will caus e th e inter rupt
to be masked, but will not clear the VME Software 1 Interrupt
St a tus bit.
MBOX3 R/W all 0Mailbox 3 Mask
0= MBO X 3 Inter rupt masked,
1=MBOX3 Interrupt enabled
MBOX2 R/W all 0Mailbox 2 Mask
0=MBOX2 Interrupt masked,
1=MBOX2 Interrupt enabled
MBOX1 R/W all 0Mailbox 1 Mask
0=MBOX1 Interrupt masked,
1=MBOX1 Interrupt enabled
MBOX0 R/W all 0Mailbox 0 Mask
0= MBO X 0 Inter rupt masked,
1=MBOX0 Interrupt enabled
SW_INT R/W all Power-up
Option “VME Software Interrupt” Mask
0 = VME Software Interrupt masked
1 =VME Software Interrupt enabled
A zero-to-one transition causes the VME software interrupt to be
asserted. Subsequent zeroing of this bit causes the interrupt to be
mask ed and th e VMEb us inte rrupt ne gat ed, b ut does not clear the
VME software interrupt status bit.
VERR R/W all 0 VERR Interrupt Mask
0 =PCI VERR Interrupt masked
1=PCI VERR Inte rrupt enab le d
LERR R/W all 0 LERR Interrupt Mask
0 =PCI LERR Interrupt masked
1 =PCI LERR Interrupt enabled
DMA R/W all 0 DMA Interrupt Mask
0=PCI DMA Interrupt masked
1=PCI DMA Interrupt enabled
LINT7-LINT0 R/W all 0 PCI Interrupt Mask
0=LINTx Interrupt masked
1 =LINTx Interrupt enab led
VINT_EN Descri ption
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-73
Table A.62 : VMEbu s Interrupt Status R e gi ster (V INT_STAT)
Regist er Name: VINT_ STAT Offset:314
Bits Function
31-24 SW_INT7 SW_INT6 SW_INT5 SW_INT4 SW_INT3 SW_INT2 SW_INT1 Reserved
23-16 Reserved MBOX3 MBOX2 MBOX1 MBOX0
15-08 Reserved SW_INT Reserved VERR LERR DMA
07-00 LINT7 LINT6 LINT5 LINT4 LINT3 LINT2 LINT1 LINT0
VINT_STAT Description
Name Type Reset By Reset State Function
SW_INT7 R/Write 1
to clear all 0 VME Software 7 Interrupt Status/Clear
0= no V ME Soft ware 7 Interrupt,
1=VME Softwa re 7 Interrupt active
SW_INT6 R/Write 1
to clear all 0 VME Software 6 Interrupt Status/Clear
0= no V ME Soft ware 6 Interrupt,
1=VME Softwa re 6 Interrupt active
SW_INT5 R/Write 1
to clear all 0 VME Software 5 Interrupt Status/Clear
0= no V ME Soft ware 5 Interrupt,
1=VME Softwa re 5 Interrupt active
SW_INT4 R/Write 1
to clear all 0 VME Software 4 Interrupt Status/Clear
0= no V ME Soft ware 4 Interrupt,
1=VME Softwa re 4 Interrupt active
SW_INT3 R/Write 1
to clear all 0 VME Software 3 Interrupt Status/Clear
0= no V ME Soft ware 3 Interrupt,
1=VME Softwa re 3 Interrupt active
SW_INT2 R/Write 1
to clear all 0 VME Software 2 Interrupt Status/Clear
0= no V ME Soft ware 2 Interrupt,
1=VME Softwa re 2 Interrupt active
SW_INT1 R/Write 1
to clear all 0 VME Software 1 Interrupt Status/Clear
0= no V ME Soft ware 1 Interrupt,
1=VME Softwa re 1 Interrupt active
MBOX3 R/Write 1
to clear all 0 Mailbox 3 Status/Cl ear
0= no Mailbox 3 Interrupt,
1=Mailbox 3 Interrupt active
MBOX2 R/Write 1
to clear all 0 Mailbox 2 Status/Cl ear
0= no Mailbox 2 Interrupt,
1=Mailbox 2 Interrupt active
MBOX1 R/Write 1
to clear all 0 Mailbox 1 Status/Cl ear
0= no Mailbox 1 Interrupt,
1=Mailbox 1 Interrupt active
MBOX0 R/Write 1
to clear all 0 Mailbox 0 Status/Cl ear
0= no Mailbox 0 Interrupt,
1=Mailbox 0 Interrupt active
Registers Universe II User Manual
App A-74 Tundra Semiconductor Corporation
SW_INT can be set with the VME64AUTO po wer -up option.
SW_INT R/Write 1
to Clear all Power-up
Option VM E Software Interrupt Status/Clear
0=VME Software Interrupt inactive,
1=VME Softwa re Interrupt active
VERR R/Write 1
to Clear all 0 VERR Interrupt Sta tus/Clear
0=VME VERR In terrupt masked,
1=VME VERR In terrupt ena ble d
LERR R/Write 1
to Clear all 0 LERR Interrupt Status/Clear
0=VM E LER R Interru pt mas ked,
1=VME LERR Interrupt enabled
DMA R/Write 1
to Clear all 0 DMA Interrupt Status/Clear
0=VME DMA Int errupt mask ed,
1=VME DMA Int errupt ena bled
LINT7-LINT0 R/Write 1
to Clear all 0 LINTx Interrupt Status/Clear
0=LINTx Interrupt masked,
1=LINTx Interrupt enabled
VINT_STAT Description
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-75
Table A.63 : VME Interrupt Map 0 Register (VINT_MAP0)
This register maps various interrupt sour ces to one of the seven VMEbus interrupt pins. A
value of 001 maps the corresponding interrupt source to VIRQ*[1], a value of 002 maps to
VIRQ*[2], etc. A v alue of 000 effectively masks th e interrupt since there is no corresponding
VIRQ*[0].
Regist er Name: VINT_ MAP0 Offse t: 318
Bits Function
31-24 Reserved LINT7 Reserved LINT6
23-16 Reserved LINT5 Reserved LINT4
15-08 Reserved LINT3 Reserved LINT2
07-00 Reserved LINT1 Reserved LINT0
VINT_MAP0 Description
Name Type Reset By Reset State Functio n
LINT7-LINT0 R/W all 0 VMEbus destination of PCI Bus interrupt source
Registers Universe II User Manual
App A-76 Tundra Semiconductor Corporation
Table A.64 : VME Inte rrupt Map 1 Register (VINT_MAP1)
This register maps various interrupt sour ces to one of the seven VMEbus interrupt pins. A
value of 001 maps the corresponding interrupt source to VIRQ*[1], a value of 002 maps to
VIRQ*[2], etc. A v alue of 000 effectively masks th e interrupt since there is no corresponding
VIRQ*[0].
SW_INT is set to 010 with the VME64AUTO power - up option.
Regist er Name: VINT_ MAP1 Of fset: 31C
Bits Function
31-24 Reserved
23-16 Reserved SW_INT
15-08 Reserved VERR
07-00 Reserved LERR Reserved DMA
VINT_MAP1 Description
Name Type Reset By Reset State Functio n
SW_INT R/W all Power-u p
Option VMEbus Software interrupt destination
VERR R/W all 0 VMEbus Error interrupt destination
LERR R/W all 0 PCI Bus Error interrupt destination
DMA R/W all 0 DMA interrupt destination
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-77
Table A.65 : Interrupt STATUS/ID Out Register (STATID)
When the Universe II responds to an interrupt a cknowledge cycl e on VMEbus it re turns an 8-
bit STAT US/ID. STATID [7:1] can be written by software to uniquely identify the VMEbus
module within the system. STATID [0] is a v alue of 0 if the Universe II is generating a
software interrupt (SW_IA CK) at the same le vel as the interrupt acknowledge cycle, otherwise
it is a value of 1.
The reset state is designed to support the VME64 Auto ID STAT US/ID value.
Regist er Name: STATID Offset: 320
Bits Function
31-24 STATID [7:0]
23-16 Reserved
15-08 Reserved
07-00 Reserved
STATID Descript i on
Name Type Reset By Reset State Functio n
STATID [7: 1] R /W all 1111111 Bits [7:1] of the STATUS/ID byte are returned wh en the
Universe II responds t o a VMEbus IACK cycle.
STATID [0] R all See be low 0 = the Uni verse I I is generat ing a SW_IACK at the same level
as the i nterrupt ackno w ledge cycle.
1 = the Universe II is not generat ing a SW_IACK at th e sa me
level as the interrupt a ckn owledg e cycle.
Registers Universe II User Manual
App A-78 Tundra Semiconductor Corporation
Table A.66 : VIRQ1 STATUS/ID Register (V1_STATID)
The Vx_STATID registers are read-only r egisters that hold the 8-bit VMEbus STATUS/ID that
is acquired when the Universe II performs a IACK cycle for a given inte rrupt level. The
Univ erse II is enabled as the interr upt handler for a gi ven inter rupt l ev el via the VI RQx bits of
the LINT_EN register. Once a vector for a given level is acquired, the Universe II does not
perform a subsequent interrupt acknowledge c ycle at that lev el until the corresponding VIRQx
bit in the LINT_STAT register is cleared.
The acquisition of a le vel x STATUS/ID by the Universe II updates the STATUS/ID f ield of the
corresponding Vx_STATID register a nd generation of a PCI inte rrupt. A VMEbus error
during the acquisition of the STATUS/ID v ector sets the ERR bi t, which means the
STATUS/ID field may not contain a valid vector.
Regist er Name: V1 _STATID Offset: 324
Bits Function
31-24 Reserved
23-16 Reserved
15-08 Reserved ERR
07-00 STATID [7:0]
V1_STATID Description
Name Type Reset By Reset State Functio n
ERR R all 0 Error Status Bit
0=STATUS/ID was acquired with out b us error
1= bus error occu rred during acquisi tion of the STATUS/ID
STATID [7:0] R all 0 STATUS/ID acquired during IACK cycle for lev el 1 VMEbus
interrupt
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-79
Table A.67 : VIRQ2 STATUS/ID Register (V2_STATID)
The Vx_STATID registers are read-only r egisters that hold the 8-bit VMEbus STATUS/ID that
is acquired when the Universe II performs a IACK cycle for a given inte rrupt level. The
Univ erse II is enabled as the interr upt handler for a gi ven inter rupt l ev el via the VI RQx bits of
the LINT_EN register. Once a vector for a given level is acquired, the Universe II does not
perform a subsequent interrupt acknowledge c ycle at that lev el until the corresponding VIRQx
bit in the LI NT_STAT register is cleared.
The acquisition of a leve l x STATUS/ID by the Universe II updates the STAT US/ID field of
the corresponding Vx_STATID regi ster and generation of a PCI interrupt. A VMEb us error
during the acquisition of the STATUS/ID vector sets the ERR bit, which means the
STATUS/ID field may not contain a valid vector.
Regist er Name: V2 _STATID Offset: 328
Bits Function
31-24 Reserved
23-16 Reserved
15-08 Reserved ERR
07-00 STATID [7:0]
V2_STATID Description
Name Type Reset By Reset State Functio n
ERR R all 0 Error Status Bit
0=STATUS/ID was acquired with out b us error
1= bus error occu rred during acquisi tion of the STATUS/ID
STATID [7:0] R all 0 STATUS/ID acquired during IACK cycle for lev el 1 VMEbus
interrupt
Registers Universe II User Manual
App A-80 Tundra Semiconductor Corporation
Table A.68 : VIRQ3 STATUS/ID Register (V3_STATID)
The Vx_STATID registers are read-only r egisters that hold the 8-bit VMEbus STATUS/ID that
is acquired when the Universe II performs a IACK cycle for a given inte rrupt level. The
Univ erse II is enabled as the interr upt handler for a gi ven inter rupt l ev el via the VI RQx bits of
the LINT_EN register. Once a vector for a given level is acquired, the Universe II does not
perform a subsequent interrupt acknowledge c ycle at that lev el until the corresponding VIRQx
bit in the LINT_STAT register is cleared.
The acquisition of a leve l x STATUS/ID by the Universe II updates the STAT US/ID field of
the corresponding Vx_STATID regi ster and generation of a PCI interrupt. A VMEb us error
during the acquisition of the STATUS/ID v ector sets the ERR bi t, which means the
STATUS/ID field may not contain a valid vector.
Regist er Name: V3 _STATID Offset: 32C
Bits Function
31-24 Reserved
23-16 Reserved
15-08 Reserved ERR
07-00 STATID [7:0]
V3_STATID Description
Name Type Reset By Reset State Functio n
ERR R all 0 Error Status Bit
0=STATUS/ID was acquired with out b us error
1= bus error occu rred during acquisi tion of the STATUS/ID
STATID [7:0] R all 0 STATUS/ID acquired during IACK c y cle for le vel 3VMEbus
interrupt
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-81
Table A.69 : VIRQ4 STATUS/ID Register (V4_STATID)
The Vx_STATID registers are read-only r egisters that hold the 8-bit VMEbus STATUS/ID that
is acquired when the Universe II performs a IACK cycle for a given inte rrupt level. The
Univ erse II is enabled as the interr upt handler for a gi ven inter rupt l ev el via the VI RQx bits of
the LINT_EN register. Once a vector for a given level is acquired, the Universe II does not
perform a subsequent interrupt acknowledge c ycle at that lev el until the corresponding VIRQx
bit in the LI NT_STAT register is cleared.
The acquisition of a leve l x STATUS/ID by the Universe II updates the STAT US/ID field of
the corresponding Vx_STATID regi ster and generation of a PCI interrupt. A VMEb us error
during the acquisition of the STATUS/ID vector sets the ERR bit, which means the
STATUS/ID field may not contain a valid vector.
Regist er Name: V4 _STATID Offset: 330
Bits Function
31-24 Reserved
23-16 Reserved
15-08 Reserved ERR
07-00 STATID [7:0]
V4_STATID Description
Name Type Reset By Reset State Functio n
ERR R all 0 Error Status Bit
0=STATUS/ID was acquired with out b us error
1= bus error occu rred during acquisi tion of the STATUS/ID
STATID [7:0] R all 0 STATUS/ID acquired during IACK cycle for lev el 4 VMEbus
interrupt
Registers Universe II User Manual
App A-82 Tundra Semiconductor Corporation
Table A.70 : VIRQ5 STATUS/ID Register (V5_STATID)
The Vx_STATID registers are read-only r egisters that hold the 8-bit VMEbus STATUS/ID that
is acquired when the Universe II performs a IACK cycle for a given inte rrupt level. The
Univ erse II is enabled as the interr upt handler for a gi ven inter rupt l ev el via the VI RQx bits of
the LINT_EN register. Once a vector for a given level is acquired, the Universe II does not
perform a subsequent interrupt acknowledge c ycle at that lev el until the corresponding VIRQx
bit in the LINT_STAT register is cleared.
The acquisition of a leve l x STATUS/ID by the Universe II updates the STAT US/ID field of
the corresponding Vx_STATID regi ster and generation of a PCI interrupt. A VMEb us error
during the acquisition of the STATUS/ID v ector sets the ERR bi t, which means the
STATUS/ID field may not contain a valid vector.
Regist er Name: V5 _STATID Offset: 334
Bits Function
31-24 Reserved
23-16 Reserved
15-08 Reserved ERR
07-00 STATID [7:0]
V5_STATID Description
Name Type Reset By Reset State Functio n
ERR R all 0 Error Status Bit
0=STATUS/ID was acquired with out b us error
1= bus error occu rred during acquisi tion of the STATUS/ID
STATID [7:0] R all 0 STATUS/ID acquired during IACK cycle for lev el 5 VMEbus
interrupt
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-83
Table A.71 : VIRQ6 STATUS/ID Register (V6_STATID)
The Vx_STATID registers are read-only r egisters that hold the 8-bit VMEbus STATUS/ID that
is acquired when the Universe II performs a IACK cycle for a given inte rrupt level. The
Univ erse II is enabled as the interr upt handler for a gi ven inter rupt l ev el via the VI RQx bits of
the LINT_EN register. Once a vector for a given level is acquired, the Universe II does not
perform a subsequent interrupt acknowledge c ycle at that lev el until the corresponding VIRQx
bit in the LI NT_STAT register is cleared.
The acquisition of a leve l x STATUS/ID by the Universe II updates the STAT US/ID field of
the corresponding Vx_STATID regi ster and generation of a PCI interrupt. A VMEb us error
during the acquisition of the STATUS/ID vector sets the ERR bit, which means the
STATUS/ID field may not contain a valid vector.
Regist er Name: V6 _STATID Offset: 338
Bits Function
31-24 Reserved
23-16 Reserved
15-08 Reserved ERR
07-00 STATID [7:0]
V6_STATID Description
Name Type Reset By Reset State Functio n
ERR R all 0 Error Status Bit
0=STATUS/ID was acquired with out b us error
1= bus error occu rred during acquisi tion of the STATUS/ID
STATID [7:0] R all 0 STATUS/ID acquired during IACK cycle for lev el 6 VMEbus
interrupt
Registers Universe II User Manual
App A-84 Tundra Semiconductor Corporation
Table A.72 : VIRQ7 STATUS/ID Register (V7_STATID)
The Vx_STATID registers are read-only r egisters that hold the 8-bit VMEbus STATUS/ID that
is acquired when the Universe II performs a IACK cycle for a given inte rrupt level. The
Univ erse II is enabled as the interr upt handler for a gi ven inter rupt l ev el via the VI RQx bits of
the LINT_EN register. Once a vector for a given level is acquired, the Universe II does not
perform a subsequent interrupt acknowledge c ycle at that lev el until the corresponding VIRQx
bit in the LINT_STAT register is cleared.
The acquisition of a leve l x STATUS/ID by the Universe II updates the STAT US/ID field of
the corresponding Vx_STATID regi ster and generation of a PCI interrupt. A VMEb us error
during the acquisition of the STATUS/ID v ector sets the ERR bi t, which means the
STATUS/ID field may not contain a valid vector.
Regist er Name: V7 _STATID Offset: 33C
Bits Function
31-24 Reserved
23-16 Reserved
15-08 Reserved ERR
07-00 STATID [7:0]
V7_STATID Description
Name Type Reset By Reset State Functio n
ERR R all 0 Error Status Bit
0=STATUS/ID was acquired with out b us error
1= bus error occu rred during acquisi tion of the STATUS/ID
STATID [7:0] R all 0 STATUS/ID acquired during IACK cycle for lev el 7 VMEbus
interrupt
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-85
Tabl e A.73 : PCI Interrupt Map 2 Register (LINT_MAP2)
This regis ter maps various interrupt sources to one of the eight PCI interrupt pins. A value of
000 maps the corresponding interrupt source to L INT# [0] , a value of 001 m aps to LINT# [1],
etc.
Regist er Name: LINT_MAP2 Offset: 340
Bits Function
31-24 Reserved LM3 Reserved LM2
23-16 Reserved LM1 Reserved LM0
15-08 Reserved MBOX3 Reserved MBOX2
07-00 Reserved MBOX1 Reserved MBOX0
LINT_MAP2 Description
Name Type Reset By Reset State Functio n
LM3 [2:0] R/W all 0 Location Monitor 3 Interrupt destination
LM2 [2:0] R/W all 0 Location Monitor 2 Interrupt destination
LM1 [2:0] R/W all 0 Location Monitor 1 Interrupt destination
LM0 [2:0] R/W all 0 Location Monitor 0 Interrupt destination
MBOX3 [2:0] R/W all 0 Mailbox 3 Interrupt destination
MBOX2 [2:0] R/W all 0 Mailbox 2 Interrupt destination
MBOX1 [2:0] R/W all 0 Mailbox 1 Interrupt destination
MBOX0 [2:0] R/W all 0 Mailbox 0 Interrupt destination
Registers Universe II User Manual
App A-86 Tundra Semiconductor Corporation
Table A.74 : VME Inte rrupt Map 2 Register (VINT_MAP2)
This register maps various interrupt sour ces to one of the seven VMEbus interrupt pins. A
value of 001 maps the corresponding interrupt source to VIRQ*[1], a value of 002 maps to
VIRQ*[2], etc. A v alue of 000 effectively masks th e interrupt since there is no corresponding
VIRQ*[0].
Regist er Name: VINT_ MAP2 Offse t: 344
Bits Function
31-24 Reserved
23-16 Reserved
15-08 Reserved MBOX3 Reserved MBOX2
07-00 Reserved MBOX1 Reserved MBOX0
VINT_MAP2 Description
Name Type Reset By Reset State Functio n
MBOX3 [2:0] R/W all 0 Mailbox 3 Interrupt destination
MBOX2 [2:0] R/W all 0 Mailbox 2 Interrupt destination
MBOX1 [2:0] R/W all 0 Mailbox 1 Interrupt destination
MBOX0 [2:0] R/W all 0 Mailbox 0 Interrupt destination
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-87
Table A.75 : Mailbox 0 Register (MBOX0)
General purpose mailbox re gister. Writes to this register will cause interrupt generation on
PCI or VMEbus if enabled in LINT_EN register.
Register Name: MBOX0 Offset:348
Bits Function
31-24 MBOX0
23-16 MBOX0
15-08 MBOX0
07-00 MBOX0
DVA Description
Name Type Rese t By Reset State Function
MBOX0
[31:0] R/W all 0 Mailbox
Registers Universe II User Manual
App A-88 Tundra Semiconductor Corporation
Table A.76 : Mailbox 1 Register (MBOX1)
General purpose mailbox re gister. Writes to this register will cause interrupt generation on
PCI or VMEbus if enabled in LINT_EN re gis ter.
Register Name: MBOX1 Offset:34C
Bits Function
31-24 MBOX1
23-16 MBOX1
15-08 MBOX1
07-00 MBOX1
DVA Description
Name Type Rese t By Reset State Function
MBOX1
[31:0] R/W all 0 Mailbox
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-89
Table A.77 : Mailbox 2 Register (MBOX2)
General purpose mailbox re gister. Writes to this register will cause interrupt generation on
PCI or VMEbus if enabled in LINT_EN register.
Register Name: MBOX2 Offset:350
Bits Function
31-24 MBOX2
23-16 MBOX2
15-08 MBOX2
07-00 MBOX2
DVA Description
Name Type Rese t By Reset State Function
MBOX2
[31:0] R/W all 0 Mailbox
Registers Universe II User Manual
App A-90 Tundra Semiconductor Corporation
Table A.78 : Mailbox 3 Register (MBOX3)
General purpose mailbox re gister. Writes to this register will cause interrupt generation on
PCI or VMEbus if enabled in LINT_EN re gis ter.
Register Name: MBOX3 Offset:354
Bits Function
31-24 MBOX3
23-16 MBOX3
15-08 MBOX3
07-00 MBOX3
DVA Description
Name Type Rese t By Reset State Function
MBOX3
[31:0] R/W all 0 Mailbox
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-91
Table A.79 : Semaphore 0 Register (SEMA0)
If a semaphore bit is a v alue of 0, the associat ed tag field can be wri tten to. If a semaphor e bit
is a value of 1, the assoc iated tag field cannot be written to.
This register can only be accessed via byte -wide acce ss .
See “Semaphores” on page 2-109.
Regist er Name: SEMA0 Offset: 358
Bits Function
31-24 SEM3 TAG3
23-16 SEM2 TAG2
15-08 SEM1 TAG1
07-00 SEM0 TAG0
SEMA0 Desc ri ption
Name Type Reset By Reset State Functio n
SEM3 R/W all 0 S emaphore 3
TAG3 [6:0] R/W all 0Tag 3
SEM2 R/W all 0 S emaphore 2
TAG2 [6:0] R/W all 0Tag2
SEM1 R/W all 0 S emaphore 1
TAG1 [6:0] R/W all 0Tag 1
SEM0 R/W all 0 S emaphore 0
TAG0 [6:0] R/W all 0Tag 0
Registers Universe II User Manual
App A-92 Tundra Semiconductor Corporation
Table A.80 : Semaphore 1 Register (SEMA1)
If a semaphore bit is a v alue of 0, the associat ed tag field can be wri tten to. If a semaphor e bit
is a value of 1, the assoc iated tag field cannot be written to.
This register can only be accessed via byte -wide access.
See “Semaphores” on page 2-109.
Regist er Name: SEMA1 Offset: 35C
Bits Function
31-24 SEM7 TAG6
23-16 SEM6 TAG6
15-08 SEM5 TAG5
07-00 SEM4 TAG4
SEMA1 Desc ri ption
Name Type Reset By Reset State Functio n
SEM3 R/W all 0 S emaphore 7
TAG3 [6:0] R/W all 0Tag 7
SEM2 R/W all 0 S emaphore 6
TAG2 [6:0] R/W all 0Tag 6
SEM1 R/W all 0 S emaphore 5
TAG1 [6:0] R/W all 0Tag 5
SEM0 R/W all 0 S emaphore 4
TAG0 [6:0] R/W all 0Tag 4
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-93
Table A.81 : Master Control Register (MAST_CTL)
Regist er Name: MAST_CTL Offset: 400
Bits Function
31-24 MAXRTRY PWON
23-16 VRL VRM VREL VOWN VOWN_ACK Reserved
15-08 Reserved PABS Reserved
07-00 BUS_NO
MAST_CTL Description
Name Type Reset By Reset State Funct ion
MAXRTRY
[3:0] R/W all 1000 Maximum Number of Retries
0000=Retry Forev er , Multiples of 64 (0001 through 1111).
Maxim um Number of retries befor e the PCI maste r interfa ce
signal s error conditio n
PWON [3:0] R/W all 0000 P os ted Writ e Transfer C ount
0000=128 by tes, 00 01=256 bytes, 0010=512 bytes, 0011=1024
bytes, 0100=2048 bytes, 0101=4096 byte s , 0110 - 1110 =
Reserved, 1111=Early release of BBSY*.
T ransf e r count at which t he PCI Sla v e Chann el Post ed Wri tes FI FO
gives up the VME Master Interface.
VRL [1:0] R/W all 11 VMEbus Reques t Level
00 = Leve l 0,01 = L eve l 1,10 =Leve l 2, 11 =Leve l 3
VRM R/W all 0 VMEbus Request Mode
0=Demand,1=Fair
VREL R/W all 0 VME bus Release Mode
0= Release Wh en D one (RWD), 1=Rel eas e on Request (ROR)
VOWN W all 0 VME Ownership Bit
0= Release V MEbus, 1=Acquire and H old VMEbus
VOWN_ACK R all 0 VME Ownership Bit Acknowledge
0= V ME bus not ow ned, 1 =V MEbus acquired and held due to
as s erti o n of VOW N
PABS [1:0] R/W all 00 PCI Aligned Burst Size
00=32-byte, 01=64-byte, 10=128-byte, 11=Reserved
Con tr ols the PCI addres s bound ary at whi ch the Un iver s e II breaks
up a PC I transa ction in the VME Slave channel (s ee “V ME Sla ve
Images” on page 2-50) and the DMA C hannel (see “FIFO
Operation and Bus O w ner ship” on page 2-92).
This field also determines when the PCI Master Module as part of
the VME Sla ve Channel will request the PC I bu s (i. e., when 32 , 64 ,
or 128 bytes are available). It does not have this effect on the DMA
Channel, which has a fixed watermark of 128 bytes (see “FIFO
Operation and Bus O w ner ship” on page 2-92).
BUS_NO [7:0] R /W all 0000 0000 PCI Bus Number
Registers Universe II User Manual
App A-94 Tundra Semiconductor Corporation
Writing a 1 to the VOWN bit in the MAS T _CTL register has the effect of ass er ting BBSY*
until a 0 is written to the VOWN bit. It does not affect the transactions in the PCI Target
Channel. The Uni verse II will not do an early release of BBSY* if the VMEbus was owned
during a transaction b y means of VO WN, regardless of the v alue of PWON.
It is important to wait until VOWN_ACK is a value of 0 before writing a value of 1 to the
VOWN bit.
In the e vent that BERR* is asserted on the VMEb us once the Univ erse II owns the VMEbus,
the user must release owner ship b y programming the V OWN bit to a value of 0, if t he
VMEbus was gained b y se tting the V OWN bit. VMEb us masters must not write a v alue of 1 to
the VOWN bit since this will lock up the VMEb us .
Once the value programmed in the PWON field is reached during dequeuing of posted writes,
the Universe II will do an early release of BBSY*. If the PWON field is programmed to a
value of 1111, the Universe II will do an early release of BBSY* at the com pletion of each
transaction. Note that the VOWN setting described abov e overrides the POWN setting.
BUS_NO is use d by the VMEbus Slave Channel when mapping VME transactions into PCI
Configur ation space . If the bus number of the VMEbus address (bits [23:16]) is equal to the
BUS _NO f ield, then the Universe II generates a Type 0 configur ation cycle, otherwise Type 1
is generated.
The PABS[1:0] field also determines when the P CI Master Module as part of the VME Sla ve
Channel will request the PCI bus (i.e., when 32, 64, or 128 byte s are available). It does not
have this effect on the DM A Channel, which has a fixed watermar k of 128 bytes (see “FIFO
Operation and Bus Ownership” on page 2-92).
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-95
Table A.82 : Miscellaneous Control Register (MISC_CTL)
VMEbus masters must not write to SW_SYSRST, and PCI masters must not write to
SW_LRST.
Regist er Name: MISC_CTL Offset: 404
Bits Function
31-24 VBTO Reserved VARB VARBTO
23-16 SW_LRST SW_SRST Reserved BI ENGBI RESCIND SYSCON V64AUTO
15-08 Reserved
07-00 Reserved
MISC _CTL Des cri ption
Name Type Reset By Reset State Functio n
VBTO R/W all 0011 VME Bus Time-out
0000=Disable, 0001=16 µsec, 0010=32 µsec, 0011=64 µsec,
0100=128 µsec, 0101=256 µsec, 0110=512 µsec, 0111=1024
µ sec, othe r s = R ESE RV ED
VARB R/W all 0 VMEbus Arbitration Mode
0=Round Robin, 1=Priority
VARBTO R/W all 01 VMEbus Ar bitration Time-out
00=Disable Timer, 01=16 µs (minimum 8µs), 10=256 µs,
others=Reserved
SW_LRST W all 0 S of tware PCI Reset
0=No ef fect, 1=Initiate LRST#
A read al ways retur ns 0.
SW_SYSRST W all 0 Softw are VMEbus SYSR ESET
0=No ef fect, 1=Initiate SYSRST*
A read al ways retur ns 0.
BI R/W all Power-up
Option BI-Mode
0=Unive rse II is not in BI-Mode,
1=Unive rse II is in BI-Mode
Write to this bit to change the Univ erse II BI-Mode sta tus. This
bit is also affected by the global BI-Mode initiator VRIRQ1*, if
this feature is enabled.
ENGBI R/W all 0 Enable Global BI-M ode Initia to r
0=Assertion of VIRQ1 ignored, 1=Assertion of VIRQ1 puts
de vice in BI-Mode
RESCIND R/W all 1 RESCIND is unused in the Uni verse II.
SYSCON R/W all Power-up
Option SYSCON
0=Uni ve r se II is not VMEb us System Controller,
1=Uni ve r se II is VMEbu s System Controller
V64AUTO R/W all Power-up
Option VME64 Auto ID
Write: 0=No effect, 1=Initiate sequence
This bit initiates Univ erse II VME64 Auto ID Sla ve
participation.
Registers Universe II User Manual
App A-96 Tundra Semiconductor Corporation
The bits VBTO, VARB and VARBTO support SYSCON functionality.
Univ erse II partic ipation in the VME64 Auto ID mechanis m is controlled by the
VME64AUTO bit. Whe n this bit is detected high, the Universe II uses the SW_IAC K
mechanis m to generate VXIRQ2 on the VMEbus, then releases VXSYS FAIL . Acces s to the
CR/CSR image is enabled when the leve l 2 interrupt acknowledge cycle comple tes. This
sequence can be initiated with a power-up option or by software writing a 1 to this bit.
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-97
Table A.83 : Miscellaneous S tatus Register (MISC_STAT)
Register Name: MISC_STAT Offset: 408
Bits Function
31-24 Reserved LCLSIZE Reserved DY4AUTO Reserved
23-16 Reserved MYBBSY Reserved DY4_DONE TXFE RXFE Reserved
15-08 DY4AUTOID
07-00 Reserved
MISC_STAT Description
Name Type Reset By Reset State Functio n
LCLSIZE R all Power-up
Option PCI Bus Size
At the trailing edge of RST#, the Universe II sa mples REQ64# to
determine the PCI Bus size. This bit reflects the result.
0=32-bit, 1=64- bit
DY4AUTO R all Power-up
Option DY4 Auto ID Enable
0=Disable, 1=Enable
MYBBSY R all 1 Universe II BBSY
0=Asserted,1=Negated
DY4DONE R all 0 DY4 Auto ID Done
0=Not done,1=Done
TXFE R all 1 PCI Targe t Cha nne l Po sted Wr ite s FIFO
0= no data in the FIFO, 1=data in the F IFO
RXFE R all 1 VME Slave Ch annel Post ed Writes FIFO
0= no data in the FIFO, 1=data in the F IFO
DY4AUTOID R none 0 DY4 Auto ID
Registers Universe II User Manual
App A-98 Tundra Semiconductor Corporation
Table A.84 : User AM Codes Register (USER_AM)
The reset state is one of the VME64 user-defined AM codes.
The USER_AM regis ter can only be used to generate an d accept AM codes 0x10 through
0x1F. These AM codes are designated as USERAM codes in the VMEbus specification.
Regist er Name: USER_AM Offset: 40C
Bits Function
31-24 0 1 USER1AM Reserved
23-16 0 1 USER2AM Reserved
15-08 Reserved
07-00 Reserved
USER_AM Descrip tion
Name Type Reset By Reset State Functio n
USER1AM
[3:0] R/W all 0 000 Use r A M C ode 1
USER2AM
[3:0] R/W all 0 000 Use r A M C ode 2
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-99
Table A.85 : VMEbu s Slave Image 0 Control (VSI0_CTL)
This register provides the general, VMEbus and PCI controls for this slave image. Note that
only transactions destined for PCI Memory space are decoupled (the posted write RXFIFO
generates on Memor y space transactions on the PCI Bus). This image has 4 Kbyte resolution.
In order for a VMEbus slave image to respond to an incoming cycle, the BM bit in the
PCI_CSR register must be enabled.
The state of PWEN and PREN are ignored if LAS is not programmed memory space.
Register Name: VSI0_CTL Offset: F00
Bits Function
31-24 EN PWEN PREN Reserved
23-16 PGM SUPER Reserved VAS
15-08 Reserved
07-00 LD64EN LLRMW Reserved LAS
VSI0_CTL Description
Name Type Reset By Reset State Function
EN R/W PWR
VME
0 Ima ge En able
0=Disable, 1=Enable
PWEN R/W PWR
VME
0 Posted Write Enable
0=Disable, 1=Enable
PREN R/W PWR
VME
0 Prefetch Read Enable
0=Disable, 1=Enable
PGM R/W PWR
VME
11 P rogram/D a ta AM Code
00=Reserved, 01=Data, 1 0=Program, 11=Both
SUPER R/W PWR
VME
11 Supe rvisor/User AM Code
00=Reserved, 01=Non-Privileged, 1 0=Supervisor, 11=Bo th
VAS R/W PWR
VME
0 VMEbus Address Space
000=A 16, 001=A 24, 010=A32, 011= Reserved, 100=Reserved,
101=Reserved, 110=User1, 111=User2
LD64EN R/W PWR
VME
0 En a ble 64 - b i t PC I Bu s Tran s ac t i ons
0=Disable, 1=Enable
LLRMW R/W PWR
VME
0 Enable PCI Bus Lock of VMEbus RMW
0=Disable, 1=Enable
LAS R/W PWR
VME
0 PCI Bus Addres s Space
00=PCI Bus Memory Space, 01=PCI Bus I/O Space, 10=PCI
Bus C onfiguration Space, 11=R es er ved
Registers Universe II User Manual
App A-100 Tundra Semiconductor Corporation
Table A.86 : VMEbu s Slave Image 0 Base Addr ess Register (V SI0_BS)
The base address specifies the lowest address in the address ra nge that will be decoded.
This image has 4 Kbyte resolution.
Register Name: VSI0_BS Offset: F04
Bits Function
31-24 BS
23-16 BS
15-08 BS Reserved
07-00 Reserved
VSI0_BS Description
Name Type Rese t By Reset State Function
BS[31:12] R/W PWR
VME
0 Base Addr es s
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-101
Table A.87 : VMEbu s Slave Image 0 Bound Addres s Register (VSI0_BD)
The addresses decoded in a slave image are those which are greater than or equal to the base
address and less than the bound register.
This image has 4 Kbyte resolution.
Register Name: VSI0_BD Offset: F08
Bits Function
31-24 BD
23-16 BD
15-08 BD Reserved
07-00 Reserved
VSI0_BD Description
Name Type Rese t By Reset State Function
BD[31:12] R/W PWR VME 0 Bound A ddress
Registers Universe II User Manual
App A-102 Tundra Semiconductor Corporation
Table A.88 : VMEbu s Slave Image 0 Translation Offset (VSI0_TO)
This image has 4 Kbyte resolution.
Register Name: VSI0_TO Offse t: F0C
Bits Function
31-24 TO
23-16 TO
15-08 TO Reserved
07-00 Reserved
VSI0_TO Description
Name Type Rese t By Reset State Function
TO[31:12] R/W PWR VME 0 Translation Offset
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-103
Table A.89 : VMEbu s Slave Image 1 Control (VSI1_CTL)
This register provides the general, VMEbus and PCI controls for this slave image. Note that
only transactions destined for PCI Memory space are decoupled (the posted write RXFIFO
generates on Memor y space transactions on the PCI Bus).
In order for a VMEbus slave image to respond to an incoming cycle, the BM bit in the
PCI_CSR register must be enabled.
The state of PWEN and PREN are ignored if LAS is not programmed memory space.
Register Name: VSI1_CTL Offset: F14
Bits Function
31-24 EN PWEN PREN Reserved
23-16 PGM SUPER Reserved VAS
15-08 Reserved
07-00 LD64EN LLRMW Reserved LAS
VSI1_CTL Description
Name Type Reset By Reset State Function
EN R/W PWR
VME
0 Ima ge En able
0=Disable, 1=Enable
PWEN R/W PWR
VME
0 Posted Write Enable
0=Disable, 1=Enable
PREN R/W PWR
VME
0 Prefetch Read Enable
0=Disable, 1=Enable
PGM R/W PWR
VME
11 P rogram/D a ta AM Code
00=Reserved, 01=Data, 1 0=Program, 11=Both
SUPER R/W PWR
VME
11 Supe rvisor/User AM Code
00=Reserved, 01=Non-Privileged, 1 0=Supervisor, 11=Bo th
VAS R/W PWR
VME
0 VMEbus Address Space
000=Reserve d, 001=A24, 010=A32, 011= Res e r ved,
100=Reserved, 101=Reserved, 110=User1, 111=User2
LD64EN R/W PWR
VME
1 En a ble 64 - b i t PC I Bu s Tran s ac t i ons
0=Disable, 1=Enable
LLRMW R/W PWR
VME
1 Enable PCI Bus Lock of VMEbus RMW
0=Disable, 1=Enable
LAS R/W PWR
VME
0 PCI Bus Addres s Space
00=PCI Bus Memory Space, 01=PCI Bus I/O Space, 10=PCI
Bus C onfiguration Space, 11=R es er ved
Registers Universe II User Manual
App A-104 Tundra Semiconductor Corporation
Table A.90 : VMEbu s Slave Image 1 Base Addr ess Register (V SI1_BS)
The base address specifies the lowest address in the address ra nge that will be decoded.
Register Name: VSI1_BS Offset: F18
Bits Function
31-24 BS
23-16 BS
15-08 Reserved
07-00 Reserved
VSI1_BS Description
Name Type Rese t By Reset State Function
BS[31:16] R/W PWR VME 0 Base Addre s s
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-105
Table A.91 : VMEbu s Slave Image 1 Bound Addres s Register (VSI1_BD)
The addresses decoded in a slave image are those which are greater than or equal to the base
address and less than the bound register.
Register Name: VSI1_BD Offset: F1C
Bits Function
31-24 BD
23-16 BD
15-08 Reserved
07-00 Reserved
VSI1_BD Description
Name Type Rese t By Reset State Function
BD[31:16] R/W PWR VME 0 Bound A ddress
Registers Universe II User Manual
App A-106 Tundra Semiconductor Corporation
Table A.92 : VMEbu s Slave Image 1 Translation Offset (VSI1_TO)
Register Name: VSI1_TO Offset: F20
Bits Function
31-24 TO
23-16 TO
15-08 Reserved
07-00 Reserved
VSI1_TO Description
Name Type Rese t By Reset State Function
TO[31:16] R/W PW R VME 0 Translation Offset
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-107
Table A.93 : VMEbu s Slave Image 2 Control (VSI2_CTL)
This register provides the general, VMEbus and PCI controls for this slave image. Note that
only transactions destined for PCI Memory space are decoupled (the posted write RXFIFO
generates on Memor y space transactions on the PCI Bus).
In order for a VMEbus slave image to respond to an incoming cycle, the BM bit in the
PCI_CSR register must be enabled.
The state of PWEN and PREN are ignored if LAS is not programmed memory space.
Register Name: VSI2_CTL Offset: F28
Bits Function
31-24 EN PWEN PREN Reserved
23-16 PGM SUPER Reserved VAS
15-08 Reserved
07-00 LD64EN LLRMW Reserved LAS
VSI2_CTL Description
Name Type Reset By Reset State Function
EN R/W PWR
VME
0 Ima ge En able
0=Disable, 1=Enable
PWEN R/W PWR
VME
0 Posted Write Enable
0=Disable, 1=Enable
PREN R/W PWR
VME
0 Prefetch Read Enable
0=Disable, 1=Enable
PGM R/W PWR
VME
11 P rogram/D a ta AM Code
00=Reserved, 01=Data, 1 0=Program, 11=Both
SUPER R/W PWR
VME
11 Supe rvisor/User AM Code
00=Reserved, 01=Non-Privileged, 1 0=Supervisor, 11=Bo th
VAS R/W PWR
VME
0 VMEbus Address Space
000=Reserve d, 001=A24, 010=A32, 011= Res e r ved,
100=Reserved, 101=Reserved, 110=User1, 111=User2
LD64EN R/W PWR
VME
0 En a ble 64 - b i t PC I Bu s Tran s ac t i ons
0=Disable, 1=Enable
LLRMW R/W PWR
VME
0 Enable PCI Bus Lock of VMEbus RMW
0=Disable, 1=Enable
LAS R/W PWR
VME
0 PCI Bus Addres s Space
00=PCI Bus Memory Space, 01=PCI Bus I/O Space, 10=PCI
Bus C onfiguration Space, 11=R es er ved
Registers Universe II User Manual
App A-108 Tundra Semiconductor Corporation
Table A.94 : VMEbu s Slave Image 2 Base Addr ess Register (V SI2_BS)
Register Name: VSI2_BS Offset: F2C
Bits Function
31-24 BS
23-16 BS
15-08 Reserved
07-00 Reserved
VSI2_BS Description
Name Type Rese t By Reset State Function
BS[31:16] R/W PWR VME 0 Base Addre s s
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-109
Table A.95 : VMEbu s Slave Image 2 Bound Addres s Register (VSI2_BD)
Register Name: VSI2_BD Offset: F30
Bits Function
31-24 BD
23-16 BD
15-08 Reserved
07-00 Reserved
VSI2_BD Description
Name Type Rese t By Reset State Function
BD[31:16] R/W PWR VME 0 Bound A ddress
Registers Universe II User Manual
App A-110 Tundra Semiconductor Corporation
Table A.96 : VMEbu s Slave Image 2 Translation Offset (VSI2_TO)
Register Name: VSI2_TO Offset: F34
Bits Function
31-24 TO
23-16 TO
15-08 Reserved
07-00 Reserved
VSI2_TO Description
Name Type Rese t By Reset State Function
TO[31:16] R/W PW R VME 0 Tran sla tio n Offset
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-111
Table A.97 : VMEbu s Slave Image 3 Control (VSI3_CTL)
This register provides the general, VMEbus and PCI controls for this slave image. Note that
only transactions destined for PCI Memory space are decoupled (the posted write RXFIFO
generates on Memor y space transactions on the PCI Bus).
In order for a VMEbus slave image to respond to an incoming cycle, the BM bit in the
PCI_CSR register must be enabled.
The state of PWEN and PREN are ignored if LAS is not programmed memory space.
Register Name: VSI3_CTL Offset: F3C
Bits Function
31-24 EN PWEN PREN Reserved
23-16 PGM SUPER Reserved VAS
15-08 Reserved
07-00 LD64EN LLRMW Reserved LAS
VSI3_CTL Description
Name Type Reset By Reset State Function
EN R/W PWR
VME
0 Ima ge En able
0=Disable, 1=Enable
PWEN R/W PWR
VME
0 Posted Write Enable
0=Disable, 1=Enable
PREN R/W PWR
VME
0 Prefetch Read Enable
0=Disable, 1=Enable
PGM R/W PWR
VME
11 P rogram/D a ta AM Code
00=Reserved, 01=Data, 1 0=Program, 11=Both
SUPER R/W PWR
VME
11 Supe rvisor/User AM Code
00=Reserved, 01=Non-Privileged, 1 0=Supervisor, 11=Bo th
VAS R/W PWR
VME
0 VMEbus Address Space
000=Reserve d, 001=A24, 010=A32, 011= Res e r ved,
100=Reserved, 101=Reserved, 110=User1, 111=User2
LD64EN R/W PWR
VME
0 En a ble 64 - b i t PC I Bu s Tran s ac t i ons
0=Disable, 1=Enable
LLRMW R/W PWR
VME
0 Enable PCI Bus Lock of VMEbus RMW
0=Disable, 1=Enable
LAS R/W PWR
VME
0 PCI Bus Addres s Space
00=PCI Bus Memory Space, 01=PCI Bus I/O Space, 10=PCI
Bus C onfiguration Space, 11=R es er ved
Registers Universe II User Manual
App A-112 Tundra Semiconductor Corporation
Table A.98 : VMEbu s Slave Image 3 Base Addr ess Register (V SI3_BS)
Register Name: VSI3_BS Offset: F40
Bits Function
31-24 BS
23-16 BS
15-08 Reserved
07-00 Reserved
VSI3_BS Description
Name Type Rese t By Reset State Function
BS[31:16] R/W PWR VME 0 Base Addre s s
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-113
Table A.99 : VMEbu s Slave Image 3 Bound Addres s Register (VSI3_BD)
Register Name: VSI3_BD Offset: F44
Bits Function
31-24 BD
23-16 BD
15-08 Reserved
07-00 Reserved
VSI3_BD Description
Name Type Rese t By Reset State Function
BD[31:16] R/W PWR VME 0 Bound A ddress
Registers Universe II User Manual
App A-114 Tundra Semiconductor Corporation
Table A.100 : VMEb us Sla ve Image 3 Translation Offset (VSI3_T O)
Register Name: VSI3_TO Offset: F48
Bits Function
31-24 TO
23-16 TO
15-08 Reserved
07-00 Reserved
VSI3_TO Description
Name Type Rese t By Reset State Function
TO[31:16] R/W PW R VME 0 Tran sla tio n Offset
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-115
Table A.101 : Location Monitor Control Register ( LM_CTL)
This register specifies the V MEbus controls for the location monitor image. This image has a
4 Kbyte res olution and a 4 Kbyte s ize. The image responds to a VME read or write within the
4 Kbyte space and matching one of the address modifier codes specified. BLTs and MBLTs
are not supported.
VMEbus address bits [4:3] are used to set the status bit in LINT_STAT for one of the four
location monitor interr upts. If the Universe II VMEb us master is the owne r of the VMEb us ,
the Universe II VMEbus slave will generate DTACK * to terminate the transaction.
The Location Monitor does not store write data and read data is undefined.
Regis ter Name: L M_ CTL Offset: F64
Bits Function
31-24 EN Reserved
23-16 PGM SUPER Reserved VAS
15-08 Reserved
07-00 Reserved
LM_CTL Description
Name Type Rese t By Reset State Function
EN R/W PWR VME 0 Ima ge En able
0= Disa ble, 1=Enabl e
PGM R/W PWR VME 11 Program/ D a ta AM Code
00=Reserved, 01=Data , 10=Program, 11=Both
SUPER R/W PWR VME 11 Supervisor/User AM Code
00=Reserved, 01=Non-Privileged, 10=Supervisor, 11=Both
VAS R /W PWR VME 0 VMEb us Address Space
000=A16, 001=A24, 010=A32, 011=Reserved, 100=Reserved,
101=Reserved , others=Reserved
Registers Universe II User Manual
App A-116 Tundra Semiconductor Corporation
Table A.102 : Location Monitor Base Addr ess Register (LM_BS)
The base address specifies the lowest address in the 4 Kbyte range that will be decoded a s a
location monitor ac cess.
Regis ter Name: L M_ BS Offset: F68
Bits Function
31-24 BS
23-16 BS
15-08 Reserved
07-00 Reserved
LM_BS Descri ption
Name Type Rese t By Reset State Function
BS [31:16] R/W PWR VME 0 Base Addres s
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-117
Table A.103 : VMEbus Regist er Access Image Control Register
(VRAI_CTL)
The VME Registe r Access Image allows access to the Unive rs e II registers with standar d
VMEbus cycles . Only single cycle and lock AM codes are accept ed. When a regis ter is
accessed with a RMW, it is locked for the duration of the transaction.
Register Name: VRAI_CTL Offset: F70
Bits Function
31-24 EN Reserved
23-16 PGM SUPER Reserved VAS
15-08 Reserved
07-00 Reserved
VRAI_CTL Desc ription
Name Type Rese t By Reset State Function
EN R/W PWR VME Power-up
Option Image Enable
0= Disa ble, 1=Enabl e
PGM R/W PWR VME 11 Program/Data AM Code
00=Reserved, 01=Data , 10=Program, 11=Both
SUPER R/W PWR VME 11 Supervisor/User AM Code
00=Reserved, 01=Non-Privileged, 10=Supervisor, 11=Both
VAS R /W PWR VME Po wer-up
Option VMEbus Address Space
00=A 16, 01 =A 24, 10= A 32, all others are r eserv ed
Registers Universe II User Manual
App A-118 Tundra Semiconductor Corporation
Table A.104 : VMEbu s Register Access Image Base Addr ess Register
(VRAI_BS)
The base address specifies the lowest address in the 4 Kbyte VMEbus Register Access Image.
The reset state is a function of the Power- up Option behaviour of the VAS field in
VRAI_CTL:
Register Name: VRAI_BS Offset: F74
Bits Function
31-24 BS
23-16 BS
15-08 BS Reserved
07-00 Reserved
VRAI_BS Description
Name Type Reset By Reset State Function
BS[31:12] R/W PWR VME Power-up
Option The base address specifies t he lo west address in the 4 Kbyte
VMEbus Register Access Image.
VRAI_CTL: VAS BS [31:24] BS [23:16] BS [15:12]
A16 0 0 Pow er-up Option VA [28:25]
A24 0 Pow e r-up Option VA [28:21] 0
A3 2 Powe r-u p O ption VA [2 8 : 21 ] 0 0
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-119
Table A.105 : VMEb us CSR Control Register (VCSR_CTL)
The EN bit al lows softw are to enable or disable the Uni verse II CR/CSR image. This image
can also be ena bled by the VME64 Auto ID process.
For CSR's not supported in the Uni verse II and for CR accesses, the LAS f ield determines the
PCI Bus comma nd that will be gener ated when the cycle is mapped to the PCI Bus.
Register Name: VCSR_CTL Offset: F80
Bits Function
31-24 EN Reserved
23-16 Reserved
15-08 Reserved
07-00 Reserved LAS
VCSR_CTL Description
Name Type Rese t By Reset State Function
EN R /W PW R ,VM E 0 Im age En able
0= Disa ble, 1=Enabl e
LAS R/W PWR VME Power-up
Option PCI Bus Address Space
00=PCI Bus Memory Space, 01=PCI Bus I/O S pace, 10=PCI
Bus C onfiguration Space, 11=Res erved
Registers Universe II User Manual
App A-120 Tundra Semiconductor Corporation
Table A.106 : VMEb us CSR Translation Offset (VCSR_TO)
For CSR's not supported in the Univ erse II and for CR accesses, the translation offset is added
to the 24-bit VMEbus address to produce a 32-bit PCI Bus address. Negative of fsets are not
supported.
Register Name: VCSR_TO Offset: F84
Bits Function
31-24 TO
23-16 TO Reserved
15-08 Reserved
07-00 Reserved
VCSR_TO Description
Name Type Rese t By Reset State Function
TO [31:24] R /W PWR VME 0 Translation Offset
TO [23:19] R/W PWR VME Power-up
Option Translation Offset
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-121
Table A.107 : VMEbus AM Code Error Log (V_AMERR)
The Universe II VMEbus Master Interface is respons ible for logging the parameters of a
posted write transac tion that results in a bus err or. Thi s register holds the address modif ier
code and the state of the IACK* signal. The re gis ter contents are qualif ied by the V_STAT bit.
Regist er Name: V_ AMERR Offset: F88
Bits Function
31-24 AMERR IACK M_ERR
23-16 V_STAT Reserved
15-08 Reserved
07-00 Reserved
V_AMERR Description
Name Type Reset By Reset State Functio n
AMERR [5:0] R PWR, VME 0 VMEbus AM Code Error Log
IACK R PWR, VME 0 VMEbus IACK Signal
M_ERR R PWR, VME 0 Multiple Error Occurred
0= Si ngle error, 1 =A t l eas t one error has occurred s ince the logs
were frozen
V_STAT R/W PWR, VME 0 VME Error Log Statu s
Reads:
0= logs invalid, 1= logs are valid and error log ging halt ed
Writes:
0= no effect, 1=clears V_STAT and ena bles err or logging
Registers Universe II User Manual
App A-122 Tundra Semiconductor Corporation
Table A.108 : VMEbus Address Error Log (VAERR)
The Universe II PCI Master Inte rface is responsible for logging the parameters of a pos ted
write transaction that results in a bus error. This register holds the address. The re gister
contents are qualified by the V_STAT bit of the V_AMERR register.
Regis ter Name: VAERR Offse t: F8C
Bits Function
31-24 VAERR
23-16 VAERR
15-08 VAERR
07-00 VAERR
VAERR Descripti on
Name Type Reset By Reset State Functio n
VAERR [31:0] R PWR, VME 0 VMEbus address error log
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-123
Table A.109 : VMEb us Sla ve Image 4 Control (VSI4_CTL)
This register provides the general, VMEbus and PCI controls for this slave image. Note that
only transactions destined for PCI Memory space are decoupled (the posted write RXFIFO
generates on Memor y space transactions on the PCI Bus). This image has 4 Kbyte resolution.
In order for a VMEbus slave image to respond to an incoming cycle, the BM bit in the
PCI_CSR register must be enabled.
The state of PWEN and PREN are ignored if LAS is not programmed memory space.
Register Name: VSI4_CTL Offset: F90
Bits Function
31-24 EN PWEN PREN Reserved
23-16 PGM SUPER Reserved VAS
15-08 Reserved
07-00 LD64EN LLRMW Reserved LAS
VSI4_CTL Description
Name Type Reset By Reset State Function
EN R/W PWR, VME 0 Im age Enab le
0=Disable, 1=Enable
PWEN R/W PWR, VME 0 Posted Write Enable
0=Disable, 1=Enable
PREN R/W PWR, VME 0 Pre fetch Re ad Enable
0=Disable, 1=Enable
PGM R/W PWR, VME 11 Pro gram/Data AM Code
00=Reserved, 01=Data, 1 0=Program, 11=Both
SUPER R/W PWR, VME 11 Sup ervisor/ User AM Code
00=Reserved, 01=Non-Privileged, 1 0=Supervisor, 11=Bo th
VAS R/W PWR, VME 0 VMEbus Address Space
000=A 16, 001=A 24, 010=A32, 011= Reserved, 100=Reserved,
101=Reserved, 110=User1, 111=User2
LD64EN R/W PWR, VME 0 Ena ble 64 - b i t PC I Bu s Tran s ac t i ons
0=Disable, 1=Enable
LLRMW R/W PWR, VME 0 Enable PCI Bus Lock of VMEbus RMW
0=Disable, 1=Enable
LAS R/W PWR, VME 0 PCI Bus A ddress Space
00=PCI Bus Memory Space, 01=PCI Bus I/O Space, 10=PCI
Bus C onfiguration Space, 11=R es er ved
Registers Universe II User Manual
App A-124 Tundra Semiconductor Corporation
Table A.110 : VMEb us Sla ve Image 4 Base Address Register (VSI4_BS)
The base address specifies the lowest address in the address ra nge that will be decoded.
This image has 4 Kbyte resolution.
Register Name: VSI4_BS Offset: F94
Bits Function
31-24 BS
23-16 BS
15-08 BS Reserved
07-00 Reserved
VSI4_BS Description
Name Type Rese t By Reset State Function
BS[31:1 2] R/W P WR VME 0 Base Address
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-125
Table A.111 : VMEb us Sla ve Image 4 Bound Address Register (VSI4_BD)
The addresses decoded in a slave image are those which are greater than or equal to the base
address and less than the bound register. If the bound re gister is 0, then the addresses decoded
are those greater than or equal to the base address.
This image has 4 Kbyte resolution.
Register Name: VSI4_BD Offset: F98
Bits Function
31-24 BD
23-16 BD
15-08 BD Reserved
07-00 Reserved
VSI4_BD Description
Name Type Rese t By Reset State Function
BD[31:12] R/W P WR V ME 0 Bound Address
Registers Universe II User Manual
App A-126 Tundra Semiconductor Corporation
Table A.112 : VMEb us Sla ve Image 4 Translation Offset (VSI4_T O)
The translation offset is added to the source address that is d ecoded and this new address
becomes the dest ination address. If a negati v e of fset is desired, the of fset must be expressed as
a two’s complement.
This image has 4 Kbyte resolution.
Register Name: VSI4_TO Offse t: F9C
Bits Function
31-24 TO
23-16 TO
15-08 TO Reserved
07-00 Reserved
VSI4_TO Description
Name Type Rese t By Reset State Function
TO[31:12] R/W PWR VME 0 Translation Offset
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-127
Table A.113 : VMEb us Sla ve Image 5 Control (VSI5_CTL)
This register provides the general, VMEbus and PCI controls for this slave image. Note that
only transactions destined for PCI Memory space are decoupled (the posted write RXFIFO
generates on Memor y space transactions on the PCI Bus).
In order for a VMEbus slave image to respond to an incoming cycle, the BM bit in the
PCI_CSR register must be enabled.
The state of PWEN and PREN are ignored if LAS is not programmed memory space.
Register Name: VSI5_CTL Offset: FA4
Bits Function
31-24 EN PWEN PREN Reserved
23-16 PGM SUPER Reserved VAS
15-08 Reserved
07-00 LD64EN LLRMW Reserved LAS
VSI5_CTL Description
Name Type Reset By Reset State Function
EN R/W PWR V ME 0 Image Enab le
0=Disable, 1=Enable
PWEN R/W PWR VME 0 Posted Write Enable
0=Disable, 1=Enable
PREN R/W PWR VME 0 Pre f etch Read Enable
0=Disable, 1=Enable
PGM R/W PWR VME 11 Program/Data A M Code
00=Reserved, 01=Data, 1 0=Program, 11=Both
SUPER R/W PWR VME 1 1 Supe rvisor/ User AM Code
00=Reserved, 01=Non-Privileged, 1 0=Supervisor, 11=Bo th
VAS R/W PWR VME 0 VMEb us Address Space
000=Reserve d, 001=A24, 010=A32, 011= Res e r ved,
100=Reserved, 101=Reserved, 110=User1, 111=User2
LD64EN R/W P WR V ME 0 Enabl e 64-bit PCI Bus Tran sacti ons
0=Disable, 1=Enable
LLRMW R/W PWR VME 0 Enable PCI Bus Lock of VMEbus RMW
0=Disable, 1=Enable
LAS R/W PWR VME 0 PCI Bus Add ress Space
00=PCI Bus Memory Space, 01=PCI Bus I/O Space, 10=PCI
Bus C onfiguration Space, 11=R es er ved
Registers Universe II User Manual
App A-128 Tundra Semiconductor Corporation
Table A.114 : VMEb us Sla ve Image 5 Base Address Register (VSI5_BS)
The base address specifies the lowest address in the address ra nge that will be decoded.
Register Name: VSI5_BS Offset: FA8
Bits Function
31-24 BS
23-16 BS
15-08 Reserved
07-00 Reserved
VSI5_BS Description
Name Type Rese t By Reset State Function
BS[31:1 6] R/W P WR VME 0 Base Address
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-129
Table A.115 : VMEb us Sla ve Image 5 Bound Address Register (VSI5_BD)
The addresses decoded in a slave image are those which are greater than or equal to the base
address and less than the bound register. If the bound re gister is 0, then the addresses decoded
are those greater than or equal to the base address,
Register Name: VSI5_BD Offset: FAC
Bits Function
31-24 BD
23-16 BD
15-08 Reserved
07-00 Reserved
VSI5_BD Description
Name Type Rese t By Reset State Function
BD[31:16] R/W P WR V ME 0 Bound Address
Registers Universe II User Manual
App A-130 Tundra Semiconductor Corporation
Table A.116 : VMEb us Sla ve Image 5 Translation Offset (VSI5_T O)
The translation offset is added to the source address that is d ecoded and this new address
becomes the dest ination address. If a negati v e of fset is desired, the of fset must be expressed as
a two’s complement.
Register Name: VSI5_TO Offset: FB0
Bits Function
31-24 TO
23-16 TO
15-08 Reserved
07-00 Reserved
VSI5_TO Description
Name Type Rese t By Reset State Function
TO[31:16] R/W PWR VME 0 Translation Offset
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-131
Table A.117 : VMEb us Sla ve Image 6 Control (VSI6_CTL)
This register provides the general, VMEbus and PCI controls for this slave image. Note that
only transactions destined for PCI Memory space are decoupled (the posted write RXFIFO
generates on Memor y space transactions on the PCI Bus).
In order for a VMEbus slave image to respond to an incoming cycle, the BM bit in the
PCI_CSR register must be enabled.
The state of PWEN and PREN are ignored if LAS is not programmed memory space.
Register Name: VSI6_CTL Offset: FB8
Bits Function
31-24 EN PWEN PREN Reserved
23-16 PGM SUPER Reserved VAS
15-08 Reserved
07-00 LD64EN LLRMW Reserved LAS
VSI6_CTL Description
Name Type Reset By Reset State Function
EN R/W PWR V ME 0 Image Enab le
0=Disable, 1=Enable
PWEN R/W PWR VME 0 Posted Write Enable
0=Disable, 1=Enable
PREN R/W PWR VME 0 Pre f etch Read Enable
0=Disable, 1=Enable
PGM R/W PWR VME 11 Program/Data A M Code
00=Reserved, 01=Data, 1 0=Program, 11=Both
SUPER R/W PWR VME 1 1 Supe rvisor/ User AM Code
00=Reserved, 01=Non-Privileged, 1 0=Supervisor, 11=Bo th
VAS R/W PWR VME 0 VMEb us Address Space
000=Reserve d, 001=A24, 010=A32, 011= Res e r ved,
100=Reserved, 101=Reserved, 110=User1, 111=User2
LD64EN R/W P WR V ME 0 Enabl e 64-bit PCI Bus Tran sacti ons
0=Disable, 1=Enable
LLRMW R/W PWR VME 0 Enable PCI Bus Lock of VMEbus RMW
0=Disable, 1=Enable
LAS R/W PWR VME 0 PCI Bus Add ress Space
00=PCI Bus Memory Space, 01=PCI Bus I/O Space, 10=PCI
Bus C onfiguration Space, 11=R es er ved
Registers Universe II User Manual
App A-132 Tundra Semiconductor Corporation
Table A.118 : VMEb us Sla ve Image 6 Base Address Register (VSI6_BS)
The base address specifies the lowest address in the address ra nge that will be decoded.
Register Name: VSI6_BS Offset: FBC
Bits Function
31-24 BS
23-16 BS
15-08 Reserved
07-00 Reserved
VSI6_BS Description
Name Type Rese t By Reset State Function
BS[31:1 6] R/W P WR VME 0 Base Address
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-133
Table A.119 : VMEb us Sla ve Image 6 Bound Address Register (VSI6_BD)
The addresses decoded in a slave image are those which are greater than or equal to the base
address and less than the bound register. If the bound re gister is 0, then the addresses decoded
are those greater than or equal to the base address,
Register Name: VSI6_BD Offset: FC0
Bits Function
31-24 BD
23-16 BD
15-08 Reserved
07-00 Reserved
VSI6_BD Description
Name Type Rese t By Reset State Function
BD[31:16] R/W P WR V ME 0 Bound Address
Registers Universe II User Manual
App A-134 Tundra Semiconductor Corporation
Table A.120 : VMEb us Sla ve Image 6 Translation Offset (VSI6_T O)
The translation offset is added to the source address that is d ecoded and this new address
becomes the dest ination address. If a negati v e of fset is desired, the of fset must be expressed as
a two’s complement.
Register Name: VSI6_TO Offse t: FC4
Bits Function
31-24 TO
23-16 TO
15-08 Reserved
07-00 Reserved
VSI6_TO Description
Name Type Rese t By Reset State Function
TO[31:16] R/W PWR VME 0 Translation Offset
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-135
Table A.121 : VMEb us Sla ve Image 7 Control (VSI7_CTL)
This register provides the general, VMEbus and PCI controls for this slave image. Note that
only transactions destined for PCI Memory space are decoupled (the posted write RXFIFO
generates on Memor y space transactions on the PCI Bus).
In order for a VMEbus slave image to respond to an incoming cycle, the BM bit in the
PCI_CSR register must be enabled.
The state of PWEN and PREN are ignored if LAS is not programmed memory space.
Register Name: VSI7_CTL Off set: FCC
Bits Function
31-24 EN PWEN PREN Reserved
23-16 PGM SUPER Reserved VAS
15-08 Reserved
07-00 LD64EN LLRMW Reserved LAS
VSI7_CTL Description
Name Type Reset By Reset State Function
EN R/W PWR V ME 0 Image Enab le
0=Disable, 1=Enable
PWEN R/W PWR VME 0 Posted Write Enable
0=Disable, 1=Enable
PREN R/W PWR VME 0 Pre f etch Read Enable
0=Disable, 1=Enable
PGM R/W PWR VME 11 Program/Data A M Code
00=Reserved, 01=Data, 1 0=Program, 11=Both
SUPER R/W PWR VME 1 1 Supe rvisor/ User AM Code
00=Reserved, 01=Non-Privileged, 1 0=Supervisor, 11=Bo th
VAS R/W PWR VME 0 VMEb us Address Space
000=Reserve d, 001=A24, 010=A32, 011= Res e r ved,
100=Reserved, 101=Reserved, 110=User1, 111=User2
LD64EN R/W P WR V ME 0 Enabl e 64-bit PCI Bus Tran sacti ons
0=Disable, 1=Enable
LLRMW R/W PWR VME 0 Enable PCI Bus Lock of VMEbus RMW
0=Disable, 1=Enable
LAS R/W PWR VME 0 PCI Bus Add ress Space
00=PCI Bus Memory Space, 01=PCI Bus I/O Space, 10=PCI
Bus C onfiguration Space, 11=R es er ved
Registers Universe II User Manual
App A-136 Tundra Semiconductor Corporation
Table A.122 : VMEb us Sla ve Image 7 Base Address Register (VSI7_BS)
The base address specifies the lowest address in the address ra nge that will be decoded.
Register Name: VSI7_BS Offset: FD0
Bits Function
31-24 BS
23-16 BS
15-08 Reserved
07-00 Reserved
VSI7_BS Description
Name Type Rese t By Reset State Function
BS[31:1 6] R/W P WR VME 0 Base Address
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-137
Table A.123 : VMEb us Sla ve Image 7 Bound Address Register (VSI7_BD)
The addresses decoded in a slave image are those which are greater than or equal to the base
address and less than the bound register. If the bound re gister is 0, then the addresses decoded
are those greater than or equal to the base address,
Register Name: VSI7_BD Offset: FD4
Bits Function
31-24 BD
23-16 BD
15-08 Reserved
07-00 Reserved
VSI7_BD Description
Name Type Rese t By Reset State Function
BD[31:16] R/W P WR V ME 0 Bound Address
Registers Universe II User Manual
App A-138 Tundra Semiconductor Corporation
Table A.124 : VMEb us Sla ve Image 7 Translation Offset (VSI7_T O)
Register Name: VSI7_TO Offse t: FD8
Bits Function
31-24 TO
23-16 TO
15-08 Reserved
07-00 Reserved
VSI7_TO Description
Name Type Rese t By Reset State Function
TO[31:16] R/W PWR VME 0 Translation Offset
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-139
Table A.125 : VMEbus CSR Bit Clear Register (VCSR_CLR)
This register implements the Bit Clear Re gis ter as defined in the VME64 specification. Note
that the RES ET bit can be written to only from the VMEb us .
Register Name: VCSR_CLR Offset: FF4
Bits Function
31-24 RESET SYSFAIL FAIL Reserved
23-16 Reserved
15-08 Reserved
07-00 Reserved
VCSR_CLR Descrip tion
Name Type Rese t By Reset State Function
RESET R/W PWR VME 0 Board Reset
Reads: 0= LRST# not asse rted, 1=LRST# asserted
Writes: 0=no effect, 1=negate LRST#
SYSFAIL R/W all Power-up
Option VMEbus SYSFAIL
Reads: 0= VXSYSFAIL not asserted, 1=VXSYSFAIL asserted
Writes:0=no effect, 1=negate VXSYSFAIL
FAIL R PWR VME 0 Board Fail
0= Bo ard has not failed
Registers Universe II User Manual
App A-140 Tundra Semiconductor Corporation
Table A.126 : VMEb us CSR Bit Set Regist er (VCSR_SET)
This register implements the Bit Set Re gister as def ine d in the VME64 spec ification. Note that
the RESET bit can be written to only from the VMEb us. Writing 1 to the RESET bit asserts
LRST#. The PCI reset remains asserted until a 1 is written to the RESET bit of the
VCSR_CLR register.
Register Name: VCSR_SET Offset: FF8
Bits Function
31-24 RESET SYSFAIL FAIL Reserved
23-16 Reserved
15-08 Reserved
07-00 Reserved
VCSR_SET Desc ription
Name Type Rese t By Reset State Function
RESET R/W PWR VME 0 Board Reset
Reads: 0= LRST# not asse rted, 1=LRST# asserted
Wr ites : 0=n o eff ect, 1=asse rt LRS T#
SYSFAIL R/W all Power-up
Option VMEbus SYSFAIL
Reads: 0= VXSYSFAIL not asserted, 1=VXSYSFAIL asserted
Writes:0=no effect, 1=assert VXSYSFAIL
FAIL R PWR VME 0 Board Fail
0= Bo ard has not failed
Univer se II User Manual Regis ters
Tundra Semiconduc tor Corporation A pp A-141
Table A.127 : VMEb us CSR Base Addr ess Register ( VCSR_BS)
The base address specifies one of thirty-one available CR/C SR windows as defined in the
VME64 specification. Each window consumes 512 Kb ytes of CR/CSR space.
Register Name: VCSR_BS Offset: FFC
Bits Function
31-24 BS Reserved
23-16 Reserved
15-08 Reserved
07-00 Reserved
VCSR_BS Description
Name Type Reset By Reset State Function
BS [23:19] R/W PWR VME 0 Base A ddres s
Registers Universe II User Manual
App A-142 Tundra Semiconductor Corporation
VMEbus Interface Components —Univ erse II User Ma nual
Tundra Semiconduc tor Corporation App B-1
Appendix B Performance
As a VMEbus bridge, the Universe II's most i mportant functi on is data transfer. This function
is performed by its three channels: the PCI Slave C hannel , the VME Slave Channel, and the
DMA Channel. Since each channel operates independently of the others and because each has
its own unique characteristics, the following analysis reviews the data transfer performance for
each channel:
• “PCI Sla ve Channel” on page B-2
• “VME Sla ve Channel” on page B-6
• “DMA Channel” on page B-14
• “Summ ary” on page B-17
Where relevant, descriptions of factors affecting performance and how they might be con-
trolled in different environments are discusse d.
The decoupled nature of the Uni verse II can cause some confusion in dis cussing performance
parameters. This is because, in a fully decoupled bus bridge each of the two opposing buses
operates at its peak performance independently of the other. The Universe II, however, because
of the fini te size of its FIFOs does not repr esent a 100% decoupled bridge. As the FIFOs fill or
empty (depending on the direction of data movement) the two buses tend to migrate to matched
performance where the higher performing bus is forced to slow down to match the other bus.
This limits the sustained performa nce of the device. Some factors such as the PCI Aligned
Burs t Size and VME request/rele ase modes can limit the effect of FIFO size and enhance per-
formance.
Another aspect in considering the performance of a device is bandwidth consumption. The
greater bandwidth consumed to transfer a given amount of data, the less is available for other
bus m asters. Decoupling significantly improves the Universe II's bandwidth consumption, and
on the PCI bus allows it to use the minimum permitted by the PCI specification.
To simplify the analysis and allow comparison with other devices, Universe II performance has
been calculated using the following assumptions:
As a PCI master:
• one clock bus grant latency
• zero wait state PCI target
As a V ME master:
• ideal VME slave response (DS* to DTACK* = 30ns)
Assumed as part of any calculation on VME performance is the inclusion of VME transceivers
with propagation del ay of 4 ns.
Performance Universe II User Manual
App B-2 T undr a Semiconductor Corporation
This appendix presents sustained performance values. In cont rast, the Universe User manual
(9000000.MD303.01) provided peak per formance numbers. This explains why some of the
performance numbers in this document appear to be lower than for the original Universe.
B.1 PCI Slave Channel
B.1.1 Coupled Cycles
B.1.1.1 Request of VMEbus
The Universe I I has a "Coupled Window T imer" (CWT in the LMISC register) which permits
the coupled channel to maintain ownership of the VM Ebus f or an extended period b eyond the
completion of a cycle. This permits subsequent coupled accesses to the VMEbus to occur back-
to-back without requirement for re-arbitration.
The CWT should be set for the expected latency between sequential coupled access es attempt-
ed by the CPU. In calculating the latency expected here, the designer needs to account for la-
tency across their host PCI bridge as well as latency encountered in re-a rbitration for the PCI
bus between each coupled access. Care must be taken not to set the CWT greater than necessary
as the Universe II blocks all decoupled write transactions with target-retry, while the coupled
channel owns the VMEbus. It is only when the CWT has expire d that the PCI bus is permitted
to enqueue transactions in the TXFIFO.
When a coupled access to the VMEbus is at tem pted, the Universe II generates a target-retry to
the PCI initiator if the coupled path does not currently own the VMEbus. This occurs if the
Universe II is not currently VMEbus mast er, or if the DMA is currently VMEbus master or if
entrie s exist in the TXFIFO.
If the Universe II does not have ownership of the VMEbus when a coupled access is attempted,
the Universe II generates a target-retry with a single wait state (See Figure B.1). The request
for the VMEbus occurs shortly after the cycle is re tried.
B.1.1.2 Read Cycles
Once the coupled channel owns the VMEbus, the Universe II propagates the cycle out to the
VMEbus. Figure B.1 shows such a coupled read cycle against an ideal VME slave. There are
10 wait states inserted by the Universe II on the PCI bus befor e it responds with TRDY#. Fur-
ther wait states are inserted for each extra 30ns in slave response.
Performing 32-bit PCI reads from VME gives a sustained performance of approximately 8.5
MB/s. Figure B.2 shows several of these accesses occur ring consecutively.
Universe II User Manual Performance
Tundra Semiconduc tor Corporation App B-3
Figure B.1 : Coupled Read Cycle - Universe II as VME Master
Figure B.2 : Sev eral Coupled Read Cycles - Univ erse II as VME Master
A[31:1]
AS*
D[31:0]
WRITE*
DS0*
DS1*
DTACK*
PCI
VMEbus
CLK
FRAME#
AD[31:0]
C/BE[3:0]
IRDY#
TRDY#
STOP#
DEVSEL#
A[31:1]
AS*
D[31:0]
WRITE*
DS0*
DS1*
DTACK*
PCI
VMEbus
CLK
FRAME#
AD[31:0]
C/BE[3:0]
IRDY#
TRDY#
STOP#
DEVSEL#
Performance Universe II User Manual
App B-4 T undr a Semiconductor Corporation
B.1.1.3 Write Cycles
The performance of coupled write cycles is similar to that of coupled read cycles except that an
extra wait state is inserted. Figure B.3 shows a coupled write cycle against an ideal VME slave.
Ten wait s tates are inser ted on the PCI bus by the Universe II before it res ponds with TRDY#.
A slower VME slave response translates directly to more wait states on the PCI bus.
The sustained performance, when generating write cycles from a 32-bit PCI bus against an ide-
al VME slave is approximately 9.3 MB/s.
Figu re B .3 : Couple d Write Cycle - Univers e II as VME Master
B.1.2 Decoupled Cycles
Only write transactions can be decoupled in the PCI Target Channel.
Effect of th e PWON Cou n te r
The Posted Write On Counter (PWON in the MAST_CTL register) controls the maxim um ten-
ure that the PCI Slave Channel will have on the VMEbus. Once thi s channel has gained own-
ership of the VMEbus for use by the TXFIFO, it only relinquishes it if the FIFO becomes empty
or if the number of bytes programmed in the counter expires. In most situations, the FIFO emp-
ties before the counter expires. However, if a great deal of data is being transf erred by a PCI
initiator to the VMEbus, then this counter ensures that only a fixed amount of VME bandwidth
is consumed.
A[31:1]
AS*
D[31:0]
WRITE*
DS0*
DS1*
DTACK*
PCI
VMEbus
CLK
FRAME#
AD[31:0]
C/BE[3:0]
IRDY#
TRDY#
STOP#
DEVSEL#
Universe II User Manual Performance
Tundra Semiconduc tor Corporation App B-5
Limiting the size of the PWON counter imposes greater arbitration overhead on data being
transferred out from the FIFO. This is true even when programmed fo r ROR mode since an
internal arbitration cycle will still occ ur. The value for the PWON counter must be weighed
from the system perspective with the impact of imposing greater latency on other channels (the
DMA and Interrupt Channels) and other VME masters in gaining ownership of the VMEbus.
On a Universe II equipped card which is only performing system control functions, the counter
would be set to minimum. On a card which is responsible for transferring considerable
amounts of performance-critical data the counter will be set much higher at the expense of sys-
tem latency.
PCI Target Response
As the P CI target during decoupled wr ite operations to the VMEbus, the Uni verse II responds
in one of two manne rs:
1. It imm ediately issues a target retry because the FIFO does not hav e suf f icient room
for a burst of one address phase and 128 b ytes of dat a. (There are no
programmable watermarks in the PCI Target Channel. The PCI Aligned Burst S ize
(PABS) does not affect the PCI Targe t Channel.)
2. It responds as a zero-wait state target receiving up to 256 bytes in a transaction.
When the FIFO is full or a 256-byte boundary has been reached, the Universe II
issues a Target-Disconnect.
In either case, the Universe II will consume the minimum possible PCI bandwidth, never in-
sert in g wait st ates.
VME Master Performa nce
As a VME master, the Universe I I waits until a full transactio n has been enqueued in the Tx-
FIFO before requesting the VMEbus and generating a VME cycle. If the V MEbus is already
owned by the decoupled path (see “Effect of the PWON Counter” on page B-4), the Universe
II still waits until a full transaction is enqueued in the FIFO before processing it.
If configured to generate non-block transfers, the Universe II can generate back-to-back VME
transfers with cycle times of approximately 180ns (AS* to AS*) against an ideal VME slave
(30-45 ns). A greater cycle time is required between the termination of one full enqueued trans-
action and the start of the next. This inter-transaction time is approxim ately 210ns. As such,
the longer the PCI transaction, the greater the sustained performance on the VMEbus. With
64-byte PCI tr ansactions, the sustained ra te is 43 MB/s. With 32-byte tr ansactions, this drops
to 23 MB/s. Each of the se numbers is calculate d with no initia l arbitration or re-arbit ration f or
the bus. Fi gure B.4 shows the Universe II dequeueing a transaction with multiple non-block
VME transfers.
Block transfers significantly increase performance. The inter-transaction period remains at ap-
proximately 210 ns for BLTs and MBL Ts, but t he data beat cycle time (DS* to DS*) drops to
Performance Universe II User Manual
App B-6 T undr a Semiconductor Corporation
about 120ns against the same ideal slave. Again the length of t he burst size affects the sus-
tained performance because of the inter-transaction time. For BLTs operating with a burst size
of 64 bytes, the sustained performance is 37 MB/s, dropping to 33 MB/s for a burst size of 32
bytes. MBLTs op erat ing with 64-byte bursts perform at a sustained rate of 66 MB/s, dropping
to 50 MB/s for 32 bytes.
Figure B.4 : Severa l Non-Block Dec oupled Writes - U niverse II as VME
Master
Figure B.5 : BLT Decoupled Write - Universe II as VME Master
B.2 VME Slave Channel
B.2.1 Coupled Cycles
B.2.1.1 Block vs. non-Block Transfers
The Universe II VME Slave Channel handles both block and non-block coupled a cces ses in
similar manners. Eac h data beat is transla ted to a si ngle PCI tr ansa ction. Once the tr ansaction
has been acknowledged on the PCI bus, the Universe II asserts DTACK* to terminate the VME
data beat.
A non-block transfer and the first beat of a BLT transfer ha ve identical timing. In each, the
Universe II decodes the access and then provides a response to the data beat. Subsequent data
A[31:1]
AS*
D[31:0]
WRITE*
DS0*
DS1*
DTACK*
VMEbus
A[31:1]
AS*
D[31:0]
WRITE*
DS0*
DS1*
DTACK*
VMEbus
Universe II User Manual Performance
Tundra Semiconduc tor Corporation App B-7
beats in the BLT transfer are shorter than the first due to the fact that no address decoding need
be perform ed in these beats.
MBLT transfers behave somewhat differently. The first beat of an MBLT transfer is address
only, and so the response is relatively fast. Subsequent data beats require acknowledgment
from the PCI bus. With a 32-bit PCI bus , the MBLT data beat (64 bits of data) requires a two
data beat PCI transaction. Because of this extra data beat required on the PCI bus, the slave
response of the Universe II during coupled MBLT cycles is at least one PCI clock greater (de-
pending upon the response from the PCI target) than that during BLT cycles.
B.2.1.2 Read Cycles
During coupled cycles, the Universe II does not acknowledge a VME transaction until it has
been acknowledged on the PCI bus. Because of this the VME slave response during coupled
reads is directly linked to the response time for the PCI target. Each clock of latency in the PCI
target response translates directly to an extra clock of latency in the Universe II's VME coupled
slave response.
The address of an incoming VME transaction is decoded and translated to an equivalent PCI
transaction. Typically, four PCI clock periods e lapse between the initial assertion of AS* on
the VMEbus and the assertion of REQ# on the PCI bus. During the data only portion of sub-
sequent beats in block transfers, the time from DS* assertion to REQ# is about 4 clocks. If the
PCI bus is parked at the Universe II, no REQ# is asserted and FR AME# is asserted 4 clocks
after AS*.
From assertion of REQ#, the Universe II does not insert any extra wait states in its operations
as an initiator on the PCI bus. Upon receiving GNT# asserted, the Universe II asserts FRAME#
in the next clock and after the required turn-around phase, asserts IRDY# to begin data transfer.
Once TRDY# is sampled asserted, the Universe II responds back to the VMEbus by asserting
DTACK*. I f the initiating VM E trans action is 64-bit and the P CI bus or PCI bus ta rget are 32
bit, then two data transfers are required on PCI before the Universe II can respond with
DTACK*. No wait states are inserted by the Universe II between these two data beats on PCI.
The assertion of DTACK* from the assertion of TRDY# has a latency of 1 clock. Figure B.6
shows a typical non-block coupled read cycle.
When accessing a PCI target with a zero wait state response, the Unive rse II VME response
becomes approximately 1 0 PCI clock periods (about 301ns in a 33MHz system) during s ingle
cycles, and the first beat of a BLT. During pure data beats in both BLT and MBLTs, the slave
response becomes 8 clocks.
Performance Universe II User Manual
App B-8 T undr a Semiconductor Corporation
Figur e B.6 : Coupled Read Cycle - Univ erse II as VME Slave
B.2.1.3 Write Cycles
Coupled writes in the VME Slave Channel operate in a similar fashion to the coupled reads.
The VME slave response is directly li nked to the response of the PCI target. In generating the
request to the PCI bus, coupled write cycles require one further clock over reads. Hence, during
single cycles, or the first beat of a BLT, the time from AS* to REQ# asserted is 3-4 PCI clocks,
while DS* to REQ# is 3 clocks for the data beat portion of a block transfer. If the PCI bus is
parked at the Universe II, REQ# is not asserted and the transaction begins immediately with
assertion of FRAME#.
As with reads , the response fr om the PC I target's assertion of TRDY# to DTACK* assertion
by the Universe II adds one clock t o the transfer. Figure B.7 shows a typical non-block coupled
write cycle.
Because write cycles on the PCI bus require one less clock than reads, due to the absence of the
turn-around phase between address and data phases, the overall slave re sponse during coupled
writes works out to the same as coupled reads against an identical target. In accessing a zero-
wait state PCI target, the Universe II's coupled write slave response then is approxim ately 10
PCI clocks. Duri ng subsequent data beats of a block transfer (either BLT or M BLT), the slave
response (DS* to DTACK*) is 8 clocks.
A[31:1]
AM[5:0]
LWORD*
AS*
D[31:0]
WRITE*
DS0*
DS1*
DTACK*
PCI
VMEbus
CLK
REQ#
GNT#
FRAME#
AD[31:0]
C/BE[3:0]
IRDY#
TRDY#
STOP#
DEVSEL#
Universe II User Manual Performance
Tundra Semiconduc tor Corporation App B-9
Figure B.7 : Coupled Write Cycle - Universe II as VME Slave
(b us parked at Universe II)
B.2.2 Decoupled Cycles
B.2.2.1 Write Cycles
Ef fect of the PC I A li g ned B urst Si ze
The PCI Aligned Burst Size (PABS in the MAST_CTL register) affects the maximum burst
size that the Universe II generates onto the PCI bus; either 32, 64, or 128 bytes. Note that the
VME Slave Channel only generates PCI bursts in response to incoming block transfers.
The greater burst size means less arbitration and addressing overhead. However, incumbent in
this is the greater average latency for other devices in the PCI system. Hence , in the VME
Slave Channel, the burst size is a trade-of f between performance and latency.
VME Slave Response
As a VME slave, the Universe II accepts data into its RXFIFO with minimum delay provided
there is room in the FIFO for a further data be at. Assertion of DTACK* is delayed if there is
insufficient room in the FIFO for the next data beat.
During non-block transfers, the Universe II must both decode the address and enqueue the data
before asserting DTACK* to acknowledge the transfer. Because of this, the slave response
A[31:1]
AM[5:0]
LWORD*
AS*
D[31:0]
WRITE*
DS0*
DS1*
DTACK*
PCI
VMEbus
CLK
FRAME#
AD[31:0]
C/BE[3:0]
IRDY#
TRDY#
STOP#
DEVSEL#
Performance Universe II User Manual
App B-10 Tundra Semiconductor Corporation
during non-block transfer s is consider ably slower than block transfer s. This slave response
time is 127ns.
During BLT transf ers, the slave response in the first data beat being both address decode and
data transfer is the same as a non-block transfer, i.e., 127ns. Subsequent data beat s, however,
are much faster. Response time for these is 50 to 56ns.
During MBLT transfers, the first phase is address only and the slave response is 127ns. Sub-
sequent phases are data only and so the slave response is the same as with BLTs i.e., 50 to 56ns.
Note that the slave response is independent of the data siz e. D16 non-block transfers have a
slave response identical to D32. BLT dat a beats have slave responses identical to MBLT data
beats.
Figure B.8 : Non-Block Decoupled Write Cycle - Universe II as VME Slave
A[31:1]
AM[5:0]
LWORD*
AS*
D[31:0]
WRITE*
DS0*
DS1*
DTACK*
PCI
VMEbus
CLK
FRAME#
AD[31:0]
C/BE[3:0]
IRDY#
TRDY#
STOP#
DEVSEL#
Universe II User Manual Performance
Tundra Semiconduc tor Corporation App B-11
Figure B.9 : BLT Decoupled Write Cycle - Universe II as VME Slave
Figure B.10 : MBLT Decoupled Write Cycle - Univ erse II as VME Sla ve
A[31:1]
AM[5:0]
AS*
D[31:0]
WRITE*
DS0*
DS1*
DTACK*
PCI
VMEbus
CLK
FRAME#
AD[31:0]
C/BE[3:0]
IRDY#
TRDY#
STOP#
DEVSEL#
A[31:1]
AM[5:0]
AS*
D[31:0]
WRITE*
DS0*
DS1*
DTACK*
PCI
VMEbus
CLK
REQ#
GNT#
FRAME#
AD[31:0]
C/BE[3:0]
IRDY#
TRDY#
STOP#
DEVSEL#
Performance Universe II User Manual
App B-12 Tundra Semiconductor Corporation
PCI Master Performance
The Universe II supports bus parking. If the Universe II requires the PCI bus it will assert REQ#
only if its GNT# is not currently asserted. When the PCI Master Module is ready to begin a
transaction a nd its GNT# is asse rted, the trans fer begins immediately. T his elimina tes a possi-
ble one clock cycle delay before beginning a transaction on the PCI bus which would exist if
the Uni v erse II did not implement b us parking. Bus parking is described in Section 3.4.3 of the
PCI Specification (Rev. 2.1).
On the PCI bus , the Universe II dequeues data from the RXFI FO once a c omple te VME tra ns -
action has been enqueued or once s ufficient data has been enqueued to form a PCI transaction
of length defined by the PABS field.
Since the Universe II does not perform any address phase deletion, non-block t ransfers are de-
queued from the RXFIFO as single data beat transactions. Only block transfers result in mul ti-
data beat PCI transactions; typically 8, 16 or 32 data beats. In either case, the Universe II does
not insert any wait states as a PCI master. The clock, after the bus has been granted to the Uni-
verse II, drive s out FRAME# to generate the address phas e. The data phases begin imme diate-
ly on the next clock. If there is more than one data phase, each phase will immediately follow
the acknowledgment of the previous phase.
In each case, because of the lack of any wait states as a PCI master, the Universe II is consum-
ing the minimum possible ba ndwidth on the PCI bus , and data will be written to the PCI bus a t
an average sustained rate equal to the rate at which the VME master is capable of writing it.
The sustained pe rfor mance on the PC I bus performing single data beat write trans actions to a
32-bit PCI bus is 15 MB/s; double this for a 64-bit bus. When performing 32-byte transactions
the sustained performance increases to 106 MB/s; 120 MB/s with 64-byte transactions. Again,
these can be doubled for a 64-bit PCI bus. Bear in mind that the PCI bus can only dequeue data
as fast as it is being enqueued on the VMEbus. Hence, as the RXFIFO empties, the sustained
performance on the PCI will drop down to match the lowe r performance on the VME side.
However, even with the decreased sustained performance, the consumed bandwidth will re-
main constant (no extra wait states are inserted while the Universe II is master of the PCI bus.)
These numbers assume the PCI bus is granted to the Universe II immediately and that the writes
are to a zero-wait state PCI target capable of accepting the full burst length. Figure B.1 through
Figure B.10 show the Universe II responding to non-block, BLT and MBLT write transactions
to a 32-bit PCI bus. Even better performance is obtained with PCI bus parking.
B.2.2.2 Prefet ched Read Cycles
To minimize its slave response, the Universe II generates pref etched reads to the PCI bus in
response to BLT and MBLT reads coming in from the VMEbus. This option must first be en-
abled on a per image basis.
When enabled, the Univer se II will respond to a block read by performing burst re ads on the
Universe II User Manual Performance
Tundra Semiconduc tor Corporation App B-13
PCI bus of length defined by the PCI Aligned Burst Size (PABS in the MAST_CTL register).
These burs t r eads c ontinue while the bloc k tr ansfer is still ac tive on the VMEbus (AS * not ne -
gated) and there is room in the RDFIFO. If there is insufficient room in the RDFIFO to con-
tinue (a common occurrence since the Universe II is capable of fetching data from the PCI bus
at a much faster rate than a VME master is capable of receiving it), then pre-fetching stops and
only continues once enough room exists in the RDFIFO for another full burst size.
The first data beat of a block transfer must wait for the first data beat to be retrieve d from the
PCI bus—thi s is essentially a coupl ed transf er. See the section on coupled tr ansfers for details
on coupled performance. However, once the pre-fetching begins, data is provided by the Uni-
verse II in subsequent data beats with a slave response of 57ns. This continues while there is
data in the RDFIFO. If the RDFIFO empties because data is being fetched fr om the PCI bus
too slowly, wait states are inserted on the VMEbus awaiting the enqueueing of more data.
On the PCI bus, the Universe II fetches data at 89 MB/s with PABS set to 32-byte transactions;
106 MB/s when set to 64-byte transactions. Even better performance is obtained if PABS is set
for 128-byte transactions. Once the RDFIFO fills, pre-fetching slows to match the rate at which
it is being read by the external VMEbus master. Bandwidth consumption, however, remains
constant, only the idle time between transactions increases.
Figure B.11 : B LT Pre-fet che d Read Cycle - Universe II as VME Slave
A[31:1]
AM[5:0]
LWORD*
AS*
D[31:0]
WRITE*
DS0*
DS1*
DTACK*
PCI
VMEbus
CLK
REQ#
GNT#
FRAME#
AD[31:0]
C/BE[3:0]
IRDY#
TRDY#
STOP#
DEVSEL#
Performance Universe II User Manual
App B-14 Tundra Semiconductor Corporation
B.3 DMA Channel
B.3.1 Relative FIFO sizes
Two fixed “watermarks” in the DMA Channel contr ol the Universe’s II requisition of the P CI
bus and VMEbus. The DMAFI FO PCI Watermark is 128 bytes. This means that during reads
from the PCI bus, the Universe II will wait for 128 bytes to be free in the DMAFIFO before
requesting the PCI bus . F or PCI writes, t he Universe II waits f or 128 bytes of data to be in the
FIFO before requesting the PCI bus. The DMAFIFO VMEbus watermark is 64 b ytes . This
means that during read s from the VMEbus, the Universe II will wait for 64 b ytes to be free in
the DMAFIFO before requesting the Vmebus. For VMEbus writes, the Universe II waits for
64 bytes of data to be in the FIFO before request ing the VMEbus.
These watermarks have been ta ilored for the relative speeds of each bus, and provide near op-
timal use of the DMA channel.
B.3.2 VMEbus Ownership Modes
The DMA has two counters that control its access to the VMEbus: the VON (VMEbus O n)
counter and the VOFF (VMEbus Off) ti mer. The VON counter controls the number of bytes
that are transferred by the DMA during any VMEbus tenure, while the VOF F timer controls
the pe riod be fore the next request after a VON time-out.
While the bus is more optimally shared between vari ous masters in the system, and average la-
tency drops as the value programmed for the VON counter drops, the sustained performance
of the DMA also drops. The DMA is typically limited by its performance on the VMEbus. As
this drops off with greater re-arbitration cycles, the average VMEbus throughput will drop.
Even if the Universe II is programmed for ROR mode, and no other channels or masters are
requesting the bus, there will be a period of time during which the DMA will pause its transfers
on the bus, due to the VON counter expiring.
An important point to consider when programming the se timers is the more often the DMA re-
linquishes its ownership of the bus, the more frequently the PCI Slave Channel will have access
to the VMEbus. If DMA tenure is too long, the TXFIFO may fill up causing any further ac-
cesses to the bus to be retried. In the same fashion, all coupled accesses will be retried while
the DMA has tenure on the bus. This can significantly affect transfer latency and should be
considered when calculating the overall system lat ency.
B.3.3 VME Trans fers
On the VMEbus, the Universe II can perform D08 through D64 transactions in either block or
non-block mode. T he time to perf orm a singl e beat, however, is independent of the bus width
Universe II User Manual Performance
Tundra Semiconduc tor Corporation App B-15
being used. Hence, a D08 transaction will tr ansfer data at 25% the rate of a D32, which in turn
is half that for D64.
There is a significant difference between the performance for block vs. non-block operations.
Because of the e xtra addressing required for each data transfe r in non-block operations, the
DMA performance is about half that compared to operating in block mode. Moreover, consid-
ering that most VME slaves respond less quickly in non-block mode, the overall performance
may drop to one-quarter of that ac hievable in block mode.
When programme d for Release-When-Done operation, the Uni verse II will perform an early
release of BBSY* when the VON counter reaches its programmed limit. This g ive s other mas-
ters a chance to use the VMEbus (and possibly acces s th e VME Slave Channel), but may de-
crease perfo rmance of the DMA Channel; this factor may also play in favor of the DMA
Channel, by pausing the PCI Target Channel’s use of the VMEbus.
B.3.3.1 Read Transfers
When performi ng non-block reads on the VMEbus , the Universe II cycle ti me (AS* to next
AS*) is approximately 209ns, which translates to about 20 MB/s when perfor ming D32 trans-
fers. F or block transfers the cycle time (DS* to next DS*) falls to about 156ns, or 25 MB/s for
D32 transfers . For multiplexed block tra nsfers (MBLTs) the c ycle time remains the same, but
because the data width doubles, the transfer rate increases to about 50MB/s.
B.3.3.2 Write Tr ansfers
Non-block writes to the VMEbus occur at 180ns cycle time (AS* to next AS*), or 23MB/s dur-
ing D32 transfers. Block writes, however, are significantly faster with a 116ns cycle time (DS*
to next DS*), or 36 MB/s. Multiplexed block transfers have slightly longer cycle times at about
112ns (DS* to next DS*), or 62 MB/s with D64 MBLTs.
B.3.4 PCI Transfers
As a master on the PCI bus, the Universe II DMA follows the same general set of rule s as the
VME Slave channel does: it never inserts any wait states into th e transfer (i.e., it never negates
IRDY# until the transaction is complete) and will whenever possible, generate full aligned
bursts as set in the PABS field of the MAST_CTL register .
Betwe en transa ctions on the PCI bus, the Univer se II DMA typically sits idle for 6 clocks.
Hence, minimizing the number of idle periods and re- arbitra tion times by setting PABS to its
maximum value of 128 bytes may increase the performance of the DMA on this bus. Higher
PABS values impl y that the Universe II will hold on to both the PCI bus and the VMEbus for
longer periods of time. The reason that PABS also may impact on VMEbus tenure is that (in
the case of PCI writes), the DMA F IFO is less likely to fill, and (in the case of PCI reads) the
Performance Universe II User Manual
App B-16 Tundra Semiconductor Corporation
DMA is less likely to go empty. However, given the relative speeds of the buses, and the rela-
tive watermarks, the effect of PABS on VMEbus utilization is not as significant as its eff ects
on the PCI bus.
While higher values of PABS increas e DMA throughput, they ma y increase system latency.
That is, there will be a longer latency for other PCI transactions, including possible transactions
coming through the VME Slave Channel (since the DMA ch annel will own the PCI bus for
longer periods of time). Also, accesses between other PCI peripherals will, on aver age, have a
longer wait before bei ng allowed to perform their transactions. P CI latency must be traded off
against possible DMA performance.
Although both read and write transactions occur on the PCI bus with zero wait states, ther e is
a period of six PCI clocks during which the Universe II re mains idle before re-requesting the
bus for the next tra ns action. PCI bus parking m ay be used to e liminate the ne e d for re -a rbitra-
tion.
With PABS set for 32-byte transactions on a 32-bit PCI bus, this translates to a peak transfer
rate of 97 MB/s for reads (including pre-fetching), 98 MB/s for writes, doubling to 194 and 196
for a 64-bit PCI bus. With PABS set for 64-byte transactions, the peak transfer rate increases
to 118 MB/s for reads, 125 MB/s for writes on a 32-bit PCI bus—236 MB/s and 250 MB/s
respectively for 64-bit PCI buses. The numbers for writes to PCI assume that data are read from
VME using BLTs.
Figure B.12 : PCI Read Transactions During DMA Operat ion
PCI
CLK
REQ#
GNT#
FRAME#
AD[31:0]
C/BE[3:0]
IRDY#
TRDY#
STOP#
DEVSEL#
Universe II User Manual Performance
Tundra Semiconduc tor Corporation App B-17
Figure B.13 : Multiple PCI Read Transactions During DMA Operation
B.4 Summary
Table B.1 : PCI Slave Channel Performance
Cy cl e T ype P er f o rm a n ce
Coupled Read
- PCI targe t re sp ons e 8 PCI clocks
Coupled Write
- PCI targe t re sp ons e 9 PCI clocks
Decoupled Write
- non-block D32
- VME cycle time
- sustai ned pe rf (32-byte PABS)
- sustai ned pe rf (64-byte PABS)
- D32 BLT
- VME cycle time
- sustai ned pe rf (32-byte PABS)
- sustai ned pe rf (64-byte PABS)
- D64 MBLT
- VME cycle time
- sustai ned pe rf (32-byte PABS)
- sustai ned pe rf (64-byte PABS)
180 ns
23 MB /s
43 MB /s
119 ns
32 MB /s
35 MB /s
119 ns
53 MB/s
59 MB /s
PCI
CLK
REQ#
GNT#
FRAME#
AD[31:0]
C/BE[3:0]
IRDY#
TRDY#
STOP#
DEVSEL#
Performance Universe II User Manual
App B-18 Tundra Semiconductor Corporation
Table B.2 : VME Slave Channel Performance
Cy cl e Ty p e P er f or m ance
VME Slave Response (ns)
Coupled Read
- non-block
- D32 BLT
- D64 BLT
301
293
322
Coupled Write
- non-block
- D32 BLT
- D64 BLT
278
264
292
Pre-fetched Read
- VME slave response (1st data beat)
- VME slave response (other data beats) 293
57
Decouple d Write
- non-block slave respons e
- block slave response (1st data beat)
- block slave response (other data beats)
127
127
50
Universe II User Manual Performance
Tundra Semiconduc tor Corporation App B-19
Table B.3 : DMA Channel Performance
Cy cl e T ype P er f o rm a n ce
MB/s
PCI Reads
- 32-byte PABS
- 64byte PABS 97 (194)a
118 (236)
a. 64-bit PCI performa nce in br ackets.
PCI Writes
- 32-byte PABS
- 64byte PABS 98 (196)
125 (250)
VME Reads
- non-block D32
- D32 BLT
- D64 MBLT
18
22
45
VME Writes
- non-block D32
- D32 BLT
- D64 MBLT
22
32
65
Performance Universe II User Manual
App B-20 Tundra Semiconductor Corporation
VMEbus Interface Components —Univ erse II User Manua l
Tundra Semiconductor Corporation App C-1
Appendix C Typical Applications
Being a bridge between standard interfaces, the Universe II r equires minimal external logic to
interface to either the VMEbus or to the PCI bus. In most applications, only transceivers to
b uffer the Uni verse II from the VMEbus , plus some reset logic are all that is r equire d. The
following information should be used only as a guide in designing the Universe II into a
PCI/ VME application. Each application will hav e its own set-up requirements.
C.1 VME Interface
C.1.1 Transceivers
The Univ erse II has been designed such t hat it requires full b uffering from VMEbus si gnals.
Necessary drive current to the VMEbus is provided by the transcei vers while at the same time
isolating the Univ erse II from potentially noisy VMEb us backplanes. In particular, complete
isolation of the Universe II from the VMEb us backplane allo ws use of ETL tr anscei ve rs which
provide high noise immunity as well as use in liv e insertion environments. The VME
community has recently standardized "VME64 Extensions" (ANSI VITA 1.1) which among
other ne w VME features, fac ilitate s li ve insertion environments.
If neither li v e insertion nor noise immunity are a concern, those buf fers that provide input only
(U15 and U17 in Figure C.1, below) may be omitted. The daisy chain input signals,
BGIN[3:0] and I A CKIN, ha ve Schmit t trigger inputs, which should rectify any mi nor noise on
these signals. If considerable noise is expected, the designer may wish to put external filters
on these signals. Bear in mind that any filtering done on these signals will detrimentally af fect
the propagation of bus grants down the daisy chain. Only extremely noisy systems or poorly
designed backplanes should require these filter s.
Figure C.1 show s one example of how to conn ect the Univer se II to the VMEbus. The
transceivers in this example were chosen to meet the following criteri a:
• provide suffic ient drive strength as required by the VME specific ation (see Table C. 1
on page C-4),
• meet Universe II skew requirements, and
• minimize part counts.
U15 and U17 in Figure C.1 are optional devices. They will provide be tter noise immunity.
Typi cal Applications Univ erse II User Manual
App C-2 Tundra Semiconductor Corporation
Figure C.1 : Universe II Connections to the VMEbus Through TTL Bu ffers
G
DIR
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
G
DIR
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
G
DIR
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
G
DIR
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
G
DIR
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
G
DIR
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
G
DIR
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
G
DIR
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
G
DIR
A0
A1
A2
G
DIR
A0
A1
A2
A3
A4
A5
B0
B1
B2
B3
B4
B5
B6
B7
U10:A
U11:
U10:B
U11:B
U11:C
U10:D
U11:D
U12:A
U12:B
U13:A
U11:A
Universe VMEbus
A[31:1],
LWORD*
D[31:0]
AM[5:0]
AS*
DS[1:0]*
DTACK*
SYSCLK
BCLR*
VSCON_DIR
VBCLR#
SYSCLK#
VSLAVE_DIR
VDTACK#
VDS_DIR
VDS1#
VDS0#
VAS_DIR
VAS#
VAM[5:0]
VWRITE#
VIACK#
WRITE*
IACK*
VAM_DIR
VD[31:0]
VA[31:1],
LWORD*
VD_DIR
VA_DIR
VOE#
U1 U2 U3 U4
U5 U6 U7 U8
U9
U10:C
Universe II Use r M anual Typ ical Appl ications
Tundra Semiconductor Corporation App C-3
Figure C.1 (continued): Universe II Connections to the VMEbus Through TTL Buffers
Vcc
VXBBSY
VRBBSY#
VXSYSFAIL
VRSYSFAIL#
VXSYSRST
VRSYSRST#
VXBERR
VRBERR#
VXBR[3:0]
VRBR[3:0]#
VXIRQ[7:1]
VRIRQ[7:1]#
7
7
4
4
U14:A
U15:A
VRACFAIL#
U15:C
U14:C
U14:D
U15:D
U14:E
U15:E
U14:F-H, U16:A-D
U15:F-H, U17:A-D
U16:E-H
U17:E-H
VIACKIN#
VIACKOUT#
VBGIN#[3:0]
VBGOUT#[3:0]
4
4
U15:B
BBSY*
ACFAIL*
SYSFAIL*
SYSRST*
BERR*
IRQ[7:1]*
BR[3:0]*
BG[3:0]IN*
BG[3:0]OUT*
IACKIN*
IACKOUT*
Universe VMEbus
U1-U9
U10, U12
U11, U13
U14, U16
U15, U17
'245
'126
'125
'642
'241
Note: U15 & U17 are optional
Typi cal Applications Univ erse II User Manual
App C-4 Tundra Semiconductor Corporation
The Univer se II, with the addition of external transcei vers, is designed to meet the tim ing
requirements of the VME specification. Refer to the VME64 specification (ANSI VITA 1.0)
for details on the VME timing. In order to meet the requirements outlined in this
speci f ic a tion, the exte rnal tra ns ceivers must meet certai n characteris tics as outlined in
Table C.2.
F Series transceivers meet the requirements specified in Table C.1 and Table C.2. A faster
family such as ABT, may also be used. Care should be taken in the choice of transceivers to
a void ground bounces and also to minimize crosstalk incurred during switching. To limit the
effects of crosstalk, the a mount of routing under these transceive rs must be kept to a
minimum. Daisy chai n signals can be especially susceptible to crosstalk.
Should the designer wish to put any further circuitry between the Universe II and the
VMEb us , that circ uitry must meet the same timing requireme nts as the t ransce iv ers in order
for the combined circuit to remain compliant with the VME64 specific ation.
Table C.1 : VMEbus Signal Drive Strength Requirements
VME bus Signal Required Drive Strength
A[31:1], D[31:0], AM[5 :0], IACK*, LWOR D*, WRITE *, DTACK* IOL ≥ 48mA
IOH ≥ 3mA
AS*, DS[1:0]*, IOL ≥ 64mA
IOH ≥ 3mA
SYSCLK* IOL ≥ 64 mA
IOH ≥ 3mA
BR[3:0]*, BSY*, IRQ[7:0]*, BERR*, SYSFAIL*, SYSRESET* IOL≥ 48 mA
Table C.2 : VMEbus Transceiver Requirem ents
Parameter From To Timing
(Input) (Output) Min Max
VA, VD, VAM, VIACK, VLWORD, VWRITE, VAS, VDSx, VDTACKa
a. Th ere are no limit s on propagation delay or ske w on the remaining buffered VME signals:
VSYSCLK, VBCLR, VXBBSY, VRBBSY, VRACFAIL, VXSYSFAIL, VRSYSFAIL, VXSYSRST,
VRSYSRST, VXBERR, VRBERR, VXIRQ, VRI RQ, VXBR, VRBR.
skew (pkg to pkg) A B 8 ns
skew (pkg to pkg) B A 4 ns
tProp D IR A 1 ns 5ns
tProp D IR B 2 ns 10ns
Cin A 25 pf
Universe II Use r M anual Typ ical Appl ications
Tundra Semiconductor Corporation App C-5
C.1.1.1 Pull-down resistors
The Uni verse II has internal pull-do wn resistors which are used for its defa ult po wer-up option
state. The pins requiring pull-ups or pull-do wns are indicated in Table 4.2 on page 4-3. (Note
that REQ64# has an internal pull-up.) These internal pull-down resistors, ranging from 25kΩ-
500kΩ, are designed to sink between 10µA-200µA. F-ser ies buffe rs, however, can source up
to 650 µA of current (w orst case). This sourced current has the ability to ov erride the internal
power up r esistors on the Uni verse II. This may ca us e the Univ ers e II to incorrectly s ample a
logic "1" on the pins . To counteract this potential problem, assuming a worst case scenario of
a 650 µA current , Tundra recommends connecting a 1K resistor to ground, in parallel, with
the internal pull-dow n resistor.
Tundra recommends that an y pins controlling the power -up options which are critical to the
application at po werup be connected to ground with a pull-do wn resistor as described abov e.
If the se options are not critical and if it is possible to reprogram these options after reset,
additional resistors need need not be added.
C.1.2 Directi on contr ol
When the Univ erse II is dri ving VMEb us lines, it dri ves the direction control signals high (i.e.,
VA_DI R, VAM_D IR , VAS_DI R, VD_DIR, VDS_DIR, VSLAVE _DIR, and VSCON_DIR).
When the VMEbus is dri ving the Uni v erse II, these signals are dri v en lo w. The control signals
in the Uni verse II do not all hav e the same functionality. Since the Universe II implements
early bus r elease, VA S_ DI R must be a separate contr o l signal.
Contention between the Univ er se II and the VME buf fers is handled since the Univ erse II
tristates it s outputs one 64MHz clock period before the buffer direction control is faced
inwards.
C.1.3 Power-u p Opt ions
Power-up options for the automatic configuration of slav e images and other Uni verse II
features are provided through the state of the VME address and data pins, VA[31:1] and
VD[31:27]. All of these signals are provided with internal pull-downs to bias these signals to
their default conditions. Should v alues other than the defaults be requi red here, either pull-ups
or activ e circuitry may be applied to these signals to provide altern ate configurations.
Power-up options are described in “Po wer -Up Options” on page 2-115.
Typi cal Applications Univ erse II User Manual
App C-6 Tundra Semiconductor Corporation
Since the power-up c onfigurations lie on pins that may be driven by the Universe II or by the
VME trans ceivers, care must be taken to ensure that there is no conflic t. During any reset
e vent, the Uni verse II does not driv e the VA or VD signals. As well, during any VMEbus reset
(SYSRST*) and for se veral CLK64 periods after , the Uni verse II ne gates V OE# to tri-state the
transceivers. During the period that these signals ar e tri- stat ed, the power-up options ar e
loaded with their values latched on the rising edge of PWRRST#.
Configur ation of power-up options is most easily accomplished through passive 10k pull-up
resistors on the appropriate VA and VD pins. The configurations may be made use r-
configurable through jumpe rs or switches as shown in Figure C.2
.
Alternati vely, an activ e ci rcuit may be designed which dri ves the VA and VD pi ns with pre-set
(or pre-programmed) values. This sort of circuit would be of value when power-up
conf igurations such as the re gister access sla ve image are stored in an external programmable
regis te r. To implement t his circuit, the VOE# output from the Uni verse II must be monitored.
When the Universe II negates this signal, the appropriate VA and VD signals may be driven
Power-up Pins
Universe VDD
Figure C.2 : Power-up Configuration Using Passive Pull-ups
Universe II Use r M anual Typ ical Appl ications
Tundra Semiconductor Corporation App C-7
and upon re-assert ion the dri ve mus t be remov ed. To a void confl ict wit h the transceiv ers, logic
must be designed such that the enabling of the transceive rs does not occur until some point
after the c onfiguration options have been r emove d from the VD and VA signals. Figure C.3
sho ws one such implementation. The delay for enabling of t he VMEbus transceiv ers could be
implemented though clocked latches.
Au to-Syscon and PCI Bus Width Power- up Options
The VME64 specifica tion provides for automatic enabling of the system controller in a VME
system through monitoring of the BGIN3* signal. If at the end of SYSRST* this pin is low,
then the system controller is enabled; otherwise it is disabled. The Universe II provides an
inter nal pull-down resistor f or this func tion. If it is in slot one, this pin wil l be sample d low. If
not in slot one, then it will be dri ven high by the previous board in the system and system
controller functions will be disabled. No external logic is required to implement this feature.
C.2 P CI Bus Interface
The Universe II provides a fully standard PCI bus inte rface compliant for both 32-bit and
64-bit designs. No e xternal transceiv ers or glue logic is required in interfacing the Univ erse II
to any other PCI com pliant devices. All signals may be routed directly to those de vices.
The Universe II’s PCI inte rface can be use d as a 32-bit bus or 64-bit bus. If used as a 32-bit
interf ace, the 64-bit pins, AD[32:63] and ACK64# are left unterminated. On a 32-bit P CI b us,
the Universe II dr i ves all it s 64-bit extension bi-direct signals (C/BE[7:4]#, AD[63:32],
REQ64#, PAR64 and ACK64#) at all times to unknown values. Independent of the setting of
the LD64EN bit, the Universe II will never attempt a 64-bit c ycle on the PCI bus if it is
powered up as 32-bit.
Power-up Pins
Universe External
Register
OE
VOE# Tranceivers
VMEbus
OE
delay
Figure C.3 : Power-up Configurat ion Using Active Circuitry
Typi cal Applications Univ erse II User Manual
App C-8 Tundra Semiconductor Corporation
REQ64# must be pulled-do wn (with a 4.7kΩ resistor) at reset for 64-bit PCI (see “PCI Bus
W idt h” on page 2-119). There is an internal pull-up on this pin which causes the Univ erse II to
default to 32-bit PCI. This power-up option provides the necessary informat ion to the
Unive rse II so that these unused pins may be left unterminated.
C.2.1 Resets
The Universe II provides several reset input and outputs which are asserted under various
conditions. These can be grouped into thre e types as shown in Ta ble C.3.
VMEbus Resets
The VMEbus resets are connected to the VMEb us as indicated in Figure C.1 on page C-2
through external buffers.
PCI bus Resets
Use of the PCI bus resets will be application dependent. The RST# input to the Universe II
should typically be tied in some fashion t o the PCI b us reset signal of the same name. This
will ensure that all Uni ve r se II PCI related functions are rese t together with the PCI bus.
The LRST# pin is a totem-pole output which is asserted due to any of the following initiators:
• PWRRST#,
• VRSYSRST#,
• local so ftwa re rese t (in th e MISC _ C TL reg ister), or
• VME CSR reset (in the VCSR_SET register).
The designer may wish to disallow the Univ erse II fr om resetting the PCI b us in which case
this output may be left unconnect ed. Otherwise LRST# should be grouped with other PCI
reset generators to assert the RST# signal such that:
RST# = LRST# & reset_source1 & reset_source2 &...
Table C.3 : Reset Signals
Group Signal Name Direction
VMEbus VXSYSRST output
VRSYSRST# input
PCI bus LRST# output
RST# input
VME_RESET# input
Power-up PWRRST# input
Universe II Use r M anual Typ ical Appl ications
Tundra Semiconductor Corporation App C-9
If the Univ erse II is the only initiator of PCI reset, LRST# may be dir e ctly connected to R ST #.
Assertion of VME_RESET causes the Universe II to assert VXSYSRST.
This signal must not by tied to the PCI RST# signal unless the Universe II
LRST# output will not generate a PCI bus reset. Connecting both LRST# and
VME_RESET# to RST# will cause a feedback loop on the reset circuitry
forcing the entire system into a endless reset.
To r eset the VMEb us through this signal it is r ecommended that it be asser ted for se v era l clock
cycles, until the Universe II asser ts RS T#, and then relea sed. This ensur es a brea k is made in
the feedback path.
Power-Up Reset
The PWRRST# input is used to pro vide reset to the Univ erse II until the power supply has
reached a stable level. It should be held asserted for 100 milliseconds after power is stable.
Typically this can be achieved through a resistor/capacitor combination although m ore
accurate solutions using under voltage sensing circuits (e.g. MC34064) are often
implemented. The pow er-up options are latched on the rising edge of PWRRST#.
JTAG Reset
The JTAG reset, TRST#, should be tied i nto the master system JTA G controller. It resets the
Univ erse II internal JTA G controller. If JTAG is not bei ng used, t his pin should be tied to
ground.
C.2.2 Local Interrupts
The Uni verse II provides eight local b us interrupts, only one of which has dri v e strength that is
fully PCI compliant. I f any of t he other se ven interrupts are to be used as interrupt outputs to
the local bus (a ll eight may be defined as either input or output), an analysis must be done on
the design to determine whether the 4 mA of dri ve that the Uni verse II provides on these lines
is sufficient for the design. If more drive is required, the lines may simply be buffered.
All Universe II i nterrupts are initially defined as i nputs. To prevent excess po wer dissipation,
any interr upts defined as inputs should alw ays be dr i ven to either high or low. Pull-ups should
be used for this purpose rather than direct drive since a mis-programming of the interrupt
regis ters may cause the local interrupts to be configured as ou tputs and potentially damage the
device.
!
Typi cal Applications Univ erse II User Manual
App C-10 Tundra Semiconductor Corporation
C.3 Man ufacturin g Test Pins
The Universe II has several signals used for manufacturing test purpos es. They are listed in
Table 2.24 on page 2-121, along with the source to which they should be tied.
C.4 Deco uplin g VDD and VSS on the Univ erse II
This section is intended to be a guide for decoupling the power and ground pins on the
Uni v er se II. A separate analog power and ground plane is not required to provide power to the
analog portion of the Universe II. Ho wever, to ensur e a ji tter free PLL operation, the analog
AVDD and AVSS pins must be nois e free. The follo wing are recommended solutions for noise
free PLL operation. The design could implement one of these solutins, but not both.
The Analog Isolation Scheme consists of the following:
• a 0.1µF capacitor between the AV DD and AVSS pins, and
• corresponding inductors between the pins and the board power and ground planes
(See Figure C.4). These inductors are not necessary, but they are recommended.
The Noise Filter Scheme f ilters out the noise using two capacitor s to f ilter high and lo w
frequencies (See Figure C.5).
Board VDD
Board VSS
AVDD
AVSS
1.5 - 220 µH
1.5 - 220 µH
0.1 µF
Figure C.4 : Analog Isolation Scheme
Universe II Use r M anual Typ ical Appl ications
Tundra Semiconduc tor Corporation A pp C-11
For both schemes, it is r ecomm ended t hat the components in v olved be t ied as close as possible
to the associat ed analog pins.
In addition to the decoupling schemes shown above, it is recommended that 0.1µF bypass
capacitors should be tied between ev ery three pairs of VDD pins and the board ground plane.
These b ypas s capacitors should also be tied as close as possible to the package.
AVDD
AVSS
0.01 µF
Bo ard V SS
Board VDD
10-38 †
(Low Freq. Bias)
22 µF (High Freq. Bias)
Figure C.5 : Noise Filter Scheme
Typi cal Applications Univ erse II User Manual
App C-12 Tundra Semiconductor Corporation
VMEbus Interface Components—Universe II User Manual
Tundra Semiconductor Corporation App D-1
Appendix D Reliability Prediction
This section is designed to help t he user to estimate the inherent reliability of the Universe II,
as based on the requirements of MIL HDBK217F. This inform ation is recommended for per-
sonnel who are familiar with the methods and lim itations contained in MIL HDBK217F. The
information serves as a guide only; meaningful results will be obtained only through careful
consideration of the device, its ope rating environment, and its application.
D.1 Physic al characteristics
• CMOS gate array
• 120,000 two-input nand gate equivalence
• 0.65 µm feature size
• 476 mils x 476 mils scri bed die size
D.2 Thermal characteristics
Idle power consumption: 1.50 Wa tts
Typical power consumption* (32-bit PCI): 2.00 Watts
Maximum power consumption (32-bit PCI): 2.70 Watts
Typical power consumption (64-bit PCI): 2.20 Watts
Maximum power consumption* (64-bit PCI): 3.20 Watts
*NOTE: Maximum power consumption is worst case consumption whe n the Universe II is
performing DMA reads from the VME bus with alternating worst case data patterns
($FFFF_FFFF, $0000_0000 on conse cutive cycles), and 100pF loading on the PCI bus .
In the majority of system applications, the Universe II will consume typical values or less.
Typical power consumption numbers are based on the Universe II remaining i dle 30%-50% of
the time, which is signif icantly less than what is conside red likely in most systems. For this
reason, it is rec omme nded tha t t ypical power c onsum ption numbers be us ed for power estima-
tion and ambient temperature calculations, as described below.
Reliability calculations of the Universe II design in Motorola’s H4EPlus Gate Array family
show that the Failure In Time (FIT) ra te is 68 at a junction te mperature of 125°C (maximum
junction temperature). (Failure in time is the basic re liability rate expressed as failure s per bil-
lion (1e-9) device hours. Mean Time Between Failures (MTBF) is the reciprocal of FIT.
MTBF is the predicted number of device hours before a failure will occur.)
Reli ability Pred iction Univ erse I I User Manual
App D-2 Tundra Semiconductor Corporation
D.3 Universe II Ambient Operating Calculations
The maximum ambient temperature of the Unive rse II ca n be calculated as follows:
Ta ≤ Tj - θja * P
Where,
Ta = Ambient temperature (°C)
Tj = Maximum Universe II Junction Temper atur e (°C)
θja = Ambient to Junc tion Thermal Impedanc e (°C / Watt)
P = Uni verse II power consumption (Watts)
The ambient to junction thermal im pedance (θja) is dependent on the air flow in linear feet per
minute over the Universe II. The values for θja over different values of air flow are as follows:
For example, the maximum ambient temperature of the 313 PBGA, 32-bit PCI environment
with 100 LFPM blowing past the Universe II is:
Ta ≤ Tj - θja * P
Ta ≤ 125 - 17.0 * 2.70
Ta ≤ 79.1 °C
Hence the maximum rated ambient tempe rature for the Universe II in this environment is
79.1°C. The thermal impedance can be improved by approximately 10% by adding thermal
conductive tape to the top of the packages and through accounting for heat dissipation int o t he
ground planes. T his would impr ove the maximum ambient temperature to 87°C in the above
example. Further improvements can be made by a dding heat sinks to the PBGA package.
Tj values of Universe II are calculated as follows (Tj = θja * P + Ta)
Table D.1 : Ambient to Junc tion Thermal Impedanc e
Air Flow (LFPM) 0 100 300
313 PBGA 20 .10 17. 0 15.1
324 CBGA 17.80 15.4 13.5
Tabl e D.2 : Ma xi mum Universe II J unc tion Tempera ture
Extended (125 C Ambient) Industrial (85 C Ambient) Commercial: (70 C Ambient)
Tj = 17.0 * 2.70 + 125 C
= 170. 9 C
Tj = 17.0 * 2.70 + 85 C
= 130.9 C
Tj = 17.0 *2.70 + 70 C
= 115.9 C
Universe II Use r M anual Reliability Pred iction
Tundra Semiconductor Corporation App D-3
D.4 Thermal vias
The 313-pin plastic BGA package co ntains thermal vias which directly pipe heat from the die
to the solder balls on the underside of the package. The solder balls use the capabilities of the
power and ground planes of the printed circuit board to draw heat out of the package.
Reli ability Pred iction Univ erse I I User Manual
App D-4 Tundra Semiconductor Corporation
VMEbus Interface Components—Universe II User Manual
Tundra Semiconduc tor Corporation App E-1
Appendix E Cycle Mapping
The Uni verse II always performs Address Invariant translati on between the PCI and VMEb us
ports. Address Invariant mapping preserves the byte ordering of a data structure in a little-
endian memory ma p and a big-endian memory map.
E.1 Little-endian Mode
Table E.1 below shows the byte lane swapping and address translation between a 32-bit little-
endian PCI bus and the VMEbus for the address invariant translation scheme.
Table E.1 : Mapping of 32-bit Littl e-Endian PCI Bus to 32-b it VMEb u s
PCI Bus Byte Lane Mapping VMEbus
Byte Enables Add ress
321010 DS1DS0A1LW
111000 D0-D7
<-> D8-D15 0101
110101 D8-D15
<-> D0-D7 1001
101110 D16-D23
<-> D8-D15 0111
011111 D24-D31
<-> D0-D7 1011
110000 D0-D7 <-> D8-D15 0001
D8-D15 <-> D0-D7
100101 D8-D15 <-> D16-D23 0010
D16-D23 <-> D8-D15
001110 D16-D23 <-> D8-D15 0011
D24-D31 <-> D0-D7
100000
D0-D7 <-> D24-D31
1000D8-D15 <-> D16-D23
D16-D23 <-> D8-D15
000101
D8-D15 <-> D16-D23
0100D16-D23 <-> D8-D15
D24-D31 <-> D0-D7
Cycle Mapping Universe II User Manual
App E-2 T undr a Semiconductor Corporation
The unpacking of multiplex e d 64-bit data from the VMEbus into two 32-bit quantities on a
little-endian PCI bus is outlined in Ta ble E.2 below.
000000
D0-D7 <-> D24-D31
0000
D8-D15 <-> D16-D23
D16-D23 <-> D8-D15
D24-D31 <-> D0-D7
Table E.2 : Mapping of 32-bit Littl e-Endian PCI Bus to 64-b it VMEb u s
Byte Enables Address PCI to VME Byt e Lane Mapping
3210210
First Transfer (D32-D63)
0000000
D0-D7 <-> A24-A31 (D56-D63)
D8-D15 <-> A16- A 23 (D 48-D55)
D16-D23 <-> A8-A15 (D40 -D 47)
D24-D31 <-> LWORD, A1-A7 (D32- D39)
Second Transfer (D0-D 31)
0000100
D0-D7 <-> D24-D31
D8-D15 <-> D16-D23
D16-D23 <-> D8-D15
D24-D31 <-> D0-D7
Table E.1 : Mapping of 32-bit Littl e-Endian PCI Bus to 32-b it VMEb u s (Continued)
PCI Bus Byte Lane Mapping VMEbus
Byte Enables Add ress
321010 DS1DS0A1LW
VMEbus Interface Components—Universe II User Manual
Tundra Semiconduc tor Corporation App F-1
Appendix F Operating and Storage
Conditions
WARNING: Stresses beyond those listed above may cause permanent damage
to the devices. These are stress ratings only, and functional operation of the
devices at these or any other conditions beyond those indicated in the
operational sections of this document is not implied. Exposure to maximum
r a ting conditions for ex tend ed periods may affect dev ice reliab ility.
Tabl e F.1 : Recomme nde d Ope ra ting Co ndit i ons
DC Supply Voltage (VDD)5 V
Ambient Operating Temperature (TA Comm er cial) 0°C to +70°C
Amb ient Operating Temperature ( TA Industrial) -40°C to +85°C
Ambient Ope rating Temperature (TA Ex tend edf ) -5 5°C to +125 °C
Tabl e F.2 : Ab so lute Maxi m u m Ra ting s
DC Supply Voltage (VSS to VDD) -0.5 to 6.0 V
Input Voltage (V IN) -0.5 t o VDD+0.5 V
DC Cu rrent Drain per Pin, Any Singl e Input or O utput ±50 mA
DC Curr ent Drain per P in, Any Parallel ed O utputs ±100 mA
DC Current Drain VDD and VSS Pins ±75 mA
Storage Temperatu re, (TSTG) 0°C to 70°C
!
Operatin g and Storag e Conditions Univ erse II User Manua l
App F-2 Tundra Semiconductor Corporation
Table F.3 : Power Dissipation
IDLE
Power Dissipat ion (32-bit PCI) 1.97W
Power Dissipat ion (64-bit PCI) 2.12W
Typical
Power Dissipat ion (32-bit PCI) 2.65W
Power Dissipat ion (64-bit PCI) 3.15W
VMEbus Interface Components—Universe II User Manual
Tundra Semiconduc tor Corporation App G-1
Appendix G Mechanical and
Ordering Information
G.1 Mechan ical In formati on
Note that dimensions and tolerancing for all mechanical drawings follow ANSI Y14.5M,
1982.
M
A2
A1
A
e
e/2
D
45° X 4
J
K X3
E
DETAIL M
H
METAL AREA
INDEX MARK
324 X B
0.25 (0.010) SC
CASBS
S
0.10 (0.004)
0.20 (0.008) C
0.10 (0.004)
C
0.15 (0.006) C
SEATING PLANE
F
F
VIEW F-F (Bottom View)
15101520
A
E
Y
K
R
Figure G.1 : Mechanical Dimensions for the 324-Pin Ceramic BGA Package
DIMENSION 324 CBGA
MIN MAX
A 2.80 mm 3.50 mm
A1 0.74 mm 0.80 mm
A2 2.55 mm 2.95 mm
B 0.50 mm 0.70 mm
D 20.85 mm 21.15 mm
E 20.85 mm 21.15 mm
e 1.00 mm (BSC)
H 7.35 mm 7.65 mm
J 1.20 mm 1.80 mm
K 2.20 mm 2.80 mm
Mechanic al Information Universe II User Manual
App G-2 Tundra Semicond uctor Corporation
The 313-PBGA s hips in two varieties: OMPAC and GTPAC. Tundra cannot predict or
guarantee whi ch vari ety of the 313-PBGA we will ship to a given customer. The dif f erences
between these packages are minor and should not impact on your board layout. This manual
includes mechanicals for both varieties of 313-PBGA. The bottom and side views of these
packages are identical. However, the top vie ws of the OMPAC and GTPAC dif fer slightly.
Figure G.2 pre sents a single mechanical diagra m for the 313-PBGA, which covers both types
of package. It gives the top, side, and bottom view of these packages. Figure G.2 should be
used for board layout.
Figure G.3 presents the specif ic top views of the 313 OMPAC and the 313 GTPA C. This
information is pr ovided for customer conv enience only. Figure G.2 is t he f igure t hat should be
used for board layout.
Universe II User Manual Mechanical Info rmation
Tundra Semiconduc tor Corporation App G-3
Figure G.2 : 313-PBGA (Generic)
Mechanic al Information Universe II User Manual
App G-4 Tundra Semicond uctor Corporation
Figure G.3 : 313-PBGA Top V iew (OMPAC and G TPAC Drawings)
Universe II User Manual Ordering Information
Tundra Semiconduc tor Corporation App G-5
G.2 Ordering Information
Tundra Semiconductor Corporation products are designated by a Product Code. When
ordering, refer to products by their full code. For detailed mechanical drawings or alternat ive
packaging requirements, ple ase contact our factory directly
Table G.1 below details the available part numers.
Table G.1 : Stan dard Ordering Information
Part Numb er PCI Frequency Temperature Package
CA91C142-33CE 33 0° to 70°C BGA (Plastic)
CA91C142-33IE 33 -40° to 85°C BGA (Plastic)
CA91C142-25EE 25 -55° to 125°C BGA (Plastic)
CA91C142-33CB 33 0° to 70°C BGA (Ce ramic)
CA91C142-33IB 33 -40° to 85°C BGA (Ceramic)
CA91C142-25EB 25 -55° to 125° C BG A (Ceramic)
CA91C142 - X X X
Part Number
Speed
33 - 33 MHz
25 - 25 MHz
Packaging
E - BGA (Pla sti c )
B - BGA (Ceramic)
Temperature
C - Commercial (0° to 70°C)
I - Industrial (-40° to 8 5°C)
E - E xte nd ed (-55° to 125°C)
Ordering Information Universe II User Manual
App G-6 Tundra Semicond uctor Corporation
VMEbu s In terfa ce Co m p on ent s—Un i v er se I I U ser M a nu a l
Tundra Semiconduc tor Corporation Index-1
A
Absolute Maximum Ratings App F-1
ACFAIL*
interrupt source 2-63
interrupts 2-62
ACK64# 2-18, 2-31, 2-33, 2-39, 2-52, 2-119,
3-5, 3-6, 4-3, App C-7
Special Cycle Generator 2-45
AD 3-5, 4-3, 4-7
and Configuration Cycles 2-21, 2-22
parity checking 2-34
Special PCI target image 2-55
Target-Disconnects 2-49
Address Translation App E-1
PCI to VME 2-54
VME to PCI 2-52
Addressing Capabilities
PCI M as te r In te rface 2-3 6
VMEbus Master Interface 2-9
ADOH Cycles 2-18, 2-45, 2-47
DMA Channel 2-96
generating 2-47
Target-Retry 2-103
Ambient Operating Temperature App F-1
Architectura l Diagram 2-3
AS* 2-19
Auto Slot ID
proprietary method 2-25
VME64 specified 2-24
A40 2-2
B
BBSY* 2-8
ADOH cycles 2-18
coupled-cycles 2-43
DMA VMEbus ownership 2- 81
BCLR* 2-9
BE RR 2-1 3
BERR* 2-13, 2-15, 2-37
coupled cycles 2-58
BGIN App C-1
BGIN3* App C-7
BG3IN* 2-115
and First Slot Detector 2-23
BI-Mode 2-28
Block Diagram 2-3
BR3-0* 2-7
BSDL 2-123
Bus Errors
DMA cont roller 2-83, 2-97
IACK cycle 2-70
parity 2-34
RXFIFO posted writes 2- 16
TXFIFO posted writes 2-49
B us O w nershi p 2-92
Bus Parking 2-31
Byte Enables App E-1
Byte Lane Mapping App E-1
Byte Ordering App E-1
C
CBGA App G-1
Cerami c BGA Package App G-1
Index
Index Universe II User Manual
Index-2 Tundra Semiconductor Corporation
CLK64 2-26, 2-112, 2-123, 3- 1, 4-3
Configuration Cycles 2-20, 2-32, 2-36, 2-78,
2-100, 2-101, 2-102, 2-103
Coupled Request Phase 2- 42
Coupled Request Time r 2-8
Coupled Transactions
error handling 2-58
PCI Target Channel 2-42
VMEbus Slave Channel 2-14
Coupled Wait Phase 2-43
Coupled Window Timer 2-8, 2-43
Cycle Mapping App E-1
Cycle Terminat ions
PCI M as te r In te rface 2-3 7
PCI Target Channel 2-49
VMEbus Master Interface 2-13
VMEbus Slave Channel 2-15, 2-16
C/BE# 2-31, 2-34, 2-37, 2-60, 2-119, 3-5, 4-3
D
Data Packing/Unpacking
PCI Target Channel 2-41
VMEbus Master Interface 2-12
Data Transf er
PCI M as te r In te rface 2-3 6
PCI Target Channel 2-39
VMEbus Master Interface 2-10
VMEbus Slave Channel 2-14, 2-15, 2-16,
2-19
Data Width 2-79
DC Current Drain App F-1
DC Supply Voltage App F-1
DCPP Register App A-61
DCPP field 2- 80
DCTL Register App A-57
LD64EN bit 2-80
L2V bit 2-78
PGM field 2-78
SUPER field 2-78
VAS field 2-78
VCT bit 2 -80
VDW bit 2-80
Designer’s Resource Center 1-5
DEVSEL# 2-32, 2-33, 2-38, 2-52, 2-61, 3-5, 4-
3
DGCS Regi ster App A-62
ACT bit 2 -79, 2-81, 2-85, 2-89, 2-97
CHAIN bit 2-79
DONE bit 2-81, 2-83, 2-85, 2-86, 2-90, 2-
91, 2-92, 2-97
GO bit 2-80, 2-81, 2-82, 2-85, 2-89, 2-90,
2-91, 2-92, 2-97
HALT bit 2-82, 2-83, 2-90, 2-97
INT_DONE bit 2-75
INT_HALT bit 2-75
INT_LERR bit 2-75, 2-83, 2-85, 2-88, 2-
95, 2-97, 2-98
INT_M_ERR bit 2-75, 2-96
INT_STOP bit 2-75, 2-83, 2-85, 2-88, 2-95
INT_VERR bit 2-75, 2-83, 2-85, 2-88, 2-
95, 2-97, 2-98
LERR bit 2-81, 2-83, 2-85, 2-97
P_ERR bit 2-81, 2-83, 2-85, 2-97
STOP bit 2-79, 2-81, 2-82, 2-83, 2-85, 2-
86, 2-90, 2-97
STOP_REQ bit 2-82, 2-85, 2-86, 2- 90
VERR bit 2-85, 2-97
VOFF field 2-81, 2-85, 2-88, 2-95
VON field 2-81, 2-82, 2-85, 2-88, 2-93, 2-
94
Direction Control App C-5
DLA Register 2-78, App A-59
Tundra Semiconduc tor Corporation Index-3
Universe II Use r Manual Index
DMA Channel
PCI requests 2-35
PCI to VME transfers 2-92
VME tot PCI tra nsfers 2-94
VMEbus release 2-9
VMEbus requests 2-7
DMA Completion 2-82
DMA Controller
defined 2-5
direct mode oper ation 2-83
error handling 2-60, 2-96
FIFO opera tion and bus ownership 2-92
interrupts 2-95
linked-list operation 2-86
DMA Inte rrupts 2-95
DMAFIFO 2-5
packing 2-92, 2-94
PCI bus watermark 2-95
VMEbus watermark 2- 94
DTACK 2-13
DTACK* 2-13, 2-17, 2-103, 4-5
Location Monitors 2-20
RXFIFO 2-16
DTBC Register App A-58
DTBC field 2-78
DVA Register 2-78, App A-60, App A -87
DY4 Systems 2-24
D_LLUE Register App A-64
UPDATE bit 2-91
D32 2-16, 2-79
E
Endian Modes App E-1
ENID 3-5, 4-3
Erro r H andling
coupled transact ions 2-58
DMA controller 2-60
parity 2-60
posted writes 2-58
prefet ched re ads 2-60
F
FIFOs
DMAFIFO 2-92
RDFIFO 2-17
RXFIFO 2-15
TXFIFO 2-44
First Slot Detector 2-23
FIT rate App D-1
FRAME# 2-18, 2-31, 2-33, 2-38, 2-43, 2-49,
3-5, 4-3
G
GNT# 2-31, 3-5, 4-3, App B-12
H
High Impedance Mode 2-122
I
IACK 2-58
IACKIN App C-1
IACKIN* 2-25
SYSCON 2-23
IACKOUT* 2-25
IACK* 2- 13, 2-23
error logging 2-58
IDSEL 2-32, 2-102, 3-5, 4-3
Index Universe II User Manual
Index-4 Tundra Semiconductor Corporation
Input Voltage App F-1
Interrupt Acknowled ge Cycles
auto-ID 2-25
bus errors 2-70
STATUS/ID 2-70
Interrupt Channel
VMEbus release 2-8
VMEbus requests 2-6
Interrupt Generation
PCI bus 2-63
VMEbus 2-65
Interrupt Handling
internal sources 2-71
PCI bus 2-68
VMEbus 2-68
Interrupter
defined 2-4
IRDY# 2-33, 2-49, 3-5, 4-3
IRQ* 2-62, 2-65
interrupt source 2-63
IRQ2*
Auto Slot ID 2-24
J
JTAG 2-123, App C-9
L
LAERR Register App A-40
LAERR field 2-16
LCLK 2-33, 2-123, 3-5, 4-3
LERR 2-37, 2-59
Linked-List Operation of DMA 2-86
LINT# 2-64, 2-69, 2-70, 2-74, 3-5, 4-3
LINT_EN Register App A-65
ACFAIL bit 2-64, 2-65
DMA bit 2-64
interrupt sources 2-64
LERR bit 2-37, 2-64
LMn bit 2-64
MBOXn bit 2-64
SW_IACK bit 2-64, 2-73, 2-74
SW_INT bit 2-64, 2-73
SYSFAIL bit 2-64, 2-65
VERR bit 2-13, 2-49, 2-64
VIR1x bits 2-64
VMEbus interrupt inputs 2-68
VOWN bit 2-64
LINT_MAP0 Register App A-69
interrupt sources 2-64
VERR field 2-64
VIRQ7-1 fields 2-64, 2-69, 2-70
VMEbus interrupt handling 2-64, 2-69
VMEbus interrupt inputs 2-64
VMEbus ownershi p bit 2-64
VOWN field 2-64
LINT_MAP1 Register App A-70
ACFAIL field 2- 64
DMA field 2-64
interrupt sources 2-64
LERR field 2-64
SW_IACK field 2-64, 2-74
SW_INT field 2-64
SYSFAIL field 2-64
LINT_MAP2 Register 2-64, App A-85
LM3-0 fields 2-76
MBOX3-0 fields 2-75
Tundra Semiconduc tor Corporation Index-5
Universe II Use r Manual Index
LINT_STAT Register 2-59, App A-67
ACFAIL bit 2-64
DMA bit 2-64
interrupt sources 2-64
LERR bit 2-64
LMx bit 2-76
MBOXn bit 2-64, 2-75
Software inte rrupts 2-73
SW_INT bit 2-73
SYSFAIL bit 2-64
VERR bit 2-64
VMEbus interrupt handling 2-69
VMEbus interrupt inputs 2-64
VOWN bit 2-64
Little-Endian Mode App E-1
LMISC Register App A-36
CWT field 2-43
LM_BS Register 2-20, 2-75, App A-116
LM_CTL Register App A-115
EN bit 2-20
SUPER field 2-20
VAS field 2-20
Location Monitors 2-19-2-20
and interrupts 2-20
interrupts 2-19, 2-75, 2-76
Locks
VMEbus Slave Channel 2-19
LOCK# 2-18, 2-19, 2-47, 2-51, 3-6, 4-3
LRST# 2-110, 2-111, 2-112, 2-114, 3-6, 4-3,
App C-8
LSIn_BD Registe rs
BD field 2-53
Power-up options 2-116
LSIn_BS Registers
BS field 2-53
Power-up options 2-116
LSIn_CTL Registers
EN bit 2-53
LAS field 2-53
PGM field 2-53
Power-up options 2-116
PWEN bit 2-44, 2-53
SUPER field 2-53
VAS field 2-53
VCT field 2-53
VDW field 2-53
LSIn_TO Registers
TO field 2-53
LSI0_BD Register App A-17
LSI0_BS Register App A-16
LSI0_CTL Register App A-15
LSI0_TO Register App A-18
LSI1_BD Register App A-21
LSI1_BS Register App A-20
LSI1_CTL Register App A-19
LSI1_TO Register App A-22
LSI2_BD Register App A-25
LSI2_BS Register App A-24
LSI2_CTL Register App A-23
LSI2_TO Register App A-26
LSI3_BD Register App A-29
LSI3_BS Register App A-28
LSI3_CTL Register App A-27
LSI3_TO Register App A-30
LSI4_BD Register App A-43
LSI4_BS Register App A-42
LSI4_CTL Register App A-41
LSI4_TO Register App A-44
LSI5_BD Register App A-47
LSI5_BS Register App A-46
LSI5_CTL Register App A-45
LSI5_TO Register App A-48
LSI6_BD Register App A-51
LSI6_BS Register App A-50
Index Universe II User Manual
Index-6 Tundra Semiconductor Corporation
LSI6_CTL Register App A-49
LSI6_TO Register App A-52
LSI7_BD Register App A-55
LSI7_BS Register App A-54
LSI7_CTL Register App A-53
LSI7_TO Register App A-56
L_CMDERR Register App A-39
CMDERR field 2-16, 2-37
L_STAT bit 2-16, 2-37
M_ERR bit 2-16, 2-37
M
Mailbox Registers 2-108
Interrupts 2-65
Master-Abort
defined 2-33
MAST_CTL Register App A-93
BUS_NO field 2-20, 2-21, 2- 22
MAXRTRY field 2-37
PABS field 2-16, 2-17, 2-35, 2-36, 2-60
PWON field 2-8, 2-11
VOWN bit 2-7, 2- 8, 2-47, 2-48, 2-75
VOWN_ACK 2-47
VOWN_ACK bit 2-7, 2-48
VREL bit 2-8, 2-48
VRL field 2-7
VRM field 2-7
MBOXn Registers 2-75, 2- 108
MBOX0 Register App A-87
MBOX1 Register App A-88
MBOX2 Register App A-89
MBOX3 Register App A-90
MD32 2-2
Mechanical App G-1
MISC_CTL Register App A-95
AUTOID bit 2-24
BI bit 2-29, 2-116
ENGBI bit 2-29
SW_LRST bit 2-111, 2-112
SW_SYSRST bit 2-112
SYSCON bit 2-23, 2-26, 2-116
VARB bit 2-27
VARBTO field 2-27
VBTO field 2-28
V64AUTO bit 2-116
MISC_STAT Register A pp A-97
DY4AUTO bit 2-116
DY4AUTOID field 2-26
DY4DONE bit 2-26
LCLSIZE bit 2-116
MYBBSY bit 2-8
RXFE bit 2-36
TXFE bit 2-8
Monarch 2-24
MTBF App D-1
N
NAND Tree Simulation 2-122
Noise Filter App C-10
Normal Mode 2-122
O
Operating Conditions App F-1
Ordering Information App G-5
P
Packaging App G-5
PAR 2-34, 2-37, 2-60, 3-6, 4-3
Tundra Semiconduc tor Corporation Index-7
Universe II Use r Manual Index
Parity
error handling 2-60
PCI M as te r In te rface 2-3 7
Parity Checking
Universe capability 2-34
Part Number App G-5
PAR64 2-34, 2-37, 2-60, 3-6, 4-3
PBGA App D-2
PCI Aligned Burst Size (PABS) 2-17, 2-35, 2-
36, 2-60, 2- 92
PCI Cycle Type s
Universe II capability 2-36
PCI Inte rface
cycle types 2-32
defined 2-4
Uni v er se II as ma st er 2-35
Universe II as slave 2-38
32-bit versus 64-bit 2-30
PCI M ast e r Inte rface
cycle terminations 2-37
data transfer 2-36
parity 2-37
PCI Requests
DMA Channel 2-35
VME Slave Channe l 2-35
PCI Slave Images
defined 2-53
PCI Target Channel
ADOH cycles 2-47
coupled transactions 2-42
cycle terminations 2-49
data packing/unpacking 2-41
data transfer 2-39
posted writes 2-44
re a d-mo dify-writ es 2-46
TXFIFO 2-44
VMEbus release 2-8
VMEbus reqests 2-6
PCI Target Image
Power-up Option 2-116
PCI Terminations
defined 2-33
PCI _ BS n Reg i st er
BS field 2-103
SPACE bit 2-103
PCI_BSn Registers
BS field 2-103
SPACE bit 2-103
PCI_BS0 Registe r App A-12
SPACE bit 2-116
PCI_BS1 Registe r App A-13
SPACE bit 2-116
PCI_CLASS Register App A-10
PCI_CSR Register App A-8
BM bi t 2-14, 2-18, 2-51, 2-52, 2-81, 2-83
power-up option 2-116
DEVSEL field 2-38
DP_D bit 2-38
D_PE bit 2-38, 2- 60
PERESP bit 2-38, 2-60
R_MA bit 2-15, 2-37
R_TA bit 2-15, 2-37
SERR_EN bit 2-39, 2-60
S_SERR bit 2-39
S_TA bit 2-49
PCI_ID Register App A-7
PCI_MISC0 Register App A-11
PCI_MISC1 Register App A-14
PERR# 2-38, 2-60, 2-61, 3-6, 4-3
PLL App C-10
PLL_TESTOUT 2-123, 3-6, 4-3
PLL_TESTSEL 2-122, 3-6, 4-4
Posted Writes
and coupled transfers 2-42
error handling 2-58
errors 2-16
PCI Target Channel 2-44
VMEbus Slave Channel 2-15
power consumption App D-1
Power Dissipation App F-2
Index Universe II User Manual
Index-8 Tundra Semiconductor Corporation
Power-up
register access 2-23
Power-up Options 2-117, App C-5
auto-ID 2-118
BI-mode 2-118
PCI bus width 2-119
PCI CSR image space 2-119
PCI slave image 2-118
SYSFAIL assertion 2-118
VME CR/CSR slave image 2-117
VME register access slave i mage 2-117
Prefetched Reads
error handling 2-60
VMEbus Slave Channel 2-16
Product Code App G-5
Pull-down resistors App C-5
PWON App B-4
PWRRST# 2-110, 2-112, 2- 113, 2-114, 2-115,
2-116, 2-120, 2-122, 3-6, 4-4, App C-6,
App C-8, App C-9
R
RDFIFO 2-3, 2-17
size 2-17
Read-Modify-Writes
PCI Target Channel 2-46
VMEbus Slave Channel 2-19
Registe r Access
at power-up 2-23
configuration space 2-102
CR/CSR access 2-106
from VMEbus 2-104
I/O space 2-103
memory space 2-103
VMEbus register access image 2-104
Register Map App A-2
Registers 2-100-2-109
Reliability App D-1
Request Modes 2-7
REQ# 2-31, 2-33, 3-6, 4-4, App B-12
REQ64# 2-18, 2-31, 2-33, 2-39, 2-52, 2-115,
2-116, 2-119, 3-6, 4-4, App C-7
Resets 2- 110
RETRY* 2-4, 2-13
RST# 2-110, 2- 112, 3-6, 4-4, App C-8, App C -
9
BI-MODE 2-29
RXFIFO 2-15
S
SCV64 1-3, 2- 24
SCY C_ADDR Regist er A pp A-32
ADDR field 2-45
SCYC_CMP Register App A-34
CMP field 2-45
SCYC_CTL Registe r App A-31
SCYC field 2-45, 2-46
SCYC_EN Register App A-33
EN field 2-45
SCYC_SWP Register App A-35
SWP field 2-45
SDONE 2-30
SEMAn Register 2-109
Semaphores 2-91, 2-109
SEMA0 Registe r 2-109, App A-91
SEMA1 Registe r 2-109, App A-92
SERR# 2-34, 2-38, 2-39, 2-60, 2-61, 3-6, 4-4
Signal Conventions 1-6
Tundra Semiconduc tor Corporation Index-9
Universe II Use r Manual Index
SLSI Register App A-37
BS field 2-56
EN bit 2-56
LAS field 2-56
PGM field 2-56
PWEN bit 2-56
SUPER field 2-56
VDW field 2-56
Special Cycle Generator 2-4, 2-45-2-48
semaphores 2-109
Special PCI Slave Image
defined 2-55
memory mapping 2-57
STATID Register 2-24, 2-66, App A-77
STATID field 2-67
STATUS/ID
provided by Universe II 2-67
STOP# 2-33, 2-49, 3-7, 4-4
Storage Conditions App F-1
Storage Temperature App F-1
SYSCON 2-123
SYSFAIL* 2-68, 2-76, 2-118
and auto ID cycle 2-24
Auto ID cycle 2-24
Auto Slot ID 2-24
interrupt source 2-63
interrupts 2-62
SYSRST* 2-24, 2-112, 2-115, 2-118, App C-
6, App C-7
Auto ID cycle 2-24
BI-Mode 2-29
T
Target-Abort
defined 2-33
Target-Disconnect
defined 2-33
Target-Retry
defined 2-33
TCK 2-123, 3-7, 4-4
TDI 2-123, 3-7, 4-4
TDO 2-123, 3-7, 4-4
Terminology 1-7
Thermal vias App D-3
Time-Outs
VMEbus 2-28
VMEbus arbiter 2-27
TMODE 2-122, 2-123, 3-7, 4-4
TMS 2-123, 3-7, 4-4
TRDY# 2-33, 2-49, 3-7, 4-4
TRST# 2-110, 2-123, 3-7, 4-4
TT L Bu ffer s App C-2
Tundra web site 1-5
TXFIFO 2-44
U
USER_AM Register 2-55, App A-98
USER1AM, USER2AM fields 2-10
V
VA 3-1, 4-4, App C-5
and Configuration Cycles 2- 21
Configuration Cycles 2-21
Location Monitor 2-76
power-up options 2-116
VAERR Register App A-122
VAERR field 2-13, 2-49
VAM 3-1, 4-4
VAM_DIR 3-1, 4-4, App C-5
VAS# 3-1, 4-4
VAS_DIR 3-2, 4-4, A pp C-5
VA_DIR 3-1, 4-4, App C-5
Index Universe II User Manual
Index-10 Tundra Semiconductor Corporation
VBCLR# 2-27, 3-2, 4-5
VBGIN 2-116
VBGI# 3-2, 4- 5
VBGO# 2-27, 3-2
VBG0# 4-5
VCOCTL 2-121, 2-123, 3-7, 4- 5
VCSR_BS Register A pp A-141
BS field 2-106
VCSR_CLR Register 2-114, App A-139
FAIL bit 2-114
RESET bit 2-111
SYSFAIL bit 2-25, 2-111, 2-114, 2-116
VCSR_CTL Register App A-119
EN bit 2-106
LAS field 2-106, 2-116
VCSR_SET Register App A-140
FAIL bit 2-114
SYSFAIL bit 2-25, 2-114, 2-116
VCSR_TO Register App A-120
TO fie ld 2- 106, 2-116
VD 3-2, 4-5
power-up options 2-116
pull-ups 2-119
VDS# 3-2, 4-5
VDS_DIR 3-2, 4-5, App C-5
VDTACK# 3-2, 4-5
VD_DIR 3-2, 4-5, App C-5
VERR 2-37, 2-59
VIACKI# 4-5
VIACKO# 3-3, 4-5
VIACK# 3-3, 4-5
VINT_EN Register App A-71
DMA bit 2-66
interrupt sources 2-66
LERR bit 2-16, 2-37, 2-66
MBOX3-0 bits 2- 66
PCI inte rrupt inputs 2-68
SW_INT bit 2-66, 2-73
SW_INT7-1 bit s 2-66, 2-73, 2-116
VERR bit 2-13, 2-49, 2-66
VINT_MAP0 Register 2-66, App A-75
VINT_MAP1 Register 2-66, App A-76
DMA field 2-66
interrupt sources 2-66
LERR field 2-66
SW_INT bit 2-116
SW_INT field 2-66, 2-73
VERR field 2-66
VINT_MAP2 Register 2-66, App A-86
MBOX3-0 fields 2-75
VINT_STAT Register 2-59, 2-66, 2-67, 2-68,
App A-73
DMA bit 2-66, 2-96
IACK cycle er ror 2-70
interrupt sources 2-66
LERR bit 2-66, 2-70
LINT7-0 bitS 2-66
LINT7-0 bits 2-75
MBOX3-0 bitS 2-66
MBOX3-0 bits 2- 75
PCI inte rrupt inputs 2-68
SW_INT bit 2-66, 2-73, 2-116
SW_INT7-1 bit s 2-66
VERR bit 2-66, 2-70
VMEbus interrupt handling 2-69
VLWORD# 3-3, 4-5
VME Slave Images
defined 2-50
Tundra Semiconduc tor Corporation Index-11
Universe II Use r Manual Index
VMEbus Arbitration 2-27
arbiter time -out 2-27
priority mode 2-27
round robin 2-27
single level 2-27
VMEbus Interface
BI-mode 2-28
configuration 2-23
CR/CSR access 2-106
defined 2-2
first slot detector 2-23
requester 2-6
system clock 2-26
system controller 2-26
Univer se as mast er 2-9
Univer se as slave 2- 13
VMEbus release 2-8
VMEbus time-out 2-28
VMEbus Mas t er Int erface
addressing capabi lities 2-9
cycle terminations 2-13
data packing/unpacking 2-12
data transfer 2-10
VMEbus Register Access Ima ge 2-104
VMEbus Requester
demand mode 2-7
DMA Channel 2-7
fair mode 2-7
Interrupt Channel 2-6
PCI Target Channel 2-6
request le vels 2-7
VMEbus Slave Channel
coupled transactions 2-14
errors 2-16
locks 2-18
PCI requests 2-35
posted writes 2-15
prefetched reads 2-16
RDFIFO 2-17
re a d-mo dify-writ es 2-19
RXFIFO 2-15
VMEbus System Controller
IACK daisy chain 2-27
VMEbus arbitrati on 2-27
VME_RESET App C-9
VME_RESET# 2-110, 2-112, 2- 114, 3-7, 4-5,
App C-8, App C-9
Vn_STATID Registers 2-69
ERR bit 2-70
STATID field 2-69
VOE# 2-119, 2-120, 3-3, 4-5, App C-6
VOFF timer 2-82, 2-93, 2-95
Voltage App F-1
VON 2-81
VRACFAIL# 3-3, 4-5
VRAI_BS Register App A-118
BS field 2-23, 2-104, 2-116
VRAI_CTL Register App A-117
EN bit 2-104, 2-116
PGM field 2-104
SUPER field 2-104
VAS field 2-104
VRBBSY# 2-27, 3-3, 4-5
VRBERR# 3-3, 4-5
VRBR# 2-27, 3-3, 4-6
VRIRQ 2-29, 2-63
VRIRQ# 3-3, 4-6
VRSYSFAIL# 3-4, 4-6
VRSYSRST# 2-110, 2-112, 3-4, 4-6, App C -8
VSCON_DIR 3-4, 4-6, App C -5
VSIn_BD Registers
BD field 2- 50
VSIn_BS Registers
BS field 2-50
Index Universe II User Manual
Index-12 Tundra Semiconductor Corporation
VSIn_CTL Registers
and Type 0 configuration cycles 2-22
EN bit 2-50
LAS field 2-50
LD64EN bit 2-17, 2-50
LLRMW bit 2-19, 2-50
PGM field 2-50
PREN bit 2-16, 2- 50
PWEN bit 2-15, 2-50
SUPER field 2-50
Type 0 configuration cycles 2-21
VAS field 2-50
VSIn_TO Registers
TO fie ld 2- 50
VSI0_BD Register App A-101
VSI0_BS Regis ter App A-100
VSI0_CTL Register App A-99
VSI0_TO Register App A- 102
VSI1_BD Register App A-105
VSI1_BS Regis ter App A-104
VSI1_CTL Register App A-103
VSI1_TO Register App A- 106
VSI2_BD Register App A-109
VSI2_BS Regis ter App A-108
VSI2_CTL Register App A-107
VSI2_TO Register App A- 110
VSI3_BD Register App A-113
VSI3_BS Regis ter App A-112
VSI3_CTL Register App A-111
VSI3_TO Register App A- 114
VSI4_BD Register App A-125
VSI4_BS Regis ter App A-124
VSI4_CTL Register App A-123
VSI4_TO Register App A- 126
VSI5_BD Register App A-129
VSI5_BS Regis ter App A-128
VSI5_CTL Register App A-127
VSI5_TO Register App A- 130
VSI6_BD Register App A-133
VSI6_BS Register App A-132
VSI6_CTL Register App A-131
VSI6_TO Register App A-134
VSI7_BD Register App A-137
VSI7_BS Register App A-136
VSI7_CTL Register App A-135
VSI7_TO Register App A-138
VSLAVE_DIR 3-4, 4-6, App C-5
VSYSCLK 2-123, 3-4, 4-6
VWRITE# 3-4, 4-6
VXBBSY 3-4, 4-6
VXBERR 3-4, 4-6
VXBERR# 2-28
VXBR 3-4, 4-6
VXIRQ 3-4, 4-7
VXSYSFAIL 3-4, 4-7
VXSYSRST 3-4, 4- 7, App C-8, A pp C-9
V_AMERR Register 2-58, App A-121
AMERR field 2-13, 2-49
IACK bit 2-13, 2-70
M_ERR bit 2-13, 2-49
V_STAT bit 2-13, 2-49
V1_STATID Register App A-78
V2_STATID Register App A-79
V3_STATID Register App A-80
V4_STATID Register App A-81
V5_STATID Register App A-82
V6_STATID Register App A-83
V7_STATID Register App A-84
Tundra Semiconduc tor Corporation Sales-1
Eastern
D.C., Maryland, Virginia
Che sapeake Technologi es
3905 N atio nal Dr., S uite 42 5
Burtonsville, MD 20866
Tel: 301-236-0530
F ax: 301 -384-9596
Che sapeake Technologi es
12-616E Hampton Dr.
Mi dlothian, VA 23113
Tel: 804-379-1816
F ax: 804 -379-3474
Connecti cut, Maine, Massachuset ts,
New Hampshire, New Jersey, New
York, Rhode Island, Ver m ont, Eastern
Pennsylvania
Daner Hay es Inc.
300 Eliot S t., Suite 342
As hland, MA 01721
Tel: 508-881-0400
F ax: 508 -881-8227
Upstate New York, Delaware, Ohio
Supertech
103-A Kingsberry Dr.
Rochester, NY 14626
Tel: 716-720-0915
F ax: 716 -720-0916
EMA, Inc.
Aurora Office Plaza, Suite 291
251 West G arfield Rd.
Aurora, OH 44202
Tel: 216-562-6104
F ax: 216 -562-7498
EMA, Inc.
35 Compark Road,
Centre ville, OH 45459
Tel: 937-433-2800
F ax: 937 -433-3147
Florida
Apollo Technical Sales Co.
1275S Patrick Dr., #M2
Satellite Beach , FL 32937- 3963
Tel: 407-777-7511
F ax: 407 -777-5251
Central
Illinois, Michigan, Wisconsin
Horizon Technical Sales
4340 Cross St reet,
Do w ner ’s Grov e, IL 605 15
Tel: 630-852-2500
F ax: 630 -852-2520
Horizon Technical Sales
6011 H illdale Dr.
Hartford, WI 53027-9541
Tel: 414-670-6776
F ax: 414 -670-6778
Alabama, Georgia, Mississippi,
North Carolina, South Carolina,
Tennessee
BITS, I nc.
2707 A rti e St., Suite 10
Huntsville, AL 35805
Tel: 205-534-4020
F ax: 205 -534-0410
BITS, I nc.
1 Meca Way
Norcros s, GA 30093
Tel: 770-564-5599
F ax: 770 -564-5588
BITS, I nc.
7706 Six Fo rks Rd., Suite 101
Raleigh, NC 27615
Tel: 919-676-1880
F ax: 919 -676-1881
BITS, I nc.
2305 Keaton Ave., Suite E
Charlotte, NC 282 69
Tel: 704-510-1064
F ax: 704 -510-1065
Arkansas , Louis iana, Oklahoma,
Texas
Quad State Sales and Marketing
12160 Abrams Rd., Suite 406
Da llas, TX 75243
Tel: 972-669-8567
F ax: 972 -669-8834
Quad State Sales and Marketing
8310 Capit al of Texas Highway
Nor th, Su ite 365
Austin, TX 787331
Tel: 512-346-7002
F ax: 512 -346-3601
Quad State Sales and Marketing
10565 Katy Freeway, Sui te 212
Hou ston, TX 77024
Tel: 713-467-7749
F ax: 713 -467-5942
Quad State Sales and Marketing
110 West Commercial, Suite 210
Broken Arrow, OK 74013
Tel: 918-258-7723
F ax: 918 -258-7653
Minnesota, No rth Dakota, South
Da kota, Wes tern Wiscons in
Electromec Sales Inc.
1601 East Hi ghway 13, Suite 102
Burnsville, MN 55337
Tel: 612-894-8200
F ax: 612 -894-9352
Missouri, Souther n Illi nois, Iowa,
Kansas, Nebraska
Please c ontact Tundra Semiconductor
directly at: 1-800-267-7231
Mountain
Arizona, Ne w Mexico
Please c ontact Tundra Semiconductor
directly at: 1-800-267-7231
Worldwide Sales Network
1
USA Sales Representatives
Sales-2 Tundra Semiconductor Corporation
Colorado, Idaho, Montana, U tah,
Wyoming
In termountain C om p onent Sa les
12665 South Minuteman Dr.
Dr asper, UT 84020
Tel: 801-572-4010
F ax: 801 -572-8180
In termountain C om p onent Sa les
2801 Youngfield St., Suite 300
Golden, CO 804 01
Tel: 303-275-7150
F ax: 303 -275-7142
Western
Northern Cali fornia,
Northern Ne vada
Quo rum Technic al Sales
4701 Patrick Henry Dr.
Santa Cla ra, CA 95054
Tel: 408-980-0812
F ax: 408 -748-1163
Souther n California,
Souther n Nevad a
Please contact Tundra Semiconductor
directly at: 1-800-267-7231
Oregon, Wahington State
Electronic Sources, Inc.
6865 S.W. 105t h, Suite B
Beaverton, OR
97008
Tel: 503-627-0838
F ax: 503 -627-0238
Electronic Sources, Inc.
1603 116th Ave. N E, Suite 115,
Belle vue, WA 98004
Tel: 425-451-3500
F ax: 425 -451-1038
USA Sales Representa tives Cont’d
Tundra Semiconduc tor Corporation Sales-3
Australia
ACD
Unit 2, 17-19 Melrich Rd.
Bayswater, Victoria
Aus tralia 3153
Tel: 61-3-9762-7644
F ax: 61-3-976 2-5446
ACD
106 Belmore Rd .
North Riverwood, NSW
Aus tralia 2210
Tel: 61-2-534-6200
F ax: 61-2-534 -4910
ACD
20D Will ia m Str ee t ,
Norwood, South Australia
Australia
Tel: 61-8-364-2844
F ax: 61-8-364 -2811
ACD
Uni t 1, Technology Park
Bently, West Australia
Australia
Tel: 61-9-472-3232
F ax: 61-9-470 -2303
Belgium, The Netherlands
Microtron
Ge neraal D ewittelaan 7
2800 Mechelen
Belgium
Tel: 32-15-292929
F ax: 32-15-29 2900
Canada
Hewetson Repping, Inc.
161 H erzberg Rd
Kanata, ON K2K 2Y3
Tel: 613-271-9044
F ax: 613 -271-9040
Hewetson Repping, Inc.
215 Traders Bl vd, Unit 2
Mi ssiss auga, O N L4Z 3K 5
Tel: 905-501-8800
F ax: 905 -501-8818
Hewetson Repping, Inc.
100 boul. Al exis N ihon, suite 945
St-Laurent, PQ H4M 2P5
Tel: 514-744-6511
F ax: 514 -744-0904
Hewetson Repping, Inc.
103 Douglas Woods Grove SE
Calgary AL T2Z 2H6
Tel: 403-236-4622
Fax:403-236-4366
Denmark, Norway, Sweden
IE Kompo n ent e r A B
Ulvsundavagen 106C
Box 11113
161 11 Bromma , Sweden
Tel: 46 8 804685
F ax: 46 8 262286
Finland
Integrated Electronics OyAb
Laurinmaenkuja 3
FIN-00440 Helsinki
Finland
Tel: 358-9-586-1770
F ax: 358-9-586-1771
France
Compress
47 Rue de L’Estérel
539 94 633 Rungi s CEDE X
FRANCE
Tel: 33 1 41 802902
F ax: 33 1 46 866763
Germany
P I El ectr onic Engineering, GmbH
Keitla nderstr asse 48
74354 Besegheim-Ottmarsheim ,
Germany
Tel: 49 71 4381 1153
F ax: 49 71 4358 853
Hong Kong
Please contact Tundra Semiconductor
directly at: 613-592-0714
India
Hynetic Elect roni cs
No. 50, 2nd Cross
Gavipuram Extension,
Bangalore, 560019, India
Tel: 91-80-620852
F ax: 91-80-62 4073
Israel
Migvan Technologies and
En gin eeri ng L td .
13 Hashiloach St.
PO Box 7022
Petach-Tikva 49170, Israe l
Tel: 972-3-9240784
F ax: 972 -3-924078 7
Italy
EL. CO. MI. S.r. l.
Viale G Matteotti, 26
20095 Cusano Milanino (MI),
Italy
Tel: 39 2 619 6452
F ax: 39 2 613 4836
Japan
K.K. Rocky
4-44-11, Nogata
Nakano-ku,
Tokyo, 165 J apan
Tel: 813 3228 4511
F ax: 813 3388 1391
Tok yo Electron Ltd.
TBS Broadcast Center
3-6 Akasaka, 5-Chome
Minato-Ku
Tokyo, 107 J apan
Tel: 81-35561-7216
F ax: 81-35561- 7389
Korea
VME Te ch Inc.
627-19 Shi nsa-d ong K angna m-gu,
5th Floor, Shinsa Building,
Seoul, Korea 135 -120
Tel: 82-2-3443-1491
F ax: 82-2-344 3-1495
International Sales Represen tatives
Sales-4 Tundra Semiconductor Corporation
I & C Microsystems Co. Ltd.
8th Floor, Bethel Building,
324-1 Yangjae-D ong Seocho -Ku,
Seoul, Korea
Tel: 822-577-9131
F ax: 822 -577-9130
New Zealand
ACD
University Paton NZ Ltd.
Unit 7, 110 Mays Road,
Penrose
Auckland , NZ
Tel: 649-636-5984
F ax: 649 -636-5985
Singapore
BBS Electronics
1 Genting Link
#05-04 Perfect Industrial Building
Singapo re, 349 518
Singapore
Tel: 65 748 9851
F ax: 65 748 5965
Switzerland
Egli , Fi scher & Co, Ltd. Zurich
Got thardstrass e 6
Ch-8022
Zurich, Sw itze rlan d
Tel: 41 1 209 81 11
F ax: 41 1 201 22 75
Taiwan
Dat a Fas t E lectroni cs
6 Fl, No 27-1, A lley 169
Kang Ning Street
Hsi Chih
Taipei, Taiwan
Tel: 886 2 6921051
Fax: 886 2 6958240
United Kingdom
Tham e Components
Tham e Park Road
Thame, Oxfordshire 0X9 3UQ
Tel: 44 1 844 261188
F ax: 44 1 844 261681
Welvar Electronics Ltd.
MBM Box 66
Manor Lane, Rochester
K ent, Englan d ME5 1 H S
Tel: 44 1 634 815033
F ax: 44 1 634 832133
International Sales Represen tatives Cont’d
