Semiconductor Components Industries, LLC, 2001
May, 2001 – Rev. 5 1Publication Order Number:
MC74AC109/D
MC74AC109, MC74ACT109
Dual JK Positive
Edge-Triggered Flip-Flop
The MC74AC109/74ACT109 consists of two high–speed
completely independent transition clocked JK flip–flops. The
clocking operation is independent of rise and fall times of the clock
waveform. The JK design allows operation as a D flip–flop (refer to
MC74AC74/74ACT74 data sheet) by connecting the J and K inputs
together.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD an d SD makes bo th Q a nd Q HIGH
•Outputs Source/Sink 24 mA
•′ACT109 Has TTL Compatible Inputs
1516 14 13 12 11 10
21 34567
VCC
9
8
CD2 J2K2CP2SD2 Q2Q2
CD1 J1K1CP1SD1 Q1Q1GND
J1K1CP1SD1 Q1Q1
CDJ K CP SDQ
Q
CD1
Figure 1. Pinout; 16–Lead Packages Conductors
(Top V iew)
PIN ASSIGNMENT
PIN FUNCTION
J1, J2, K1, K2Data Inputs
CP1, CP2Clock Pulse Inputs
CD1, CD2 Direct Clear Inputs
SD1, SD2 Direct Set Inputs
Q1, Q 2, Q1, Q2Outputs
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DIP–16
N SUFFIX
CASE 648
1
16
SO–16
D SUFFIX
CASE 751B
1
16
Device Package Shipping
ORDERING INFORMATION
MC74AC109N PDIP–16 25 Units/Rail
MC74AC109D SOIC–16 48 Units/Rail
MC74AC109DR2 2500 Tape & Reel
TSSOP–16
DT SUFFIX
CASE 948F
MC74AC109DT TSSOP–16 96 Units/Rail
MC74AC109DTR2 TSSOP–16
SOIC–16
2500 Tape & Reel
MC74ACT109N PDIP–16 25 Units/Rail
MC74ACT109D SOIC–16 48 Units/Rail
MC74ACT109DR2 2500 Tape & Reel
MC74ACT109DT TSSOP–16 96 Units/Rail
MC74ACT109DTR2 TSSOP–16
SOIC–16
2500 Tape & Reel
1
16
See general marking information in the device marking
section on page 6 of this data sheet.
DEVICE MARKING INFORMATION
1
16
EIAJ–16
M SUFFIX
CASE 966
MC74AC109M EIAJ–16
MC74AC109MEL EIAJ–16 2000 Tape & Reel
MC74ACT109M EIAJ–16
MC74ACT109MEL EIAJ–16 2000 Tape & Reel
50 Units/Rail
50 Units/Rail
MC74AC109, MC74ACT109
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2
TRUTH TABLE
Inputs Outputs
SDCDCP J K Q Q
L H X X X H L
HLXX X L H
LLXXXH H
H H LLL H
H H H L Toggle
H H LHQ
0Q0–
H H HHH L
H H L X X Q0Q0–
H = HIGH Voltage Level
L = LOW Voltage Level
= LOW–to–HIGH Clock T ransition
X = Immaterial
Q0(Q0) = Previous Q0(Q0) before
LOW–to–HIGH Transition of Clock
Figure 2. Logic Symbol
SD
Q
JCP
Q
CD
K
SD
Q
JCP
Q
CD
K
SD
K
CP
J
CD
Q
Q
NOTE: This diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
(One Half Shown)
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) –0.5 to VCC +0.5 V
VOUT DC Output Voltage (Referenced to GND) –0.5 to VCC +0.5 V
IIN DC Input Current, per Pin ±20 mA
IOUT DC Output Sink/Source Current, per Pin ±50 mA
ICC DC VCC or GND Current per Output Pin ±50 mA
Tstg Storage Temperature –65 to +150 °C
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recom-
mended Operating Conditions.
MC74AC109, MC74ACT109
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3
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ Max Unit
V
Supply Voltage
′AC 2.0 5.0 6.0
V
VCC Supply Voltage ′ACT 4.5 5.0 5.5 V
VIN, VOUT DC Input Voltage, Output Voltage (Ref. to GND) 0 – VCC V
VCC @ 3.0 V – 150 –
tr, tfInput Rise and Fall Time (Note 1)
′
AC Devices exce
p
t Schmitt In
p
uts
VCC @ 4.5 V – 40 – ns/V
r,f
′AC
Devices
except
Schmitt
Inputs
VCC @ 5.5 V – 25 –
tt
f
Input Rise and Fall Time (Note 2) VCC @ 4.5 V – 10 –
ns/V
tr, tf
In ut
Rise
and
Fall
Time
(Note
2)
′ACT Devices except Schmitt Inputs VCC @ 5.5 V – 8.0 – ns/V
TJJunction Temperature (PDIP) – – 140 °C
TAOperating Ambient Temperature Range –40 25 85 °C
IOH Output Current – High – – –24 mA
IOL Output Current – Low – – 24 mA
1. VIN from 30% to 70% VCC; see individual Data Sheets for devices that dif fer from the typical input rise and fall times.
2. VIN from 0.8 V to 2.0 V ; see individual Data Sheets for devices that differ from the typical input rise and fall times.
DC CHARACTERISTICS
74AC 74AC
Symbol Parameter VCC
(V) TA = +25°CTA =
–40°C to
+85°CUnit Conditions
Typ Guaranteed Limits
VIH Minimum High Level 3.0 1.5 2.1 2.1 VOUT = 0.1 V
g
Input Voltage 4.5 2.25 3.15 3.15 V or VCC – 0.1 V
5.5 2.75 3.85 3.85
VIL Maximum Low Level 3.0 1.5 0.9 0.9 VOUT = 0.1 V
Input Voltage 4.5 2.25 1.35 1.35 V or VCC – 0.1 V
5.5 2.75 1.65 1.65
VOH Minimum High Level 3.0 2.99 2.9 2.9 IOUT = –50 µA
g
Output Voltage 4.5 4.49 4.4 4.4 V
5.5 5.49 5.4 5.4
*VIN = VIL or VIH
3.0 – 2.56 2.46
V
–12 mA
4.5 – 3.86 3.76
V
IOH –24 mA
5.5 – 4.86 4.76 –24 mA
VOL Maximum Low Level 3.0 0.002 0.1 0.1 IOUT = 50 µA
Output Voltage 4.5 0.001 0.1 0.1 V
5.5 0.001 0.1 0.1
*VIN = VIL or VIH
3.0 – 0.36 0.44
V
12 mA
4.5 – 0.36 0.44
V
IOL 24 mA
5.5 – 0.36 0.44 24 mA
IIN Maximum Input
55
–
±01
±10
µA
VI=V
CC GND
Leakage Current 5.5 – ±
0
.
1
±
1
.
0
µ
A
V
I =
V
CC,
GND
IOLD †Minimum Dynamic
Ot tC t
5.5 – – 75 mA VOLD = 1.65 V Max
IOHD Output Current 5.5 – – –75 mA VOHD = 3.85 V Min
ICC Maximum Quiescent
55
–
40
40
µA
VIN =V
CC or GND
Q
Supply Current 5.5 –
4
.
0
40
µ
A
V
IN =
V
CC or
GND
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
MC74AC109, MC74ACT109
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4
AC CHARACTERISTICS (For Figures and W aveforms – See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74AC 74AC
Symbol Parameter VCC*
(V) TA = +25°C
CL = 50 pF
TA = –40°C
to +85°C
CL = 50 pF Unit Fig.
No.
Min Typ Max Min Max
fmax
Maximum Clock 3.3 125 – – 100 –
MHz
3
–
3
f
max Frequency 5.0 150 – – 125 –
MH
z
3
–
3
tPLH
Propagation Delay 3.3 4.0 – 13.5 3.5 16.0
ns
3
–
6
tPLH
gy
CPn to Qn or Qn5.0 2.5 – 10.0 2.0 10.5 ns
3
–
6
tPHL
Propagation Delay 3.3 3.0 – 14.0 3.0 14.5
ns
3
–
6
tPHL
gy
CPn to Qn or Qn5.0 2.0 – 10.0 1.5 10.5 ns
3
–
6
tPLH
Propagation Delay 3.3 3.0 – 12.0 2.5 13.0
ns
3
–
6
tPLH
gy
CDn or SDn to Qn or Qn5.0 2.5 – 9.0 2.0 10.0 ns
3
–
6
tPHL
Propagation Delay 3.3 3.0 – 12.0 3.0 13.5
ns
3
–
6
tPHL
gy
CDn or SDn to Qn or Qn5.0 2.0 – 9.5 2.0 10.5 ns
3
–
6
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
AC OPERATING REQUIREMENTS
74AC 74AC
Symbol Parameter VCC*
(V) TA = +25°C
CL = 50 pF
TA = –40°C
to +85°C
CL = 50 pF Unit Fig.
No.
Typ Guaranteed Minimum
ts
Set–up T ime, HIGH or LOW 3.3 – 6.5 7.5
ns
3–9
ts
Set u
Time,
HIGH
or
LOW
Jn or Kn to CPn
3.3
5.0 –
6.5
4.5
7.5
5.0 ns
3
–
9
th
Hold T ime, HIGH or LOW 3.3 – 0 0
ns
3–9
th
Hold
Time,
HIGH
or
LOW
Jn or Kn to CPn
3.3
5.0 –
0
0.5
0
0.5 ns
3
–
9
tw
Pulse Width 3.3 – 4.0 4.5
ns
3–6
tw
Pulse
Width
CPn or CDn or SDn
3.3
5.0 –
4.0
3.5
4.5
3.5 ns
3
–
6
trec
Recovery TIme 3.3 – 0 0
ns
3–9
trec
Recovery
TIme
CDn or SDn to CP
3.3
5.0 –
0
0
0
0ns
3
–
9
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
DC CHARACTERISTICS
74ACT 74ACT
Symbol Parameter VCC
(V) TA = +25°CTA =
–40°C to
+85°CUnit Conditions
Typ Guaranteed Limits
VIH Minimum High Level 4.5 1.5 2.0 2.0
V
VOUT = 0.1 V
g
Input Voltage 5.5 1.5 2.0 2.0
V
or VCC – 0.1 V
VIL Maximum Low Level 4.5 1.5 0.8 0.8
V
VOUT = 0.1 V
Input Voltage 5.5 1.5 0.8 0.8
V
or VCC – 0.1 V
VOH Minimum High Level 4.5 4.49 4.4 4.4
V
IOUT = –50 µA
g
Output Voltage 5.5 5.49 5.4 5.4
V
*VIN = VIL or VIH
4.5 – 3.86 3.76 V
IOH
–24 mA
5.5 – 4.86 4.76
I
OH –24 mA
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
MC74AC109, MC74ACT109
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5
DC CHARACTERISTICS (continued)
Symbol ConditionsUnit
74ACT74ACT
VCC
(V)
ParameterSymbol ConditionsUnit
TA =
–40°C to
+85°C
TA = +25°C
VCC
(V)
ParameterSymbol ConditionsUnit
Guaranteed LimitsTyp
VCC
(V)
Parameter
VOL Maximum Low Level 4.5 0.001 0.1 0.1
V
IOUT = 50 µA
Output Voltage 5.5 0.001 0.1 0.1
V
*VIN = VIL or VIH
4.5 – 0.36 0.44 V
IOL
24 mA
5.5 – 0.36 0.44
I
OL 24 mA
IIN Maximum Input
55
–
±01
±10
µA
VI=V
CC GND
Leakage Current 5.5 – ±
0
.
1
±
1
.
0
µ
A
V
I =
V
CC,
GND
∆ICCT Additional Max. ICC/Input 5.5 0.6 – 1.5 mA VI = VCC – 2.1 V
IOLD †Minimum Dynamic
Ot tC t
5.5 – – 75 mA VOLD = 1.65 V Max
IOHD Output Current 5.5 – – –75 mA VOHD = 3.85 V Min
ICC Maximum Quiescent
55
–
40
40
µA
VIN =V
CC or GND
Q
Supply Current 5.5 –
4
.
0
40
µ
A
V
IN =
V
CC or
GND
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
AC CHARACTERISTICS (For Figures and W aveforms – See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74ACT 74ACT
Symbol Parameter VCC*
(V) TA = +25°C
CL = 50 pF
TA = –40°C
to +85°C
CL = 50 pF Unit Fig.
No.
Min Typ Max Min Max
fmax
Maximum Clock
50
145
–
–
125
–
MHz
3–3
f
max
Maximum
Clock
Frequency 5.
0
14
5 – –
12
5 –
MH
z
3
–
3
tPLH
Propagation Delay
50
40
–
11 0
35
13 0
ns
3–6
tPLH
Pro agation
Delay
CPn to Qn or Qn5.
0
4
.
0
–
11
.
0
3
.5
13
.
0
ns
3
–
6
tPHL
Propagation Delay
50
30
–
10 0
25
11 5
ns
3–6
tPHL
Pro agation
Delay
CPn to Qn or Qn5.
0
3
.
0
–
10
.
0
2
.5
11
.5 ns
3
–
6
tPLH
Propagation Delay
50
25
–
95
20
10 5
ns
3–6
tPLH
Pro agation
Delay
CDn or SDn to Qn or Qn5.
0
2
.5 –
9
.5
2
.
0
10
.5 ns
3
–
6
tPHL
Propagation Delay
50
25
–
10 0
20
11 5
ns
3–6
tPHL
Pro agation
Delay
CDn or SDn to Qn or Qn5.
0
2
.5 –
10
.
0
2
.
0
11
.5 ns
3
–
6
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
AC OPERATING REQUIREMENTS
74ACT 74ACT
Symbol Parameter VCC*
(V) TA = +25°C
CL = 50 pF
TA = –40°C
to +85°C
CL = 50 pF Unit Fig.
No.
Typ Guaranteed Minimum
ts
Set–up T ime, HIGH or LOW
50
–
20
25
ns
3–9
ts
Set u
Time,
HIGH
or
LOW
Jn or Kn to CPn5.
0
–
2
.
0
2
.5 ns
3
–
9
th
Hold T ime, HIGH or LOW
50
–
20
20
ns
3–9
th
Hold
Time,
HIGH
or
LOW
Jn or Kn to CPn5.
0
–
2
.
0
2
.
0
ns
3
–
9
tw
Pulse Width
50
–
50
60
ns
3–6
tw
Pulse
Width
CPn or CDn or SDn 5.
0
– 5.
0
6
.
0
ns
3
–
6
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
MC74AC109, MC74ACT109
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6
AC OPERATING REQUIREMENTS (continued)
Symbol Fig.
No.
Unit
74ACT74ACT
VCC*
(V)
ParameterSymbol Fig.
No.
Unit
TA = –40°C
to +85°C
CL = 50 pF
TA = +25°C
CL = 50 pF
VCC*
(V)
ParameterSymbol Fig.
No.
Unit
Guaranteed MinimumTyp
VCC*
(V)
Parameter
trec
Recovery TIme
50
–
0
0
ns
3–9
trec
Recovery
TIme
CDn or SDn to CP 5.
0
–
0
0
ns
3
–
9
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
CAPACITANCE
Symbol Parameter Value
Typ Unit Test Conditions
CIN Input Capacitance 4.5 pF VCC = 5.0 V
CPD Power Dissipation Capacitance 35 pF VCC = 5.0 V
MARKING DIAGRAMS
A = Assembly Location
WL, L = W afer Lot
YY, Y = Year
WW, W = W ork Week
AC109
AWLYWW
MC74AC109N
AWLYYWW AC
109
ALYW
ACT109
AWLYWW ACT
109
ALYW
MC74ACT109N
AWLYYWW
DIP–16 SO–16 TSSOP–16 EIAJ–16
74AC109
ALYW
74ACT109
ALYW
MC74AC109, MC74ACT109
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7
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
FC
S
HGD
J
L
M
16 PL
SEATING
18
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
PDIP–16
N SUFFIX
16 PIN PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45
G
8 PLP
–B–
–A–
M
0.25 (0.010) B S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
SO–16
D SUFFIX
16 PIN PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
MC74AC109, MC74ACT109
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8
PACKAGE DIMENSIONS
TSSOP–16
DT SUFFIX
16 PIN PLASTIC TSSOP PACKAGE
CASE948F–01
ISSUE O
ÇÇÇ
ÇÇÇ
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C--- 1.20 --- 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.18 0.28 0.007 0.011
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
SECTION N–N
SEATING
PLANE
IDENT.
PIN 1
18
16 9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
L
2X L/2
–U–
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
–T–
–V–
–W–
0.25 (0.010)
16X REFK
N
N
EIAJ–16
M SUFFIX
16 PIN PLASTIC EIAJ PACKAGE
CASE966–01
ISSUE O
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.18 0.27 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 0.78 --- 0.031
A1
HE
Q1
LE
10 0
10
LEQ1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL
CONDITION. DAMBAR CANNOT BE LOCATED ON
THE LOWER RADIUS OR THE FOOT. MINIMUM
SPACE BETWEEN PROTRUSIONS AND
ADJACENT LEAD TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005) 0.10 (0.004)
1
16 9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
MC74AC109, MC74ACT109
http://onsemi.com
9
Notes
MC74AC109, MC74ACT109
http://onsemi.com
10
Notes
MC74AC109, MC74ACT109
http://onsemi.com
11
Notes
MC74AC109, MC74ACT109
http://onsemi.com
12
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MC74AC109/D
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