CDCE62002RHBT - Texas Instruments High-Performance Analog

CDCE62002

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SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

Check for Samples: CDCE62002

1FEATURES •Flexible Inputs With Innovative Smart

Multiplexer Feature:

•Frequency Synthesizer With PLL/VCO and –Two Universal Differential Inputs Accept

Partially Integrated Loop Filter Frequencies from 1 MHz up to 500 MHz

•Fully Configurable Outputs Including (LVPECL), 500 MHz (LVDS), or 250 MHz

Frequency and Output Format (LVCMOS).

•Smart Input Multiplexer Automatically –One Auxiliary Input Accepts Crystals in the

Switches Between one of two Reference Range of 2MHz–42MHz

Inputs. –Clock Generator Mode Using Crystal Input

•Multiple Operational Modes Include Clock –Smart Input Multiplexer can be Configured

Generation via Crystal, SERDES Startup Mode, to Automatically Switch Between Highest

Jitter Cleaning, and Oscillator Based Holdover Priority Clock Source Available Allowing

Mode. for Fail-Safe Operation.

•Integrated EEPROM Determines Device •Typical Power Consumption 750mW at 3.3V

Configuration at Power-up.

•Integrated EEPROM Stores Default Settings;

•Excellent Jitter Performance Therefore, the Device can Power up in a

•Integrated Frequency Synthesizer Including Known, Predefined State.

PLL, Multiple VCOs, and Loop Filter: •Offered in QFN-32 Package

–Full Programmability Facilitates Phase •ESD Protection Exceeds 2kV HBM

Noise Performance Optimization Enabling

Jitter Cleaner Mode •Industrial Temperature Range –40°C to 85°C

–Programmable Charge Pump Gain and APPLICATIONS

Loop Filter Settings

–Unique Dual-VCO Architecture Supports a •Data Converter and Data Aggregation Clocking

Wide Tuning Range 1.750 GHz –2.356 GHz. •Wireless Infrastructure

•Universal Output Blocks Support up to 2 •Switches and Routers

Differential, 4 Single-Ended, or Combinations •Medical Electronics

of Differential or Single-Ended: •Military and Aerospace

–0.5 ps RMS (10 kHz to 20 MHz) Output Jitter •Industrial

Performance •Clock Generation and Jitter Cleaning

–Low Output Phase Noise: –130 dBc/Hz at

1 MHz offset, Fc = 491.52 MHz

–Output Frequency Ranges From 10.94 MHz

to 1.175 GHz in Synthesizer Mode

–LVPECL, LVDS and LVCMOS

–Independent Output Dividers Support

Divide Ratios for 1, 2, 3, 4, 5, 8, 10, 12, 16,

20, 24 and 32.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

SERDES CleanedClock

Data

CDCE62002

RecoveredClock ASICClock

ASIC

CDCE62002

SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION

The CDCE62002 is a high performance clock generator featuring low output jitter, a high degree of configurability

via a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored for

clocking data converters and high-speed digital signals, the CDCE62002 achieves jitter performance under 0.5

ps RMS(1). It incorporates a synthesizer block with partially integrated loop filter, a clock distribution block

including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock

distribution block includes two individually programmable outputs that can be configured to provide different

combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique

output frequency (ranging from 10.94 MHz to 1.175 GHz(2)). If Both outputs are configured in single-ended mode

(e.g., LVCMOS), the CDCE62002 supports up to four outputs. The input block includes one universal differential

inputs which support frequencies up to 500 MHz and an auxiliary input that can be configured to connect to an

external AT-Cut crystal via an on board oscillator block. The smart input multiplexer has two modes of operation,

manual and automatic. In manual mode, the user selects the synthesizer reference via the SPI interface. In

automatic mode, the input multiplexer will automatically select between the highest priority input clock available.

Figure 1. CDCE62002 Application Example

(1) 10 kHz to 20 MHz integration bandwidth.

(2) Frequency range depends on operational mode and output format selected.

Product Folder Link(s): CDCE62002

5mm x 5mm

32 pin QFN

Thermal Pad

(must be soldered to ground)

2 3 4 5 6 71

21 20 19 1824 23 22

SPI_LE

TESTSYNC

REG_CAP3

GND_PLLDIV

EXT_LFP

VCC_PLLA

REG_CAP2

EXT_LFN

REG_CAP1

VCC_PLLD

VCC_AUX

VBB

AUX_IN

SPI_MISO

VCC_PLLDIV

REG_CAP4

VCC_VCO

VCC_IN

REF_IN-

REF_IN+

VCC_OUT1

U0N

U0P

VCC_OUT0

U1P

VCC_OUT1

U1N

PLL_LOCK 32

SPI_MOSI

VCC_OUT0

SPI_CLK

RHB PACKAGE

(TOP VIEW)

CDCE62002

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SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

DEVICE INFORMATION

PIN FUNCTIONS

Table 1. CDCE62002 Pin Functions(1)

PIN TYPE DESCRIPTION

NAME QFN

VCC_OUT0 9, 12 Power 3.3V Supply for the Output Buffers.

VCC_OUT1 13, 16

VCC_PLLDIV 22 Power 3.3V Supply Power for the PLL circuitry.

VCC_PLLD 4 Power 3.3V Supply Power for the PLL circuitry.

VCC_PLLA 28 A. Power 3.3V Supply Power for the PLL circuitry.

VCC_VCO 24 A. Power 3.3V Supply Power for the VCO Circuitry.

VCC_IN 31 A. Power 3.3V Supply Power for Input Buffer Circuitry

VCC_AUX 1 A. Power 3.3V Supply Power for Crystal/Auxiliary Input Buffer Circuitry

GND_PLLDIV 21 Ground Ground for PLL Divider circuitry. (short to GND)

GND PAD Ground Ground is on Thermal PAD. See Layout recommendation

3-state LVCMOS Output that is enabled when SPI_LE is asserted low. It is the serial Data Output to the SPI bus

SPI_MISO 7 O interface.

(1) It is furthermore recommended to use a supply filter for each VCC supply domain independently. A minimum requirement is to group the

supplies into four independent groups:

VCC_PLLA + VCC_VCO

VCC_PLLD + VCC_PLLDIV

VCC_IN + VCC_AUXIN

VCC_OUT0 + VCC_OUT1

All VCC pins need to be connected for the device to operate properly.

Product Folder Link(s): CDCE62002

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SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

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Table 1. CDCE62002 Pin Functions(1) (continued)

PIN TYPE DESCRIPTION

NAME QFN

LVCMOS input, control Latch Enable for Serial Programmable Interface.

SPI_LE 18 I Note: The SPI_LE signal has to be high in order for the EEPROM to load correctly on the Rising edge of PD. The

input has an internal 150-kΩpull-up resistor

SPI_CLK 17 I LVCMOS input, serial Control Clock Input for the SPI bus interface, with Hysteresis.

SPI_MOSI 8 I LVCMOS input, Master Out Slave In as a serial Control Data Input to CDCE62002 for the SPI bus interface.

PD or Power Down Pin is an active low pin and can be activated externally or via the corresponding Bit in SPI

While PD is asserted (low), the device is shut down. When PD switches high the EEPROM becomes loaded into

the RAM. After the selected input clock signal becomes available, the VCO starts calibration and the PLL aims to

PD 6 I achieve lock. All Output dividers become initiated. During self-calibration, the outputs are held static (e.g. logical

zero). PD pin has an internal 150-kΩpull-up resistor.

Note: The SPI_LE signal has to be high in order for the EEPROM to load correctly into RAM on the Rising edge of

PD.

AUX_IN 2 I Auxiliary Input is a Crystal input pin that connect to an internal oscillator circuitry.

REF_IN+ 29 I Universal Input Buffer (LVPECL, LVDS, LVCMOS) positive input for the Reference Clock.

Universal Input Buffer (LVPECL, LVDS,) negative input for the Reference Clock. This pin must be pulled to ground

REF_IN–30 I through 1kΩresistor when input is selected LVCMOS.

PLL_LOCK 32 O PLL Lock indicator

TESTSYNC 19 I Reserved Pin. Pull this pin down to ground using 1kΩresistor.

REG_CAP1 5 Analog Capacitor for the internal Regulator. Connect to a 10 μF Capacitor (Y5V)

REG_CAP2 27 Analog Capacitor for the internal Regulator. Connect to a 10 μF Capacitor (Y5V)

REG_CAP3 20 Analog Capacitor for the internal Regulator. Connect to a 10 μF Capacitor (Y5V)

REG_CAP4 23 Analog Capacitor for the internal Regulator. Connect to a 10 μF Capacitor (Y5V)

VBB 3 Analog Capacitor for the internal termination Voltage. Connect to a 1 μF Capacitor (Y5V)

EXT_LFP 25 Analog External Loop Filter Input Positive

EXT_LFN 26 Analog External Loop Filter Input Negative.

The outputs of CDCE62002 are user definable and can be any combination of up to 2 LVPECL outputs, 2 LVDS

U0P:U0N 11,10 O outputs or up to 4 LVCMOS outputs. The outputs are selectable via SPI interface. The power-up setting is

15,14

U1P:U1N EEPROM configurable.

Product Folder Link(s): CDCE62002

SPI_LE

SPI _CLK

SPI_MOSI

SPI_MISO

Output

Divider 0

U0 P

U0N

Output

Divider 1

U1 P

U1N

PFD /

CP Prescaler

Feedback

Divider

Input

Divider

Reference

Divider

REF_IN

XTAL /

AUX _IN

EEPROM

Interface

Control

EXT _LFP

EXT _LFN

CDCE62002

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SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

FUNCTIONAL DESCRIPTION

Figure 2. CDCE62002 Block Diagram

The CDCE62002 comprises of four primary blocks: the interface and control block, the input block, the output

block, and the synthesizer block. In order to determine which settings are appropriate for any specific

combination of input/output frequencies, a basic understanding of these blocks is required. The interface and

control block determines the state of the CDCE62002 at power-up based on the contents of the on-board

EEPROM. In addition to the EEPROM, the SPI port is available to configure the CDCE62002 by writing directly

to the device registers after power-up. The input block selects which of the two input ports is available for use by

the synthesizer block. The output block provides two separate clock channels that are fully programmable. The

synthesizer block multiplies and filters the input clock selected by the input block.

NOTE

This Section of the data sheet provides a high-level description of the features of the

CDCE62002 for purpose of understanding its capabilities. For a complete description of

device registers and I/O, refer to the Device Configuration Section.

Product Folder Link(s): CDCE62002

Device

Hardware

Static RAM Device Registers

Interface

Control

SPI_ LE

SPI_ CLK

SPI_ MOSI

SPI_ MISO

EEPROM Device Registers

REF_IN

XTAL/

AUX_IN

LVPECL/LVDS 500 MHz

LVCMOS 250 MHz

Crystal: 2 MHz – 42 MHz

Synthesizer

Reference

SmartMUX

Control

ReferenceDivider

/1 - /8

CDCE62002

SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

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Interface and Control Block

The CDCE62002 is a highly flexible and configurable architecture and as such contains a number of registers so

that the user may specify device operation. The contents of three 28-bit wide registers implemented in static

RAM determine device configuration at all times. On power-up, the CDCE62002 copies the contents of the

EEPROM into the RAM and the device begins operation based on the default configuration stored in the

EEPROM. Systems that do not have a host system to communicate with the CDCE62002 use this method for

device configuration. After power-up, the host system may overwrite the contents of the RAM via the SPI (Serial

Peripheral Interface) port. This enables the configuration and reconfiguration of the CDCE62002 during system

operation. Finally, the device offers the ability to copy the contents of the RAM into EEPROM

Figure 3. CDCE62002 Interface and Control Block

Input Block

The Input Block includes one Universal Input Buffer and an Auxiliary Input. The Input Block buffers the incoming

signals and facilitates signal routing to the Internal Synthesizer Block via the smart multiplexer (called the Smart

MUX). The CDCE62002 can divide the REF_IN signal via the dividers present on the inputs of the first stage of

the Smart MUX.

Figure 4. CDCE62002 Input Block

Product Folder Link(s): CDCE62002

PFD/

Prescaler

/2,/3,/4,/5

Input Divider

/1 - /256

SMART_MUX

SYNTH

/1,/2,/5,/8,/10,/16,/20

/8 - /1280

1.75 GHz –

2.356 GHz

Feedback Divider

Feedback Bypass Divider

/1,2,3,4,5

UxP

UxN

/1 - /8 /2

DigitalPhase Adjust (7-bits)

SYNTH

Sync

Pulse Enable

LVDSClockDividerModule 0 & 1

LVPECL

OutputBufferControl

CDCE62002

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SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

Synthesizer Block

Figure 5 presents a high-level overview of the Synthesizer Block on the CDCE62002. This block contains the

Phase lock loop, internal loop filter and dual Voltage controlled oscillators. Only one VCO is selected at a time.

The loop is closed after a Prescaler divider that feeds the output stage the feedback divider.

Figure 5. CDCE62002 Synthesizer Block

Output Block

Both identical output blocks incorporate a Clock Divider Module (CDM), and a universal output buffer. If an

individual clock output channel is not used, then the user should disable the Output Buffer for the unused

channel to save device power. Each channel includes 4-bit in register “0”to control the divide ratio. The output

divider supports divide ratios from divide of 1 (bypass the divider) 2, 3, 4, 5, 8, 10, 12, 16, 20, 24 and 32.

Figure 6. CDCE62002 Output Block

Product Folder Link(s): CDCE62002

Output

Divider 0

U0P

U0N

Output

Divider 1

U1P

U1N

PFD/

CP Prescaler

Feedback

Divider

Input

Divider

Reference

Divider

EXT_LFP

EXT_LFN

FOUT

Fin

OUT IN

F F

R I O

= × × ×

OUT

1.750GHz O P F 2.356GHz< × × <

COMP

R I

=×

CDCE62002

SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

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COMPUTING THE OUTPUT FREQUENCY

Figure 7 presents the block diagram of the CDCE62002 synthesizer highlighting the clock path for a single

output. It also identifies the following regions containing dividers comprising the complete clock path:

•R: Is the Reference divider values.

•O: The output divider value (see Output Block for more details)

•I: The input divider value (see Synthesizer Block for more details)

•P: The Prescaler divider value (see Synthesizer Block of more details)

•F: The cumulative divider value of all dividers falling within the feedback divider (see Synthesizer Block for

more details)

Figure 7. CDCE62002 Clock Path –Synthesizer

With respect to Figure 7, any output frequency generated by the CDCE62002 relates to the input frequency

connected to the Synthesizer Block by the following equation:

(1)

Equation 1 holds true subject to the following constraints:

(2)

And the comparison frequency FCOMP,

40.0 kHz ≤FCOMP ≤40 MHz

Where:

(3)

When AUX_IN is selected as the input, R can be set to 1 in Equation 1 and Equation 3.

Product Folder Link(s): CDCE62002

CDCE62002

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SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted) (1)

VALUE / UNIT

Supply voltage range VCC(2) –0.5 V to 4.6 V

Input voltage range, VI(3) –0.5 V to VCC + 0.5 V

Output voltage range, VO(3) –0.5 V to VCC + 0.5 V

Input Current (VI<0, VI>VCC) ±20 mA

Output current for LVPECL/LVCMOS Outputs (0 <VO<VCC)±50 mA

Maximum junction temperature, TJ125°C

Storage temperature range, Tstg –65°C to 150°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2) All supply voltages have to be supplied simultaneously.

(3) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

THERMAL CHARACTERISTICS

Package Thermal Resistance for QFN (RGZ) Package

Airflow (lfm) θJP (°C/W) θJA (°C/W)

0 JEDEC Compliant Board (3X3 VIAs on PAD) 1.13 35

200 JEDEC Compliant Board (3X3 VIAs on PAD) 1.13 28.3

400 JEDEC Compliant Board (3X3 VIAs on PAD) 1.13 27.2

PACKAGE

The CDCE62002 is packaged in a 32-Pin Lead Free “Green”Plastic Quad Flatpack Package with enhanced

bottom thermal pad for heat dissipation. The Texas Instruments Package Designator is; RHB (S-PQFP-N32).

Please refer to the Mechanical Data appendix at the end of this document for more information.

ELECTRICAL CHARACTERISTICS

recommended operating conditions for the CDCE62002 Device for under the specified Industrial temperature range of –40°C

to 85°CPARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT

POWER SUPPLY

Supply voltage, VCC_OUT, VCC_PLLDIV, VCC_PLLD, VCC_IN, and VCC_AUX 3 3.3 3.6 V

Analog Supply Voltage, VCC_PLLA, &VCC_VCO 3 3.3 3.6 V

PLVPECL REF at 30.72MHz, Outputs are LVPECL 850 mW

Output 1 = 491.52 MHz

Output 2 = 245.76 MHz

PLVDS REF at 30.72MHz, Outputs are LVDS 750 mW

In case of LVCMOS Outputs (1) =

245.76MHz

PLVCMOS REF at 30.72MHz, Outputs are LVCMOS 800 mW

POFF REF at 30.72MHz Outputs are disabled 450 mW

PPD Device is Powered Down 40 mW

DIFFERENTIAL INPUT MODE (REF_IN)

Differental Input amplitude, (VIN+ –VIN–) 0.1 1.3 V

Common-mode input voltage, VIC 1.0 VCC–03 V

VI= VCC,

IIH Differential input current High (No internal Termination) 20 μA

VCC = 3.6 V

VI= 0 V,

IIL Differential input current Low (No internal Termination) –20 μA

VCC = 3.6 V

Input Capacitance on REF_IN 3 pF

CRYSTAL INPUT SPECIFICATIONS

On-chip Load Capacitance 8 10 pF

Equivalent Series Resistance (ESR) 50 Ω

(1) All typical values are at VCC = 3.3 V, temperature = 25°C.

Product Folder Link(s): CDCE62002

CDCE62002

SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

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ELECTRICAL CHARACTERISTICS (continued)

recommended operating conditions for the CDCE62002 Device for under the specified Industrial temperature range of –40°C

to 85°CPARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT

LVCMOS INPUT MODE (SPI_CLK,SPI_MOSI,SPI_LE,PD, REF_IN)

VIL Low-level input voltage LVCMOS 0 0.3 VCC V

VIH High-level input voltage LVCMOS 0.7 VCC VCC V

VIK LVCMOS input clamp voltage VCC = 3 V, II=–18 mA –1.2 V

IIH LVCMOS input current VI = VCC, VCC = 3.6 V 20 μA

IIL LVCMOS input (Except REF_IN) VI= 0 V, VCC = 3.6 V –10 –40 μA

IIL LVCMOS input (REF_IN) VI= 0 V, VCC = 3.6 V –10 10 μA

CIInput capacitance (LVCMOS signals) VI= 0 V or VCC = 3 3 pF

SPI OUTPUT (MISO) / PLL_LOCK

IOH High-level output current VCC = 3.3 V, VO= 1.65 V –30 mA

IOL Low-level output current VCC = 3.3 V, VO= 1.65 V 33 mA

High-level output voltage for LVCMOS

VOH VCC = 3 V, IOH =–100 μA VCC–0.5 V

outputs

Low-level output voltage for LVCMOS

VOL VCC = 3 V, IOH = 100 μA 0.3 V

outputs

COOutput capacitance o MISO VCC = 3.3 V; VO= 0 V or VCC 3 pF

IOZH 5μA

3-state output current VO= VCC, VO= 0 V

IOZL –5μA

EEPROM

EEcyc Programming cycle of EEPROM 100 1000 Cycles

EEret Data retention 10 Years

VBB ( INPUT BUFFER INTERNAL TERMINATION VOLTAGE REFERENCE)

VBB Input termination voltage IBB = –0.2 mA, Depending on the setting 1.2 1.9 V

INPUT BUFFERS INTERNAL TERMINATION RESISTORS (REF_IN)

Termination resistance Single ended 5 kΩ

PHASE DETECTOR

fCPmax Charge pump frequency 0.04 40 MHz

Product Folder Link(s): CDCE62002

5 pF

LVCMOS

CDCE62002

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SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

ELECTRICAL CHARACTERISTICS (Continued)

recommended operating conditions for the CDCE62002 Device for under the specified Industrial temperature range of –40°C

to 85°CPARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT

LVCMOS

fclk Output frequency, see Figure below Load = 5 pF to GND 250 MHz

VOH High-level output voltage for LVCMOS VCC = min to max IOH =–100 μA VCC–0 V

outputs .5

VOL Low-level output voltage for LVCMOS VCC = min to max IOL = 100 μA 0.3 V

outputs

IOH High-level output current VCC = 3.3 V VO= 1.65 V –30 mA

IOL Low-level output current VCC = 3.3 V VO= 1.65 V 33 mA

tsko Skew, output to output For Y0 to Y1 Both Outputs set at 122.88 MHz, 75 ps

Reference = 30.72 MHz

COOutput capacitance on Y0 to Y1 VCC = 3.3 V; VO= 0 V or VCC 5 pF

IOZH Tristate LVCMOS output current VO= VCC 5μA

IOZL Tristate LVCMOS output current VO= 0 V -5 μA

IOPDH Power Down output current VO= VCC 25 μA

IOPDL Power Down output current VO= 0 V 5 μA

Duty cycle LVCMOS 45% 55%

tslew-rate Output rise/fall slew rate 3.6 5.2 V/ns

(1) All typical values are at VCC = 3.3 V, temperature = 25°C.

Product Folder Link(s): CDCE62002

LVDSDC Termination Test

Oscilloscope100Ω

CDCE62002

SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

www.ti.com

ELECTRICAL CHARACTERISTICS (Continued)

recommended operating conditions for the CDCE62002 Device for under the specified Industrial temperature range of –40°C

to 85°CPARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT

LVDS OUTPUT

fclk Output frequency Configuration Load (see Figure below) 0 800 MHz

|VOD| Differential output voltage RL= 100 Ω270 550 mV

ΔVOD LVDS VOD Magnitude Change 50 mV

VOS Offset Voltage –40°C to 85°C 1.24 V

ΔVOS VOS Magnitude Change 40 mV

Short Circuit Vout+ to Ground VOUT = 0 27 mA

Short Circuit Vout- to Ground VOUT = 0 27 mA

tsk(o) Skew, output to output For Y0 to Y1 Both Outputs set at 122.88 MHz 10 ps

Reference = 30.72 MHz

COOutput capacitance on Y0 to Y1 VCC = 3.3 V; VO = 0 V or VCC 5 pF

IOPDH Power Down output current VO= VCC 25 μA

IOPDL Power Down output current VO= 0 V 5 μA

Duty Cycle 45% 55%

tr/ tfRise and fall time 20% to 80% of VOPP 110 160 190 ps

LVCMOS-TO-LVDS

tskP_C Output skew between LVCMOS and LVDS outputs VCC/2 to Crosspoint 1.4 1.7 2.0 ns

(1) All typical values are at VCC = 3.3 V, temperature = 25°C.

Product Folder Link(s): CDCE62002

LVPECL DC Termination Test

50W50W

Oscilloscope

LVPECL AC Termination Test

50W

Oscilloscope

150W150W

Vcc-2

CDCE62002

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SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

ELECTRICAL CHARACTERISTICS (Continued)

recommended operating conditions for the CDCE62002 Device for under the specified Industrial temperature range of –40°C

to 85°C

PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT

LVPECL OUTPUT

fclk Output frequency Configuration Load (see Figure below) 0 1175 MHz

VOH LVPECL high-level output voltage Load VCC –1.1 VCC –0.88 V

VOL LVPECL low-level output voltage Load VCC –2.02 VCC –1.48 V

|VOD| Differential output voltage 510 870 mV

tsko Skew, output to output For Y0 to Y1 Both Outputs set at 122.88 MHz 15 ps

CO Output capacitance on Y0 to Y1 VCC = 3.3 V; VO = 0 V or VCC 5 pF

IOPDH Power Down output current VO= VCC 25 μA

IOPDL Power Down output current VO= 0 V 5 μA

Duty Cycle 45% 55%

tr/ tfRise and fall time 20% to 80% of VOPP 55 75 135 ps

LVDS-TO- LVPECL

tskP_C Output skew between LVDS and LVPECL outputs Crosspoint to Crosspoint 130 200 280 ps

LVCMOS-TO- LVPECL

tskP_C Output skew between LVCMOS and LVPECL outputs VCC/2 to Crosspoint 1.6 1.8 2.2 ns

LVPECL Hi-PERFORMANCE OUTPUT

VOH LVPECL high-level output voltage Load VCC –1.11 VCC –0.91 V

VOL LVPECL low-level output voltage Load VCC –2.06 VCC –1.84 V

|VOD| Differential output voltage 670 950 mV

tr/ tfRise and fall time 20% to 80% of VOPP 55 75 135 ps

(1) All typical values are at VCC = 3.3 V, temperature = 25°C.

Product Folder Link(s): CDCE62002

f − Frequency − MHz

450

500

550

600

650

700

750

800

850

900

950

1000

0 200 400 600 800 1000 1200

LVPECL Output V oltage Swing − mV

G001

TA = 25°C

RL = 50 Ω to VCC − 2 V

VCC = 3.6 V

VCC = 3.3 V

VCC = 3 V

f − Frequency − MHz

650

700

750

800

850

900

950

1000

1050

1100

1150

1200

0 200 400 600 800 1000 1200

High-Performance LVPECL Output Voltage Swing − mV

G002

TA = 25°C

RL = 50 Ω to VCC − 2 V

VCC = 3.6 V

VCC = 3.3 V

VCC = 3 V

f − Frequency − MHz

225

250

275

300

325

350

375

400

425

450

475

500

0 100 200 300 400 500 600 700 800 900

LVDS Output V oltage Swing − mV

G003

TA = 25°C

RL = 100 Ω

VCC = 3.6 V

VCC = 3.3 V

VCC = 3 V

f − Frequency − MHz

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

50 100 150 200 250 300

LVCMOS Output V oltage Swing − V

G004

TA = 25°C

CL = 5 pF

VCC = 3.6 V

VCC = 3.3 V

VCC = 3 V

CDCE62002

SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

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HIGH-PERFORMANCE LVPECL

LVPECL OUTPUT VOLTAGE SWING OUTPUT VOLTAGE SWING

vs vs

FREQUENCY FREQUENCY

Figure 8. Figure 9.

LVDS OUTPUT VOLTAGE SWING LVCMOS OUTPUT VOLTAGE SWING

vs vs

FREQUENCY FREQUENCY

Figure 10. Figure 11.

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TIMING REQUIREMENTS

over recommended ranges of supply voltage, load and operating free-air temperature range (unless otherwise noted)

PARAMETER MIN TYP MAX UNIT

REF_IN REQUIREMENTS

fREF –Diff IN-DIV Maximum clock frequency applied to reference divider when (Register 0 Bit 9 = 1) 500 MHz

fREF –Diff REF_DIV Maximum clock frequency applied to reference divider when (Register 0 Bit 9 = 0) 250 MHz

fREF–Single For Single ended Inputs ( LVCMOS) on REF_IN 250 MHz

Duty Cycle Duty cycle of REF_IN 40% 60%

INTERNAL TIMING REQUIREMENTS

fSMUX Maximum clock frequency applied to Smart MUX input 250 MHz

fINDIV Maximum clock frequency applied to Input Divider 200 MHz

AUXILARY_IN REQUIREMENTS

fREF –Crystal AT-Cut Crystal Input 2 42 MHz

Drive Level 0.1 mW

Maximum shunt capacitance 7 pF

PD REQUIREMENTS

tr/ tfRise and fall time of the PD signal from 20% to 80% of VCC 4 ns

PHASE NOISE ANALYSIS

Table 2. Phase Noise for 30.72MHz External Reference

Phase Noise Specifications under following configuration: VCO = 1966.08 MHz, REF_IN = 30.72MHz,

PFD Frequency = 30.72MHz, Charge Pump Current = 1.5mA Loop BW = 400kHz at 3.3V and 25°C.

Reference LVPECL-HP LVPECL LVDS LVCMOS

PHASE NOISE AT UNIT

30.72MHz 491.52MHz 491.52MHz 491.52MHz 122.88MHz

10Hz –108 –84 –84 –85 –97 dBc/Hz

100Hz –130 –98 –98 –97 –111 dBc/Hz

1kHz –134 –106 –106 –106 –118 dBc/Hz

10kHz –152 –118 –118 –118 –130 dBc/Hz

100kHz –156 –121 –121 –121 –133 dBc/Hz

1MHz –157 –131 –131 –130 –142 dBc/Hz

10MHz — –146 –146 –145 –151 dBc/Hz

20MHz — –146 –146 –145 –151 dBc/Hz

Jitter(RMS) 195 319 316 332.2 372.1 fs

10k~20MHz (10k~1MHz)

Table 3. Phase Noise for 25MHz Crystal Reference

Phase Noise Specifications under following configuration: VCO = 2000.00 MHz, AUX_IN-REF = 25.00MHz,

PFD Frequency = 25.00MHz, Charge Pump Current = 1.5mA Loop BW = 400kHz 3.3V and 25°C.

LVPECL-HP LVDS LVCMOS

PHASE NOISE AT UNIT

500.00MHz 250.00MHz 125.00MHz

10Hz –72 –72 –79 dBc/Hz

100Hz –97 –97 –103 dBc/Hz

1kHz –111 –111 –118 dBc/Hz

10kHz –120 –120 –126 dBc/Hz

100kHz –124 –124 –130 dBc/Hz

1MHz –136 –136 –142 dBc/Hz

10MHz –147 –147 –151 dBc/Hz

20MHz –148 –148 –151 dBc/Hz

Jitter(RMS) 10k~20MHz 426 426 443 fs

Product Folder Link(s): CDCE62002

Device

Registers

Interface

Control

Smart

MUX Frequency

Synthesizer

Output

Channel 1

Output

Channel 0

EEPROM

Input

Block Synthesizer

Block

Output Blocks

Interface

Control

Block

CDCE62002

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OUTPUT TO OUTPUT ISOLATION

Table 4. Output to Output Isolation

WORST SPUR UNIT

The Output to Output Isolation was tested at 3.3V supply and 25°C ambient temperature (Default Configuration):

Output 1 Measured Channel In LVDS Signaling at 125MHz –70 dB

Output 0 Aggressor Channel LVPECL 156.25MHz

DEVICE CONFIGURATION

The Functional Description Section described four different functional blocks contained within the CDCE62002.

Figure 12 depicts these blocks along with a high-level functional block diagram of the circuit elements comprising

each block. The balance of this section focuses on a detailed discussion of each functional block from the

perspective of how to configure them.

Figure 12. CDCE62002 Circuit Blocks

Product Folder Link(s): CDCE62002

SPI_CLK

SPI_MOSI

SPI_LE

SPI_MISO

SPI_LE

SPI_CLK

SPI_MOSI

SPI_MISO

SPI_CLK

SPI_MOSI

SPI_MISO

SPI_LE

SPI_CLK

SPI_MOSI

SPI_MISO

SPI_LE

SPI Master

SPI Slave

CDCE62002

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INTERFACE AND CONTROL BLOCK

The Interface and Control Block includes a SPI interface, one control pin, a non-volatile memory array in which

the device stores default configuration data, and an array of device registers implemented in Static RAM. This

RAM, also called the device registers, configures all hardware within the CDCE62002.

SPI (Serial Peripheral Interface)

The serial interface of CDCE62002 is a simple bidirectional SPI interface for writing and reading to and from the

device registers. It implements a low speed serial communications link in a master/slave topology in which the

CDCE62002 is a slave. The SPI consists of four signals:

•SPI_CLK:Serial Clock (Output from Master) –the CDCE62002 and the master host clock data in and out on

the rising edge of SPI_CLK. Data transitions therefore occur on the falling edge of the clock. (LVCMOS Input

Buffer)

•SPI_MOSI: Master Output Slave Input (LVCMOS Input Buffer).

•SPI_MISO: Master Input Slave Output (Open Drain LVCMOS Buffer)

•SPI_LE: Latch Enable (Output from Master). The falling edge of SPI_LE initiates a transfer. If SPI_LE is high,

no data transfer can take place. (LVCMOS Input Buffer).

SPI Interface Master

The Interface master can be designed using a FPGA or a micro controller. The CDCE62002 acts as a slave to

the SPI master and only supports nonconsecutive read and write command. The SPI clock should start and stop

with respect to the SPI_LE signal as shown in Figure 13 SPI_MOSI, SPI_CLK and SPI_LE are generated by the

SPI Master. SPI_MISO is generated by the SPI slave the CDCE62002.

Figure 13. CDCE62002 SPI Read/Write Command

SPI Consecutive Read/Write Cycles to the CDCE62002

Figure 14 Illustrates how two consecutive SPI cycles are performed between a SPI Master and the CDCE62002

SPI Slave.

Figure 14. Consecutive Read/Write Cycles

Product Folder Link(s): CDCE62002

Bit 0Bit1Bit 29 Bit 30 Bit31

SPI _MOSI

SPI _CLK

SPI _LE

SPI _CLK

SPI _MOSI

SPI _MISO

SPI _LE

Bit30 Bit31

Bit0 Bit1

CDCE62002

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Writing to the CDCE62002

Figure 15 illustrates a Write to RAM operation. Notice that the latching of the first data bit in the data stream (Bit

0) occurs on the first rising edge of SPI_CLK after SPI_LE transitions from a high to a low. For the CDCE62002,

data transitions occur on the falling edge of SPI_CLK. A rising edge on SPI_LE signals to the CDCE62002 that

the transmission of the last bit in the stream (Bit 31) has occurred.

Figure 15. CDCE62002 SPI Write Operation

Reading from the CDCE62002

Figure 16 shows how the CDCE62002 executes a Read Command. The SPI master first issues a Read

Command to initiate a data transfer from the CDCE62002 back to the host (see Table 5). This command

specifies the address of the register of interest. By transitioning SPI_LE from a low to a high, the CDCE62002

resolves the address specified in the appropriate bits of the data field. The host drives SPI_LE low and the

CDCE62002 presents the data present in the register specified in the Read Command on SPI_MISO.

Figure 16. CDCE62002 SPI Read Operation

Writing to EEPROM

After the CDCE62002 detects a power-up and completes a reset cycle, the device copies the contents of the

on-chip EEPROM into the Device Registers. (SPI_LE signal has to be HIGH in order for the EEPROM to load

correctly during the rising edge of Power_Down signal).

The host issues a special commands shown in Figure 17 to copy the contents of Device Registers 0 and 1into

EERPOM.

•Copy RAM to EEPROM –Unlock, Execution of this command can happen many times.

After the command is initiated, power must remain stable and the host must not access the CDCE62002 for at

least 50 ms to allow the EEPROM to complete the write cycle and to avoid the possibility of EEPROM corruption.

CDCE62002 SPI Command Structure

The CDCE62002 supports three commands issued by the Master via the SPI:

•Write to RAM

•Read Command

•Copy RAM to EEPROM –unlock

Figure 17 provides a summary of the CDCE62002 SPI command structure. The host (master) constructs a Write

to RAM command by specifying the appropriate register address in the address field and appends this value to

the beginning of the data field. Therefore, a valid command stream must include 32 bits, transmitted LSB first.

The host must issue a Read Command to initiate a data transfer from the CDCE62002 back to the host. This

command specifies the address of the register of interest in the data field.

Product Folder Link(s): CDCE62002

Bit0 Bit1 Bit30 Bit31

SPI_CLK

Bit29

SPI_MOSI

SPI_LE

t4t5

t2t3

Bit30 Bit31

Bit0 = 0 Bit1 Bit2

t4t5

SPI_CLK

SPI_MOSI

SPI_LE

SPI_MOSO

CDCE62002

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NOTE: ‘A’indicates address bits.

Figure 17. CDCE62002 SPI Command Structure

SPI CONTROL INTERFACE TIMING

Figure 18. Timing Diagram for SPI Write Command

Figure 19. Timing Diagram for SPI Read Command

Table 5. SPI Bus Timing Characteristics

Parameter MIN TYP MAX UNIT

fClock Clock Frequency for the SPI_CLK 20 MHz

t1SPI_LE to SPI_CLK setup time 10 ns

t2SPI_MOSI to SPI_CLK setup time 10 ns

t3SPI_MOSI to SPI_CLK hold time 10 ns

t4SPI_CLK high duration 25 ns

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Table 5. SPI Bus Timing Characteristics (continued)

Parameter MIN TYP MAX UNIT

t5SPI_CLK low duration 25 ns

t6SPI_CLK to SPI_LE Hold time 10 ns

t7SPI_LE Pulse Width 20 ns

t8SPI_CLK to MISO data valid 10 ns

t9SPI_LE to SPI_MISO Data Valid 10 ns

Device Registers: Register 0 address 0x00

Table 6. CDCE62002 Register 0 Bit Definitions

BIT NAME BLOCK

0 INBUFSELX INBUFSELX Input Buffer Select (LVPECL,LVDS or LVCMOS) EEPROM

XY(00 ) Disabled, (01) LVPECL, (10) LVDS, (11) LVCMOS

1 INBUFSELY INBUFSELY EEPROM

The VBB internal Biasing will be determined from this setting

2 REFSEL See specific section for more detailed description and configuration EEPROM

setup.

00 –RESERVED

Smart MUX

Bits(2,3) 10 –REF_IN Select

3 AUXSEL EEPROM

01–AUX_IN Select

11 –Auto Select ( Reference then AUX)

4 ACDCSEL Input Buffers If Set to “1”DC Termination, If set to “0”AC Termination EEPROM

5 TERMSEL Input Buffers If Set to “0”Input Buffer Internal Termination Enabled EEPROM

6 REFDIVIDE 0 EEPROM

Reference Divider Settings ( Refer to Table 11)

7 REFDIVIDE 1 EEPROM

See specific section for more detailed description and configuration

8 REFDIVIDE 2 EEPROM

setup.

9 REFDIVIDE 3 EEPROM

10 RESERVED Always Set to "0" EEPROM

11 I70TEST TEST Set to “0”for Normal Operation. EEPROM

12 ATETEST TEST Set to “0”for Normal Operation. EEPROM

13 LOCKW(0) PLL Lock Lock-detect window Bit 0 EEPROM

14 LOCKW(1) PLL Lock Lock-detect window Bit 1 EEPROM

15 OUT0DIVRSEL0 Output 0 EEPROM

Output 0 Divider Settings (Refer to Table 12)

16 OUT0DIVRSEL1 Output 0 EEPROM

See specific section for more detailed description and configuration

17 OUT0DIVRSEL2 Output 0 EEPROM

setup.

18 OUT0DIVRSEL3 Output 0 EEPROM

19 OUT1DIVRSEL0 Output 1 EEPROM

Output 1 Divider Settings (Refer to Table 12)

20 OUT1DIVRSEL1 Output 1 EEPROM

See specific section for more detailed description and configuration

21 OUT1DIVRSEL2 Output 1 EEPROM

setup.

22 OUT1DIVRSEL3 Output 1 EEPROM

High Performance, If this Bit is set to “1”:

–Increases the Bias in the device to achieve Best Phase Noise on the

Output Divider

–It changes the LVPECL Buffer to Hi Swing in LVPECL.

23 HIPERORMANCE Output 0 &1 EEPROM

–It increases the current consumption by 20mA (Typical)

–This setting only applies to LVPECL output buffers. If none of these

two outputs are LVPECL, this bit should be set to zero.

24 OUTBUFSEL0X Output 0 EEPROM

Output Buffer mode select for OUTPUT “0”.

(X,Y)=00:Disabled, 01:LVCMOS, 10:LVDS, 11:LVPECL

25 OUTBUFSEL0Y Output 0 EEPROM

26 OUTBUFSEL1X Output 1 EEPROM

Output Buffer mode select for OUTPUT “1”.

(X,Y)=00:Disabled, 01:LVCMOS, 10:LVDS, 11:LVPECL

27 OUTBUFSEL1Y Output 1 EEPROM

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Table 7. Reference Input AC/DC Input Termination Table

REFERENCE INPUT VBB VOLTAGE

BITS TERMINATION TERMINATION

INTERNAL TERMINATION 0 1 4 5 GENERATOR 5kΩto VBB 5kΩto VBB

External Termination X X X 1 —OPEN OPEN

Disabled 0 0 X X —OPEN OPEN

LVCMOS 1 1 X 0 —OPEN OPEN

LVPECL-AC 0 1 0 0 1.9V CLOSED CLOSED

LVPECL-DC 0 1 1 0 1.0V CLOSED CLOSED

LVDS-AC 1 0 0 0 1.2V CLOSED CLOSED

LVDS-DC 1 0 1 0 1.2V CLOSED CLOSED

Device Registers: Register 1 address 0x01

Table 8. CDCE62002 Register 1 Bit Definitions

BIT NAME DESCRIPTION / FUNCTION

BIT BLOCK

0 SELVCO VCO Core VCO Select –See Table 16 for details EEPROM

1 SELINDIV0 VCO Core EEPROM

2 SELINDIV1 VCO Core EEPROM

3 SELINDIV2 VCO Core EEPROM

4 SELINDIV3 VCO Core EEPROM

Input Divider Settings (Refer to Table 13)

See specific section for more detailed description and configuration setup.

5 SELINDIV4 VCO Core EEPROM

6 SELINDIV5 VCO Core EEPROM

7 SELINDIV6 VCO Core EEPROM

8 SELINDIV7 VCO Core EEPROM

9 SELPRESCA VCO Core EEPROM

PRESCALER Setting. (Refer to Table 17)

See specific section for more detailed description and configuration setup.

10 SELPRESCB VCO Core EEPROM

11 SELFBDIV0 VCO Core EEPROM

12 SELFBDIV1 VCO Core EEPROM

13 SELFBDIV2 VCO Core EEPROM

14 SELFBDIV3 VCO Core EEPROM

FEEDBACK DIVIDER Setting (Refer to Table 14)

See specific section for more detailed description and configuration setup.

15 SELFBDIV4 VCO Core EEPROM

16 SELFBDIV5 VCO Core EEPROM

17 SELFBDIV6 VCO Core EEPROM

18 SELFBDIV7 VCO Core EEPROM

19 SELBPDIV0 VCO Core EEPROM

BYPASS DIVIDER Setting (Refer to Table 15)See specific section for more

20 SELBPDIV1 VCO Core EEPROM

detailed description and configuration setup.

21 SELBPDIV2 VCO Core EEPROM

22 LFRCSEL0 VCO Core EEPROM

23 LFRCSEL1 VCO Core EEPROM

Loop Filter &Charge Pump Control Setting (Refer to Table 18)

See specific section for more detailed description and configuration setup.

24 LFRCSEL2 VCO Core EEPROM

25 LFRCSEL3 VCO Core EEPROM

26 RESERVED Status TI Use Only; set '0' EEPROM

27 RESERVED Status Read Only; May read back to 1 or 0; set '1' while writing EEPROM

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Device Registers: Register 2 address 0x02

Table 9. CDCE62002 Register 2 Bit Definitions

BIT NAME DESCRIPTION / FUNCTION

BIT BLOCK

0 RESERVED Diagnostics TI Test Registers. For TI Use Only RAM

1 RESERVED Diagnostics TI Test Registers. For TI Use Only RAM

2 RESERVED Diagnostics TI Test Registers. For TI Use Only RAM

3 RESERVED Diagnostics TI Test Registers. For TI Use Only RAM

4 RESERVED Diagnostics TI Test Registers. For TI Use Only RAM

5 RESERVED Diagnostics TI Test Registers. For TI Use Only RAM

6 PLLLOCKPIN Status Read Only: Status of the PLL Lock Pin Driven by the device. PLL Lock = 1 RAM

Power Down mode “On”when set to “0”, Off when set to “1”is normal

7 PD Control RAM

operation (PD bit does not load the EEPROM into RAM when set to "1").

8 SYNC Control If toggled “1-0-1”this bit forces “SYNC“resynchronize the Output Dividers. RAM

9 RESERVED Diagnostics TI Test Registers. For TI Use Only RAM

10 VERSION0 Read Only RAM

11 VERSION1 Read Only RAM

12 VERSION2 Read Only RAM

This bit selects the VCO calibration mode. If CALSELECT = '0' , toggling PD#

bit (Register 2 bit 7) will calibrate the VCO. When CALSELECT = '1' ,

13 CALSELECT VCO Core RAM

toggling the PLLRESET bit (Register 2 bit 20) will calibrate the VCO.

Default value = '0'

14 RESERVED Diagnostics TI Test Registers. For TI Use Only RAM

15 RESERVED Diagnostics TI Test Registers. For TI Use Only RAM

16 RESERVED Diagnostics TI Test Registers. For TI Use Only RAM

17 RESERVED Diagnostics TI Test Registers. For TI Use Only RAM

18 RESERVED Diagnostics TI Test Registers. For TI Use Only RAM

19 RESERVED Diagnostics TI Test Registers. For TI Use Only RAM

When CALSELECT='1' this bit forces a VCO calibration when toggled

20 PLLRESET Diagnostics RAM

"1-0-1". If CALSELECT='0' this bit is ignored.

21 TITSTCFG0 Diagnostics TI Test Registers. For TI Use Only RAM

22 TITSTCFG1 Diagnostics TI Test Registers. For TI Use Only RAM

23 TITSTCFG2 Diagnostics TI Test Registers. For TI Use Only RAM

24 TITSTCFG3 Diagnostics TI Test Registers. For TI Use Only RAM

25 RESERVED Diagnostics TI Test Registers. For TI Use Only RAM

26 RESERVED Diagnostics TI Test Registers. For TI Use Only RAM

27 RESERVED Diagnostics TI Test Registers. For TI Use Only RAM

Product Folder Link(s): CDCE62002

Device

OFF

Active Mode

Power ON

Reset

Power Down Sync

VCO

CAL

Power

Applied

Delay

Finished

CAL Done

Power Down = ON

Power Down = OFF

Sync = ON

Sync = OFF

Power Down = ON

PLLRESET= ON

CDCE62002

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SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

Device Control

Figure 20 provides a conceptual explanation of the CDCE62002 Device operation. Table 10 defines how the

device behaves in each of the operational states.

Figure 20. CDCE62002 Device State Control Diagram

Table 10. CDCE62002 Device State Definitions

Output Output

SPI Port PLL

State Device Behavior Entered Via Exited Via Divider Buffer

Status Status Status Status

After device power supply reaches

approximately 2.35V, the contents of Power applied to the device or Power On Reset and EEPROM

Power-On EEPROM are copied into the Device upon exit from Power Down State loading delays are finished OR the OFF Disabled Disabled OFF

Reset Registers, thereby initializing the device via the PD pin set HIGH. PD pin is set LOW.

hardware .

The voltage controlled oscillator is

calibrated based on the PLL settings Delay process in the Power-On

VCO CAL and the incoming reference clock. After Reset State is finished or Calibration Process in completed ON Enabled Disabled OFF

the VCO has been calibrated, the device PLLRESET=ON

enters Active Mode automatically.

CAL Done (VCO calibration Disabled Disabled or

Active Mode Normal Operation process finished) or Sync = OFF Power Down or PLLRESET=ON ON Enabled or Enabled

(from Sync State). Enabled

Used to shut down all hardware and

Resets the device after exiting the

Power Down State. Therefore, the

Power Down PD pin is pulled LOW. PD pin is pulled HIGH. ON Disabled Disabled Disabled

EEPROM contents will eventually be

copied into RAM after the Power Down

State is exited.

Sync synchronizes both outputs dividers Sync Bit in device register 2 bit 8 Sync bit in device register 2 bit 8 is

Sync so that they begin counting at the same ON Enabled Disabled Disabled

is set LOW set HIGH

time

Product Folder Link(s): CDCE62002

XTAL

25Mhz

U0P

U0N

U1P

U1N

LVPECL

156.25Mhz

LVDS

125Mhz

AUTO

25Mhz

CDCE62002

Default Programing

72A000E0

8389A061

EEPROM

25 MHz

(LVPECL AC coupled)

25 MHz

156.25 MHz

125 MHz

CDCE62002

SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

www.ti.com

External Control Pins

Power Down (PD)

When pulled LOW, PD activates the Power Down state which shuts down all hardware and resets the device.

Restoring PD high will cause the CDCE62002 to exit the Power Down State. This causes the device to behave

as if it has been powered up including copying the EEPROM contents into RAM. PD pin also has a shadowed

PD bit residing in Register 2 Bit 7. When asserted Low it puts the device in Power Down Mode, but it does not

load the EEPROM when the bits is disserted.

NOTE

The SPI_LE signal has to be high in order for the EEPROM to load correctly into RAM on

the Rising edge of PD Pin.

FACTORY DEFAULT PROGRAMMING

The CDCE62002 is factory pre-programmed to work with 25 MHz input from the reference input or from the

auxiliary input with auto switching enabled. An internal PFD of 6.25 MHz and about 400 KHz loop bandwidth.

Output 0 is pre-programmed as an LVPECL driver to output 156.25 MHz and output 1 is pre-programmed as

LVDS driver to output 125 MHz.

Figure 21. CDCE62002 Default Factory Programming

Product Folder Link(s): CDCE62002

ReferenceDivider

/1 - /8

REF_IN

XTAL /

AUX_IN

LVPECL : 500 MHz

LVDS: 500 MHz

LVCMOS : 250 MHz

Crystal : 2 MHz – 42 MHz

Smart

MUX

SmartMUX

Control

2 3

8 7 6

UniversalInputBuffers

SmartMultiplexer

AuxiliaryInput

Pre-Divider

/1 or /2

CDCE62002

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SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

INPUT BLOCK

The Input Block includes one Universal Input Buffers, an Auxiliary Input, and a Smart Multiplexer.

Figure 22. CDCE62002 Input Block With References to Registers

The CDCE62002 provides a Reference Divider that divides the clock exiting Reference (REF_IN) input buffer.

Table 11. CDCE62002 Reference Divider Settings

REFERENCE DIVIDER TOTAL

DIVIDE

BIT NAME →REFDIVIDE3 REFDIVIDE2 REFDIVIDE1 REFDIVIDE0 RATIO

0 0 0 0 /1

0 0 0 1 /2

0 0 1 0 /3

0 0 1 1 /4

0 1 0 0 /5

0 1 0 1 /6

0 1 1 0 /7

0 1 1 1 /8

1 0 0 0 /2

1 0 0 1 /4

1 0 1 0 /6

1 0 1 1 /8

1 1 0 0 /10

1 1 0 1 /12

1 1 1 0 /14

1 1 1 1 /16

Product Folder Link(s): CDCE62002

Universal Input Control

PN PP

0 1 4

REF_IN

1uF

5k 5k

TERMSEL INBUFSELY INBUFSELX ACDCSEL P N VBB Input buffer Mode

0 1.9V LVPECL – AC coupled

1 0 1 1.2V note (1)

0 1.2V LVDS – AC coupled

0 1 1

ON ON

1.2V LVDS – DC coupled

1 1 X --- LVCMOS

1 X X X OFF OFF --- Input Buffer Termination Disabled

note (1): This setting is not recommended.

ReferenceDivider

/1 - /8

REF_IN

XTAL /

AUX_IN

Smart

MUX

SmartMUX

Control

2 3

876

SmartMultiplexer

Pre-Divider

/1 or /2

REFSEL AUXSEL

0.2 0.3

AUXSelect

0 0 Reserved

1 0 REFSelect

0 1

AutoSelect

1 1

Setting SmartMux

Mode

CDCE62002

SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

www.ti.com

Reference Input Buffer

Figure 23 shows the key elements of a Universal Input Buffer (UIB). A UIB supports multiple formats along with

different termination and coupling schemes. The CDCE62002 implements the UIB by including on board

switched termination, a programmable bias voltage generator, and a multiplexer. The CDCE62002 provides a

high degree of configurability on the UIB to facilitate most existing clock input formats. REF_IN only provides

biasing internally. It is recommended to terminate externally if needed.

Figure 23. CDCE62002 Universal Input Buffer

Smart Multiplexer Dividers

Figure 24. CDCE62002 Smart Multiplexer

In Auto Select Mode the Smart Mux switches automatically between Reference input and Auxiliary input with a

preference to the Reference input. In order for the Smart Mux to function correctly the frequency after the

reference divider and the Auxiliary Input signal frequency should be within 20% of each other or one of them

should be zero or ground. In REF Select mode, it is recommended to connect AUX_IN to GND with a 1k

pull-down resistor. In AUX Select mode it is recommended to pull REF_INp high and REF_INn low with a 1k

resistor each.

Product Folder Link(s): CDCE62002

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Auxiliary Input Port

The auxiliary input on the CDCE62002 is designed to connect to an AT-Cut Crystal with a total load capacitance

of 8 pF to 10pF. One side of the crystal connects to Ground while the other side connects to the Auxiliary input of

the device. The circuit accepts crystals from 2 to 42 MHz. See the Crystal Input Interface section for crystal load

selection.

Figure 25. CDCE62002 Auxiliary Input Port

Product Folder Link(s): CDCE62002

ClockDividerModule 1

UxP

UxN

SYNTH

Sync

Pulse Enable

LVDS

ClockDividerModule 0

LVPECL

OutputBufferControl

Registers 0

18171615

Registers 0

22212019

OUTPUT 0 OUTPUT 1

CDCE62002

SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

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OUTPUT BLOCK

The output block includes two identical output channels. Each output channel comprises of a clock divider

module, and a universal output buffer as shown in Figure 26.

Figure 26. CDCE62002 Output Channel

Table 12. CDCE62002 Output Divider Settings

OUTPUT DIVIDERS SETTING

DIVIDER 0 →0.18 0.17 0.16 0.15 DIVIDE RATIO

DIVIDER 1 →0.22 0.21 0.20 0.19

0 0 0 0 Disabled

0 0 0 1 /1

0 0 1 0 /2

0 0 1 1 /3

0 1 0 0 /4

0 1 0 1 /5

0 1 1 0 /6

0 1 1 1 Disabled

1 0 0 0 /8

1 0 0 1 Disabled

1 0 1 0 /10

1 0 1 1 /20

1 1 0 0 /12

1 1 0 1 /24

1 1 1 0 /16

1 1 1 1 /32

Product Folder Link(s): CDCE62002

PFD/

Prescaler

/2,/3,/4,/5

Input Divider

/1 - /256

SMART _MUX

SYNTH

/1,/2,/5,/8,/10,/16,/20

/8 - /1280

Feedback Divider

1.75 GHz –

2.356 GHz

22232425

Loop Filter and Charge Pump

Current Settings

2345678

Input Divider Settings

Prescaler

12131415161718

Feedback Divider

192021

Feedback Bypass Divider

VCO Select

CDCE62002

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SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

SYNTHESIZER BLOCK

Figure 27 provides an overview of the CDCE62002 synthesizer block. The Synthesizer Block provides a Phase

Locked Loop, a partially integrated programmable loop filter, and two Voltage Controlled Oscillators (VCO). The

synthesizer block generates an output clock called “SYNTH”and drives it onto the Internal Clock Distribution

Bus.

Figure 27. CDCE62002 Synthesizer Block

Input Divider

The Input Divider divides the clock signal selected by the Smart Multiplexer and presents the divided signal to

the Phase Frequency Detector / Charge Pump of the frequency synthesizer.

Table 13. CDCE62002 Input Divider Settings

INPUT DIVIDER SETTINGS DIVIDE

SELINDIV7 SELINDIV6 SELINDIV5 SELINDIV4 SELINDIV3 SELINDIV2 SELINDIV1 SELINDIV0 RATIO

1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1

000000001

000000012

000000103

000000114

000001005

000001016

–––––––––

11111111256

Product Folder Link(s): CDCE62002

CDCE62002

SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

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Feedback and Feedback Bypass Divider

Table 14 shows how to configure the Feedback divider for various divide values:

Table 14. CDCE62002 Feedback Divider Settings

FEEDBACK DIVIDER DIVIDE

SELFBDIV7 SELFBDIV6 SELFBDIV5 SELFBDIV4 SELFBDIV3 SELFBDIV2 SELFBDIV1 SELFBDIV0 RATIO

1.18 1.17 1.16 1.15 1.14 1.13 1.12 1.11

000000008

0000000112

0000001016

0000001120

0000010124

0000011032

0000100136

0000011140

0000101048

0001100056

0000101160

0000111064

0001010172

0000111180

0001100184

0001011096

00010011100

01001001108

00011010112

00010111120

00011110128

00011011140

00110101144

00011111160

00111001168

01001011180

00110110192

00110011200

01010101216

00111010224

00110111240

01011001252

00111110256

00111011280

01010110288

01010011300

00111111320

01011010336

01010111360

01011110384

11011000392

01110011400

Product Folder Link(s): CDCE62002

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SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

Table 14. CDCE62002 Feedback Divider Settings (continued)

FEEDBACK DIVIDER DIVIDE

SELFBDIV7 SELFBDIV6 SELFBDIV5 SELFBDIV4 SELFBDIV3 SELFBDIV2 SELFBDIV1 SELFBDIV0 RATIO

1.18 1.17 1.16 1.15 1.14 1.13 1.12 1.11

01011011420

10110101432

01111010448

01011111480

10010011500

10111001504

01111110512

01111011560

10110110576

11011001588

10010111600

01111111640

10111010672

10011011700

10110111720

10111110768

11011010784

10011111800

10111011840

11011110896

10111111960

11011011980

111111101024

110111111120

111111111280

Table 15 shows how to configure the Feedback Bypass Divider.

Product Folder Link(s): CDCE62002

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Table 15. CDCE62002 Feedback Bypass Divider Settings

FEEDBACK BYPASS DIVIDER

SELBPDIV2 SELBPDIV1 SELBPDIV0 DIVIDE RATIO

1.21 1.20 1.19

0002

0015

0108

0 1 1 10

1 0 0 16

1 0 1 20

1 1 0 RESERVED

1 1 1 1(bypass)

VCO Select

Table 16 illustrates how to control the dual voltage controlled oscillators.

Table 16. CDCE62002 VCO Select

VCO SELECT VCO CHARACTERISTICS

BIT NAME →SELVCO

0 Low 1750 2046

1 High 2040 2356

Prescaler

Table 17 shows how to configure the prescaler.

Table 17. CDCE62002 Prescaler Settings

SETTINGS

SELPRESCB SELPRESCA DIVIDE RATIO

1.10 1.9

005

104

013

112

Product Folder Link(s): CDCE62002

PFD/

EXT_LFNEXT_LFP

externalinternal externalinternal

R2 C2

Registers 0

2325 22

CDCE62002

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SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

Loop Filter

Figure 28 depicts the loop filter topology of the CDCE62002. It facilitates both internal and external

implementations providing optimal flexibility.

Figure 28. CDCE62002 Loop Filter Topology

Internal Loop Filter Component Configuration

Figure 28 illustrates the switching between four fixed internal loop filter settings and the external loop filter

setting. Table 18 shows that the CDCE62002 has 16 settings different settings for the loop filter. Four of the

settings are internal and twelve are external.

Table 18. CDCE62002 Loop Filter Settings

Charge

LFRCSEL Pump

3 2 1 0 Loop Filter C1 C2 R2 R3 C3 Current

0 0 0 0 Internal 1.5 pF 473.5 pF 4.0k 5k 2.5 pF 1.5 mA

0 0 0 1 Internal 1.5 pF 473.5 pF 4.0k 5k 2.5 pF 400 μA

0 0 1 0 Internal 1.5 pF 473.5 pF 2.7k 5k 2.5 pF 250 μA

0 0 1 1 Internal 1.5 pF 473.5 pF 2.7k 5k 2.5 pF 150 μA

0 1 0 0 External X X X 20k 112 pF 1.0 mA

0 1 0 1 External X X X 20k 112 pF 2.0 mA

0 1 1 0 External X X X 20k 112 pF 3.0 mA

0 1 1 1 External X X X 20k 112 pF 3.75 mA

1 0 0 0 External X X X 10k 100 pF 1.0 mA

1 0 0 1 External X X X 10k 100 pF 2.0 mA

1 0 1 0 External X X X 10k 100 pF 3.0 mA

1 0 1 1 External X X X 10k 100 pF 3.75 mA

1 1 0 0 External X X X 5k 100 pF 1.0 mA

1 1 0 1 External X X X 5k 64 pF 2.0 mA

1 1 1 0 External X X X 5k 48 pF 3.0 mA

1 1 1 1 External X X X 5k 38 pF 3.75 mA

Product Folder Link(s): CDCE62002

PFD/

FromInputDivider

FromFeedbackDivider

ToLoopFilter

FromInputDivider

FromFeedbackDivider

Locked

Unlocked

FromInputDivider

FromFeedbackDivider

LockDetectWindow (Max)

LockDetectWindow Adjust

(a) (b)

13 14

FromLockDetector PLL_LOCK

1 = Locked

O = Unlocked

(c)

CDCE62002

SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

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Lock Detect

The CDCE62002 provides a lock detect indicator circuit that can be detected on an external Pin PLL_LOCK (Pin

32) and internally by reading PLLLOCKPIN bit (6) in Register 2.

Two signals whose phase difference is less than a prescribed amount are ‘locked’otherwise they are ‘unlocked’.

The phase frequency detector / charge pump compares the clock provided by the input divider and the feedback

divider; using the input divider as the phase reference. The lock detect circuit implements a programmable lock

detect window. Table 19 shows an overview of how to configure the lock detect feature. The PLL_LOCK pin will

possibly jitter several times between lock and out of lock until the PLL achieves a stable lock. If desired, choosing

a wide loop bandwidth and a high number of successive clock cycles virtually eliminates this characteristic.

PLL_LOCK will return to out of lock, if just one cycle is outside the lock detect window or if a cycle slip occurs.

Figure 29. CDCE62002 Lock Detect

Table 19. CDCE62002 Lock Detect Control

LOCK DETECT LOCK DETECT

BIT NAME →LOCKW(1) LOCKW(0) WINDOW

0 0 2.1 ns

0 1 4.6 ns

1 0 7.2 ns

1 1 19.9 ns

VCO Calibration

The CDCE62002 includes two on-chip LC oscillator-based VCOs with low phase noise covering a frequency

range of 1.75 GHz to 2.356 GHz. The VCO must be calibrated to ensure proper operation over the valid device

operating conditions. VCO calibration is controlled by the reference clock input. This calibration requires that the

PLL be set up properly to lock the PLL loop and that the reference clock input be present.

The device enters self-calibration of the VCO automatically at power up, after the registers have been loaded

from the EEPROM and an input clock signal is detected. If there is no input clock available during power up, the

VCO will wait for reference clock before starting calibration.

If the input signal is not valid during self-calibration, it is necessary to re-initiate VCO calibration after the input

clock signal stabilizes. IMPORTANT NOTE: Re-calibration is also necessary anytime a PLL setting is changed

(e.g. divider ratios in the PLL or loop filter settings are adjusted).

VCO calibration can be initiated by writing to register 2 bits 7, 13 and 20.

Product Folder Link(s): CDCE62002

( ) ( )

D-

+ +

S S

L,R O L,A O

C Cf =

f2 C C 2 C C

CDCE62002

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SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

Table 20. VCO Calibration Method Through Register Programming

CALSELECT PLLRESET PD VCO CALIBRATION MECHANISM(1)

Reg 2.13 2.20 2.7

VCO calibration starts at PLLRESET toggling low-to-high. The outputs turn off for the duration of

1 1-0-1 1 the calibration, which is a few ns.

Device is powered down when PD is toggle 1-to-0. All outputs are disabled while PD is zero. After

0 X 1-0-1 asserting PD from zero to one the VCO becomes calibrated and immediately afterwards the

device outputs turn on.

(1) A VCO calibration is also initiated if the external PD pin is toggle high-low-high. In this case all EEPROM registers become reloaded into

the device and the CALSELECT bit is reset to 0.

Crystal Input Interface

Fundamental mode is the recommended oscillation mode of operation for the input crystal and parallel

resonance is the recommended type of circuit for the crystal.

A crystal load capacitance refers to all capacitances in the oscillator feedback loop. It is equal to the amount of

capacitance seen between the terminals of the crystal in the circuit. For parallel resonant mode circuits, the

correct load capacitance is necessary to ensure the oscillation of the crystal within the expected parameters.

The CDCE62002 implements an input crystal oscillator circuitry, known as the Colpitts oscillator, and requires

one pad of the crystal to interface with the AUX_IN pin; the other pad of the crystal is tied to ground. In this

crystal interface, it is important to account for all sources of capacitance when calculating the correct value for

the discrete capacitor component, CL, for a design.

The CDCE62002 has been characterized with 10-pF parallel resonant crystals. The input crystal oscillator stage

in the CDCE62002 is designed to oscillate at the correct frequency for all parallel resonant crystals with low-pull

capability and rated with a load capacitance that is equal to the sum of the on-chip load capacitance at the

AUX_IN pin (10-pF), crystal stray capacitance, and board parasitic capacitance between the crystal and AUX_IN

pin.

The normalized frequency error of the crystal, as a result of load capacitance mismatch, can be calculated as

Equation 4:

(4)

Where:

CSis the motional capacitance of the crystal

C0is the shunt capacitance of the crystal

CL,R is the rated load capacitance for the crystal

CL,A is the actual load capacitance in the implemented PCB for the crystal

Δf is the frequency error of the crystal

f is the rated frequency of the crystal

The first three parameters can be obtained from the crystal vendor.

To minimize the frequency error of the crystal to meet application requirements, the difference between the rated

load capacitance and the actual load capacitance should be minimized and a crystal with low-pull capability (low

CS) should be used.

For example, if an application requires less than ±50 ppm frequency error and a crystal with less than ±50 ppm

frequency tolerance is picked, the characteristics are as follows: C0= 7 pF, CS= 10 pF, and CL,R = 12 pF. To

meet the required frequency error, calculate CL,A using Equation 4 to be 17 pF. Subtracting CL,R from CL,A,

results in 5 pF; care must be taken during printed circuit board (PCB) layout with the crystal and the CDCE62002

to ensure that the sum of the crystal stray capacitance and board parasitic capacitance is less than the

calculated 5 pF.

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Good layout practices are fundamental to the correct operation and reliability of the oscillator. It is critical to

locate the crystal components very close to the XIN pin to minimize routing distances. Long traces in the

oscillator circuit are a very common source of problems. Do not route other signals across the oscillator circuit.

Also, make sure power and high-frequency traces are routed as far away as possible to avoid crosstalk and

noise coupling. Avoid the use of vias; if the routing becomes very complex, it is better to use 0-Ωresistors as

bridges to go over other signals. Vias in the oscillator circuit should only be used for connections to the ground

plane. Do not share ground connections; instead, make a separate connection to ground for each component

that requires grounding. If possible, place multiple vias in parallel for each connection to the ground plane.

Especially in the Colpitts oscillator configuration, the oscillator is very sensitive to capacitance in parallel with the

crystal. Therefore, the layout must be designed to minimize stray capacitance across the crystal to less than 5 pF

total under all circumstances to ensure proper crystal oscillation. Be sure to take into account both PCB and

crystal stray capacitance.

Start-up Time Estimation

The CDCE62002 startup time can be estimated based on the parameters defined in Table 21 and graphically

shown in Figure 30.

Table 21. Start-up Time Dependencies

PARAMETER DEFINITION DESCRIPTION METHOD OF DETERMINATION

Power-supply rise time to low limit of Power On Time required for power supply to ramp to

tpul Power-up time (low limit) Reset (POR) trip point 2.27 V

Power-up time (high Power-supply rise time to high limit of Power On Time required for power supply to ramp to

tpuh limit) Reset (POR) trip point 2.64 V

After POR releases, the Colpitts oscillator is 500 µs best-case and 800 µs worst-case

enabled. This start-up time is required for the

trsu Reference start-up time (This is only for crystal connected to

oscillator to generate the requisite signal levels for AUX_IN)

the delay block to be clocked by the reference input tdelay = 16384 x tid

Internal delay time generated from the clock. This

tdelay Delay time tid = period of input clock to the input

delay provides time for the oscillator to stabilize. divider

VCO calibration time generated from the PFD clock. tVCO_CAL = 550 x tPFD

tVCO_CAL VCO calibration time This process selects the operating point for the tPFD = period of the PFD clock

VCO based on the PLL settings. tPLL_LOCK = 3/LBW

Time required for PLL to lock within ±10 ppm of

tPLL_LOCK PLL lock time reference frequency LBW = PLL Loop Bandwidth

Figure 30. Start-up Time dependencies

Product Folder Link(s): CDCE62002

No Solder Mask

Internal

Power

Plane

Component Side

Back Side

Solder Mask

Thermal Vias

QFN-32 Thermal Slug

(package bottom)

Thermal

Dissipation

Pad (back side)

Internal

Ground

Plane

Component & Back Side Component Side

Only

CDCE62002

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SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

Device Power Calculation and Thermal Management

The CDCE62002 is a high performance device; therefore careful attention must be paid to device configuration

and printed circuit board layout with respect to power consumption. Table 22 provides the power consumption for

the individual blocks within the CDCE62002. To estimate total power consumption, calculate the sum of the

products of the number of blocks used and the power dissipated of each corresponding block.

Table 22. CDCE62002 Power Consumption

INTERNAL BLOCK POWER DISSIPATED NUMBER OF BLOCKS

(Power at 3.3V) PER BLOCK (mW) PER DEVICE

Input Circuit 32 1

PLL and VCO Core 333 1

Output Divider 92 2

Output Buffer ( LVPECL) 150 2

Output Buffer (LVDS) 95 2

Output Buffer (LVCMOS) 62 4

This power estimate determines the degree of thermal management required for a specific design. Observing

good thermal layout practices enables the thermal pad on the backside of the QFN-32 package to provide a

good thermal path between the die contained within the package and the ambient air. This thermal pad also

serves as the ground connection the device; therefore, a low inductance connection to the ground plane is

essential.

Figure 31. CDCE62002 Recommended PCB Layout

CDCE62002 Power Supply Bypassing –Recommended Layout

Figure 32 shows a conceptual layout focusing on power supply bypass capacitor placement. If the capacitors are

mounted on the back side, 0402 components can be employed; however, soldering to the Thermal Dissipation

Pad can be difficult. If the capacitors are mounted on the component side, 0201 components must be used to

facilitate signal routing. In either case, the connections between the capacitor and the power supply terminal on

the device must be kept as short as possible.

Figure 32. CDCE62002 Power Supply Bypassing

Product Folder Link(s): CDCE62002

XTAL /

AUX_IN Output

Divider 0

U0P

U0N

PFD/

CP Prescaler

Feedback

Divider

Input

Divider

Smart

MUX

Output

Divider 1

U1P

U1N

SERDES

Cleaned Clock

Data

Recovered Clock

Output

Divider 0

U0P

U0N

Output

Divider 1

U1P

U1N

PFD/

CP Prescaler

Feedback

Divider

Input

Divider

Reference

Divider

REF_IN

XTAL /AUX_IN

EXT_LFP EXT _LFN

CDCE62002

SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

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APPLICATION INFORMATION AND GENERAL USAGE HINTS

Clock Generator

The CDCE62002 can generate 1 to 4 low noise clocks from a single crystal or crystal oscillator as follows:

Figure 33. CDCE62002 as a Clock Generator

SERDES Startup and Clock Cleaner

The CDCE62002 can serve as a SERDES device companion by providing a crystal based reference for the

SERDES device to lock to receive data stream and when the SERDES locks to the data and outputs the

recovered clock the CDCE62002 can switch and use the recovered clock and serve as a jitter cleaner.

Figure 34. CDCE62002 Clocking SERDES

Since the jitter of the recovered clock can be above 100 ps (RMS) the output jitter from CDCE62002 can be as

low and 6 ps (RMS) depending on the external loop filter configuration.

Product Folder Link(s): CDCE62002

jitter 10

in total

SNR 20log 2 jitter

é ù

=ê ú

ë û

( ) ( )

2 2

total ADC CLK

jitter jitter jitter= +

A D C

S N R 6 .0 2 N 1 .7 6= +

DataConverterJitterRequirements

100

110

120

130

140

1 10 100 1000 10000

InputBandwidth(MHz)

SNR(dB)

Resolution(bits)

1ps

350fs

100fs

50fs

CDCE62002

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CLOCKING ADCS WITH THE CDCE62002

High-speed analog to digital converters incorporate high input bandwidth on both the analog port and the sample

clock port. Often the input bandwidth far exceeds the sample rate of the converter. Engineers regularly

implement receiver chains that take advantage of the characteristics of bandpass sampling. This implementation

trend often causes engineers working in communications system design to encounter the term “clock limited

performance”. Therefore, it is important to understand the impact of clock jitter on ADC performance. The

following equation shows the relationship of data converter signal to noise ratio (SNR) to total jitter:

(5)

Total jitter comprises two components: the intrinsic aperture jitter of the converter and the jitter of the sample

clock:

(6)

With respect to an ADC with N-bits of resolution, ignoring total jitter, ADC quantization error, and input noise, the

following equation shows the relationship between resolution and SNR: (7)

Figure 35 plots Equation 5 and Equation 7 for constant values of total jitter. When used in conjunction with most

ADCs, the CDCE62002 supports a total jitter performance value of <1ps.

Figure 35. Data Converter Jitter Requirements

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REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (June, 2009) to Revision A Page

•Added NOTE: All VCC pins need to be connected for the device to operate properly. ....................................................... 3

•Added information to Pin 18 description - The input has an internal 150-kΩpull-up resist ................................................. 4

•Changed graphic input naming ............................................................................................................................................. 5

•Changed graphic input naming ............................................................................................................................................. 6

•Changed PLVPECL, PLVDS, PLVCMOS and POFF Unit values From: W To: mW .......................................................................... 9

•Deleted underscore before IN+ ............................................................................................................................................. 9

•Deleted 6 from 8006 ........................................................................................................................................................... 12

•Changed Y4 to Y1 .............................................................................................................................................................. 13

•Added tr/ tfMIN, TYP, and MAX values ............................................................................................................................. 13

•Added (Reg 0 RAM bit 9 = 0) to fREF –Diff REF_DIV ................................................................................................................. 15

•Changed REF into REF_IN ................................................................................................................................................ 15

•Changed part number error ................................................................................................................................................ 17

•Changed REFERENCE to REF_IN and AUXILARY to AUX_IN, Table 6 .......................................................................... 20

•Changed power to current .................................................................................................................................................. 20

•Changed the description of bits 0 - 5 To: TI Test Registers. For TI Use Only in Table 9 .................................................. 22

•Changed graphic ................................................................................................................................................................. 23

•Changed Table 10 .............................................................................................................................................................. 23

•Changed PDDRESET to PLLRESET, in Table 10 ............................................................................................................. 23

•Changed Power_Down to PD, in Table 10 ......................................................................................................................... 23

•Changed PRI_IN to REF_IN in Figure 22 ........................................................................................................................... 25

•Changed PRI_IN to REF_IN ............................................................................................................................................... 26

•Changed PRI_IN to REF_IN ............................................................................................................................................... 38

Changes from Revision A (July, 2009) to Revision B Page

•Deleted feature reference to "Single Ended Clock Source or Crystal."and "LVCMOS Input of up to 75MHz"................... 1

•Deleted references to single ended inputs and CMOS clock from description. ................................................................... 2

•Changed the description of Pin 2, AUX_IN .......................................................................................................................... 4

•Deleted references to EEPROM Locking from "Interface and Control Block"section ......................................................... 6

•Deleted "LVCMOS INPUT MODE (AUX_IN)"section from Electrical Characteristic ........................................................... 9

•Changed Crystal Shunt Capacitance to Crystal Load Capacitance with a MIN value of 8 .................................................. 9

•Deleted "LVCMOS INPUT MODE (AUX_IN)"section from Electrical Characteristic ......................................................... 10

•Deleted fREF –Single paramter from AUXILARY_IN_REQUIRMENTS ................................................................................... 15

•Changed EXTFEEDBACK to RESERVED for bit 10 in Table 6 ......................................................................................... 20

•Changed EELOCK to RESERVED for bit 30 in Table 8 ..................................................................................................... 21

•Changed Auxiliary Input Port section .................................................................................................................................. 27

•Deleted External Feed Back Mode section ........................................................................................................................ 27

•Deleted External Feedback Option section ........................................................................................................................ 38

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SCAS882D –JUNE 2009–REVISED FEBRUARY 2012

Changes from Revision B (February 2010) to Revision C Page

•Changed Pin Functions table, Pins 9, 12 to VCC_OUT0. Pins 13 and 16 to VCC_OUT1 .................................................. 3

•Changed pin 31 From: Power To: A. Power in Pin Functions table ..................................................................................... 3

•Changed Pin 7 to open drain in Pin Functions table ............................................................................................................ 3

•Changed Note1 of the Pin Functions table ........................................................................................................................... 3

•Changed the description of Pin 30, REF_IN-. ...................................................................................................................... 4

•Changed the description of Pin 19, TESTSYNC To: Reserved Pin.....resistor. ................................................................... 4

•Deleted Dividers and from ELEC CHARACTERISTICS table in row POFF ........................................................................... 9

•Changed Crytal input section first row From: Crystal Load Capacitance To: On-chip Load Capacitance ........................... 9

•Added SPI OUTPUT row From: PLL To: PLL_LOCK ......................................................................................................... 10

•Changed tr/ tfMax value From: 735 To: 135 ...................................................................................................................... 13

•Deleted (Reg 0 RAM bit 9 = 1) and (Reg 0 RAM bit 9 = 0) from the TIMING REQUIREMENTS table ............................. 15

•Added Driver Level and Max shunt capacitance to AUXILARY_IN REQUIREMENT in the TIMING REQUIREMENTS

table .................................................................................................................................................................................... 15

•Deleted Columns from Table 2: LVDS-HP and LVCMOS-HP ............................................................................................ 15

•Changed Table 3 ................................................................................................................................................................ 15

•Changed the OUTPUT TO OUTPUT ISOLATION section ................................................................................................. 16

•Deleted the SPI CONTROL INTERFACE TIMING section ................................................................................................ 16

•Changed figure Figure 12 ................................................................................................................................................... 16

•Changed the INTERFACE AND CONTROL BLOCK section ............................................................................................. 17

•Changed Table 7, RAM BITS To REGISTER BITS ........................................................................................................... 21

•Deleted the First four rows in Table 8 and the first column ................................................................................................ 21

•Deleted (6 settings+DisAble+Enable) in Register bit 19 of Table 8 ................................................................................... 21

•Added ; set '0'to TI use Only in bit 26 in Table 8 ............................................................................................................... 21

•Changed the description of bit 27 in Table 8 ...................................................................................................................... 21

•Deleted the First four rows in Table 9 and the first column ................................................................................................ 22

•Changed Figure 21 ............................................................................................................................................................. 24

•Changed the Reference Input Buffer section ..................................................................................................................... 26

•Changed Figure 23 ............................................................................................................................................................. 26

•Changed the Smart Multiplexer Dividers section ................................................................................................................ 26

•Changed Changed the text in the Smart Multiplexer Divider section ................................................................................. 26

•Changed Figure 27 ............................................................................................................................................................. 29

•Deleted column "3 db Corner C3R3"from Table 18 .......................................................................................................... 33

•Added sections: VCO Calibration, Crystal Input Interface, and Startup Time .................................................................... 34

•Changed Figure 34 ............................................................................................................................................................. 38

Changes from Revision C (March 2011) to Revision D Page

•Added a sentence below Equation 3 .................................................................................................................................... 8

•Added 3 rows in TIMING REQUIREMENTS table, under Duty Cycle row ......................................................................... 15

•Added a reference to Table 11 and 2 references to Table 12 in Table 6 ........................................................................... 20

•Added 6 crossreferences to Table 8 ................................................................................................................................... 21

•Changed changed last row in Table 8 Description column, from "always reads 1"to "May read back to 1 or 0"............. 21

•Changed last row last column in Figure 23 truth table from "Disabled"to "Input Buffer Termination Disabled"................ 26

•Changed in Table 13, second column, 5th and 6th row from 1 to 0 .................................................................................. 29

Product Folder Link(s): CDCE62002

PACKAGE OPTION ADDENDUM

www.ti.com 27-Jul-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

CDCE62002RHBR ACTIVE VQFN RHB 32 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CDCE

62002

CDCE62002RHBT ACTIVE VQFN RHB 32 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CDCE

62002

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

CDCE62002RHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2

CDCE62002RHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 27-Jul-2013

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CDCE62002RHBR VQFN RHB 32 3000 338.1 338.1 20.6

CDCE62002RHBT VQFN RHB 32 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 27-Jul-2013

Pack Materials-Page 2

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