1
LT1619
1619fa
Low Voltage Current Mode
PWM Controller
, LTC and LT are registered trademarks of Linear Technology Corporation.
The LT
®
1619 is a fixed frequency PWM controller for
implementing current mode DC/DC converters with mini-
mum external parts. The LT1619 operates with input
voltages ranging from 1.9V to 18V and is suitable for a
variety of battery-powered and distributed DC/DC con-
verters. The internal rail-to-rail N-channel MOSFET driver
operates either from the input in the nonbootstrapped
mode or from the output in bootstrapped operation. The
driver is designed to drive a low side power transistor in
boost, SEPIC, flyback and other topologies.
Converter efficiency is improved at heavy loads with a
53mV current sense voltage and at light load with Burst
Mode operation. The operating frequency is internally set
at 300kHz. The oscillator can also be synchronized exter-
nally up to 500kHz. No load quiescent current is 140µA and
shutdown current is 15µA.
The LT1619 is available in 8-lead MSOP and SO packages.
■
Wide V
IN
Range: 1.9V to 18V
■
300kHz Fixed Frequency Current Mode Control
■
1A Rail-to-Rail N-Channel MOSFET Driver
■
Low 53mV Current Limit Threshold Voltage
Improves Efficiency
■
Implements Boost, SEPIC and Flyback Converters
Requiring Low Side Power Transistors
■
Internal Current Sense Amplifier
with Leading Edge Blanking
■
Up to 500kHz External Synchronization
■
Burst Mode
®
Operation for High Efficiency
at Light Load
■
140µA Quiescent Current
■
15µA Shutdown Current
■
8-Lead MSOP and SO Packages
■
3.3V to 5V DC/DC Converters
■
Distributed Power Supplies
■
Isolated Power Supplies
Figure 1. High Efficiency 3.3V to 5V DC/DC Converter
Burst Mode is a registered trademark of Linear Technology Corporation.
LOAD CURRENT (mA)
75
EFFICIENCY (%)
80
85
90
95
1 100 1000
1619 F01a
70 10
Efficiency
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
+
0.1µF
0.1µF
15nF
220pF
V
IN
3.3V
L1
5.6µH
5A
D1
M1
Si9804
V
OUT
5V
2.2A
R
SENSE
0.01Ω
1619 F01
75k
37.4k
12.4k
C1
22µF
C1: PANASONIC EEFCDOK220R
C
OUT
: KEMET T495X227K010AS (×2)
D1: MBRD835L
L1: COILCRAFT DO5022P-562
+
C
OUT
440µF
S/S
FB
V
C
GND
8
7
6
5
1
2
3
4
V
IN
DRV
GATE
SENSE
LT1619
2
LT1619
1619fa
Input Voltage (V
IN
) ................................... –0.3V to 20V
Gate Drive Supply Voltage (DRV) ............. –0.3V to 20V
Shutdown/Synch Voltage (S/S) ................ –0.3V to 20V
Feedback Voltage (FB) .............................................. V
IN
Compensation Voltage (V
C
) ...................................... 3V
Gate Drive Output Current (GATE) ........................ ±1.5A
Current Sense Voltage (SENSE) .................–0.5V to V
IN
Operating Temperature Range (Note 2) .. –40°C to 85°C
Junction Temperature (Note 3)............................. 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)..................300°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
T
JMAX
= 125°C, θ
JA
= 200°C/W
T
JMAX
= 125°C, θ
JA
= 120°C/W
(Note 1)
ORDER PART
NUMBER
MS8 PART MARKING
LT1619EMS8
LTHC
1
2
3
4
S/S
FB
V
C
GND
8
7
6
5
V
IN
DRV
GATE
SENSE
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
ORDER PART
NUMBER
S8 PART MARKING
LT1619ES8
1619
1
2
3
4
8
7
6
5
TOP VIEW
V
IN
DRV
GATE
SENSE
S/S
FB
V
C
GND
S8 PACKAGE
8-LEAD PLASTIC SO
PARAMETER CONDITIONS MIN TYP MAX UNITS
Reference Voltage Measured at the FB Pin ●1.22 1.24 1.26 V
Reference Line Regulation 1.9V ≤ V
IN
≤ 18V 0.004 0.05 %/V
FB Input Bias Current V
FB
= V
REF
10 25 nA
Error Amplifier Transconductance 80 170 260 µΩ
–1
Error Amplifier Output Source Current V
FB
= 1V, V
COMP
= 1V 4 8.7 14 µA
Error Amplifier Output Sink Current V
FB
= 1.5V, V
COMP
= 1V 4 8.7 14 µA
Error Amplifier Clamp Voltage V
FB
= 1V 1.6 2.2 V
Undervoltage Lockout Threshold 1.65 1.85 V
Input Voltage Range ●1.9 18 V
Switching Frequency 1.9V ≤ V
IN
≤ 18V ●220 300 360 kHz
Synchronization Frequency Range 370 500 kHz
Maximum Duty Cycle ●88 92 %
Current Limit Threshold ●40 53 66 mV
Burst Mode Operation Current Limit 10 mV
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VIN = VDRV = 2.5V, VS/S = VIN, COMP open, VSENSE = 0V unless otherwise noted.
ABSOLUTE AXI U RATI GS
WWWU
PACKAGE/ORDER I FOR ATIO
UU
W
ELECTRICAL CHARACTERISTICS
3
LT1619
1619fa
PARAMETER CONDITIONS MIN TYP MAX UNITS
Current Sense Input Current V
SENSE
= 0V ●–90 –120 –150 µA
Current Limit Delay 150 ns
Driver Output Rise Time C
L
= 3300pF 30 ns
Driver Output Fall Time C
L
= 3300pF 35 ns
Driver Output High Level I
OUT
= –20mA V
DRV
– 0.6 V
DRV
– 0.35 V
I
OUT
= –200mA V
DRV
– 1.6 V
DRV
– 1.2 V
Driver Output Low Level I
OUT
= 20mA 100 200 mV
I
OUT
= 200mA 0.5 0.7 V
Shutdown Driver Output Level V
S/S
= 0V, I
OUT
= 20mA 100 200 mV
Idle Mode Driver Output Level V
S/S
= V
IN
, V
FB
= 1.5V, I
OUT
= 20mA 100 200 mV
S/S Pin Current V
S/S
= V
IN
4µA
V
S/S
= 0V –2 µA
Operating Supply Current V
FB
= 1V 9 mA
Quiescent Supply Current V
S/S
= V
IN
, V
FB
= 1.5V ●140 220 µA
Shutdown Supply Current V
S/S
= 0V 15 19 µA
V
S/S
= 0V, V
IN
= 18V, T
A
= 85°C40µA
Shutdown Threshold 0.45 1.2 V
Shutdown Delay 12 17 33 µs
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VIN = VDRV = 2.5V, VS/S = VIN, COMP open, VSENSE = 0V unless otherwise noted.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2: The LT1619E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: T
J
is calculated from the ambient temperature T
A
, the power
dissipation P
D
and the thermal resistance θ
JA
of the package according to
the formula:
T
J
= T
A
+ P
D
• θ
JA
ELECTRICAL CHARACTERISTICS
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Bandgap Voltage vs Temperature IS/S vs VS/S S/S Pin Current vs Temperature
TEMPERATURE (°C)
–40
BANDGAP VOLTAGE (V)
1.241
1.243
80 100
1619 G01
–20 0 20 40 60 120
1.245
1.235
1.227
1.225
1.233
1.231
1.229
1.237
1.239
V
IN
= 2.5V
V
S/S
(V)
0
I
S/S
(µA)
5
4
3
2
1
0
–1
–2
–3 4.0
1619 G02
1.0 2.0 3.0 5.03.50.5 1.5 2.5 4.5
T
A
= –40°C
T
A
= 25°C
T
A
= 85°C
TEMPERATURE (°C)
–40
S/S PIN CURRENT (µA)
1
3
120
1619 G03
–1
–3 040 80
–20 20 60 100
5
0
2
–2
4
V
S/S
= 0V
V
S/S
= 2.5V
4
LT1619
1619fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Shutdown Supply Current
vs Input Voltage Idle Mode Supply Current
vs Temperature Frequency Deviation from
Nominal vs Temperature
INPUT VOLTAGE (V)
0
SUPPLY CURRENT (µA)
45
40
35
30
25
20
15
10
516
1619 G04
4 8 12 20142 6 10 18
T
A
= –40°C
T
A
= 85°C
T
A
= 25°C
TEMPERATURE (°C)
–40
140
IDLE MODE SUPPLY CURRENT (µA)
150
160
170
180
04080 120
1619 G05
190
200
–20 20 60 100
V
IN
= 2.5V
TEMPERATURE (°C)
–40
DEVIATION FROM NOMINAL FREQUENCY (%)
8
20
1619 G06
2
–2
–20 0 40
–4
–6
–8
–10
10
6
4
0
60 80 100
V
IN
= 2.5V
NOMINAL FREQUENCY = 300kHz
Maximum Duty Ratio
vs Temperature Deviation from Nominal
Frequency vs Input Voltage Current Limit Threshold
vs Temperature
TEMPERATURE (°C)
–40 –20
90
DUTY RATIO (%)
92
95
040 60
1619 G07
91
94
93
20 80 100
V
IN
= 2.5V
INPUT VOLTAGE (V)
0
FREQUENCY DEVIATION (%)
2
4
6
16
1619 G08
0
–2
–4 4810 20
8
12
2618
14
T
A
= 25°C
NOMINAL FREQUENCY = 300kHZ
TEMPERATURE (°C)
–40
CURRENT LIMIT THRESHOLD (mV)
57
20
1619 G09
54
52
–20 0 40
51
50
58
56
55
53
60 80 100
V
IN
= 2.5V
Burst Mode Operation Current
Limit Threshold vs Temperature SENSE Pin Input Bias Current
vs Temperature SENSE Pin Input Bias Current
vs Sense Voltage
TEMPERATURE (°C)
–40
8
10
14
20 60
1619 G10
6
4
–20 0 40 80 100
2
0
12
CURRENT LIMIT THRESHOLD (mV)
V
IN
= 2.5V
DUTY CYCLE = 0
TEMPERATURE (°C)
–40
SENSE PIN CURRENT (µA)
–115
–117
–119
–121
–123
–125
–127
–129
–131
–133
–135 040 60
1619 G11
–20 20 80 100
V
SENSE
= 0V
V
SENSE
(mV)
–10
SENSE PIN CURRENT (µA)
60
1619 G12
010
20 30 40 50
–90
–95
–100
–105
–110
–115
–120
–125
–130
T
A
= 25°C
5
LT1619
1619fa
–
+
–
+
Q
R
I
LIM
1619 F02
CURRENT
LIMIT
COMPARATOR
S
Σ
++
–
+
DRIVER
280ns
CURRENT
SENSE
AMP
GATE
DRV
V
IN
6
GND
4
SENSE
R
SENSE
LOAD
5
7
LEADING
EDGE
BLANKING
C1
SYNC
RAMP COMP
300kHz
OSCILLATOR
SHUTDOWN
DELAY REF/BIAS
S/S 1
FB
1.24V
1.8V
V
C
V
IN
CLK
IDLE
UVLO
–
+
V
B
–
+
A1
–
+
A2
ERROR
AMPLIFIER
2
3 8
g
m
Figure 2. LT1619 Block Diagram
S/S (Pin 1): Shutdown and Synchronization. Shutdown is
active low with a typical threshold voltage of 0.9V. For
normal operation, the S/S pin is tied to V
IN
. To externally
synchronize the controller, drive the S/S pin with pulses.
FB (Pin 2): The inverting Input of the Error Amplifier.
Connect the resistor divider tap here. Set V
OUT
according
to V
OUT
= 1.24(1 + R1/R2). See Figure 1.
V
C
(Pin 3): Compensation Pin for the Error Amplifier. V
C
is
the output of the transconductance amplifier. Overall loop
is compensated with an RC network from this pin to the
ground.
GND (Pin 4): Ground. Connect to local ground plane.
SENSE (Pin 5): The Input of the Current Sense Amplifier.
The SENSE pin is connected to the source of the N-channel
MOSFET and to a sense resistor to the ground. The current
limit threshold is internally set at 53mV, giving a maximum
switch current of 53mV/R
SENSE
.
GATE (Pin 6): The Output of the MOSFET Driver.
DRV (Pin 7): The Pull-Up Supply of the MOSFET Driver. Tie
this pin to V
IN
(Pin 8) for nonbootstrapped operation or to
the converter output for bootstrapped operation.
V
IN
(Pin 8): Supply or Battery Input. Must be closely
bypassed to the ground plane.
UU
U
PI FU CTIO S
BLOCK DIAGRA
W
6
LT1619
1619fa
The LT1619 is a fixed frequency current mode switching
regulator PWM controller that can be used in boost, SEPIC
or flyback modes. The device operates from an input
supply range of 1.9V to 18V, and has a separate supply pin
(DRV) for the gate driver. The DRV pin can be bootstrapped
to V
OUT
for additional gate enhancement in low voltage
applications like 3.3V to 5V boost converters, or con-
nected to the input supply for higher voltage inputs.
To best understand operation of the LT1619, please refer
to Figure 2, the Block Diagram. The gate drive circuit turns
on the external MOSFET at the trailing edge of oscillator
output signal CLK. MOSFET current is sensed with an
external resistor (R
SENSE
of Figure 1). A leading edge
blanking circuit disables the current sense amplifier for
280ns immediately following switch turn-on, preventing
gate charging current from prematurely tripping the PWM
comparator. A slope compensating ramp, derived from
the oscillator, is added to the current sense output. The
driver turns off the MOSFET when this sum exceeds the
error amplifier output V
C
. The switch current is limited
with a separate comparator. The compensating ramp is a
progressive nonlinear function of the operating duty ratio
whereas the current limit does not vary with the duty ratio.
Error amplifier output V
C
determines the peak switch cur-
rent required to regulate the output voltage. V
C
can be
considered a measure of output current. At heavy loads,
V
C
is in its upper range. Average and peak inductor cur-
rents are high. In this range, the inductor tends to run in
continuous conduction mode (CCM), where current is al-
ways flowing in the inductor. As load current decreases,
average and peak inductor current decreases. When the
average inductor current falls below 1/2 of the peak-to-peak
inductor current ripple, the converter enters discontinu-
ous conduction mode (DCM), where current in the induc-
tor reaches zero sometime during the discharge phase.
Further reduction in output current moves V
C
towards its
lower operating range, decreasing inductor current. Hys-
teretic comparator A1 determines if V
C
is too low for the
LT1619 to operate efficiently. As V
C
falls below the trip
voltage VB, A1’s output goes high, turning off all blocks
except the error amplifier, A1 and A2. The LT1619 enters
the idle state and switching stops. The device draws just
140µA from the input in the idle state. Output load current
discharges the output capacitor, causing the output volt-
age to decrease. As V
OUT
decreases, V
C
increases. As V
C
increases above V
B
, switching action begins, delivering
power to the output. The switch current sense threshold is
about 10mV in this V
C
region. If the output load remains
light, the output voltage will rise and V
C
will fall, causing
the converter to idle again. This is known as Burst Mode
operation. The burst frequency depends on input voltage,
output voltage, inductance and output capacitance. Out-
put voltage ripple during Burst Mode operation is usually
higher than when the converter is switching continuously.
Burst Mode operation increases light load efficiency be-
cause it delivers more energy per clock cycle than possible
with discontinuous mode operation and extremely low
peak switch current, allowing fewer switching cycles to
maintain a given output. IC supply current therefore be-
comes a small fraction of the total input current.
Setting Output Voltage
The output voltage of the LT1619 is set with resistive
divider R1 and R2 connected from the output to ground as
detailed in Figure 3. The divider tap is tied to the device FB
pin. Current through R2 should be significantly higher
than the FB pin bias current of 25nA. With R2 = 10k, the
input bias current of the error amplifier is 0.02% of the
current in R2.
Figure 3. Feedback Resistive Divider
Synchronization and Shutdown
The S/S pin (Pin 1) can be used to synchronize the
oscillator to an external source. The S/S pin is tied to the
input (V
IN
> 1.9V) for normal operation. The oscillator in
the LT1619 can be externally synchronized by driving the
S/S pin with a pulse train with an amplitude of at least 1V.
The maximum allowable rise time is a function of the
pulse amplitude, as shown in Table 1. Rise times equal to
OPERATIO
U
V
O
R1 R1
R2
V
O
= 1.24V 1 +
– 1
R2
1619 F03
()
V
O
1.24
R1 = R2
()
LT1619
FB
7
LT1619
1619fa
OPERATIO
U
Inductor
The value of the inductor is usually selected so that the
peak-to-peak ripple current is less than 30% of the maxi-
mum inductor current. The inductor should be able to
handle the maximum inductor current at full load without
saturation. Powder iron cores are not suitable for high
frequency switch mode power supply applications be-
cause of their high core losses. Ferrite cores have very low
core losses and are the material of choice for high fre-
quency DC/DC converters.
Power MOSFET Driver
The LT1619 is capable of driving a low side N-channel
power MOSFET with up to 60nC of total gate charge (Q
g
).
An external driver is recommended for MOSFETs with
greater than 80nC of total gate charge. The peak gate drive
current varies from 0.5A with V
DRV
= 2.5V to 1.2A with
V
DRV
= 10V. The MOSFET driver is capable of charging the
gate of the power MOSFET to within 350mV of the upper
gate drive supply rail (DRV). It can also pull the gate of the
MOSFET to within 100mV of ground during turnoff. The
upper supply rail of the gate drive is brought out as a device
pin (DRV) for design flexibility. In a boost converter
design, the DRV pin can be tied to the converter output if
the minimum input voltage is insufficient to fully enhance
the power MOSFET. During start-up, the MOSFET is driven
with a gate voltage starting from V
IN
– V
D
(V
D
is the
forward voltage of the rectifying diode). As the output
voltage rises, the gate drive also increases until steady
state is reached. If the steady-state converter output
voltage exceeds the maximum allowable gate source
voltage and the input voltage is sufficient to enhance the
MOSFET, the DRV pin is tied to the input supply. For a
SEPIC converter, the DRV pin can be tied to the input or
diode OR’ed from the input and the output (Figure 4).
Figure 4. SEPIC Converter with Diode OR’ed Gate Drive Supply
or less than the number specified in Table 1 are accept-
able. The maximum duty cycle is essentially unaffected by
synchronization.
The device will go into shutdown mode if the S/S pin
voltage stays below the shutdown threshold of 0.45V for
more than 33µs. This shutdown delay is reset whenever
the S/S pin voltage rises above the shutdown threshold.
Applying a logic low signal at the S/S pin causes the gate
drive output to go low. Although all circuits in the LT1619
are disabled, the pull-down circuit in the MOSFET buffer is
still biased on. It is capable of shunting any leakage or
transient current at the GATE pin to ground, eliminating
the need for an external bleed resistor. The LT1619 con-
sumes 15µA in shutdown.
The LT1619 is guaranteed to start with a minimum V
IN
of
1.85V. Comparator A2 senses the input voltage and gen-
erates an undervoltage lockout (UVLO) signal if V
IN
falls
below this minimum. While in undervoltage lockout, V
C
is
pulled low and the LT1619 stops switching. The supply
current drawn by the device falls to 140µA.
Table 1. Maximum Allowable Rise Time of Synchronization
Pulse. Rise Time Can Be Slower if Clock Amplitude is Higher
SYNCHRONIZATION MAXIMUM ALLOWABLE
AMPLITUDE (V) RISE TIME (ns)
1.2 120
1.5 220
2.0 350
2.5 470
3.0 530
DRV
V
IN
V
OUT
R
S
1619 F03
LT1619
GND
•
•
+
+
APPLICATIO S I FOR ATIO
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LT1619
1619fa
Power MOSFET
MOSFET power dissipation can be separated into fre-
quency independent and frequency dependent compo-
nents. The R
DS(ON)
loss in the switch is the product of the
mean square switch current and switch R
DS(ON)
and it
does not vary with the operating frequency.
The frequency-dependent switching losses consist of 1)
switch transition loss due to finite rise and fall times of the
drain source voltage and the drain current 2) gate switch-
ing loss, i.e., a packet of charge Q
g
(the total gate charge)
which is moved from the gate drive power supply to
ground in every switch cycle, and 3) the drain switching
loss, charge stored on the parasitic drain capacitance,
C
OSS
is dumped to ground as the switch is turned on. The
transistor loss can be expressed as:
P
LOSS
= I
DRMS2
R
DS(ON)
+ transition loss + Q
g
V
G
f
S
+ 1/2C
OSS
V
DS(OFF)2
f
S
where the transition loss can be estimated with:
TransitionLoss I CV f
I
DRSS DS OFF S
G AVG
=
()
()
2
Q
g
= The total gate charge
V
G
= Gate drive voltage ≈ V
DRV
I
G(AVG)
= The average MOSFET buffer output current
f
S
= Operating frequency
C
RSS
= The average C
GD
between V
DS
= 0V
and V
DS
= V
DS(OFF)
At low V
DS(OFF)
(≤12V) and operating frequencies below
500kHz, the ohmic losses often dominate. For high voltage
converters, the transition loss and C
OSS
charge dumping
loss can dramatically impact the converter efficiency.
MOSFETs with lower parasitic capacitances but higher
R
DS(ON)
may actually provide better efficiency in these
situations.
Capacitors
In a switch mode DC/DC converter, output ripple voltage
is the product of the equivalent series resistance (ESR) of
the output capacitor and the peak-to-peak capacitor
current. Depending on topology, current feeding the out-
put capacitor can be continuous or discontinuous. The input
current can also be continuous or discontinuous even if the
inductor current itself is continuous. In boost topology, the
inductor is in series with the input source so the input
current is continuous and the output current is discontinu-
ous. In buck-boost or flyback converters, the inductor is
not in series with the input source nor the output, so nei-
ther the input current nor output current is continuous.
Whenever a terminal current is discontinuous, the capaci-
tor at that terminal should be chosen to handle the ripple
current. Capacitor reliability will be adversely affected if
the ripple current exceeds the maximum allowable rat-
ings. This maximum rating is specified as the RMS ripple
current. Several capacitors may be mounted in parallel to
meet the size and ripple current requirements.
Besides the ripple voltage requirements, the output ca-
pacitor also needs to be sized for acceptable output
voltage variation under load transients.
Current Sensing Resistor R
SENSE
The LT1619 drives a low side N-channel MOSFET switch.
The switch current is sensed with an external resistor
R
SENSE
connected between the source of the MOSFET and
ground. The internal blanking circuit blocks the voltage
spike developed across R
SENSE
for 280ns at switch turn-
on. The switch is turned off when the instantaneous
voltage across R
SENSE
exceeds the current limit threshold,
V
SENSE
. Allowing variations in V
SENSE
yields:
RV
I
SENSE SENSE MIN
LMAX
=
()
()
The current limit threshold is constant and does not vary
with duty ratio.
Due to low signal level of the sense voltage, low inductance
sense resistors are required to reduce switching noise.
Low TC resistors maintain constant current limit over
temperature. Dale WSL and IRC series sense resistors
meet these criteria.
APPLICATIO S I FOR ATIO
WUUU
9
LT1619
1619fa
Diode
Schottky diodes are recommended for low output voltage
applications because of their low forward voltage. Since
Schottky diodes have negligible stored charge, charge
dumping loss is also reduced. The reverse breakdown
voltage of the diode should exceed the maximum reverse
voltage stress of the topology used. The diode should also
be able to carry the peak diode current with acceptable
foward voltage. For the boost converter in Figure 1, the
peak inductor current is approximately 5A. A Motorola
MBRD835 is used due to its low forward voltage.
Lowering Burst Mode Operation Current Limit
The LT1619 automatically enters Burst Mode operation as
V
C
voltage falls below V
B
. The corresponding switch
current is the Burst Mode operation switch current thresh-
old, I
D(BURST)
.
The effective Burst Mode operation current threshold can
be lowered by adding an offset to the input of the current
sense amplifier so that the switch current appears higher
to the PWM comparator. This has the effect of shifting the
V
C
operating range above V
B
. Although Burst Mode opera-
tion is not entirely disabled, the peak switch current before
entering Burst Mode operation is greatly reduced due to
the offset of the current sense amplifier. The peak switch
current is also determined by the current sense amplifier
blanking.
To lower the Burst Mode operation current sense thresh-
old, a resistor ROS is added between the SENSE pin and
the sense resistor RSENSE (Figure 5). The input bias
current IBIAS of the current sense amplifier, which has a
tolerance of ±25% and is temperature stable, develops an
offset voltage at the sense input. The value of ROS required
for non-Burst Mode operation can be obtained with the
expression:
I
BIAS
R
OS
≥ V
SENSE(BURST)
where
V
SENSE(BURST)
= (Burst Mode operation peak switch
current, I
D(BURST)
) • R
SENSE
For example, if I
BIAS
= 120µA and V
SENSE(BURST)
= 10mV:
RmV
A
OS
≥µ=Ω
10
120 83
Allowing for 25% and 30% variations in I
BAIS
and
V
SENSE(BURST)
respectively:
R
OS
= (1.25)(1.3)(83Ω)
Choose R
OS
= 137Ω to completely disable Burst Mode
operation. Lower values of R
OS
(for example, 50Ω to
100Ω) can be used to lower the effective Burst Mode
current limit.
The value of the sense resistor is then adjusted to compen-
sate for the reduced full-scale sense voltage.
I
BIAS
R
OS
+ I
L(MAX)
R
SENSE
= 40mV
Filtering Current Sense Signal
I
n a current mode converter, the current sense circuit
senses the switch current and terminates the switch
conduction. In the LT1619, the current sense amplifier
has a full-scale input voltage range from the ground to the
current limit threshold (53mV). Due to high speed switch-
ing transients and parasitic trace inductances, the current
sense signal VSENSE tends to be noisy. If the VSENSE
switching transient is excessive, the current sense ampli-
fier will amplify the spurious transient instead, resulting in
jittery operation. In situations where the internal leading
edge blanking is inadequate, a lowpass filter (Figure 6)
with corner frequency about 5 times the switching
fre
quency can be used to further attenuate high speed
switching transients. In Figure 6 the lowpass filter R
OS
and
C
S
has a corner frequency of:
Figure 5. Lowering Burst Mode Operation Current Limit
–
+
5
4
GND
SENSE RSENSE
ROS
CURRENT
SENSE
AMPLIFIER
IBIAS = 120µA
1619 F05
ID
IBIAS = 120µA
APPLICATIO S I FOR ATIO
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10
LT1619
1619fa
fRC f
CORNER OS S S
=≈
1
25
π
(The input impedance of the sense amplifier at the SENSE
pin is 2500Ω and R
OS
is typically less than 137Ω.) Typical
values for R
OS
and C
S
are 100Ω and 1nF. The 100Ω value
for R
OS
reduces Burst Mode threshold; use 10Ω and 10nF
when this is not desireable.
Figure 7. Implementing Undervoltage Lockout
+
–
V
V
I
0
ZENER
DIODE AVALANCHE
DIODE
BV < 5V
I
Figure 8. I-V Characteristics of Zener
and Avalanche Breakdown Diodes
S/S
FB
VC
GND
8
7
6
5
1
2
3
4
VIN
DRV
GATE
SENSE
LT1619
R3
C1
R4
VIN
1619 F09
Figure 9. Filtering Input Voltage Ripple in UVLO Circuit
Use of Shutdown Function to
Modify Undervoltage Lockout
The LT1619 is designed to operate from an input supply
with voltage as low as 1.85V. Shutdown is activated when
the S/S pin is pulled below 0.45V. The shutdown threshold
is slightly greater than one junction diode forward voltage
and has the temperature characteristics of a junction
diode. The S/S pin is normally tied to the input when
operating from a low voltage input source.
Consider the 12V to –65V isolated flyback converter (see
Typical Applications). The converter draws 3A at low line
while delivering 0.4A to the output. If the S/S pin is tied to
the input, then the LT1619 will start switching as soon as
V
IN
exceeds the internal UVLO threshold. With full load,
the converter can draw much higher than the steady-state
3A from the input source during start-up. If the input
source is current limited, the input voltage will collapse
and latch low.
The start-up problem can be prevented by adding a zener
diode and a resistor to the S/S pin (Figure 7). This is
equivalent to increasing undervoltage lockout voltage of
the controller. Before V
IN
exceeds the zener voltage V
Z
, the
S/S pin current is shunted to the ground through the
Figure 6. Current Sense Filter for Improving Jitter Performance
resistor R3. The voltage developed across R3 due to I
S/S
should be less than the shutdown threshold. The LT1619
remains off until V
IN
exceeds the sum of V
Z
and the
shutdown threshold. True zener diodes (BV < 5V) and
higher voltage avalanche diodes have different I-V charac-
teristics (Figure 8). They need to be biased appropriately
(value of R3) in order to obtain correct UVLO threshold.
When implementing UVLO with converters with high input
ripple voltages (such as flyback and forward), the circuit
in Figure 7 is modified and shown in Figure 9.
PWM
COMPARATOR CURRENT
SENSE
AMPLIFIER
SENSE
C
S
R
SENSE
V
SENSE
+
–
R
OS
I
D
GND
1619 F06
LT1619
–
+
5
4
S/S
FB
V
C
GND
8
7
6
5
1
2
3
4
V
IN
DRV
GATE
SENSE
LT1619
R3
V
Z
V
IN
I
S/S
1619 F07
I
S/S
V
S/S
= 0
R3 < SHUTDOWN THRESHOLD
≈ –2µA
UVLO THRESHOLD = V
Z
+ SHUTDOWN
THRESHOLD ≈ V
Z
+ V
BE
()
I
S/S
V
S/S
= 0
APPLICATIO S I FOR ATIO
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11
LT1619
1619fa
Here the input voltage ripple is filtered with R3, R4 and C1
so as to prevent the input ripple from falsely tripping the
LT1619 synchronization circuit. It is recommended that:
RR
and RRC f
OSC
41
53
1
2341
≈
π
()
<<
||
Implementation of Hysteretic UVLO
with External Synchronization
The UVLO circuit shown in Figure 10 operates down to
0.9V supply voltage. Algebraically the UVLO trip points
are:
S/S
FB
VC
GND
8
7
6
5
1
2
3
4
VIN
DRV
GATE
SENSE
LT1619
R9
510k
R7
51k
VIN
CLK
D1
BAT85
Q2
2N2222
VIN UPPER TRIP POINT = 10V
VIN LOWER TRIP POINT = 8.4V
1619 F10
R8
30k
8.2V
R5
51k
+
–
R6
51k
Q1
2N2222
Figure 10. Addition of Hysteresis UVLO While Synchronizing the
LT1619. Component Values Shown are for the Upper and the
Lower VIN Trip Points of 10V and 8.4V. In UVLO, the Gate Drive
is Disabled by Pulling the VC Pin Low. Disabling the Clock Shuts
Down the LT1619. If Not Synchronized, the Collector of Q2 Can
Be Tied to the S/S Pin and the Diode D1 Can Be Eliminated
The collector votage of Q2 is made about 1.4V at the V
IN
lower trip voltage. This is necessary to prevent the UVLO
circuit from interfering with the feedback amplifier in the
LT1619.
Trickle Current Start from High Voltage Supplies
The low shutdown and idle mode quiescent supply cur-
rents of the LT1619 can be utilized to implement trickle
current start from high voltage input sources (such as a
36V to 72V telecom bus). The trickle current start-up
circuit in Figure 11 is modified from the UVLO circuit of
Figure 10. R10 is a high value resistor that charges the
storage capacitor C2 during start-up. Before V
CC
reaches
the upper UVLO trip point, Q2 holds the S/S pin low. The
LT1619 draws shutdown mode current (≈15µA) from V
CC
.
Q2 collector can also be tied to the V
C
pin through a diode
as in Figure 10. The LT1619 will then draw idle mode
quiescent current (≈140µA) from V
CC
. R10 should be able
to charge C2 while supplying current to the UVLO circuit
and the LT1619. Maximizing R5 to R9 values reduces
power dissipation in R10.
When V
CC
crosses the upper UVLO threshold, the LT1619
starts switching and its current consumption increases.
Before the bootstrap takes over, the LT1619 draws its
current from C2. V
CC
ramps towards the lower UVLO
threshold. Increasing the value of C2 allows more time for
the bootstrap circuit to establish itself before the converter
enters undervoltage lockout.
S/S
FB
VC
GND
8
7
6
5
1
2
3
4
VIN
DRV
GATE
SENSE
LT1619
BOOTSTRAP
WINDING
T1
D2
R9
R7
VCC
HV VIN
Q2
1619 F11
R8
C2
R10
R5
R6
Q1
Figure 11. Trickle Current Start-Up with Bootstrapped VCC
VVV R
RR
and
VRRR
RVV RRR
RR RR
UVLOHysteresis V V R
RRR
V
VR
RR
R
INH Z BE
INL Z BE
INH INL Z
BE
=+ +
=+
()
++
()
+
()
==
++
+
15
67
579
5
579
56 79
5
579
5
67
5
||
|| ||
|| ||
–
|| –|||| R R
R
79
6
+
()
APPLICATIO S I FOR ATIO
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12
LT1619
1619fa
Increasing Ramp Compensation While Synchronizing
The LT1619 is synchronized by forced discharge of the
internal timing ramp. The timing ramp amplitude de-
creases as the synchronization frequency increases. Since
the internal compensation ramp is derived from the timing
ramp, reduced timing ramp results in diminished com-
pensating ramp. If the LT1619 is synchronized at frequen-
cies 20% to 30% higher than the free-running frequency,
external ramp compensation will be required. Figures 12
and 13 show two such schemes.
In both figures the compensating ramps are kept linear by
making R11-C1 and R14-C2 products substantially higher
than the synchronizing period. The compensation ramps,
whose peak amplitudes are made between 1/4 to 1/3 of the
current limit threshold, are developed across R13. As a
result, the effective current limit threshold is reduced by
the sum of the compensating ramp and the offset voltage
developed across R13 due to the SENSE pin input bias
current (see Figure 5). Moreover, the current limit thresh-
old becomes duty cycle dependent.
PC Board Layout and Other Practical Considerations
The following is recommended for PC board layout:
1. Trace lengths of the branches carrying switched cur-
rent should be kept short. For example, in the boost
converter of Figure 1, the circuit loop formed by M1,
R
SENSE
, D1 and C
OUT
carries switched current. The size
of this loop must be minimized. R
SENSE
and C
OUT
should be grounded to a single point on a large ground
plane. This reduces switching noise and overall con-
verter jitter. It is also preferable to ground the input
capacitor C1 close to the common point between C
OUT
and R
SENSE
although this is less important.
2. Keep the trace between the sense resistor and the
SENSE pin short. When sensing high switch current,
Kelvin connection to R
SENSE
is necessary.
3. Bypass both the V
IN
and DRV pins with ceramic capaci-
tors next to the IC and the ground plane.
4. Keep high voltage switching nodes, such as the drain
and gate of the MOSFET, away from the FB and V
C
pins.
5. Use inductor so that its ripple current is between 1/4
and 1/3 of its peak current. Steeper inductor current
ramp results in sharper PWM comparator switching,
hence less jitter.
6. In most cases, filtering the current sense signal is not
necessary for jitter-free operation.
Figure 14 is the PC board layout for the 5V/8A and 12V/5A
boost converters shown in Figures 15a and 16a.
S/S
FB
VC
GND
8
7
6
5
1
2
3
4
VIN
DRV
GATE
SENSE
LT1619
RSENSE
CLK
D2
1N4148
Q1
2N2222
R11
100k
R12
2200Ω
R13
51Ω
MAIN POWER
TRANSISTOR
C1
220pF
1619 F12
S/S
FB
VC
GND
8
7
6
5
1
2
3
4
VIN
DRV
GATE
SENSE
LT1619
RSENSE
CLK
D2
1N4148 D3
1N4148
R14
8200Ω
R15
2400Ω
R13
51Ω
C2
2.2nF
1619 F13
Figure 12. Increasing Ramp Compensation. Q1 Buffers the C1
Ramp. D2 Discharges C1. Values Shown are for 10V Gate Drive
and 15mV Ramp Across R13 at 90% Duty Cycle and 500kHz
Figure 13. Externally Increasing Ramp Compensation. Similar
to Figure 12 Except That C2 is Not Buffered with Transistor
APPLICATIO S I FOR ATIO
WUUU
13
LT1619
1619fa
1
2
3
4
8
7
6
5
G
G
S
DD
CIN2
LT1619 M1
RSENSE
VOUT
VIN
S
M1
CDRV
1619 F14
GND
R1
RC
CP
D1
L1
CZ
CIN1 COUT1, 2
R2
Figure 14. Recommended Component Placement for the Boost Converters in Figures 15a and 16a
APPLICATIO S I FOR ATIO
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14
LT1619
1619fa
APPLICATIO S I FOR ATIO
WUUU
S/S
FB
V
C
GND
8
7
6
5
1
2
3
4
V
IN
DRV
GATE
SENSE
LT1619
+
R
C
75k
C
Z
15nF
C
IN1
: SANYO POSCAP 6TPB150M ×2
C
OUT1
: SANYO POSCAP 10TPB220M ×4
D1: MOTOROLA MBRB1545CT
L1: SUMIDA CEPH149-1R0
R
SENSE
: PANASONIC 0.002Ω 1W
C
IN2
1µF
CERAMIC
C
IN1
300µF
+
C
OUT1
220µF
×4
L1
1µH
V
IN
3.3V
D1
M1
FDS6680A
×2
C
DRV
0.1µF
CERAMIC
C
P
150pF R
SENSE
C
OUT2
10µF
CERAMIC
R1
37400Ω
5V
8A
1619 F15a
R2
12400Ω
Figure 15a. 3.3V to 5V/8A Boost Converter
LOAD CURRENT (A)
0.01
83
EFFICIENCY (%)
87
88
89
0.1 1 10
1619 F15b
86
85
84
V
IN
= 3.3V
Figure 15b. Efficiency of the 5V/8A Boost Converter
15
LT1619
1619fa
APPLICATIO S I FOR ATIO
WUUU
S/S
FB
VC
GND
8
7
6
5
1
2
3
4
VIN
DRV
GATE
SENSE
LT1619 +
RC
68.1k
CZ
2200pF
CIN1: SANYO OS-CON 10SA100M
COUT1: SANYO OS-CON 16SA150M ×4
D1: MOTOROLA MBRB1545CT
L1: SUMIDA CDEP149-1R8
RSENSE: PANASONIC 0.002Ω 1W
CIN2
1µF
CERAMIC
CIN1
100µF
+
COUT1
600µF
L1
1.8µH
VIN
5V
D1
M1
FDS6690A
×2
CDRV
0.1µF
CERAMIC
CP
47pF
RSENSE
COUT2
10µF
CERAMIC
R1
107k
12V
5A
1619 F15a
R2
12400Ω
Figure 16a. 5V to 12V/5A Boost Converter
LOAD CURRENT (A)
0.01
89
EFFICIENCY (%)
90
91
92
93
0.1 1 10
1619 F16b
88
87
86
85
94
95 V
IN
= 5V
Figure 16b. Efficiency of the 12V/5A Boost Converter
16
LT1619
1619fa
Figure 17a. 5V to –48V Cuk Converter
LOAD CURRENT (mA)
10
79
EFFICIENCY (%)
81
83
85
87
100 1000
1619 F17b
90
89
80
82
84
86
88
V
IN
= 5.25V
V
IN
= 4.75V
V
IN
= 5V
Figure 17b. Efficiency of the 5V to –48V Cuk
TYPICAL APPLICATIO S
U
10µFSUD45N05-20L
50V, 0.018Ω
43nC
1µF
T1
•
4.7µF
FILM
22nF
T1: COILTRONICS CTX02-14261, EFD20-3F3, 6 WINDINGS EACH, 12µH
2.2nF
15Ω
1619 F17a
30Ω220pF
2N5210
36k
1.1k
+
470µF
35V
SANYO MV-GX
–48V/0.5A
+
470µF
35V
SANYO MV-GX
S/S
FB
V
C
GND
8
7
6
5
1
2
3
4
V
IN
DRV
GATE
SENSE
•
•
•
•
•
4.7µF
FILM
MBRS340T3
MBRS340T3
1500µF
6.3V
SANYO MV-GX
1N749
4.3V
V
IN
4.75V TO
5.25V
2N5210
10.5k
1%
12k1M
0.007Ω
432k
1%
LT1619
+
17
LT1619
1619fa
Figure 18a. Isolated Local SLIC Power Supply (Flyback) 20W Total Output Power (65V/0.3A or 32.5V/0.6A)
T1
W1
W4
W3
W2
•
•
•
•
10µFIRLR024N
55V, 0.065Ω
Q
G
= 15nC
330pF
50V
1µF
0.1µF
150µF
20V
SANYO
20SV150M
(OS-CON)
43Ω
MBRS1100T3
1619 F18a
43Ω
1/4W
100Ω
82k
20k
8.1V
10k
S/S
FB
V
C
GND
8
7
6
5
1
2
3
4
V
IN
DRV
GATE
SENSE
1k
1W
1µF
50V
330pF
100V 2.2µF
40V
470pF
2.2µF
40V
–32.5V
–65V
0.22µF
50V
MBRS1100T3
MBRS1100T3
V
IN
10.5V TO
13.7V
0.008Ω
62k
100Ω
6.2V
10k
470Ω
CNY17-3
121Ω
220pF
2.49k
T1
PHILIPS EFD20-3F3-A100-S
CORE SET (0.013" GAP, AI = 100nH/T
2
W4 6T TRIFILAR 28AWG
W1 6T TRIFILAR 28AWG
W3 24T 28AWG
W2 24T 28AWG
2mil
POLYESTER
FILM
LT1619
LT1431
1
2
3
4
8
7
6
5
COLL
NC
V+
NC
REF
NC
FGND
SGND
LOAD CURRENT (mA)
10
50
EFFICIENCY (%)
60
70
90
100 1000
1619 F18b
80
55
65
85
75
V
IN
= 13.7V
V
IN
= 12V
V
IN
= 10.5V
Figure 18b. Efficiency of the Isolated Local SLIC (Flyback)
TYPICAL APPLICATIO S
U
18
LT1619
1619fa
PACKAGE DESCRIPTION
U
MSOP (MS8) 0802
0.53 ± 0.015
(.021 ± .006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.077)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.13 ± 0.076
(.005 ± .003)
0.86
(.034)
REF
0.65
(.0256)
BSC
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
12
34
4.90 ± 0.15
(1.93 ± .006)
8765
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
NOTE 4
0.52
(.206)
REF
5.23
(.206)
MIN
3.2 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 ± 0.04
(.0165 ± .0015)
TYP
0.65
(.0256)
BSC
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
19
LT1619
1619fa
PACKAGE DESCRIPTION
U
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0°– 8° TYP
.008 – .010
(0.203 – 0.254)
SO8 0502
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
1
N
234
N/2
.150 – .157
(3.810 – 3.988)
NOTE 3
8765
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN
N
1 2 3 N/2
.160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
20
LT1619
1619fa
LT/TP 1002 1K REV A • PRINTED IN USA
LINEAR TECHNO LOGY CORPORATION 2000
PART NUMBER DESCRIPTION COMMENTS
LT1370 500kHz, 6A Switching Regulator Boost, Buck, Flyback, Forward, Inverting; 42V Switch Voltage
LT1372 500kHz, 1.5A Switching Regulator SO-8, 2.7V ≤ V
IN
≤ 30V, 42V Switch Voltage
LT1613 1.4MHz, SOT-23 DC/DC Converter Fixed Frequency, 0.9V ≤ V
IN
≤ 10V, 36V Switch Voltage
LTC1624 Switching Regulator Controller SO-8, Drives N-Ch MOSFET, 3.5V ≤ V
IN
≤ 36V
LT1680 Synchronous Boost Controller Synchronous Operation for High Current/High Efficiency
LT1698 Isolated or Nonisolated 10W to 100W 50% Lower Cost than Quarter Brick and Half Brick Modules
Power Supply Solution with Multiple Outputs Fits the Foot Print
LTC1871 No R
SENSE
Boost, Flyback, SEPIC Controller 2.5V ≤ V
IN
≤ 36V, Current Mode Control, 50kHz to 1MHz
Adjustabe Frequency, MSOP-10
LTC1872 SOT-23 Boost Controller 550kHz Fixed Frequency, Current Mode
LT1946 1.2MHz, 65A DC/DC Converter MSOP-8, 5V to 12V/400mA
LT3710/LT3781 Isolated or Nonisolated 10W to 100W 50% Lower Cost than Quarter Brick and Half Brick Modules
Power Supply Solution with Multiple Outputs Fits the Foot Print
RELATED PARTS
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
TYPICAL APPLICATIO
U
V
IN
DRV
LT1619
GATE
SENSE
FB
S/S
14
R9
2.2k
C4, C5: VITRAMON VJ1825Y155MXB (1825/X7R)
C6: TAIYO YUDEN LMK325BJ106MN (1210/X7R)
C8: TAIYO YUDEN EMK316BJ105ML (1206/X7R)
T1: COILTRONICS VP1-0190 (ER11/5, 6 WINDINGS EACH 12.2µH)
R7
30Ω
D3
MBRS0530T1 Q3
MMFT3055VL
D2
MBRS340T3
Q1
FMMT3904
D4
1N4687
4.3V
LOW LEVEL
(I
ZT
= 50µA)
C9
2.2nF
C8
1µF
16V
C7
220pF
3
876
6
3
5
2
5
2
GND V
C
R8
0.015Ω
R10
1.24k
1%
R5
100Ω
R6
3.74k
1% C1
0.022µF
C6
10µF
10V
V
OUT
5V
0.5A
1619 TA01
C5
1.5µF
100V
••
••
10
T1
7
11
8
4
1
12
9
••
C4
1.5µF
100V
V
IN
4V TO 28V
R3
5.6k
Figure 19. 2.5W, 4VIN-28VIN to 5V/0.5A Nonisolated Supply
