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LM25101

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Controller

VIN

RGATE

CBOOT

0.1µF

1.0µF

VDD

VCC

OUT1

OUT2

VDD

VSS

Optional external

fast recovery diode

RBOOT

RGATE

DBOOT

Anti-Parallel Diode

(Optional)

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Design

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM25101

SNVS859C –JULY 2012–REVISED SEPTEMBER 2016

LM25101 3-A, 2-A, and 1-A 80-V Half-Bridge Gate Drivers

1 Features

1• Independent High and Low Driver Logic Inputs

• Bootstrap Supply Voltage up to 100-V DC

• Drives Both a High-Side and Low-Side N-Channel

MOSFETs

• Fast Propagation Times (25 ns Typical)

• Drives 1000-pF Load With 8-ns Rise and Fall

Times

• Excellent Propagation Delay Matching (3 ns

Typical)

• Supply Rail Undervoltage Lockout

• Low Power Consumption

• Pin Compatible With HIP2100 and HIP2101

2 Applications

• Motor-Controlled Drivers

• Half and Full Bridge Power Converters

• Synchronous Buck Converters

• Two Switch Forward Power Converters

• Forward With Active Clamp Converters

• 48-V Server Power

• Solar DC-DC and DC-AC Converters

3 Description

The LM25101 high-voltage gate driver is designed to

drive both the high-side and the low-side N-Channel

MOSFETs in a synchronous buck or a half-bridge

configuration. The A version provides a full 3-A of

gate drive while the B and C versions provide 2-A

and 1-A, respectively. The outputs are independently

controlled with TTL input thresholds. An integrated

high voltage diode is provided to charge the high-side

gate drive bootstrap capacitor. A robust level shifter

operates at high speed while consuming low power

and providing clean level transitions from the control

logic to the high-side gate driver. Undervoltage

lockout is provided on both the low-side and the high-

side power rails.

These devices are available in the standard 8-pin

SOIC, 8-pin SO-PowerPAD, 8-pin WSON, 10-pin

WSON, and 8-pin MSOP PowerPAD packages.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

LM25101

MSOP PowerPAD (8) 3 mm × 3 mm

WSON (8) 4 mm × 4 mm

WSON (10) 4 mm × 4 mm

SO PowerPAD (8) 3.9 mm × 4.89 mm

SOIC (8) 3.91 mm × 4.9 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Simplified Application Diagram

LM25101

SNVS859C –JULY 2012–REVISED SEPTEMBER 2016

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Product Folder Links: LM25101

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Device Options....................................................... 3

6 Pin Configuration and Functions......................... 3

7 Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 Switching Characteristics.......................................... 7

7.7 Typical Characteristics.............................................. 8

8 Detailed Description............................................ 12

8.1 Overview................................................................. 12

8.2 Functional Block Diagram....................................... 12

8.3 Feature Description................................................. 12

8.4 Device Functional Modes........................................ 13

9 Application and Implementation ........................ 14

9.1 Application Information............................................ 14

9.2 Typical Application.................................................. 14

10 Power Supply Recommendations ..................... 16

11 Layout................................................................... 17

11.1 Layout Guidelines ................................................. 17

11.2 Layout Example .................................................... 18

12 Device and Documentation Support................. 19

12.1 Receiving Notification of Documentation Updates 19

12.2 Community Resources.......................................... 19

12.3 Trademarks........................................................... 19

12.4 Electrostatic Discharge Caution............................ 19

12.5 Glossary................................................................ 19

13 Mechanical, Packaging, and Orderable

Information........................................................... 19

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (March 2013) to Revision C Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation

section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section.................................................................................................. 1

• Added Thermal Information table........................................................................................................................................... 5

Changes from Original (March 2013) to Revision A Page

• Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 1

1VDD 10 LO

2HB 9 VSS

3HO 8 LI

4HS 7 HI

5NC 6 NC

Not to scale

Thermal Pad

1VDD 8 LO

2HB 7 VSS

3HO 6 LI

4HS 5 HI

Not to scale

Thermal Pad

1VDD 8 LO

2HB 7 VSS

3HO 6 LI

4HS 5 HI

Not to scale

1VDD 8 LO

2HB 7 VSS

3HO 6 LI

4HS 5 HI

Not to scale

PowerPAD

LM25101

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5 Device Options

Table 1. Input/Output Options

Part Number Input Thresholds Peak Output Current

LM25101A TTL 3 A

LM25101B TTL 2 A

LM25101C TTL 1 A

6 Pin Configuration and Functions

DGN and DDA Packages

8-Pin MSOP and SO PowerPAD

Top View

NGT Package

8-Pin WSON

Top View

D Package

8-Pin SOIC

Top View

DPR Package

10-Pin WSON

Top View

LM25101

SNVS859C –JULY 2012–REVISED SEPTEMBER 2016

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Product Folder Links: LM25101

(1) TI recommends that the exposed thermal pad on the bottom of the applicable packages is soldered to ground plane of the PCB, and the

ground plane should extend out from beneath the IC to help dissipate heat.

Pin Functions

PIN TYPE DESCRIPTION

NAME MSOP

PowerPAD WSON

(8) WSON

(10) SO

PowerPAD SOIC

HB 2 2 2 2 2 PWR High-side gate driver bootstrap rail. Connect the positive

terminal of the bootstrap capacitor to HB and the

negative terminal to HS. The bootstrap capacitor should

be placed as close to the IC as possible.

HI 5 5 7 5 5 I High-side driver control input. The LM25101 inputs have

TTL type thresholds. Unused inputs should be tied to

ground and not left open.

HO 3 3 3 3 3 O High-side gate driver output. Connect to the gate of

high-side MOSFET with a short, low inductance path.

HS 4 4 4 4 4 GND High-side MOSFET source connection. Connect to the

bootstrap capacitor negative terminal and the source of

the high-side MOSFET.

LI 6 6 8 6 6 I Low-side driver control input. The LM25101 inputs have

TTL type thresholds. Unused inputs should be tied to

ground and not left open.

LO 8 8 10 8 8 O Low-side gate driver output. Connect to the gate of the

low-side MOSFET with a short, low inductance path.

NC — — 5, 6 — — — No connection

VDD 1 1 1 1 1 PWR Positive gate drive supply. Locally decouple to VSS

using a low ESR and ESL capacitor located as close to

the IC as possible.

VSS 7 7 9 7 7 GND Ground return. All signals are referenced to this ground.

Thermal

Pad PowerPAD Thermal

Pad Thermal

Pad PowerPAD — — Solder to the ground plane under the IC to aid in heat

dissipation.(1)

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. For

performance limits and associated test conditions, see the Electrical Characteristics tables.

(2) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS node will generally not

exceed –1 V. However, in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage

transiently. If negative transients occur, the HS voltage must never be more negative than VDD – 15 V. For example, if VDD = 10 V, the

negative transients at HS must not exceed –5 V.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

VDD to VSS −0.3 18 V

HB to HS −0.3 18 V

LI or HI Input −0.3 VDD + 0.3 V

LO Output −0.3 VDD + 0.3 V

HO Output VHS - 0.3 VHB + 0.3 V

HS to VSS(2) –5 100 V

HB to VSS 100 V

Junction temperature, TJ150 °C

Storage temperature, Tstg –55 150 °C

LM25101

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SNVS859C –JULY 2012–REVISED SEPTEMBER 2016

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(1) The Human Body Model (HBM) is a 100-pF capacitor discharged through a 1.5-kΩresistor into each pin.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic discharge

Human-body model (HBM), per

ANSI/ESDA/JEDEC JS-001(1) All pins except 2, 3, and 4 ±2000

Pins 2, 3, and 4 ±1000

Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250

Machine model (MM) ±100

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT

VDD Supply voltage VDD 9 14 V

VHS Voltage HS –1 100 – VDD V

VHB Voltage HB VHS + 8 VHS + 14 V

HS slew rate 50 V/ns

TJJunction temperature –40 125 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.4 Thermal Information

THERMAL METRIC(1)

LM25101A, LM25101B LM25101C

UNITD (SOIC) DDA (SO

PowerPAD) NGT

(WSON) DPR

(WSON) D (SOIC) DPR

(WSON) DGN (MSOP

PowerPAD)

8 PINS 8 PINS 8 PINS 10 PINS 8 PINS 10 PINS 8 PINS

RθJA Junction-to-ambient thermal

resistance 108.2 46.1 38.2 37.8 111.5 39.8 54.1 °C/W

RθJC(top) Junction-to-case (top) thermal

resistance 50.6 53.5 36.3 35.8 54.2 39.1 55.9 °C/W

RθJB Junction-to-board thermal resistance 49.1 13.8 15.2 15.0 52.3 17.1 15.1 °C/W

ψJT Junction-to-top characterization

parameter 7.6 4.2 0.3 0.3 9.0 0.4 2.4 °C/W

ψJB Junction-to-board characterization

parameter 48.5 13.9 15.4 15.3 51.7 17.3 15.1 °C/W

RθJC(bot) Junction-to-case (bottom) thermal

resistance — 3.9 4.5 4.4 — 6.1 4.6 °C/W

LM25101

SNVS859C –JULY 2012–REVISED SEPTEMBER 2016

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Product Folder Links: LM25101

(1) Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through

correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

7.5 Electrical Characteristics

Typical values apply for TJ= 25°C only. Minimum and maximum limits apply for TJ= –40°C to 125°C.(1) Unless otherwise

specified, VDD = VHB = 12 V, VSS = VHS = 0 V, No Load on LO or HO.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY CURRENTS

IDD VDD quiescent current VLI = VHI = 0 V 0.25 0.4 mA

IDDO VDD operating current f = 500 kHz 2.0 3 mA

IHB Total HB quiescent current VLI = VHI = 0 V 0.06 0.2 mA

IHBO Total HB operating current f = 500 kHz 1.6 3 mA

IHBS HB to VSS current (quiescent) VHS = VHB = 100 V 0.1 10 µA

IHBSO HB to VSS current (operating) f = 500 kHz 0.4 mA

INPUT PINS

VIL Input voltage threshold Rising Edge 1.3 1.8 2.3 V

VIHYS Input voltage hysteresis 50 mV

RIInput pulldown resistance 100 200 400 kΩ

UNDER VOLTAGE PROTECTION

VDDR VDD rising threshold 6.0 6.9 7.4 V

VDDH VDD threshold hysteresis 0.5 V

VHBR HB rising threshold 5.7 6.6 7.1 V

VHBH HB threshold hysteresis 0.4 V

BOOT STRAP DIODE

VDL Low-current forward voltage IVDD-HB = 100 µA 0.52 0.85 V

VDH High-current forward voltage IVDD-HB = 100 mA 0.8 1 V

RD Dynamic resistance IVDD-HB = 100 mA 1.0 1.65 Ω

LO AND HO GATE DRIVER

VOL Low-level output voltage IHO = ILO = 100 mA A version 0.12 0.25 VB version 0.16 0.4

C version 0.28 0.65

VOH High-level output voltage IHO = ILO = 100 mA

VOH = VDD – VLO or

VOH = VHB – VHO

A version 0.24 0.45 VB version 0.28 0.60

C version 0.60 1.10

IOHL Peak pullup current HO, VLO = 0 V A version 3 AB version 2

C version 1

IOLL Peak pulldown current HO, VLO = 12 V A version 3 AB version 2

C version 1

HI tHPLH

tLPLH tHPHL

tLPHL

tMOFF

tMON

LM25101

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SNVS859C –JULY 2012–REVISED SEPTEMBER 2016

Product Folder Links: LM25101

(1) Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through

correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

7.6 Switching Characteristics

Typical values apply for TJ= 25°C only. Minimum and maximum limits apply for TJ= –40°C to 125°C.(1) Unless otherwise

specified, VDD = VHB = 12 V, VSS = VHS = 0 V, No Load on LO or HO.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tLPHL LO turnoff propagation delay LI falling to LO falling 22 56 ns

tLPLH LO turnon propagation delay LI rising to LO rising 26 56 ns

tHPHL HO turnoff propagation delay HI falling to HO falling 22 56 ns

tHPLH LO turnon propagation delay HI rising to HO rising 26 56 ns

tMON Delay matching LO ON and HO OFF 4 10 ns

tMOFF Delay matching LO OFF and HO ON 4 10 ns

tRC, tFC Either output rise and fall time CL= 1000 pF 8 ns

tROutput rise time (3 V to 9 V) CL= 0.1 µF A version 430 nsB version 570

C version 990

tFOutput fall time (3 V to 9 V) CL= 0.1 µF A version 260 nsB version 430

C version 715

tPW Minimum input pulse duration that changes

the output 50 ns

tBS Bootstrap diode reverse recovery time IF= 100 mA, IR= 100 mA 37 ns

Figure 1. Timing Diagram

0.1 1 10 100 1000

FREQUENCY (kHz)

100

1000

10000

100000

CURRENT (PA)

VDD = 12V CL = 4400 pF

CL = 1000 pF

CL = 0 pF

-50 -25 0 25 50 75 100 125 150

TEMPERATURE (oC)

0.7

0.9

1.1

1.3

1.5

1.7

1.9

2.1

2.3

CURRENT (mA)

IDDO

IHBO

02 4 68 10 12

OUTPUT VOLTAGE (V)

0.0

3.5

CURRENT (A)

0.5

1.0

1.5

2.0

2.5

3.0

LM25101B

LM25101C

LM25101A

VDD = 12V

02 4 68 10 12

OUTPUT VOLTAGE (V)

0.0

3.5

CURRENT (A)

0.5

1.0

1.5

2.0

2.5

3.0

LM25101B

LM25101C

LM25101A

VDD = 12V

7 8 9 10 11 12 13 14 15

CURRENT (A)

VDD (V)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

LM25101B

LM25101C

LM25101A

7 8 9 10 11 12 13 14 15

CURRENT (A)

VDD (V)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

LM25101B

LM25101C

LM25101A

LM25101

SNVS859C –JULY 2012–REVISED SEPTEMBER 2016

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Product Folder Links: LM25101

7.7 Typical Characteristics

Figure 2. Peak Sourcing Current vs Supply Voltage Figure 3. Peak Sinking Current vs Supply Voltage

Figure 4. Sink Current vs Output Voltage Figure 5. Source Current vs Output Voltage

Figure 6. IDD vs Frequency Figure 7. Operating Current vs Temperature

-25 0 25 50 75 100 125 150

TEMPERATURE (oC)

0.30

0.35

0.40

0.45

0.50

0.55

0.60

HYSTERESIS (V)

-50

VHBH

VDDH

1.00E-06

1.00E-05

1.00E-04

1.00E-03

1.00E-02

1.00E-01

ID (A)

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

VD (V)

T = 25°C

T = -40°C

T = 150°C

-50 -25 0 25 50 75 100 125 150

TEMPERATURE (°C)

CURRENT (PA)

IDD

IHB

100

150

200

250

300

350

-50 -25 0 25 50 75 100 125 150

TEMPERATURE (°C)

6.30

6.40

6.50

6.60

6.70

6.80

6.90

7.00

7.10

7.20

7.30

THRESHOLD (V)

VHBR

VDDR

0.1 1 10 100 1000

FREQUENCY (kHz)

100

1000

10000

100000

CURRENT (PA)

HB = 12V,

HS = 0V

CL = 0 pF

CL = 4400 pF

CL = 1000 pF

8 9 10 11 12 13 14 15 16

VDD, VHB (V)

100

150

200

250

300

350

400

CURRENT (PA)

IDD

IHB

LM25101

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Typical Characteristics (continued)

Figure 8. IHB vs Frequency Figure 9. Quiescent Current vs Supply Voltage

Figure 10. Quiescent Current vs Temperature Figure 11. Undervoltage Rising Thresholds

vs Temperature

Figure 12. Undervoltage Threshold Hysteresis

vs Temperature Figure 13. Bootstrap Diode Forward Voltage

78 9 10 11 12 13 14

VDD (V)

0.1

0.8

VOH (V)

0.2

0.3

0.4

0.5

0.6

0.7

LM25101B

LM25101C

LM25101A

IOUT = -100 mA

-50 -25 0 25 50 75 100 125 150

VOL (V)

TEMPERATURE (°C)

0.00

0.50

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

LM25101B

LM25101C

LM25101A

VDD = 12V

T_PLH

T_PHL

-50 -25 0 25 50 75 100 125 150

TEMPERATURE (°C)

DELAY (ns)

-50 -25 0 25 50 75 100 125 150

VOH (V)

TEMPERATURE (°C)

0.0

1.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

LM25101B

LM25101C

LM25101A

VDD = 12V

THRESHOLD VOLTAGE (V)

-50 -25 0 25 50 75 100 125 150

TEMPERATURE (°C)

1.80

1.81

1.82

1.83

1.84

1.85

1.86

1.87

1.88

1.89

1.90

1.91

1.92

Rising

Falling

THRESHOLD VOLTAGE (V)

8 9 10 11 12 13 14 15 16

VDD (V)

1.80

1.81

1.82

1.83

1.84

1.85

1.86

1.87

1.88

1.89

1.90

1.91

1.92

Rising

Falling

LM25101

SNVS859C –JULY 2012–REVISED SEPTEMBER 2016

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Typical Characteristics (continued)

Figure 14. Input Threshold vs Temperature Figure 15. Input Threshold vs Supply Voltage

Figure 16. Propagation Delay vs Temperature Figure 17. LO and HO Gate Drive:

High Level Output Voltage vs Temperature

Figure 18. LO and HO Gate Drive:

Low Level Output Voltage vs Temperature Figure 19. LO and HO Gate Drive:

Output High Voltage vs Supply Voltage

78 9 10 11 12 13 14 15

VDD (V)

VOL (V)

0.10

0.15

0.35

0.20

0.25

0.30

LM25101B

LM25101A

IOUT = 100 mA

LM25101C

LM25101

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Typical Characteristics (continued)

Figure 20. LO and HO Gate Drive:

Output Low Voltage vs Supply Voltage

UVLO

DRIVER

UVLO LEVEL

SHIFT

DRIVER

VDD

VSS

LM25101

SNVS859C –JULY 2012–REVISED SEPTEMBER 2016

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Product Folder Links: LM25101

8 Detailed Description

8.1 Overview

To operate fast switching of power MOSFETs at high switching frequencies and to reduce associated switching

losses, a powerful gate driver is employed between the PWM output of controller and the gates of the power

semiconductor devices. Also, gate drivers are indispensable when it is impossible for the PWM controller to

directly drive the gates of the switching devices. With the advent of digital power, this situation is often

encountered because the PWM signal from the digital controller is often a 3.3 V logic signal which cannot

effectively turn on a power switch. Level shift circuitry is needed to boost the 3.3-V signal to the gate-drive

voltage (such as 12 V) in order to fully turn on the power device and minimize conduction losses. Traditional

buffer drive circuits based on NPN or PNP bipolar transistors in totem-pole arrangement prove inadequate with

digital power because they lack level-shifting capability. Gate drivers effectively combine both the level-shifting

and buffer-drive functions. Gate drivers also find other needs such as minimizing the effect of high-frequency

switching noise (by placing the high-current driver IC physically close to the power switch), driving gate-drive

transformers and controlling floating power-device gates, reducing power dissipation and thermal stress in

controllers by moving gate charge power losses from the controller into the driver.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Start-Up and UVLO

Both top and bottom drivers include UVLO protection circuitry which monitors the supply voltage (VDD) and

bootstrap capacitor voltage (VHB-HS) independently. The UVLO circuit inhibits each output until sufficient supply

voltage is available to turn on the external MOSFETs, and the built-in UVLO hysteresis prevents chattering

during supply voltage variations. When the supply voltage is applied to the VDD pin of the LM25101, the top and

bottom gates are held low until VDD exceeds the UVLO threshold, typically about 6.9 V. Any UVLO condition on

the bootstrap capacitor (VHB-HS) will only disable the high-side output (HO).

LM25101

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(1) VHB-HS > VHBR

Table 2. VDD UVLO Feature Logic Operation

CONDITION(1) HI LI HO LO

VDD – VSS < VDDR during device start-up H L L L

VDD – VSS < VDDR during device start-up L H L L

VDD – VSS < VDDR during device start-up H H L L

VDD – VSS < VDDR during device start-up L L L L

VDD – VSS < VDDR – VDDH after device start-up H L L L

VDD – VSS < VDDR – VDDH after device start-up L H L L

VDD – VSS < VDDR – VDDH after device start-up H H L L

VDD – VSS < VDDR – VDDH after device start-up L L L L

(1) VDD>VDDR

Table 3. VHB-HS UVLO Feature Logic Operation

CONDITION(1) HI LI HO LO

VHB→HS < VHBR during device start-up H L L L

VHB–HS < VHBR during device start-up L H L H

VHB–HS < VHBR during device start-up H H L H

VHB–HS < VHBR during device start-up L L L L

VHB–HS < VHBR – VHBH after device start-up H L L L

VHB–HS < VHBR – VHBH after device start-up L H L H

VHB–HS < VHBR – VHBH after device start-up H H L H

VHB–HS < VHBR – VHBH after device start-up L L L L

8.3.2 Level Shift

The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to

the switch node (HS). The level shift allows control of the HO output which is referenced to the HS pin and

provides excellent delay matching with the low-side driver.

8.3.3 Output Stages

The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance,

and high peak current capability of both outputs allow for efficient switching of the power MOSFETs. The low-

side output stage is referenced to VSS and the high-side is referenced to HS.

8.4 Device Functional Modes

The device operates in normal mode and UVLO mode. See Start-Up and UVLO for more information on UVLO

operation mode. In normal mode when the VDD and VHB–HS are above UVLO threshold, the output stage is

dependent on the states of the HI and LI pins. Unused inputs should be tied to ground and not left open.

(1) HO is measured with respect to the HS pin.

(2) LO is measured with respect to the VSS pin.

Table 4. INPUT and OUTPUT Logic Table

HI LI HO(1) LO(2)

LLLL

L H L H

H L H L

HHHH

LM25101

PWM

Controller

VIN

RGATE

CBOOT

0.1µF

1.0µF

VDD

VCC

OUT1

OUT2

VDD

VSS

Optional external

fast recovery diode

RBOOT

RGATE

DBOOT

Anti-Parallel Diode

(Optional)

LM25101

SNVS859C –JULY 2012–REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: LM25101

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LM25101 is a high voltage gate driver designed to drive both the high-side and low-side N-Channel

MOSFETs in a half or full bridge configuration or in a synchronous buck circuit. The floating high side driver is

capable of operating with supply voltages up to 100 V. This allows for N-Channel MOSFETs control in half-

bridge, full-bridge, push-pull, two switch forward, and active clamp topologies. The outputs are independently

controlled. Each channel is controlled by its respective input pins (HI and LI), allowing full and independent

flexibility to control the state (ON and OFF) of the output.

9.2 Typical Application

Figure 21. Application Diagram

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 5 as the input parameters.

Table 5. Design Parameters

PARAMETER EXAMPLE VALUE

Gate driver LM25101 (C version)

MOSFET CSD19534KCS

VDD 10 V

QG17 nC

fSW 500 kHz

OLL LOL Gate FET_Int

IR R R

 

OHL LOH Gate GFET_Int

IR R R

 

DD DH

OLH HOL Gate GFET_Int

V V

IR R R



 

DD DH

OHH Gate GFET_IHOH nt

V V 10V 1.0V

I 0.5A

R R R 1.1V /100mA 4.7 2.2



   :  :

LM25101

www.ti.com

SNVS859C –JULY 2012–REVISED SEPTEMBER 2016

Product Folder Links: LM25101

(1) This value is either provided directly by the data sheet or is estimated from the testing conditions using RHOH = VOHH / IHO.

9.2.2 Detailed Design Procedure

9.2.2.1 Selecting External Gate Driver Resistor

External gate driver resistor (RGATE) is sized to reduce ringing caused by parasitic inductances and capacitances

and also to limit the current coming out of the gate driver.

Peak HO pullup current is calculated using Equation 1.

where

• IOHHis the peak pullup current

• VDHis the bootstrap diode forward voltage drop

• RHOHis the gate driver internal HO pullup resistance (1)

• RGateis the external gate drive resistance

• R(GFET_Int) is the MOSFET internal gate resistance, provided by the transistor data sheet (1)

Similarly, Peak HO pulldown current is calculated using Equation 2.

where

• RHOL is the HO pulldown resistance (2)

Peak LO pullup current is calculated using Equation 3.

where

• RLOH is the LO pullup resistance (3)

Peak LO pulldown current is calculated using Equation 4.

where

• RLOL is the LO pulldown resistance (4)

If the application requires fast turnoff, an anti-paralleled diode on RGate may be used to bypass the external gate

drive resistor and speed up the turnoff transition.

LM25101

SNVS859C –JULY 2012–REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: LM25101

9.2.3 Application Curves

Figure 22 and Figure 23 show the rising and falling time and turnon and turnoff propagation delay testing

waveform at room temperature. Each channel (HI, LI, HO, LO) is labeled and displayed on the left hand of the

waveform.

The HI and LI pins are shorted together for these test waveforms. Therefore, the propagation delay matching

between the channels can be measured and inspected.

CL= 1 nF VDD = 12 V fSW = 500 kHz

Figure 22. Rising Time and Turnon Propagation Delay

CL= 1 nF VDD = 12 V fSW = 500 kHz

Figure 23. Falling Time and Turnoff Propagation Delay

10 Power Supply Recommendations

The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate

driver losses are related to the switching frequency (f), output load capacitance on LO and HO (CL), and supply

voltage (VDD), which can be roughly calculated using Equation 5.

PDGATES = 2 × f × CL× VDD2(5)

There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and

HO outputs. Figure 24 shows the measured gate driver power dissipation versus frequency and load

capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the

power losses driving the output loads and agrees well with Equation 5.Figure 24 can be used to approximate the

power losses due to the gate drivers.

The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the

bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these

events happens once per cycle, the diode power loss is proportional to frequency. Larger capacitive loads

require more energy to recharge the bootstrap capacitor resulting in more losses. Higher input voltages (VIN) to

the half bridge result in higher reverse recovery losses. Figure 25 was generated based on calculations and lab

measurements of the diode recovery time and current under several operating conditions and can be used to

approximate the diode power dissipation.

The total IC power dissipation can be estimated from these plots by summing the gate drive losses with the

bootstrap diode losses for the intended application.

0.1 1.0 10.0 100.0 1000.0

SWITCHING FREQUENCY (kHz)

0.001

0.010

0.100

1.000

POWER (W)

CL = 4400 pF

CL = 0 pF

CL = 1000 pF

110 100 1000

SWITCHING FREQUENCY (kHz)

POWER (W)

0.001

0.010

0.100

CL = 4400 pF

CL = 0 pF

LM25101

www.ti.com

SNVS859C –JULY 2012–REVISED SEPTEMBER 2016

Product Folder Links: LM25101

VDD = 12 V Neglecting Diode Losses

Figure 24. Gate Driver Power Dissipation (LO + HO)

VIN = 50 V

Figure 25. Diode Power Dissipation

11 Layout

11.1 Layout Guidelines

The optimum performance of high and low-side gate drivers cannot be achieved without following certain

guidelines during circuit-board layout.

• Low ESR and ESL capacitors must be connected close to the IC, between the VDD and VSS pins and

between the HB and HS pins to support the high peak currents being drawn from VDD during start-up of the

external MOSFET.

• To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be

connected between the MOSFET drain and ground (VSS).

• To avoid large negative transients on the switch node (HS pin), the parasitic inductances must be minimized

in the source of the top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier).

• Grounding Considerations:

– The first priority in designing grounding connections is to confine to a minimal physical area the high peak

currents that charge and discharge the MOSFET gate. This decreases the loop inductance and minimizes

noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as possible

to the gate driver.

– The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground

referenced bypass capacitor, and low-side MOSFET body diode. The bootstrap capacitor is recharged on

a cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor. The

recharging occurs in a short time interval and involves high peak current. Minimizing this loop length and

area on the circuit board is important to ensure reliable operation.

Figure 26 shows a recommended layout pattern for the driver. If possible a single layer placement is preferred.

To Hi-Side FET To Low-Side FET

Single Layer

Option

GND

Multi Layer

Option

Recommended Layout for Driver IC and

Passives

VSS

PowerPAD

VDD

LM25101

SNVS859C –JULY 2012–REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: LM25101

11.2 Layout Example

Figure 26. Recommended Layout Pattern

LM25101

www.ti.com

SNVS859C –JULY 2012–REVISED SEPTEMBER 2016

Product Folder Links: LM25101

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.3 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM25101AM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L25101

LM25101AMR/NOPB ACTIVE SO PowerPAD DDA 8 95 RoHS & Green SN Level-3-260C-168 HR -40 to 125 L25101

AMR

LM25101AMRX/NOPB ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green SN Level-3-260C-168 HR -40 to 125 L25101

AMR

LM25101AMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L25101

LM25101ASD-1/NOPB ACTIVE WSON NGT 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 25101A1

LM25101ASD/NOPB ACTIVE WSON DPR 10 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 25101A

LM25101ASDX-1/NOPB ACTIVE WSON NGT 8 4500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 25101A1

LM25101ASDX/NOPB ACTIVE WSON DPR 10 4500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 25101A

LM25101BMA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L25101

BMA

LM25101BMAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L25101

BMA

LM25101BSD/NOPB ACTIVE WSON DPR 10 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 25101B

LM25101BSDX/NOPB ACTIVE WSON DPR 10 4500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 25101B

LM25101CMA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L25101

CMA

LM25101CMAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L25101

CMA

LM25101CMY/NOPB ACTIVE HVSSOP DGN 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 CMYN

LM25101CMYE/NOPB ACTIVE HVSSOP DGN 8 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 CMYN

LM25101CMYX/NOPB ACTIVE HVSSOP DGN 8 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 CMYN

LM25101CSD/NOPB ACTIVE WSON DPR 10 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 25101C

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM25101CSDX/NOPB ACTIVE WSON DPR 10 4500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 25101C

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM25101AMRX/NOPB SO

Power

PAD

DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LM25101AMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LM25101ASD-1/NOPB WSON NGT 8 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LM25101ASD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LM25101ASDX-1/NOPB WSON NGT 8 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LM25101ASDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LM25101BMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LM25101BSD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LM25101BSDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LM25101CMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LM25101CMY/NOPB HVSSOP DGN 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LM25101CMYE/NOPB HVSSOP DGN 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LM25101CMYX/NOPB HVSSOP DGN 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LM25101CSD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LM25101CSDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 6-Sep-2019

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM25101AMRX/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0

LM25101AMX/NOPB SOIC D 8 2500 367.0 367.0 35.0

LM25101ASD-1/NOPB WSON NGT 8 1000 210.0 185.0 35.0

LM25101ASD/NOPB WSON DPR 10 1000 210.0 185.0 35.0

LM25101ASDX-1/NOPB WSON NGT 8 4500 367.0 367.0 35.0

LM25101ASDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0

LM25101BMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0

LM25101BSD/NOPB WSON DPR 10 1000 210.0 185.0 35.0

LM25101BSDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0

LM25101CMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0

LM25101CMY/NOPB HVSSOP DGN 8 1000 210.0 185.0 35.0

LM25101CMYE/NOPB HVSSOP DGN 8 250 210.0 185.0 35.0

LM25101CMYX/NOPB HVSSOP DGN 8 3500 367.0 367.0 35.0

LM25101CSD/NOPB WSON DPR 10 1000 210.0 185.0 35.0

LM25101CSDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 6-Sep-2019

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

6X 0.65

1.95

8X 0.38

0.25

5.05

4.75 TYP

SEATING

PLANE

0.15

0.05

0.25

GAGE PLANE

0 -8

1.1 MAX

0.23

0.13

1.88

1.58

2.0

1.7

B3.1

2.9

NOTE 4

3.1

2.9

NOTE 3

0.7

0.4

PowerPAD VSSOP - 1.1 mm max heightDGN0008A

SMALL OUTLINE PACKAGE

4218836/A 11/2019

0.13 C A B

PIN 1 INDEX AREA

SEE DETAIL A

0.1 C

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-187.

PowerPAD is a trademark of Texas Instruments.

A 20

DETAIL A

TYPICAL

SCALE 4.000

EXPOSED THERMAL PAD

www.ti.com

EXAMPLE BOARD LAYOUT

0.05 MAX

ALL AROUND 0.05 MIN

ALL AROUND

8X (1.4)

8X (0.45)

6X (0.65)

(4.4)

(R0.05) TYP

(2)

NOTE 9

(3)

NOTE 9

(1.22)

(0.55)

( 0.2) TYP

VIA

(1.88)

(2)

PowerPAD VSSOP - 1.1 mm max heightDGN0008A

SMALL OUTLINE PACKAGE

4218836/A 11/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

9. Size of metal pad may vary due to creepage requirement.

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 15X

SYMM

SOLDER MASK

DEFINED PAD

METAL COVERED

BY SOLDER MASK

SEE DETAILS

15.000

METAL

SOLDER MASK

OPENING METAL UNDER

SOLDER MASK SOLDER MASK

OPENING

EXPOSED METAL

SOLDER MASK DETAILS

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

8X (1.4)

8X (0.45)

6X (0.65)

(4.4)

(R0.05) TYP

(1.88)

BASED ON

0.125 THICK

STENCIL

(2)

BASED ON

0.125 THICK

STENCIL

PowerPAD VSSOP - 1.1 mm max heightDGN0008A

SMALL OUTLINE PACKAGE

4218836/A 11/2019

1.59 X 1.690.175 1.72 X 1.830.15 1.88 X 2.00 (SHOWN)0.125 2.10 X 2.240.1

SOLDER STENCIL

OPENING

STENCIL

THICKNESS

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

11. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

EXPOSED PAD 9:

100% PRINTED SOLDER COVERAGE BY AREA

SCALE: 15X

SYMM

METAL COVERED

BY SOLDER MASK SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

www.ti.com

PACKAGE OUTLINE

6X 1.27

8X 0.51

0.31

3.81

TYP

0.25

0.10

0 - 8 0.15

0.00

2.71

2.11

3.4

2.8 0.25

GAGE PLANE

1.27

0.40

4214849/A 08/2016

PowerPAD SOIC - 1.7 mm max heightDDA0008B

PLASTIC SMALL OUTLINE

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MS-012.

PowerPAD is a trademark of Texas Instruments.

0.25 C A B

PIN 1 ID

AREA

NOTE 4

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.400

EXPOSED

THERMAL PAD

TYP

6.2

5.8

1.7 MAX

NOTE 3

5.0

4.8

B4.0

3.8

www.ti.com

EXAMPLE BOARD LAYOUT

(5.4)

(1.3) TYP

( ) TYP

VIA

0.2

(R ) TYP0.05

0.07 MAX

ALL AROUND 0.07 MIN

ALL AROUND

8X (1.55)

8X (0.6)

6X (1.27)

(2.95)

NOTE 9

(4.9)

NOTE 9

(2.71)

(3.4)

SOLDER MASK

OPENING

(1.3)

TYP

4214849/A 08/2016

PowerPAD SOIC - 1.7 mm max heightDDA0008B

PLASTIC SMALL OUTLINE

SYMM

SEE DETAILS

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK

OPENING

METAL COVERED

BY SOLDER MASK

SOLDER MASK

DEFINED PAD

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

PADS 1-8

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

(R ) TYP0.05

8X (1.55)

8X (0.6)

6X (1.27)

(5.4)

(2.71)

(3.4)

BASED ON

0.125 THICK

STENCIL

4214849/A 08/2016

PowerPAD SOIC - 1.7 mm max heightDDA0008B

PLASTIC SMALL OUTLINE

2.29 X 2.870.175 2.47 X 3.100.150 2.71 X 3.40 (SHOWN)0.125 3.03 X 3.800.1

SOLDER STENCIL

OPENING

STENCIL

THICKNESS

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

SYMM

BASED ON

0.125 THICK

STENCIL

BY SOLDER MASK

METAL COVERED SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

www.ti.com

PACKAGE OUTLINE

8X 0.35

0.25

3 0.05

2.4

2.6 0.05

6X 0.8

0.8 MAX

0.05

0.00

8X 0.5

0.3

A4.1

3.9 B

4.1

3.9

(0.2) TYP

WSON - 0.8 mm max heightNGT0008A

PLASTIC SMALL OUTLINE - NO LEAD

4214935/A 08/2020

PIN 1 INDEX AREA

SEATING PLANE

0.08 C

PIN 1 ID 0.1 C A B

0.05 C

THERMAL PAD

EXPOSED

SYMM

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

SCALE 3.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

8X (0.3)

(3)

(3.8)

6X (0.8)

(2.6)

( 0.2) VIA

TYP (1.05)

(1.25)

8X (0.6)

(R0.05) TYP

WSON - 0.8 mm max heightNGT0008A

PLASTIC SMALL OUTLINE - NO LEAD

4214935/A 08/2020

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

SYMM 9

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

SOLDER MASK

OPENING

SOLDER MASK

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

SOLDER MASK

OPENING

SOLDER MASK DETAILS

NON SOLDER MASK

DEFINED

(PREFERRED)

EXPOSED

METAL

www.ti.com

EXAMPLE STENCIL DESIGN

(R0.05) TYP

(1.31)

(0.675)

8X (0.3)

8X (0.6)

(1.15)

(3.8)

(0.755)

6X (0.8)

WSON - 0.8 mm max heightNGT0008A

PLASTIC SMALL OUTLINE - NO LEAD

4214935/A 08/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 9:

77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

SYMM

METAL

TYP

SYMM 9

MECHANICAL DATA

DPR0010A

www.ti.com

SDC10A (Rev A)

www.ti.com

PACKAGE OUTLINE

.228-.244 TYP

[5.80-6.19]

.069 MAX

[1.75]

6X .050

[1.27]

8X .012-.020

[0.31-0.51]

.150

[3.81]

.005-.010 TYP

[0.13-0.25]

0 - 8 .004-.010

[0.11-0.25]

.010

[0.25]

.016-.050

[0.41-1.27]

4X (0 -15 )

.189-.197

[4.81-5.00]

NOTE 3

B .150-.157

[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)

[1.04]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

.010 [0.25] C A B

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.800

www.ti.com

EXAMPLE BOARD LAYOUT

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

(.213)

[5.4]

6X (.050 )

[1.27]

8X (.061 )

[1.55]

8X (.024)

[0.6]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED

METAL

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SYMM

SEE

DETAILS

SYMM

www.ti.com

EXAMPLE STENCIL DESIGN

8X (.061 )

[1.55]

8X (.024)

[0.6]

6X (.050 )

[1.27] (.213)

[5.4]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

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