TPA2010D1 www.ti.com SLOS417C - OCTOBER 2003 - REVISED SEPTEMBER 2007 2.5-W MONO FILTER-FREE CLASS-D AUDIO POWER AMPLIFIER FEATURES APPLICATIONS * Maximum Battery Life and Minimum Heat - Efficiency With an 8- Speaker: - 88% at 400 mW - 80% at 100 mW - 2.8-mA Quiescent Current - 0.5-A Shutdown Current * Only Three External Components - Optimized PWM Output Stage Eliminates LC Output Filter - Internally Generated 250-kHz Switching Frequency Eliminates Capacitor and Resistor - Improved PSRR (-75 dB) and Wide Supply Voltage (2.5 V to 5.5 V) Eliminates Need for a Voltage Regulator - Fully Differential Design Reduces RF Rectification and Eliminates Bypass Capacitor - Improved CMRR Eliminates Two Input Coupling Capacitors * Wafer Chip Scale Packaging (WCSP) - NanoFreeTM Lead-Free (YZF) - NanoStarTM SnPb (YEF) * * * * 1 2 Wireless or Cellular Handsets and PDAs Personal Navigation Devices General Portable Audio Devices Linear Vibrator Drivers SEE ALSO * TPA2032D1, TPA2033D1, TPA2034D1 DESCRIPTION The TPA2010D1 (sometimes referred to as TPA2010) is a 2.5-W high efficiency filter-free class-D audio power amplifier (class-D amp) in a 1,45 mm x 1,45 mm wafer chip scale package (WCSP) that requires only three external components. Features like 88% efficiency, -75-dB PSRR, improved RF-rectification immunity, and 8 mm2 total PCB area make the TPA2010D1 (TPA2010) class-D amp ideal for cellular handsets. A fast start-up time of 1 ms with minimal pop makes the TPA2010D1 (TPA2010) ideal for PDA applications. In cellular handsets, the earpiece, speaker phone, and melody ringer can each be driven by the TPA2010D1. The TPA2010D1 allows independent gain while summing signals from seperate sources, and has a low 36 V noise floor, A-weighted. APPLICATION CIRCUIT To Battery Internal Oscillator + RI Differential Input - RI VDD CS IN_ PWM 9-BALL WAFER CHIP SCALE YZF, YEF PACKAGES TPA2010D1 DIMENSIONS (TOP VIEW OF PCB) VO+ HBridge VO- + 1,55 mm 1,40 mm IN+ IN+ GND A1 A2 A3 VDD PVDD GND B2 B3 B1 VO- GND SHUTDOWN Bias Circuitry INTPA2010D1 C1 SHUTDOWN VO+ C2 C3 1,55 mm 1,40 mm Note: Pin A1 is marked with a "0" for Pb-free (YZF) and a "1" for SnPb (YEF). 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree, NanoStar are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2003-2007, Texas Instruments Incorporated TPA2010D1 www.ti.com SLOS417C - OCTOBER 2003 - REVISED SEPTEMBER 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA PACKAGE -40C to 85C (1) PART NUMBER SYMBOL Wafer chip scale package (YEF) TPA2010D1YEF (1) AJZ Wafer chip scale packaging - Lead free (YZF) TPA2010D1YZF (1) AKO The YEF and YZF packages are only available taped and reeled. To order add the suffix R to the end of the part number for a reel of 3000, or add the suffix T to the end of the part number for a reel of 250 (e.g. TPA2010D1YEFR). ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) TPA2010D1 VDD Supply voltage VI Input voltage In active mode -0.3 V to 6 V In SHUTDOWN mode -0.3 V to 7 V -0.3 V to VDD + 0.3 V Continuous total power dissipation See Dissipation Rating Table TA Operating free-air temperature -40C to 85C TJ Operating junction temperature -40C to 150C Tstg Storage temperature -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) YZF 260C YEF 235C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VDD Supply voltage 2.5 5.5 VIH High-level input voltage SHUTDOWN V 1.3 VDD V VIL Low-level input voltage SHUTDOWN RI Input resistor Gain 20 V/V (26 dB) 0 0.35 VIC Common mode input voltage range VDD = 2.5 V, 5.5 V, CMRR -49 dB 0.5 VDD-0.8 V TA Operating free-air temperature -40 85 C 15 V k PACKAGE DISSIPATION RATINGS (1) 2 PACKAGE DERATING FACTOR (1) TA 25C POWER RATING TA = 70C POWER RATING TA = 85C POWER RATING YEF 7.8 mW/C 780 mW 429 mW 312 mW YZF 7.8 mW/C 780 mW 429 mW 312 mW Derating factor measure with High K board. Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): TPA2010D1 TPA2010D1 www.ti.com SLOS417C - OCTOBER 2003 - REVISED SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS TA = 25C (unless otherwise noted) PARAMETER TEST CONDITIONS TYP MAX 1 25 mV VDD = 2.5 V to 5.5 V -75 -55 dB Common mode rejection ratio VDD = 2.5 V to 5.5 V, VIC = VDD/2 to 0.5 V, VIC = VDD/2 to VDD -0.8 V -68 -49 dB |IIH| High-level input current VDD = 5.5 V, VI = 5.8 V 100 A |IIL| Low-level input current VDD = 5.5 V, VI = -0.3 V 5 A |VOS| Output offset voltage (measured differentially) VI = 0 V, AV = 2 V/V, VDD = 2.5 V to 5.5 V PSRR Power supply rejection ratio CMRR I(Q) Quiescent current I(SD) Shutdown current rDS(on) f(sw) Static drain-source on-state resistance MIN VDD = 5.5 V, no load 3.4 VDD = 3.6 V, no load 2.8 VDD = 2.5 V, no load 2.2 3.2 V(SHUTDOWN)= 0.35 V, VDD = 2.5 V to 5.5 V 0.5 2 VDD = 2.5 V 700 VDD = 3.6 V 500 VDD = 5.5 V 400 4.9 mA A m Output impedance in SHUTDOWN V(SHUTDOWN) = 0.35 V >1 Switching frequency VDD = 2.5 V to 5.5 V 200 250 300 Gain VDD = 2.5 V to 5.5 V 285 kW RI 300 kW RI 315 kW RI Resistance from shutdown to GND UNIT k 300 kHz V V k OPERATING CHARACTERISTICS TA = 25C, Gain = 2 V/V, RL = 8 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VDD = 5 V THD + N = 10%, f = 1 kHz, RL = 4 THD + N = 1%, f = 1 kHz, RL = 4 PO Output power THD + N = 10%, f = 1 kHz, RL = 8 THD + N = 1%, f = 1 kHz, RL = 8 Total harmonic distortion plus noise VDD = 3.6 V 1.3 VDD = 2.5 V 0.52 VDD = 5 V 2.08 VDD = 3.6 V 1.06 VDD = 2.5 V 0.42 VDD = 5 V 1.45 VDD = 3.6 V 0.73 VDD = 2.5 V 0.33 VDD = 5 V 1.19 VDD = 3.6 V 0.59 0.18% VDD = 3.6 V, PO = 0.5 W, RL = 8 , f = 1 kHz 0.19% VDD = 2.5 V, PO = 200 mW, RL = 8 , f = 1 kHz 0.20% f = 217 Hz, V(RIPPLE) = 200 mVpp kSVR Supply ripple rejection ratio SNR Signal-to-noise ratio VDD = 5 V, PO = 1 W, RL = 8 Vn Output voltage noise VDD = 3.6 V, f = 20 Hz to 20 kHz, Inputs ac-grounded with Ci = 2 F No weighting 48 A weighting 36 CMRR Common mode rejection ratio VDD = 3.6 V, VIC = 1 Vpp f = 217 Hz -63 ZI Input impedance 142 VDD = 3.6 V W W W W 0.26 VDD = 5 V, PO = 1 W, RL = 8 , f = 1 kHz VDD = 3.6 V, Inputs ac-grounded with Ci = 2 F Start-up time from shutdown -67 dB 97 dB 150 VRMS dB 158 1 Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): TPA2010D1 UNIT 2.5 VDD = 2.5 V THD+N TYP MAX k ms 3 TPA2010D1 www.ti.com SLOS417C - OCTOBER 2003 - REVISED SEPTEMBER 2007 Terminal Functions TERMINAL NAME YEF, YZF I/O DESCRIPTION IN- C1 I Negative differential input IN+ A1 I Positive differential input VDD B1 I Power supply VO+ C3 O Positive BTL output GND A2, B3 I High-current ground VO- A3 O Negative BTL output SHUTDOWN C2 I Shutdown terminal (active low logic) PVDD B2 I Power supply FUNCTIONAL BLOCK DIAGRAM *Gain = 150 k RI *Gain = 2 V/V B1, B2 VDD 150 k IN- C1 _ + VDD + _ Deglitch Logic Gate Drive + _ Deglitch Logic Gate Drive A3 VO- _ + _ + + _ IN+ A1 150 k C2 SHUTDOWN TTL SD Input Buffer 300 k Notes: * Total gain = 4 2x Biases and References Ramp Generator Startup Protection Logic C3 VO+ OC Detect A2, B3 GND 150 k RI Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): TPA2010D1 TPA2010D1 www.ti.com SLOS417C - OCTOBER 2003 - REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS TABLE OF GRAPHS FIGURE Efficiency vs Output power 1, 2 Power dissipation vs Output power 3, 4 Supply current vs Output power 5, 6 I(Q) Quiescent current vs Supply voltage 7 I(SD) Shutdown current vs Shutdown voltage 8 PD PO Output power THD+N Total harmonic distortion plus noise vs Supply voltage 9 vs Load resistance 10, 11 vs Output power 12, 13 vs Frequency 14, 15, 16, 17 vs Common-mode input voltage KSVR Supply voltage rejection ratio vs Frequency GSM power supply rejection KSVR Supply voltage rejection ratio CMRR Common-mode rejection ratio 18 19, 20, 21 vs Time 22 vs Frequency 23 vs Common-mode input voltage 24 vs Frequency 25 vs Common-mode input voltage 26 TEST SET-UP FOR GRAPHS CI TPA2010D1 RI + Measurement Output - IN+ CI OUT+ Load RI INVDD + OUT- 30 kHz Low Pass Filter + Measurement Input - GND 1 F VDD - Notes: (1) CI was Shorted for any Common-Mode input voltage measurement (2) A 33-H inductor was placed in series with the load resistor to emulate a small speaker for efficiency measurements. (3) The 30-kHz low-pass filter is required even if the analyzer has an internal low-pass filter. An RC low pass filter (100 , 47 nF) is used on each output for the data sheet graphs. Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): TPA2010D1 5 TPA2010D1 www.ti.com SLOS417C - OCTOBER 2003 - REVISED SEPTEMBER 2007 EFFICIENCY vs OUTPUT POWER 90 90 80 VDD = 5 V, RL = 8 , 33 H 70 60 50 40 Class AB. VDD = 5 V, RL = 8 30 20 40 Class AB. VDD = 5 V, RL = 4 20 0 0.2 0.4 0.6 1 0.8 0 1.2 VDD = 5 V, RL = 4 , 0.4 0.2 VDD = 5 V, RL = 8 0 1.2 1.4 1.6 1.8 2 0 0.5 1 1.5 2 Figure 1. Figure 2. Figure 3. POWER DISSIPATION vs OUTPUT POWER SUPPLY CURRENT vs OUTPUT POWER SUPPLY CURRENT vs OUTPUT POWER Class-AB 3.6 V, 8 0.4 0.3 VDD = 3.6 V, RL = 4 0.2 0.1 VDD = 3.6 V, RL = 8 , 33 H 0 0.2 0.4 0.6 0.8 1 400 VDD = 2.5 V 300 200 100 VDD = 5 V, VDD = 3.6 V 200 150 100 VDD = 2.5 V 50 VDD = 5 V 0 0.5 1 1.5 2 0 2.5 0.2 0.4 0.6 0.8 1.2 1 PO - Output Power - W PO - Output Power - W PO - Output Power - W Figure 4. Figure 5. Figure 6. SUPPLY CURRENT vs SUPPLY VOLTAGE SUPPLY CURRENT vs SHUTDOWN VOLTAGE OUTPUT POWER vs LOAD RESISTANCE RL = 8 , (resistive) RL = 8 , 33 H 3.5 3 2.5 1.5 VDD = 5 V 1 VDD = 3.6 V VDD = 2.5 V 0.5 4.5 5 5.5 VDD - Supply Voltage - V Figure 7. VDD = 3.6 V 1.5 VDD = 2.5 V 1 0 0 4 VDD = 5 V 2 0.5 No Load 3.5 PO at 10% THD Gain = 2 V/V f = 1 kHz 2.5 PO - Output Power - W I (SD) - Shutdown Current - A 4.5 1.4 3 2 5 3 RL = 8 , 33 H 0 0 1.2 2.5 250 VDD = 3.6 V I DD - Supply Current - mA I DD - Supply Current - mA 0.5 300 RL = 4 , 33 H 500 Class-AB 3.6 V, 4 2 2.5 0.6 PO - Output Power - W 0.6 4 Class-AB 5 V, 8 0.8 PO - Output Power - W 600 0 0.2 0.4 0.6 0.8 1 1 PO - Output Power - W 0.7 P D - Power Dissipation - W VDD = 2.5 V, RL = 4 , 33 H 50 10 0 0 I DD - Supply Current - mA VDD = 3.6 V, RL = 4 , 33 H Class-AB 5 V, 4 1.2 VDD = 5 V, RL = 4 , 33 H 60 30 10 6 1.4 70 Efficiency - % VDD = 2.5 V, RL = 8 , 33 H POWER DISSIPATION vs OUTPUT POWER P D - Power Dissipation - W 100 80 Efficiency - % EFFICIENCY vs OUTPUT POWER 0 0.1 0.2 0.3 0.4 Shutdown Voltage - V Figure 8. Submit Documentation Feedback 0.5 4 8 12 16 20 24 28 32 RL - Load Resistance - Figure 9. Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): TPA2010D1 TPA2010D1 www.ti.com SLOS417C - OCTOBER 2003 - REVISED SEPTEMBER 2007 3 2.5 VDD = 5 V PO at 1% THD Gain = 2 V/V f = 1 kHz 1.5 VDD = 3.6 V 1 Gain = 2 V/V f = 1 kHz 2.5 PO - Output Power - W VDD = 2.5 V 0.5 RL = 4 , 10% THD 2 RL = 4 , 1% THD 1.5 1 RL = 8 ,10% THD 0.5 0 2.5 0 4 8 12 16 20 24 RL - Load Resistance - 28 32 RL = 8 ,1% THD 3 3.5 4 4.5 VCC - Supply Voltage - V 5 20 RL = 4 , f = 1 kHz, Gain = 2 V/V 10 5 2.5 V 3V 2 3.6 V 1 5V 0.5 0.2 0.1 20m 50m 100m 200m 500m 1 PO - Output Power - W 2 3 Figure 11. Figure 12. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 20 RL = 8 , f = 1 kHz, Gain = 2 V/V 10 5 2.5 V 3V 3.6 V 2 5V 1 0.5 0.2 0.1 5m 10m 20m 50m 100m 200m 500m 1 2 THD+N - Total Harmonic Distortion + Noise - % Figure 10. 10 VDD = 5 V CI = 2 F RL = 8 Gain = 2 V/V 5 2 PO = 50 mW PO = 250 mW 1 0.5 PO = 1W 0.2 0.1 0.05 0.02 VDD = 3.6 V CI = 2 F RL = 8 Gain = 2 V/V 5 2 PO = 25 mW PO = 125 mW 1 0.5 PO = 500 mW 0.2 0.1 0.05 0.02 0.01 0.005 0.01 20 PO - Output Power - W 10 THD+N - Total Harmonic Distortion + Noise - % PO - Output Power - W 2 THD+N - Total Harmonic Distortion + Noise - % TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE THD+N - Total Harmonic Distortion + Noise - % OUTPUT POWER vs LOAD RESISTANCE 50 100 200 500 1k 2k 5k 10k 20k 20 50 100 200 500 1k 2k f - Frequency - Hz 5k 10k 20k Figure 15. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs COMMON MODE INPUT VOLTAGE 10 VDD = 2.5 V CI = 2 F RL = 8 Gain = 2 V/V 5 2 PO = 15 mW PO = 75 mW 1 0.5 PO = 200 mW 0.2 0.1 0.05 0.02 0.01 20 50 100 200 500 1k 2k 5k 10k 20k f - Frequency - Hz Figure 16. 10 PO = 250 mW CI = 2 F RL = 4 Gain = 2 V/V 5 2 1 VDD = 3.6 V VDD = 3 V 0.5 0.2 VDD = 2.5 V 0.1 0.05 0.02 0.01 VDD = 4 V 20 50 100 200 VDD = 5 V 500 1k 2k 5k 10k 20k f - Frequency - Hz Figure 17. THD+N - Total Harmonic Distortion + Noise - % Figure 14. THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % f - Frequency - Hz Figure 13. 10 f = 1 kHz PO = 200 mW VDD = 2.5 V 1 VDD = 5 V VDD = 3.6 V 0.1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 Figure 18. Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): TPA2010D1 5 VIC - Common Mode Input Voltage - V 7 TPA2010D1 www.ti.com SLOS417C - OCTOBER 2003 - REVISED SEPTEMBER 2007 SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY -30 Inputs ac-grounded CI = 2 F RL = 8 Gain = 2 V/V -50 VDD = 2. 5 V VDD = 3.6 V -60 -70 -80 -30 Inputs ac-grounded CI = 2 F RL = 4 Gain = 2 V/V -40 VDD = 2.5 V -50 -60 VDD = 3.6 V -70 -80 100 1k VDD = 5 V -60 -70 VDD = 3.6 V -80 VDD = 2.5 V -90 20 -50 VDD = 5 V VDD = 5 V -90 Inputs floating RL = 8 -40 -90 20 10 k 20 k 100 1k 20 10 k 20 k 100 Figure 19. 1k 10 k 20 k f - Frequency - Hz f - Frequency - Hz f - Frequency - Hz Figure 20. GSM POWER SUPPLY REJECTION vs TIME GSM POWER SUPPLY REJECTION vs FREQUENCY 0 C1 - High 3.6 V -50 C1 - Amp 512 mV -100 VO - Output Voltage - dBV VDD 200 mV/div C1 - Duty 12% VOUT 20 mV/div 0 VDD Shown in Figure 22 CI = 2 F, Inputs ac-grounded Gain = 2V/V -50 -100 -150 0 400 t - Time - 2 ms/div 800 -40 VDD = 3.6 V VDD = 2. 5 V -50 VDD = 5 V -60 -70 -80 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 DC Common Mode Voltage - V Figure 24. 8 2000 -50 VIC = 200 mVPP RL = 8 Gain = 2 V/V -55 -60 VDD = 3.6 V -65 -70 -75 20 100 1k f - Frequency - Hz 10 k 20 k Figure 25. Submit Documentation Feedback COMMON-MODE REJECTION RATIO vs COMMON-MODE INPUT VOLTAGE CMRR - Common Mode Rejection Ratio - dB -30 COMMON-MODE REJECTION RATIO vs FREQUENCY CMRR - Common Mode Rejection Ratio - dB Sopply Ripple Rejection Ratio - dB -20 1600 Figure 23. SUPPLY RIPPLE REJECTION RATIO vs DC COMMON MODE VOLTAGE 0 1200 f - Frequency - Hz Figure 22. -10 -150 V DD - Supply Voltage - dBV -40 Sopply Ripple Rejection Ratio - dB Sopply Ripple Rejection Ratio - dB -30 SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY Sopply Ripple Rejection Ratio - dB SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY 0 -10 -20 -30 -40 VDD = 3.6 V VDD = 2.5 V -50 -60 -70 -80 VDD = 5 V, Gain = 2 -90 -100 0 1 2 3 4 5 VIC - Common Mode Input Voltage - V Figure 26. Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): TPA2010D1 TPA2010D1 www.ti.com SLOS417C - OCTOBER 2003 - REVISED SEPTEMBER 2007 APPLICATION INFORMATION FULLY DIFFERENTIAL AMPLIFIER The TPA2010D1 is a fully differential amplifier with differential inputs and outputs. The fully differential amplifier consists of a differential amplifier and a common-mode amplifier. The differential amplifier ensures that the amplifier outputs a differential voltage on the output that is equal to the differential input times the gain. The common-mode feedback ensures that the common-mode voltage at the output is biased around VDD/2 regardless of the common-mode voltage at the input. The fully differential TPA2010D1 can still be used with a single-ended input; however, the TPA2010D1 should be used with differential inputs when in a noisy environment, like a wireless handset, to ensure maximum noise rejection. Advantages of Fully DIfferential Amplifiers * Input-coupling capacitors not required: - The fully differential amplifier allows the inputs to be biased at voltage other than mid-supply. For example, if a codec has a midsupply lower than the midsupply of the TPA2010D1, the common-mode feedback circuit will adjust, and the TPA2010D1 outputs will still be biased at midsupply of the TPA2010D1. The inputs of the TPA2010D1 can be biased from 0.5 V to VDD -0.8 V. If the inputs are biased outside of that range, input-coupling capacitors are required. * Midsupply bypass capacitor, C(BYPASS), not required: - The fully differential amplifier does not require a bypass capacitor. This is because any shift in the midsupply affects both positive and negative channels equally and cancels at the differential output. * Better RF-immunity: - GSM handsets save power by turning on and shutting off the RF transmitter at a rate of 217 Hz. The transmitted signal is picked-up on input and output traces. The fully differential amplifier cancels the signal much better than the typical audio amplifier. COMPONENT SELECTION Figure 27 shows the TPA2010D1 typical schematic with differential inputs and Figure 28 shows the TPA2010D1 with differential inputs and input capacitors, and Figure 29 shows the TPA2010D1 with single-ended inputs. Differential inputs should be used whenever possible because the single-ended inputs are much more susceptible to noise. Table 1. Typical Component Values (1) REF DES VALUE EIA SIZE MANUFACTURER RI 150 k (0.5%) 0402 Panasonic PART NUMBER ERJ2RHD154V CS 1 F (+22%, -80%) 0402 Murata GRP155F50J105Z CI (1) 3.3 nF (10%) 0201 Murata GRP033B10J332K CI is only needed for single-ended input or if VICM is not between 0.5 V and VDD - 0.8 V. CI = 3.3 nF (with RI = 150 k) gives a high-pass corner frequency of 321 Hz. Input Resistors (RI) The input resistors (RI) set the gain of the amplifier according to Equation 1. V Gain + 2 x 150 kW R V I (1) Resistor matching is very important in fully differential amplifiers. The balance of the output on the reference voltage depends on matched ratios of the resistors. CMRR, PSRR, and cancellation of the second harmonic distortion diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or better to keep the performance optimized. Matching is more important than overall tolerance. Resistor arrays with 1% matching can be used with a tolerance greater than 1%. Place the input resistors very close to the TPA2010D1 to limit noise injection on the high-impedance nodes. For optimal performance the gain should be set to 2 V/V or lower. Lower gain allows the TPA2010D1 to operate at its best, and keeps a high voltage at the input making the inputs less susceptible to noise. Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): TPA2010D1 9 TPA2010D1 www.ti.com SLOS417C - OCTOBER 2003 - REVISED SEPTEMBER 2007 Decoupling Capacitor (CS) The TPA2010D1 is a high-performance class-D audio amplifier that requires adequate power supply decoupling to ensure the efficiency is high and total harmonic distortion (THD) is low. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 1 F, placed as close as possible to the device VDD lead works best. Placing this decoupling capacitor close to the TPA2010D1 is very important for the efficiency of the class-D amplifier, because any resistance or inductance in the trace between the device and the capacitor can cause a loss in efficiency. For filtering lower-frequency noise signals, a 10 F or greater capacitor placed near the audio power amplifier would also help, but it is not required in most applications because of the high PSRR of this device. Input Capacitors (CI) The TPA2010D1 does not require input coupling capacitors if the design uses a differential source that is biased from 0.5 V to VDD -0.8 V (shown in Figure 27). If the input signal is not biased within the recommended common-mode input range, if needing to use the input as a high pass filter (shown in Figure 28), or if using a single-ended source (shown in Figure 29), input coupling capacitors are required. The input capacitors and input resistors form a high-pass filter with the corner frequency, fc, determined in Equation 2. 1 fc + 2p R C I I (2) The value of the input capacitor is important to consider as it directly affects the bass (low frequency) performance of the circuit. Speakers in wireless phones cannot usually respond well to low frequencies, so the corner frequency can be set to block low frequencies in this application. Equation 3 is reconfigured to solve for the input coupling capacitance. 1 C + I 2p R f c I (3) If the corner frequency is within the audio band, the capacitors should have a tolerance of 10% or better, because any mismatch in capacitance causes an impedance mismatch at the corner frequency and below. For a flat low-frequency response, use large input coupling capacitors (1 F). However, in a GSM phone the ground signal is fluctuating at 217 Hz, but the signal from the codec does not have the same 217 Hz fluctuation. The difference between the two signals is amplified, sent to the speaker, and heard as a 217 Hz hum. To Battery Internal Oscillator + RI - SHUTDOWN RI CS IN_ Differential Input VDD PWM HBridge VO+ VO- + IN+ GND Bias Circuitry TPA2010D1 Filter-Free Class D Figure 27. Typical TPA2010D1 Application Schematic With Differential Input for a Wireless Phone 10 Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): TPA2010D1 TPA2010D1 www.ti.com SLOS417C - OCTOBER 2003 - REVISED SEPTEMBER 2007 To Battery Internal Oscillator CI RI CI CS INPWM _ Differential Input VDD HBridge VO- + RI VO+ IN+ GND Bias Circuitry SHUTDOWN TPA2010D1 Filter-Free Class D Figure 28. TPA2010D1 Application Schematic With Differential Input and Input Capacitors To Battery Internal Oscillator CI RI Single-ended Input VDD CS IN_ PWM HBridge VO- + RI VO+ IN+ CI GND Bias Circuitry SHUTDOWN TPA2010D1 Filter-Free Class D Figure 29. TPA2010D1 Application Schematic With Single-Ended Input SUMMING INPUT SIGNALS WITH THE TPA2010D1 Most wireless phones or PDAs need to sum signals at the audio power amplifier or just have two signal sources that need separate gain. The TPA2010D1 makes it easy to sum signals or use separate signal sources with different gains. Many phones now use the same speaker for the earpiece and ringer, where the wireless phone would require a much lower gain for the phone earpiece than for the ringer. PDAs and phones that have stereo headphones require summing of the right and left channels to output the stereo signal to the mono speaker. Summing Two Differential Input Signals Two extra resistors are needed for summing differential signals (a total of 5 components). The gain for each input source can be set independently (see Equation 4 and Equation 5, and Figure 30). V V Gain 1 + O + 2 x 150 kW V R V I1 I1 (4) V V Gain 2 + O + 2 x 150 kW V R V I2 I2 (5) If summing left and right inputs with a gain of 1 V/V, use RI1 = RI2 = 300 k. Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): TPA2010D1 11 TPA2010D1 www.ti.com SLOS417C - OCTOBER 2003 - REVISED SEPTEMBER 2007 If summing a ring tone and a phone signal, set the ring-tone gain to Gain 2 = 2 V/V, and the phone gain to gain 1 = 0.1 V/V. The resistor values would be. . . RI1 = 3 M, and = RI2 = 150 k. Differential Input 1 + RI1 - RI1 + RI2 To Battery Internal Oscillator Differential Input 2 RI2 CS IN_ - VDD PWM HBridge VO+ VO- + IN+ GND SHUTDOWN Bias Circuitry Filter-Free Class D Figure 30. Application Schematic With TPA2010D1 Summing Two Differential Inputs Summing a Differential Input Signal and a Single-Ended Input Signal Figure 31 shows how to sum a differential input signal and a single-ended input signal. Ground noise can couple in through IN+ with this method. It is better to use differential inputs. The corner frequency of the single-ended input is set by CI2, shown in Equation 8. To assure that each input is balanced, the single-ended input must be driven by a low-impedance source even if the input is not in use V V Gain 1 + O + 2 x 150 kW V R V I1 I1 (6) V V Gain 2 + O + 2 x 150 kW V R V I2 I2 (7) 1 C + I2 2p RI2 f c2 (8) If summing a ring tone and a phone signal, the phone signal should use a differential input signal while the ring tone might be limited to a single-ended signal. Phone gain is set at gain 1 = 0.1 V/V, and the ring-tone gain is set to gain 2 = 2 V/V, the resistor values would be... RI1 = 3 M, and = RI2 = 150 k. The high pass corner frequency of the single-ended input is set by CI2. If the desired corner frequency is less than 20 Hz... 12 Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): TPA2010D1 TPA2010D1 www.ti.com C I2 C I2 u SLOS417C - OCTOBER 2003 - REVISED SEPTEMBER 2007 1 2p 150kW 20Hz (9) u 53 nF (10) RI1 Differential Input 1 Single-Ended Input 2 RI1 CI2 R I2 To Battery Internal Oscillator CS IN_ RI2 VDD PWM HBridge VO+ VO- + IN+ CI2 GND Bias Circuitry SHUTDOWN Filter-Free Class D Figure 31. Application Schematic With TPA2010D1 Summing Differential Input and Single-Ended Input Signals Summing Two Single-Ended Input Signals Four resistors and three capacitors are needed for summing single-ended input signals. The gain and corner frequencies (fc1 and fc2) for each input source can be set independently (see Equation 11 through Equation 14, and Figure 32). Resistor, RP, and capacitor, CP, are needed on the IN+ terminal to match the impedance on the IN- terminal. The single-ended inputs must be driven by low impedance sources even if one of the inputs is not outputting an ac signal. V V Gain 1 + O + 2 x 150 kW V R V I1 I1 (11) V V Gain 2 + O + 2 x 150 kW V R V I2 I2 (12) 1 C + I1 2p R f I1 c1 (13) 1 C + I2 2p R f I2 c2 (14) C +C ) C P I1 I2 (15) R R I2 R + I1 P R ) R I1 I2 (16) Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): TPA2010D1 13 TPA2010D1 www.ti.com SLOS417C - OCTOBER 2003 - REVISED SEPTEMBER 2007 Single-Ended Input 1 Single-Ended Input 2 CI1 R I1 To Battery CI2 R I2 Internal Oscillator CS IN_ RP VDD PWM VO+ HBridge VO- + IN+ CP GND SHUTDOWN Bias Circuitry Filter-Free Class D Figure 32. Application Schematic With TPA2010D1 Summing Two Single-Ended Inputs BOARD LAYOUT In making the pad size for the WCSP balls, it is recommended that the layout use nonsolder mask defined (NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and the opening size is defined by the copper pad width. Figure 33 and Table 2 show the appropriate diameters for a WCSP layout. The TPA2010D1 evaluation module (EVM) layout is shown in the next section as a layout example. Copper Trace Width Solder Pad Width Solder Mask Opening Copper Trace Thickness Solder Mask Thickness Figure 33. Land Pattern Dimensions 14 Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): TPA2010D1 TPA2010D1 www.ti.com SLOS417C - OCTOBER 2003 - REVISED SEPTEMBER 2007 Table 2. Land Pattern Dimensions SOLDER PAD DEFINITIONS COPPER PAD SOLDER MASK OPENING COPPER THICKNESS STENCIL OPENING STENCIL THICKNESS Nonsolder mask defined (NSMD) 275 m (+0.0, -25 m) 375 m (+0.0, -25 m) 1 oz max (32 m) 275 m x 275 m Sq. (rounded corners) 125 m thick NOTES: 1. Circuit traces from NSMD defined PWB lands should be 75 m to 100 m wide in the exposed area inside the solder mask opening. Wider trace widths reduce device stand off and impact reliability. 2. Recommend solder paste is Type 3 or Type 4. 3. Best reilability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the intended application. 4. For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 m to avoid a reduction in thermal fatigue performance. 5. Solder mask thickness should be less than 20 m on top of the copper circuit pattern. 6. Best solder stencil preformance is achieved using laser cut stencils with electro polishing. Use of chemically etched stencils results in inferior solder paste volume control. 7. Trace routing away from WCSP device should be balanced in X and Y directions to avoid unintentional component movement due to solder wetting forces. Component Location Place all the external components very close to the TPA2010D1. The input resistors need to be very close to the TPA2010D1 input pins so noise does not couple on the high impedance nodes between the input resistors and the input amplifier of the TPA2010D1. Placing the decoupling capacitor, CS, close to the TPA2010D1 is important for the efficiency of the class-D amplifier. Any resistance or inductance in the trace between the device and the capacitor can cause a loss in efficiency. Trace Width Recommended trace width at the solder balls is 75 m to 100 m to prevent solder wicking onto wider PCB traces. Figure 34 shows the layout of the TPA2010D1 evaluation module (EVM). For high current pins (VDD, GND VO+, and VO-) of the TPA2010D1, use 100-m trace widths at the solder balls and at least 500-m PCB traces to ensure proper performance and output power for the device. For input pins (IN-, IN+, and SHUTDOWN) of the TPA2010D1, use 75-m to 100-m trace widths at the solder balls. IN- and IN+ pins need to run side-by-side to maximize common-mode noise cancellation. Placing input resistors, RIN, as close to the TPA2010D1 as possible is recommended. Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): TPA2010D1 15 TPA2010D1 www.ti.com SLOS417C - OCTOBER 2003 - REVISED SEPTEMBER 2007 75 mm 100 mm 100 mm 100 mm 375 mm (+0, -25 mm) 275 mm (+0, -25 mm) 100 mm Circular Solder Mask Opening Paste Mask (Stencil) = Copper Pad Size 75 mm 100 mm 75 mm Figure 34. Close Up of TPA2010D1 Land Pattern From TPA2010D1 EVM EFFICIENCY AND THERMAL INFORMATION The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factor for the YEF and YEZ packages are shown in the dissipation rating table. Converting this to JA: 1 1 q + + + 128.2CW JA 0.0078 Derating Factor (17) Given JA of 128.2C/W, the maximum allowable junction temperature of 150C, and the maximum internal dissipation of 0.4 W (2.25 W, 4- load, 5-V supply, from Figure 3), the maximum ambient temperature can be calculated with the following equation. T Max + T Max * q P + 150 * 128.2 (0.4) + 98.72C A J JA Dmax (18) Equation 18 shows that the calculated maximum ambient temperature is 98.72C at maximum power dissipation with a 5-V supply and 4- a load, see Figure 3. The TPA2010D1 is designed with thermal protection that turns the device off when the junction temperature surpasses 165C ~ 190C to prevent damage to the IC. Also, using speakers more resistive than 4- dramatically increases the thermal performance by reducing the output current and increasing the efficiency of the amplifier. ELIMINATING THE OUTPUT FILTER WITH THE TPA2010D1 This section focuses on why the user can eliminate the output filter with the TPA2010D1. 16 Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): TPA2010D1 TPA2010D1 www.ti.com SLOS417C - OCTOBER 2003 - REVISED SEPTEMBER 2007 Effect on Audio The class-D amplifier outputs a pulse-width modulated (PWM) square wave, which is the sum of the switching waveform and the amplified input audio signal. The human ear acts as a band-pass filter such that only the frequencies between approximately 20 Hz and 20 kHz are passed. The switching frequency components are much greater than 20 kHz, so the only signal heard is the amplified input audio signal. Traditional Class-D Modulation Scheme The traditional class-D modulation scheme, which is used in the TPA005Dxx family, has a differential output where each output is 180 degrees out of phase and changes from ground to the supply voltage, VDD. Therefore, the differential pre-filtered output varies between positive and negative VDD, where filtered 50% duty cycle yields 0 volts across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in Figure 35. Note that even at an average of 0 volts across the load (50% duty cycle), the current to the load is high causing a high loss and thus causing a high supply current. OUT+ OUT+5 V Differential Voltage Across Load 0V -5 V Current Figure 35. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms Into an Inductive Load With no Input TPA2010D1 Modulation Scheme The TPA2010D1 uses a modulation scheme that still has each output switching from 0 to the supply voltage. However, OUT+ and OUT- are now in phase with each other with no input. The duty cycle of OUT+ is greater than 50% and OUT- is less than 50% for positive voltages. The duty cycle of OUT+ is less than 50% and OUT- is greater than 50% for negative voltages. The voltage across the load sits at 0 volts throughout most of the switching period greatly reducing the switching current, which reduces any I2R losses in the load. Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): TPA2010D1 17 TPA2010D1 www.ti.com SLOS417C - OCTOBER 2003 - REVISED SEPTEMBER 2007 OUT+ OUTDifferential Voltage Across Load Output = 0 V +5 V 0V -5 V Current OUT+ OUTDifferential Voltage Output > 0 V +5 V 0V Across Load -5 V Current Figure 36. The TPA2010D1 Output Voltage and Current Waveforms Into an Inductive Load Efficiency: Why You Must Use a Filter With the Traditional Class-D Modulation Scheme The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is large for the traditional modulation scheme because the ripple current is proportional to voltage multiplied by the time at that voltage. The differential voltage swing is 2 x VDD and the time at each voltage is half the period for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive, whereas an LC filter is almost purely reactive. The TPA2010D1 modulation scheme has very little loss in the load without a filter because the pulses are very short and the change in voltage is VDD instead of 2 x VDD. As the output power increases, the pulses widen making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most applications the filter is not needed. An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow through the filter instead of the load. The filter has less resistance than the speaker that results in less power dissipated, which increases efficiency. Effects of Applying a Square Wave Into a Speaker If the amplitude of a square wave is high enough and the frequency of the square wave is within the bandwidth of the speaker, a square wave could cause the voice coil to jump out of the air gap and/or scar the voice coil. A 250-kHz switching frequency, however, is not significant because the speaker cone movement is proportional to 1/f2 for frequencies beyond the audio band. Therefore, the amount of cone movement at the switching frequency is very small. However, damage could occur to the speaker if the voice coil is not designed to handle the additional power. To size the speaker for added power, the ripple current dissipated in the load needs to be calculated by subtracting the theoretical supplied power, PSUP THEORETICAL, from the actual supply power, PSUP, at maximum output power, POUT. The switching power dissipated in the speaker is the inverse of the measured efficiency, MEASURED, minus the theoretical efficiency, THEORETICAL. 18 Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): TPA2010D1 TPA2010D1 www.ti.com P SLOS417C - OCTOBER 2003 - REVISED SEPTEMBER 2007 (at max output power) SUP THEORETICAL P P P + SUP - SUP THEORETICAL (at max output power) SPKR P P OUT OUT P SPKR SPKR +P +P SUP -P (19) (20) 1 1 * (at max output power) OUT h MEASURED h THEORETICAL (21) R hTHEORETICAL + R L (at max output power) ) 2r L DS(on) (22) The maximum efficiency of the TPA2010D1 with a 3.6 V supply and an 8- load is 86% from Equation 22. Using equation Equation 21 with the efficiency at maximum power (84%), we see that there is an additional 17 mW dissipated in the speaker. The added power dissipated in the speaker is not an issue as long as it is taken into account when choosing the speaker. When to Use an Output Filter Design the TPA2010D1 without an output filter if the traces from amplifier to speaker are short. The TPA2010D1 passed FCC and CE radiated emissions with no shielding with speaker trace wires 100 mm long or less. Wireless handsets and PDAs are great applications for class-D without a filter. A ferrite bead filter can often be used if the design is failing radiated emissions without an LC filter, and the frequency sensitive circuit is greater than 1 MHz. This is good for circuits that just have to pass FCC and CE because FCC and CE only test radiated emissions greater than 30 MHz. If choosing a ferrite bead, choose one with high impedance at high frequencies, but very low impedance at low frequencies. Use an LC output filter if there are low frequency (< 1 MHz) EMI sensitive circuits and/or there are long leads from amplifier to speaker. Figure 37 and Figure 38 show typical ferrite bead and LC output filters. Ferrite Chip Bead OUTP 1 nF Ferrite Chip Bead OUTN 1 nF Figure 37. Typical Ferrite Chip Bead Filter (Chip bead example: NEC/Tokin: N2012ZPS121) 33 H OUTP 1 F 33 H OUTN 1 F Figure 38. Typical LC Output Filter, Cutoff Frequency of 27 kHz Submit Documentation Feedback Copyright (c) 2003-2007, Texas Instruments Incorporated Product Folder Link(s): TPA2010D1 19 PACKAGE OPTION ADDENDUM www.ti.com 5-Sep-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPA2010D1YEFR NRND DSBGA YEF 9 TBD Call TI Call TI TPA2010D1YEFT NRND DSBGA YEF 9 TBD Call TI Call TI TPA2010D1YZFR ACTIVE DSBGA YZF 9 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM TPA2010D1YZFT ACTIVE DSBGA YZF 9 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 10-Oct-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) TPA2010D1YZFR DSBGA YZF 9 3000 180.0 8.4 TPA2010D1YZFR DSBGA YZF 9 3000 180.0 TPA2010D1YZFT DSBGA YZF 9 250 180.0 TPA2010D1YZFT DSBGA YZF 9 250 180.0 1.65 1.65 0.81 4.0 8.0 Q1 8.4 1.65 1.65 0.81 4.0 8.0 Q1 8.4 1.65 1.65 0.81 4.0 8.0 Q1 8.4 1.65 1.65 0.81 4.0 8.0 Q1 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 10-Oct-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPA2010D1YZFR DSBGA YZF 9 3000 210.0 185.0 35.0 TPA2010D1YZFR DSBGA YZF 9 3000 220.0 220.0 34.0 TPA2010D1YZFT DSBGA YZF 9 250 210.0 185.0 35.0 TPA2010D1YZFT DSBGA YZF 9 250 220.0 220.0 34.0 Pack Materials-Page 2 D: Max = 1.482 mm, Min =1.422 mm E: Max = 1.48 mm, Min = 1.42 mm D: Max = 1.482 mm, Min =1.422 mm E: Max = 1.48 mm, Min = 1.42 mm IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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