Dual 8-/10-/12-/14-/16-Bit 250 MSPS Digital-to-Analog Converters AD9741/AD9743/AD9745/AD9746/AD9747 FEATURES GENERAL DESCRIPTION High dynamic range, dual DACs Low noise and intermodulation distortion Single carrier WCDMA ACLR = 80 dBc @ 61.44 MHz IF Innovative switching output stage permits useable outputs beyond Nyquist frequency LVCMOS inputs with dual-port or optional interleaved single-port operation Differential analog current outputs are programmable from 8.6 mA to 31.7 mA full scale Auxiliary 10-bit current DACs with source/sink capability for external offset nulling Internal 1.2 V precision reference voltage source Operates from 1.8 V and 3.3 V supplies 315 mW power dissipation Small footprint, Pb-free, 72-Lead LFCSP The AD9741/AD9743/AD9745/AD9746/AD9747 are pincompatible, high dynamic range, dual digital-to-analog converters (DACs) with 8-/10-/12-/ 14-/16-bit resolutions and sample rates of up to 250 MSPS. The devices include specific features for direct conversion transmit applications, including gain and offset compensation, and they interface seamlessly with analog quadrature modulators, such as the ADL5370. APPLICATIONS PRODUCT HIGHLIGHTS Wireless infrastructure: WCDMA, CDMA2000, TD-SCDMA, WiMAX Wideband communications: LMDS/MMDS, point-to-point Instrumentation: RF signal generators, arbitrary waveform generators 1. Low noise and intermodulation distortion (IMD) enables high quality synthesis of wideband signals. 2. Proprietary switching output for enhanced dynamic performance. 3. Programmable current outputs and dual auxiliary DACs provide flexibility and system enhancements. A proprietary, dynamic output architecture permits synthesis of analog outputs even above Nyquist by shifting energy away from the fundamental and into the image frequency. Full programmability is provided through a serial peripheral interface (SPI) port. In addition, some pin-programmable features are offered for those applications without a controller. FUNCTIONAL BLOCK DIAGRAM CLKP CLKN 16-BIT DAC1 IOUT1P 16-BIT DAC2 IOUT2P INTERFACE LOGIC PID<15:0> IOUT1N IOUT2N GAIN DAC 10 CMOS INTERFACE GAIN DAC OFFSET DAC OFFSET DAC AUX1P AUX1N AUX2P AUX2N 06569-001 FSADJ CSB SCLK SDO SDIO SERIAL PERIPHERAL INTERFACE INTERNAL REFERENCE AND BIAS REFIO P2D<15:0> Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved. AD9741/AD9743/AD9745/AD9746/AD9747 TABLE OF CONTENTS Features .............................................................................................. 1 Instruction Byte .......................................................................... 18 Applications....................................................................................... 1 MSB/LSB Transfers .................................................................... 19 General Description ......................................................................... 1 Serial Interface Port Pin Descriptions ..................................... 19 Product Highlights ........................................................................... 1 SPI Register Map ............................................................................ 20 Functional Block Diagram .............................................................. 1 SPI Register Descriptions .............................................................. 21 Revision History ............................................................................... 2 Digital Inputs and Outputs ........................................................... 22 Specifications..................................................................................... 3 Input Data Timing ..................................................................... 22 DC Specifications ......................................................................... 3 Dual-Port Mode Timing ........................................................... 22 AC Specifications.......................................................................... 5 Single-Port Mode Timing ......................................................... 22 Digital and Timing Specifications.............................................. 7 SPI Port, Reset, and Pin Mode.................................................. 22 Absolute Maximum Ratings............................................................ 8 Driving the DAC Clock Input .................................................. 23 Thermal Resistance ...................................................................... 8 Full-Scale Current Generation ................................................. 23 ESD Caution.................................................................................. 8 DAC Transfer Function ............................................................. 24 Pin Configurations and Function Descriptions ........................... 9 Analog Modes of Operation ..................................................... 24 Typical Performance Characteristics ........................................... 14 Auxiliary DACS .......................................................................... 25 Terminology .................................................................................... 17 Power Dissipation....................................................................... 25 Theory of Operation ...................................................................... 18 Outline Dimensions ....................................................................... 27 Serial Peripheral Interface ......................................................... 18 Ordering Guide .......................................................................... 27 General Operation of the Serial Interface ............................... 18 REVISION HISTORY 5/07--Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD9741/AD9743/AD9745/AD9746/AD9747 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, full-scale digital input, maximum sample rate, unless otherwise noted. Table 1. AD9741, AD9743, and AD9745 Parameter RESOLUTION ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) MAIN DAC OUTPUTS Offset Error Offset Error Temperature Coefficient Gain Error Gain Error Temperature Coefficient Gain Matching (DAC1 to DAC2) Full-Scale Output Current Output Compliance Voltage Output Resistance AUXILIARY DAC OUTPUTS Resolution Full-Scale Output Current Output Compliance Voltage Range--Sink Current Output Compliance Voltage Range--Source Current Output Resistance Monotonicity REFERENCE INPUT/OUTPUT Output Voltage Output Voltage Temperature Coefficient External Input Voltage Range Input or Output Resistance POWER SUPPLY VOLTAGES AVDD33, DVDD33 CVDD18, DVDD18 POWER SUPPLY CURRENTS IAVDD33 IDVDD33 ICVDD18 IDVDD18 POWER DISSIPATION fDAC = 250 MSPS, fOUT = 20 MHz DAC Outputs Disabled Full Device Power-Down OPERATING TEMPERATURE Min AD9741 Typ Max 8 Min Min AD9745 Typ Max 12 Unit Bits 0.03 0.05 0.05 0.10 0.13 0.25 LSB LSB 0.001 1.0 2.0 100 1.0 0.001 1.0 2.0 100 1.0 0.001 1.0 2.0 100 1.0 %FSR ppm/C %FSR ppm/C %FSR mA V M 8.6 -1.0 31.7 +1.0 8.6 -1.0 10 31.7 +1.0 -2.0 0.8 0 1 10 +2.0 1.6 1.6 1.2 10 10 1.2 10 1.3 1.15 5 1.2 10 1.3 1.15 5 3.47 1.90 +2.0 1.6 1.6 1 10 3.13 1.70 -2.0 0.8 0 1 10 31.7 +1.0 10 10 +2.0 1.6 1.6 1.15 8.6 -1.0 10 10 -2.0 0.8 0 -40 AD9743 Typ Max 10 3.13 1.70 1.3 5 3.47 1.90 3.13 1.70 Bits mA V V M Bits V ppm/C V k 3.47 1.90 V V 56 10 18 28 60 14 22 32 56 10 18 29 60 14 22 33 56 11 18 30 60 15 22 34 mA mA mA mA 300 115 3 345 300 115 3 345 305 120 3 350 mW mW mW C +85 Rev. 0 | Page 3 of 28 -40 +85 -40 +85 AD9741/AD9743/AD9745/AD9746/AD9747 TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, full-scale digital input, maximum sample rate, unless otherwise noted. The AD9745 is repeated in Table 2 so the user can compare it with all other parts. Table 2. AD9745, AD9746, and AD9747 Parameter RESOLUTION ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) MAIN DAC OUTPUTS Offset Error Offset Error Temperature Coefficient Gain Error Gain Error Temperature Coefficient Gain Matching (DAC1 to DAC2) Full-Scale Output Current Output Compliance Voltage Output Resistance AUXILIARY DAC OUTPUTS Resolution Full-Scale Output Current Output Compliance Voltage Range--Sink Current Output Compliance Voltage Range--Source Current Output Resistance Monotonicity REFERENCE INPUT/OUTPUT Output Voltage Output Voltage Temperature Coefficient External Input Voltage Range Input or Output Resistance POWER SUPPLY VOLTAGES AVDD33, DVDD33 CVDD18, DVDD18 POWER SUPPLY CURRENTS IAVDD33 IDVDD33 ICVDD18 IDVDD18 POWER DISSIPATION fDAC = 250 MSPS, fOUT = 20 MHz DAC Outputs Disabled Full Device Power-Down OPERATING TEMPERATURE Min AD9745 Typ Max 12 Min Min AD9747 Typ Max 16 Unit Bits 0.13 0.25 0.5 1.0 2.0 4.0 LSB LSB 0.001 0.1 2.0 100 1.0 0.001 0.1 2.0 100 1.0 0.001 0.1 2.0 100 1.0 %FSR ppm/C %FSR ppm/C %FSR mA V M 8.6 -1.0 31.7 +1.0 8.6 -1.0 10 31.7 +1.0 -2.0 0.8 0 1 10 +2.0 1.6 1.6 1.2 10 10 1.2 10 1.3 1.15 5 1.2 10 1.3 1.15 5 3.47 1.90 +2.0 1.6 1.6 1 10 3.13 1.70 -2.0 0.8 0 1 10 31.7 +1.0 10 10 +2.0 1.6 1.6 1.15 8.6 -1.0 10 10 -2.0 0.8 0 -40 AD9746 Typ Max 14 3.13 1.70 1.3 5 3.47 1.90 3.13 1.70 Bits mA V V M Bits V ppm/C V k 3.47 1.90 V V 56 11 18 30 60 15 22 34 56 12 18 31 60 16 22 35 56 12 18 32 60 16 22 36 mA mA mA mA 305 120 3 350 310 125 3 355 310 125 3 355 mW mW mW C +85 Rev. 0 | Page 4 of 28 -40 +85 -40 +85 AD9741/AD9743/AD9745/AD9746/AD9747 AC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, full-scale digital input, maximum sample rate, unless otherwise noted. Table 3. AD9741, AD9743, and AD9745 Parameter SPURIOUS FREE DYNAMIC RANGE (SFDR) fDAC = 250 MSPS, fOUT = 20 MHz fDAC = 250 MSPS, fOUT = 70 MHz fDAC = 250 MSPS, fOUT = 180 MHz 1 INTERMODULATION DISTORTION (IMD) fDAC = 250 MSPS, fOUT = 20 MHz fDAC = 250 MSPS, fOUT = 70 MHz fDAC = 250 MSPS, fOUT = 180 MHz1 CROSSTALK fDAC = 250 MSPS, fOUT = 20 MHz fDAC = 250 MSPS, fOUT = 70 MHz fDAC = 250 MSPS, fOUT = 180 MHz1 ADJACENT CHANNEL LEAKAGE RATIO (ACLR) SINGLE CARRIER WCDMA fDAC = 245.76 MSPS, fOUT = 15.36 MHz fDAC = 245.76 MSPS, fOUT = 61.44 MHz fDAC = 245.76 MSPS, fOUT = 184.32 MHz1 NOISE SPECTRAL DENSITY (NSD) fDAC = 245.76 MSPS, fOUT = 15.36 MHz fDAC = 245.76 MSPS, fOUT = 61.44 MHz fDAC = 245.76 MSPS, fOUT = 184.32 MHz1 1 Min AD9741 Typ Max Min AD9743 Typ Max Min AD9745 Typ Max Unit 70 70 64 80 70 64 82 70 66 dBc dBc dBc 80 80 72 80 80 72 86 80 74 dBc dBc dBc 80 80 80 80 80 80 80 80 80 dBc dBc dBc 54 54 54 66 66 64 76 76 72 dBc dBc dBc -132 -132 -135 -144 -144 -147 -155 -155 -155 dBm/Hz dBm/Hz dBm/Hz Mix Mode. Rev. 0 | Page 5 of 28 AD9741/AD9743/AD9745/AD9746/AD9747 TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, full-scale digital input, maximum sample rate, unless otherwise noted. The AD9745 is repeated in Table 4 so the user can compare it with all other parts. Table 4. AD9745, AD9746, and AD9747 Parameter SPURIOUS FREE DYNAMIC RANGE (SFDR) fDAC = 250 MSPS, fOUT = 20 MHz fDAC = 250 MSPS, fOUT = 70 MHz fDAC = 250 MSPS, fOUT = 180 MHz1 INTERMODULATION DISTORTION (IMD) fDAC = 250 MSPS, fOUT = 20 MHz fDAC = 250 MSPS, fOUT = 70 MHz fDAC = 250 MSPS, fOUT = 180 MHz1 CROSSTALK fDAC = 250 MSPS, fOUT = 20 MHz fDAC = 250 MSPS, fOUT = 70 MHz fDAC = 250 MSPS, fOUT = 180 MHz1 ADJACENT CHANNEL LEAKAGE RATIO (ACLR) SINGLE CARRIER WCDMA fDAC = 245.76 MSPS, fOUT = 15.36 MHz fDAC = 245.76 MSPS, fOUT = 61.44 MHz fDAC = 245.76 MSPS, fOUT = 184.32 MHz1 NOISE SPECTRAL DENSITY (NSD) fDAC = 245.76 MSPS, fOUT = 15.36 MHz fDAC = 245.76 MSPS, fOUT = 61.44 MHz fDAC = 245.76 MSPS, fOUT = 184.32 MHz1 1 Min AD9745 Typ Max Min AD9746 Typ Max Min AD9747 Typ Max Unit 82 70 66 82 70 66 82 70 66 dBc dBc dBc 86 80 74 86 80 74 86 80 74 dBc dBc dBc 80 80 80 80 80 80 80 80 80 dBc dBc dBc 76 76 72 78 78 74 82 80 74 dBc dBc dBc -155 -155 -155 -163 -160 -158 -165 -162 -160 dBm/Hz dBm/Hz dBm/Hz Mix Mode. Rev. 0 | Page 6 of 28 AD9741/AD9743/AD9745/AD9746/AD9747 DIGITAL AND TIMING SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, full-scale digital input, maximum sample rate, unless otherwise noted. Table 5. AD9741/AD9743/AD9745/AD9746/AD9747 Parameter DAC CLOCK INPUTS (CLKP, CLKN) Differential Peak-to-Peak Voltage Single-Ended Peak-to-Peak Voltage Common-Mode Voltage Input Current Input Frequency DATA CLOCK OUTPUT (DCO) Output Voltage High Output Voltage Low Output Current DAC Clock to Data Clock Output Delay (tDCO) DATA PORT INPUTS Input Voltage High Input Voltage Low Input Current Data to DAC Clock Setup Time (tDBS Dual-Port Mode) Data to DAC Clock Hold Time (tDBH Dual-Port Mode) DAC Clock to Analog Output Data Latency (Dual-Port Mode) Data or IQSEL Input to DAC Clock Setup Time (tDBS Single-Port Mode) Data or IQSEL Input to DAC Clock Hold Time (tDBH Single-Port Mode) DAC Clock to Analog Output Data Latency (Single-Port Mode) SERIAL PERIPHERAL INTERFACE SCLK Frequency (fSCLK) SCLK Pulse Width High (tPWH) SCLK Pulse Width Low (tPWL) CSB to SCLK Setup Time (tS) CSB to SCLK Hold Time (tH) SDIO to SCLK Setup Time (tDS) SDIO to SCLK Hold Time (tDH) SCLK to SDIO/SDO Data Valid Time (tDV) RESET Pulse Width High WAKE-UP TIME AND OUTPUT LATENCY From DAC Outputs Disabled From Full Device Power-Down DAC Clock to Analog Output Latency (Dual-Port Mode) DAC Clock to Analog Output Latency (Single-Port Mode) Rev. 0 | Page 7 of 28 Min Typ Max Unit 400 800 300 400 1600 800 500 1 250 mV mV mV A MHz 0.4 10 2.8 V V mA ns 2.4 2.0 2.2 2.0 0.8 1 400 1200 7 400 1200 8 40 10 10 1 0 1 0 1 10 200 1200 7 8 V V A ps ps Cycles ps ps Cycles MHz ns ns ns ns ns ns ns ns s s Cycles Cycles AD9741/AD9743/AD9745/AD9746/AD9747 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter AVDD33, DVDD33 DVDD18, CVDD18 AVSS DVSS CVSS REFIO IOUT1P, IOUT1N, IOUT2P, IOUT2P, AUX1P, AUX1N, AUX2P, AUX2N P1D15 to P1D0, P2D15 to P2D0 CLKP, CLKN RESET, CSB, SCLK, SDIO, SDO Junction Temperature Storage Temperature With Respect to AVSS DVSS CVSS AVSS DVSS CVSS DVSS CVSS AVSS CVSS AVSS DVSS AVSS AVSS Thermal resistance tested using JEDEC standard 4-layer thermal test board with no airflow. Rating -0.3 V to +3.6 V Table 7. -0.3 V to +1.98 V -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3 V to AVDD33 + 0.3 V -1.0 V to AVDD33 + 0.3 V DVSS -0.3 V to DVDD33 + 0.3 V CVSS DVSS -0.3 V to CVDD18 + 0.3 V -0.3 V to DVDD33 + 0.3 V 125C -65C to +150C Package Type CP-72-1 (Exposed Pad Soldered to PCB) JA 25 Unit C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. 0 | Page 8 of 28 AD9741/AD9743/AD9745/AD9746/AD9747 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 AVDD33 AVDD33 AVSS IOUT1P IOUT1N AVSS AUX1P AUX1N AVSS AUX2N AUX2P AVSS IOUT2N IOUT2P AVSS AVDD33 AVDD33 REFIO PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS AD9741 (TOP VIEW) NC NC NC NC NC NC DCO NC DVDD33 DVSS IQSEL NC P2D7 P2D6 P2D5 P2D4 P2D3 P2D2 NC = NO CONNECT PIN 1 INDICATOR 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 FSADJ RESET CSB SCLK SDIO SDO DVSS DVDD18 NC NC NC NC NC NC NC NC P2D0 P2D1 06569-006 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 CVDD18 CVSS CLKP CLKN CVSS CVDD18 DVSS DVDD18 P1D7 P1D6 P1D5 P1D4 P1D3 P1D2 P1D1 P1D0 NC NC Figure 2. AD9741 Pin Configuration Table 8. AD 9741 Pin Function Descriptions Pin No. 1, 6 2, 5 3 4 7, 28, 48 8, 47 9 to 16 17 to 24, 26, 30, 39 to 46 25 27 29 31 to 38 49 50 51 52 53 54 55 56, 57, 71, 72 58, 61, 64, 67, 70 59 60 62 63 65 66 68 69 EPAD Mnemonic CVDD18 CVSS CLKP CLKN DVSS DVDD18 P1D<7:0> NC DCO DVDD33 IQSEL P2D<7:0> SDO SDIO SCLK CSB RESET FSADJ REFIO AVDD33 AVSS IOUT2P IOUT2N AUX2P AUX2N AUX1N AUX1P IOUT1N IOUT1P AVSS Description Clock Supply Voltage (1.8 V). Clock Supply Common (0 V). Differential DAC Clock Input. Complementary Differential DAC Clock Input. Digital Supply Common (0 V). Digital Core Supply Voltage (1.8 V). Port 1 Data Bit Inputs. No Connect. Data Clock Output. Use to clock data source. Digital I/O Supply Voltage (3.3 V). I/Q Framing Signal for Single-Port Mode Operation. Port 2 Data Bit Inputs. Serial Peripheral Interface Data Output. Serial Peripheral Interface Data Input and Optional Data Output. Serial Peripheral Interface Clock Input. Serial Peripheral Interface Chip Select Input. Active low. Hardware Reset. Active high. Full-Scale Current Output Adjust. Connect a 10 k resistor to AVSS. Reference Input/Output. Connect a 0.1 F capacitor to AVSS. Analog Supply Voltage (3.3 V). Analog Supply Common (0 V). DAC2 Current Output True. Sources full-scale current when input data bits are all 1. DAC2 Current Output Complement. Sources full-scale current when data bits are all 0. Auxiliary DAC2 Default Current Output Pin. Auxiliary DAC2 Optional Output Pin. Enable through SPI. Auxiliary DAC1 Optional Output Pin. Enable through SPI. Auxiliary DAC1 Default Current Output Pin. Complementary DAC1 Current Output. Sources full-scale current when data bits are all 0. DAC1 Current Output. Sources full-scale current when data bits are all 1. Exposed Thermal Pad. Must be soldered to copper pour on top surface of PCB for mechanical stability and must be electrically tied to low impedance GND plane for low noise performance. Rev. 0 | Page 9 of 28 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 AVDD33 AVDD33 AVSS IOUT1P IOUT1N AVSS AUX1P AUX1N AVSS AUX2N AUX2P AVSS IOUT2N IOUT2P AVSS AVDD33 AVDD33 REFIO AD9741/AD9743/AD9745/AD9746/AD9747 AD9743 (TOP VIEW) NC NC NC NC NC NC DCO NC DVDD33 DVSS IQSEL NC P2D9 P2D8 P2D7 P2D6 P2D5 P2D4 NC = NO CONNECT PIN 1 INDICATOR 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 FSADJ RESET CSB SCLK SDIO SDO DVSS DVDD18 NC NC NC NC NC NC P2D0 P2D1 P2D2 P2D3 06569-005 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 CVDD18 CVSS CLKP CLKN CVSS CVDD18 DVSS DVDD18 P1D9 P1D8 P1D7 P1D6 P1D5 P1D4 P1D3 P1D2 P1D1 P1D0 Figure 3. AD9743 Pin Configuration Table 9. AD 9743 Pin Function Descriptions Pin No. 1, 6 2, 5 3 4 7, 28, 48 8, 47 9 to 18 19 to 24, 26, 30, 41 to 46 25 27 29 31 to 40 49 50 51 52 53 54 55 56, 57, 71, 72 58, 61, 64, 67, 70 59 60 62 63 65 66 68 69 EPAD Mnemonic CVDD18 CVSS CLKP CLKN DVSS DVDD18 P1D<9:0> NC DCO DVDD33 IQSEL P2D<9:0> SDO SDIO SCLK CSB RESET FSADJ REFIO AVDD33 AVSS IOUT2P IOUT2N AUX2P AUX2N AUX1N AUX1P IOUT1N IOUT1P AVSS Description Clock Supply Voltage (1.8 V). Clock Supply Common (0 V). Differential DAC Clock Input. Complementary Differential DAC Clock Input. Digital Supply Common (0 V). Digital Core Supply Voltage (1.8 V). Port 1 Data Bit Inputs. No Connect. Data Clock Output. Use to clock data source. Digital I/O Supply Voltage (3.3 V). I/Q Framing Signal for Single-Port Mode Operation. Port 2 Data Bit Inputs. Serial Peripheral Interface Data Output. Serial Peripheral Interface Data Input and Optional Data Output. Serial Peripheral Interface Clock Input. Serial Peripheral Interface Chip Select Input. Active low. Hardware Reset. Active high. Full-Scale Current Output Adjust. Connect a 10 k resistor to AVSS. Reference Input/Output. Connect a 0.1 F capacitor to AVSS. Analog Supply Voltage (3.3 V). Analog Supply Common (0 V). DAC2 Current Output True. Sources full-scale current when input data bits are all 1. DAC2 Current Output Complement. Sources full-scale current when data bits are all 0. Auxiliary DAC2 Default Current Output Pin. Auxiliary DAC2 Optional Output Pin. Enable through SPI. Auxiliary DAC1 Optional Output Pin. Enable through SPI. Auxiliary DAC1 Default Current Output Pin. Complementary DAC1 Current Output. Sources full-scale current when data bits are all 0. DAC1 Current Output. Sources full-scale current when data bits are all 1. Exposed Thermal Pad. Must be soldered to copper pour on top surface of PCB for mechanical stability and must be electrically tied to low impedance GND plane for low noise performance. Rev. 0 | Page 10 of 28 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 AVDD33 AVDD33 AVSS IOUT1P IOUT1N AVSS AUX1P AUX1N AVSS AUX2N AUX2P AVSS IOUT2N IOUT2P AVSS AVDD33 AVDD33 REFIO AD9741/AD9743/AD9745/AD9746/AD9747 AD9745 (TOP VIEW) P1D1 P1D0 NC NC NC NC DCO NC DVDD33 DVSS IQSEL NC P2D11 P2D10 P2D9 P2D8 P2D7 P2D6 NC = NO CONNECT PIN 1 INDICATOR 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 FSADJ RESET CSB SCLK SDIO SDO DVSS DVDD18 NC NC NC NC P2D0 P2D1 P2D2 P2D3 P2D4 P2D5 06569-004 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 CVDD18 CVSS CLKP CLKN CVSS CVDD18 DVSS DVDD18 P1D11 P1D10 P1D9 P1D8 P1D7 P1D6 P1D5 P1D4 P1D3 P1D2 Figure 4. AD9745 Pin Configuration Table 10. AD9745 Pin Function Descriptions Pin No. 1, 6 2, 5 3 4 7, 28, 48 8, 47 9 to 20 21 to 24, 26, 30, 43 to 46 25 27 29 31 to 42 49 50 51 52 53 54 55 56, 57, 71, 72 58, 61, 64, 67, 70 59 60 62 63 65 66 68 69 EPAD Mnemonic CVDD18 CVSS CLKP CLKN DVSS DVDD18 P1D<11:0> NC DCO DVDD33 IQSEL P2D<11:0> SDO SDIO SCLK CSB RESET FSADJ REFIO AVDD33 AVSS IOUT2P IOUT2N AUX2P AUX2N AUX1N AUX1P IOUT1N IOUT1P AVSS Description Clock Supply Voltage (1.8 V). Clock Supply Common (0 V). Differential DAC Clock Input. Complementary Differential DAC Clock Input. Digital Supply Common (0 V). Digital Core Supply Voltage (1.8 V). Port 1 Data Bit Inputs. No Connect. Data Clock Output. Use to clock data source. Digital I/O Supply Voltage (3.3 V). I/Q Framing Signal for Single-Port Mode Operation. Port 2 Data Bit Inputs. Serial Peripheral Interface Data Output. Serial Peripheral Interface Data Input and Optional Data Output. Serial Peripheral Interface Clock Input. Serial Peripheral Interface Chip Select Input. Active low. Hardware Reset. Active high. Full-Scale Current Output Adjust. Connect 10 k resistor to AVSS. Reference Input/Output. Connect a 0.1 F capacitor to AVSS. Analog Supply Voltage (3.3 V). Analog Supply Common (0 V). DAC2 Current Output True. Sources full-scale current when input data bits are all 1. DAC2 Current Output Complement. Sources full-scale current when data bits are all 0. Auxiliary DAC2 Default Current Output Pin. Auxiliary DAC2 Optional Output Pin. Enable through SPI. Auxiliary DAC1 Optional Output Pin. Enable through SPI. Auxiliary DAC1 Default Current Output Pin. Complementary DAC1 Current Output. Sources full-scale current when data bits are all 0. DAC1 Current Output. Sources full-scale current when data bits are all 1. Exposed Thermal Pad. Must be soldered to copper pour on top surface of PCB for mechanical stability and must be electrically tied to low impedance GND plane for low noise performance. Rev. 0 | Page 11 of 28 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 AVDD33 AVDD33 AVSS IOUT1P IOUT1N AVSS AUX1P AUX1N AVSS AUX2N AUX2P AVSS IOUT2N IOUT2P AVSS AVDD33 AVDD33 REFIO AD9741/AD9743/AD9745/AD9746/AD9747 AD9746 (TOP VIEW) P1D3 P1D2 P1D1 P1D0 NC NC DCO NC DVDD33 DVSS IQSEL NC P2D13 P2D12 P2D11 P2D10 P2D9 P2D8 NC = NO CONNECT PIN 1 INDICATOR 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 FSADJ RESET CSB SCLK SDIO SDO DVSS DVDD18 NC NC P2D0 P2D1 P2D2 P2D3 P2D4 P2D5 P2D6 P2D7 06569-003 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 CVDD18 CVSS CLKP CLKN CVSS CVDD18 DVSS DVDD18 P1D13 P1D12 P1D11 P1D10 P1D9 P1D8 P1D7 P1D6 P1D5 P1D4 Figure 5. AD9746 Pin Configuration Table 11. AD9746 Pin Function Descriptions Pin No. 1, 6 2, 5 3 4 7, 28, 48 8, 47 9 to 22 23, 24, 26, 30, 45, 46 25 27 29 31 to 44 49 50 51 52 53 54 55 56, 57, 71, 72 58, 61, 64, 67, 70 59 60 62 63 65 66 68 69 EPAD Mnemonic CVDD18 CVSS CLKP CLKN DVSS DVDD18 P1D<13:0> NC DCO DVDD33 IQSEL P2D<13:0> SDO SDIO SCLK CSB RESET FSADJ REFIO AVDD33 AVSS IOUT2P IOUT2N AUX2P AUX2N AUX1N AUX1P IOUT1N IOUT1P AVSS Description Clock Supply Voltage (1.8 V). Clock Supply Common (0 V). Differential DAC Clock Input. Complementary Differential DAC Clock Input. Digital Supply Common (0 V). Digital Core Supply Voltage (1.8 V). Port 1 Data Bit Inputs. No Connect. Data Clock Output. Use to clock data source. Digital I/O Supply Voltage (3.3 V). I/Q Framing Signal for Single-Port Mode Operation. Port 2 Data Bit Inputs. Serial Peripheral Interface Data Output. Serial Peripheral Interface Data Input and Optional Data Output. Serial Peripheral Interface Clock Input. Serial Peripheral Interface Chip Select Input. Active low. Hardware Reset. Active high. Full-Scale Current Output Adjust. Connect a 10 k resistor to AVSS. Reference Input/Output. Connect a 0.1 F capacitor to AVSS. Analog Supply Voltage (3.3 V). Analog Supply Common (0 V). DAC2 Current Output True. Sources full-scale current when input data bits are all 1. DAC2 Current Output Complement. Sources full-scale current when data bits are all 0. Auxiliary DAC2 Default Current Output Pin. Auxiliary DAC2 Optional Output Pin. Enable through SPI. Auxiliary DAC1 Optional Output Pin. Enable through SPI. Auxiliary DAC1 Default Current Output Pin. Complementary DAC1 Current Output. Sources full-scale current when data bits are all 0. DAC1 Current Output. Sources full-scale current when data bits are all 1. Exposed Thermal Pad. Must be soldered to copper pour on top surface of PCB for mechanical stability and must be electrically tied to low impedance GND plane for low noise performance. Rev. 0 | Page 12 of 28 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 AVDD33 AVDD33 AVSS IOUT1P IOUT1N AVSS AUX1P AUX1N AVSS AUX2N AUX2P AVSS IOUT2N IOUT2P AVSS AVDD33 AVDD33 REFIO AD9741/AD9743/AD9745/AD9746/AD9747 AD9747 (TOP VIEW) P1D5 P1D4 P1D3 P1D2 P1D1 P1D0 DCO NC DVDD33 DVSS IQSEL NC P2D15 P2D14 P2D13 P2D12 P2D11 P2D10 NC = NO CONNECT PIN 1 INDICATOR 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 FSADJ RESET CSB SCLK SDIO SDO DVSS DVDD18 P2D0 P2D1 P2D2 P2D3 P2D4 P2D5 P2D6 P2D7 P2D8 P2D9 06569-002 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 CVDD18 CVSS CLKP CLKN CVSS CVDD18 DVSS DVDD18 P1D15 P1D14 P1D13 P1D12 P1D11 P1D10 P1D9 P1D8 P1D7 P1D6 Figure 6. AD9747 Pin Configuration Table 12. AD9747 Pin Function Descriptions Pin No. 1, 6 2, 5 3 4 7, 28, 48 8, 47 9 to 24 25 26, 30 27 29 31 to 46 49 50 51 52 53 54 55 56, 57, 71, 72 58, 61, 64, 67, 70 59 60 62 63 65 66 68 69 EPAD Mnemonic CVDD18 CVSS CLKP CLKN DVSS DVDD18 P1D<15:0> DCO NC DVDD33 IQSEL P2D<15:0> SDO SDIO SCLK CSB RESET FSADJ REFIO AVDD33 AVSS IOUT2P IOUT2N AUX2P AUX2N AUX1N AUX1P IOUT1N IOUT1P AVSS Description Clock Supply Voltage (1.8 V). Clock Supply Common (0 V). Differential DAC Clock Input. Complementary Differential DAC Clock Input. Digital Supply Common (0 V). Digital Core Supply Voltage (1.8 V). Port 1 Data Bit Inputs. Data Clock Output. Use to clock data source. No Connect. Digital I/O Supply Voltage (3.3 V). I/Q Framing Signal for Single-Port Mode Operation. Port 2 Data Bit Inputs. Serial Peripheral Interface Data Output. Serial Peripheral Interface Data Input and Optional Data Output. Serial Peripheral Interface Clock Input. Serial Peripheral Interface Chip Select Input. Active low. Hardware Reset. Active high. Full-Scale Current Output Adjust. Connect a 10 k resistor to AVSS. Reference Input/Output. Connect a 0.1 F capacitor to AVSS. Analog Supply Voltage (3.3 V). Analog Supply Common (0 V). DAC2 Current Output. Sources full-scale current when input data bits are all 1. Complementary DAC2 Current Output. Sources full-scale current when data bits are all 0. Auxiliary DAC2 Default Current Output Pin. Auxiliary DAC2 Optional Output Pin. Enable through SPI. Auxiliary DAC1 Optional Output Pin. Enable through SPI. Auxiliary DAC1 Default Current Output Pin. Complementary DAC1 Current Output. Sources full-scale current when data bits are all 0. DAC1 Current Output. Sources full-scale current when data bits are all 1. Exposed Thermal Pad. Must be soldered to copper pour on top surface of PCB for mechanical stability and must be electrically tied to low impedance GND plane for low noise performance. Rev. 0 | Page 13 of 28 AD9741/AD9743/AD9745/AD9746/AD9747 TYPICAL PERFORMANCE CHARACTERISTICS 100 100 90 90 80 125MSPS 70 60 60 50 50 20 40 60 80 100 120 fOUT (MHz) 40 0 20 90 80 80 IMD (dBc) 90 70 60 50 50 200 225 250 fOUT (MHz) 40 125 120 150 175 200 225 250 250 fOUT (MHz) Figure 8. AD9747 SFDR vs. fOUT, Mix Mode, 250 MSPS Figure 11. AD9747 IMD vs. fOUT, Mix Mode, 250 MSPS 90 -152 -154 85 NORMAL MODE -156 MIX MODE NSD (dBm/Hz) 80 ACLR (dBc) 100 70 60 06569-008 SFDR (dBc) 100 175 80 Figure 10. AD9747 IMD vs. fOUT, Normal Mode 100 150 60 fOUT (MHz) Figure 7. AD9747 SFDR vs. fOUT, Normal Mode 40 125 40 06569-011 0 06569-012 40 06569-010 IMD (dBc) 250MSPS 70 06569-007 SFDR (dBc) 250MSPS 125MSPS 80 MIX MODE 75 70 -158 NORMAL MODE -160 -162 -164 65 0 50 100 150 fOUT (MHz) 200 250 -168 06569-009 60 -166 Figure 9. AD9747 ACLR vs. fOUT, Single Carrier WCDMA, 245.76 MSPS 0 50 100 150 fOUT (MHz) 200 Figure 12. AD9747 NSD vs. fOUT, Single Carrier WCDMA, 245.76 MSPS Rev. 0 | Page 14 of 28 AD9741/AD9743/AD9745/AD9746/AD9747 100 100 90 90 IMD (dBc) 10mAFS 30mAFS 20mAFS 60 50 50 0 20 40 60 80 100 120 fOUT (MHz) 30mAFS 70 60 40 06569-036 SFDR (dBc) 70 40 10mAFS 80 0 20 40 60 80 100 120 fOUT (MHz) Figure 13. AD9747 SFDR vs. Analog Output, 250 MSPS 06569-039 20mAFS 80 Figure 16. AD9747 IMD vs. Analog Output, 250 MSPS 100 100 90 90 0dBFS 0dBFS -3dBFS 70 -6dBFS 60 60 50 50 0 20 40 60 80 100 120 fIN (MHz) 40 85 85 80 80 IMD (dBc) 90 75 60 80 100 120 75 70 70 RANGE OF POSSIBLE SFDR PERFORMANCE IS DEPENDENT ON INPUT DATA TIMING RELATIVE TO THE DAC CLOCK. SEE INPUT DATA TIMING SECTION. 10 20 30 40 50 60 70 65 80 90 100 110 fOUT (MHz) 06569-038 SFDR (dBc) 40 Figure 17. AD9747 IMD vs. Digital Input, 250 MSPS 90 60 20 fIN (MHz) Figure 14. AD9747 SFDR vs. Digital Input, 250 MSPS 65 0 -6dBFS Figure 15. AD9747 SFDR vs. fOUT Over Input Data Timing 60 RANGE OF IMD PERFORMANCE IS ESSENTIALLY INDEPENDENT OF INPUT DATA TIMING RELATIVE TO THE DAC CLOCK. SEE INPUT DATA TIMING SECTION. 10 20 30 40 50 60 70 80 90 100 110 fOUT (MHz) Figure 18. AD9747 IMD vs. fOUT Over Input Data Timing Rev. 0 | Page 15 of 28 06569-041 40 -3dBFS 70 06569-040 IMD (dBc) 80 06569-037 SFDR (dBc) 80 AD9741/AD9743/AD9745/AD9746/AD9747 1 -130 0 -135 -140 NORMAL MODE NSD (dBm/Hz) AOUT (dBm) -1 -2 MIX MODE -3 -145 -150 -155 -4 25 50 75 100 125 150 175 200 225 250 fOUT (MHz) Figure 19. Nominal Power in the Fundamental, IFS = 20 mA -165 80 ACLR (dBc) 75 70 65 60 AD9743 AD9745 AD9746 AD9747 06569-043 55 AD9741 AD9743 AD9745 AD9746 AD9747 Figure 21. NSD vs. Bit Resolution, Single Carrier WCDMA, 245.76 MSPS, fCARRIER fCARRIER = 61.44 MHz 85 50 AD9741 06569-044 0 06569-042 -160 -5 Figure 20. ACLR vs. Bit Resolution, Single Carrier WCDMA, 245.76 MSPS, fCARRIER = 61.44 MHz Rev. 0 | Page 16 of 28 AD9741/AD9743/AD9745/AD9746/AD9747 TERMINOLOGY Integral Nonlinearity (INL) The maximum deviation of the actual analog output from the ideal output, as determined by a straight line drawn from zero scale to full scale. Temperature Drift Temperature drift is specified as the maximum change in a parameter from ambient temperature (25C) to either TMIN or TMAX and is typically reported as ppm/C. Differential Nonlinearity (DNL) A measure of the maximum deviation in analog output associated with any single value change in the digital input code relative to an ideal LSB. Spurious-Free Dynamic Range (SFDR) The difference in decibels between the peak amplitude of a test tone and the peak amplitude of the largest spurious signal over the specified bandwidth. Monotonicity A DAC is monotonic if the analog output increases or remains constant in response to an increase in the digital input. Intermodulation Distortion (IMD) The difference in decibels between the maximum peak amplitude of two test tones and the maximum peak amplitude of the distortion products created from the sum or difference of integer multiples of the test tones. Offset Error The deviation of the output current from the ideal zero-scale current. For differential outputs, 0 mA is expected at IOUTP when all inputs are low, and 0 mA is expected at IOUTN when all inputs are high. Gain Error The deviation of the output current from the ideal full-scale current. Actual full-scale output current is determined by subtracting the output (when all inputs are low) from the output (when all inputs are high). Adjacent Channel Leakage Ratio (ACLR) The ratio between the measured power of a wideband signal within a channel relative to the measured power in an empty adjacent channel. Noise Spectral Density (NSD) The measured noise power over a 1 Hz bandwidth seen at the analog output. Output Compliance Range The range of allowable voltage seen by the analog output of a current output DAC. Operation beyond the compliance limits may cause output stage saturation and/or a breakdown resulting in nonlinear performance. Rev. 0 | Page 17 of 28 AD9741/AD9743/AD9745/AD9746/AD9747 THEORY OF OPERATION The AD9741/AD9743/AD9745/AD9746/AD9747 combine many features to make them very attractive for wired and wireless communications systems. The dual DAC architecture facilitates easy interfacing to common quadrature modulators when designing single sideband transmitters. In addition, the speed and performance of the devices allow wider bandwidths and more carriers to be synthesized than in previously available products. All features and options are software programmable through the SPI port. SERIAL PERIPHERAL INTERFACE SDO SCLK AD9747 CSB The remaining SCLK edges are for Phase 2 of the communication cycle, which is the data transfer between the serial port controller and the system controller. Phase 2 can be a transfer of 1, 2, 3, or 4 data bytes as determined by the instruction byte. Using multibyte transfers is usually preferred although single-byte data transfers are useful to reduce CPU overhead or when only a single register access is required. All serial port data is transferred to and from the device in synchronization with the SCLK pin. Input data is always latched on the rising edge of SCLK whereas output data is always valid after the falling edge of SCLK. Register contents change immediately upon writing to the last bit of each transfer byte. SPI PORT 06569-013 SDIO transfer, and a reference register address for the first byte of the data transfer. A logic high on the CSB pin followed by a logic low resets the SPI port to its initial state and defines the start of the instruction cycle. From this point, the next eight rising SCLK edges define the eight bits of the instruction byte for the current communication cycle. Figure 22. SPI Port The SPI port is a flexible, synchronous serial communications port allowing easy interfacing to many industry-standard microcontrollers and microprocessors. The port is compatible with most synchronous transfer formats including both the Motorola SPI and Intel(R) SSR protocols. When synchronization is lost, the device has the ability to asynchronously terminate an I/O operation whenever the CSB pin is taken to logic high. Any unwritten register content data is lost if the I/O operation is aborted. Taking CSB low then resets the serial port controller and restarts the communication cycle. The interface allows read and write access to all registers that configure the AD9741/AD9743/AD9745/AD9746/AD9747. Single or multiple byte transfers are supported as well as MSBfirst or LSB-first transfer formats. Serial data input/output can be accomplished through a single bidirectional pin (SDIO) or through two unidirectional pins (SDIO/SDO). INSTRUCTION BYTE The serial port configuration is controlled by Register 0x00, Bits<7:6>. It is important to note that any change made to the serial port configuration occurs immediately upon writing to the last bit of this byte. Therefore, it is possible with a multibyte transfer to write to this register and change the configuration in the middle of a communication cycle. Care must be taken to compensate for the new configuration within the remaining bytes of the current communication cycle. Use of a single-byte transfer when changing the serial port configuration is recommended to prevent unexpected device behavior. GENERAL OPERATION OF THE SERIAL INTERFACE There are two phases to any communication cycle with the AD9741/AD9743/AD9745/AD9746/AD9747: Phase 1 and Phase 2. Phase 1 is the instruction cycle, which writes an instruction byte into the device. This byte provides the serial port controller with information regarding Phase 2 of the communication cycle: the data transfer cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data The instruction byte contains the information shown in the following bit map. MSB B7 R/W B6 N1 B5 N0 B4 A4 B3 A3 B2 A2 B1 A1 LSB B0 A0 Bit 7, R/W, determines whether a read or a write data transfer occurs after the instruction byte write. Logic high indicates a read operation. Logic 0 indicates a write operation. Bits<6:5>, N1 and N0, determine the number of bytes to be transferred during the data transfer cycle. The bits decode as shown in Table 13. Table 13. Byte Transfer Count N1 0 0 1 1 N0 0 1 0 1 Description Transfer one byte Transfer two bytes Transfer three bytes Transfer four bytes Bits<4:0>, A4, A3, A2, A1, and A0, determine which register is accessed during the data transfer of the communications cycle. For multibyte transfers, this address is a starting or ending address depending on the current data transfer mode. For MSBfirst format, the specified address is an ending address or the most significant address in the current cycle. Remaining register addresses for multiple byte data transfers are generated Rev. 0 | Page 18 of 28 AD9741/AD9743/AD9745/AD9746/AD9747 The serial port can support both MSB-first and LSB-first data formats. This functionality is controlled by Register 0x00, Bit 6. The default is Logic 0, which is MSB-first format. When using MSB-first format (LSBFIRST = 0), the instruction and data bit must be written from MSB to LSB. Multibyte data transfers in MSB-first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes are loaded into sequentially lower address locations. In MSB-first mode, the serial port internal address generator decrements for each byte of the multibyte data transfer. When using LSB-first format (LSBFIRST = 1), the instruction and data bit must be written from LSB to MSB. Multibyte data transfers in LSB-first format start with an instruction byte that includes the register address of the least significant data byte. Subsequent data bytes are loaded into sequentially higher address locations. In LSB-first mode, the serial port internal address generator increments for each byte of the multibyte data transfer. Use of a single-byte transfer when changing the serial port data format is recommended to prevent unexpected device behavior. Serial Data Out (SDO) Data is read from this pin for protocols that use separate lines for transmitting and receiving data. The configuration of this pin is controlled by Register 0x00, Bit 7. If this bit is set to a Logic 1, the SDO pin does not output data and is set to a high impedance state. INSTRUCTION CYCLE DATA TRANSFER CYCLE CSB SCLK SDIO R/W N1 N0 A4 A3 A2 A1 A0 SDO D7 D6N D5N D30 D20 D10 D00 D7 D6N D5N D30 D20 D10 D00 06569-014 MSB/LSB TRANSFERS The configuration of this pin is controlled by Register 0x00, Bit 7. The default is Logic 0, which configures the SDIO pin as unidirectional. Figure 23. Serial Register Interface--MSB First INSTRUCTION CYCLE DATA TRANSFER CYCLE CSB SCLK SDIO A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20 D4N D5 N D6N D7N D00 D10 D2 0 D4N D5N D6N D7 N SDO 06569-015 internally by the serial port controller by decrementing from the specified address. For LSB-first format, the specified address is a beginning address or the least significant address in the current cycle. Remaining register addresses for multiple byte data transfers are generated internally by the serial port controller by incrementing from the specified address. Figure 24. Serial Register Interface Timing--LSB First SERIAL INTERFACE PORT PIN DESCRIPTIONS Chip Select Bar (CSB) tS Active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communication lines. CSB must stay low during the entire communication cycle. Incomplete data transfers are aborted anytime the CSB pin goes high. SDO and SDIO pins go to a high impedance state when this input is high. CSB tPWH tPWL tDS SDIO INSTRUCTION BIT 7 INSTRUCTION BIT 6 Figure 25. Timing Diagram for SPI Register Write CSB SCLK Serial Data I/O (SDIO) tDV SDIO SDO DATA BIT N DATA BIT N - 1 Figure 26. Timing Diagram for SPI Register Read Rev. 0 | Page 19 of 28 06569-017 The serial clock pin is used to synchronize data to and from the device and to run the internal state machines. The maximum frequency of SCLK is 40 MHz. All data input is registered on the rising edge of SCLK. All data is driven out on the falling edge of SCLK. tDH 06569-016 SCLK Serial Clock (SCLK) Data is always written into the device on this pin. However, SDIO can also function as a bidirectional data output line. fSCLK -1 AD9741/AD9743/AD9745/AD9746/AD9747 SPI REGISTER MAP Reading any register returns previously written values for all defined register bits, unless otherwise noted. Change serial port configuration or execute software reset in single byte instruction only to avoid unexpected device behavior. Table 14. Register Name SPI Control Data Control Power Down DAC Mode Select DAC1 Gain LSB DAC1 Gain MSB AUX DAC1 LSB AUX DAC1 MSB DAC2 Gain LSB DAC2 Gain MSB AUX DAC2 LSB AUX DAC2 MSB Address 0x00 0x02 0x03 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 Default 0x00 0x00 0x00 0x00 0xF9 0x01 0x00 0x00 0xF9 0x01 0x00 0x00 Bit 7 SDIODIR DATTYPE PD_DCO Bit 6 LSBFIRST ONEPORT Bit 5 SWRESET PD_AUX2 Bit 4 Bit 3 INVDCO PD_AUX1 Bit 2 PD_BIAS PC_CLK DAC1MOD<1:0> DAC1FSC<7:0> Bit 1 Bit 0 PD_DAC2 PD_DAC1 DAC2MOD<1:0> DAC1FSC<9:8> AUXDAC1<7:0> AUX1PIN AUX1DIR AUXDAC1<9:8> DAC2FSC<7:0> DAC2FSC<9:8> AUXDAC2<7:0> AUX2PIN AUX2DIR Rev. 0 | Page 20 of 28 AUXDAC2<9:8> AD9741/AD9743/AD9745/AD9746/AD9747 SPI REGISTER DESCRIPTIONS Table 15. Register SPI Control Data Control Address 0x00 0x02 Power Down 0x03 DAC Mode Select 0x0A Bit 7 Name SDIODIR 6 LSBFIRST 5 SWRESET 7 DATTYPE 6 ONEPORT 4 7 5 4 3 2 1 0 3:2 INVDCO PD_DCO PD_AUX2 PD_AUX1 PD_BIAS PD_CLK PD_DAC2 PD_DAC1 DAC1MOD<1:0> 1:0 DAC2MOD<1:0> DAC1 Gain 0x0B 0x0C 7:0 1:0 DAC1FSC<7:0> DAC1FSC<9:8> AUX DAC1 0x0D 0x0E 7:0 1:0 AUXDAC1<7:0> AUXDAC1<9:8> 7 AUX1PIN 6 AUX1DIR DAC2 Gain 0x0F 0x10 7:0 1:0 DAC2FSC<7:0> DAC2FSC<9:8> AUX DAC2 0x11 0x12 7:0 1:0 AUXDAC2<7:0> AUXDAC2<9:8> 7 AUX2PIN 6 AUX2DIR Description 0, operate SPI in 4-wire mode, SDIO pin operates as an input only 1, operate SPI in 3-wire mode, SDIO pin operates as a bidirectional I/O line 0, LSBFIRST off, SPI serial data mode is MSB to LSB 1, LSBFIRST on, SPI serial data mode is LSB to MSB 0, resume normal operation following software RESET 1, software RESET; loads default values to all registers (except Register 0x00) 0, DAC input data is twos complement binary format 1, DAC input data is unsigned binary format 0, normal two port input mode 1, optional single port input mode, interleaved data received on Port 1 only 1, inverts data clock output signal 1, power down data clock output 1, power down AUX2 DAC 1, power down AUX1 DAC 1, power down reference voltage bias circuit 1, power down DAC clock input circuit 1, power down DAC2 analog output 1, power down DAC1 analog output 00, selects normal mode, DAC1 01, selects mix mode, DAC1 10, selects return-to-zero mode, DAC1 00, selects normal mode, DAC2 01, selects mix mode, DAC2 10, selects return-to-zero mode, DAC2 DAC1 full-scale 10-bit adjustment word 0x03FF, sets full-scale current to the maximum value of 31.66 mA 0x01F9, sets full-scale current to the nominal value of 20.0 mA 0x0000, sets full-scale current to the minimum value of 8.64 mA Auxiliary DAC1 10-bit output current adjustment word 0x03FF, sets output current magnitude to 2.0 mA 0x0200, sets output current magnitude to 1.0 mA 0x0000, sets output current magnitude to 0.0 mA 0, AUX1P output pin is active 1, AUX1N output pin is active 0, configures AUX1 DAC output to source current 1, configures AUX1 DAC output to sink current DAC2 full-scale 10-bit adjustment word 0x03FF, sets full-scale current to the maximum value of 31.66 mA 0x01F9, sets full-scale current to the nominal value of 20.0 mA 0x0000, sets full-scale current to the minimum value of 8.64 mA Auxiliary DAC2 10-bit output current adjustment word 0x03FF, sets output current magnitude to 2.0 mA 0x0200, sets output current to 1.0 mA 0x0000, sets output current to 0.0 mA 0, AUX2P output pin is active 1, AUX2N output pin is active 0, configures AUX2 DAC output to source current 1, configures AUX2 DAC output to sink current Rev. 0 | Page 21 of 28 AD9741/AD9743/AD9745/AD9746/AD9747 DIGITAL INPUTS AND OUTPUTS In single-port mode, when the IQSEL input is high, Port 1 data is delivered to DAC1 and when IQSEL is low, Port 1 data is delivered to DAC2. The IQSEL input should always coincide and be time-aligned with the other data bus signals. In singleport mode, minimum setup and hold times apply to the IQSEL input as well as to the input data signals. In dual-port mode, the IQSEL input is ignored. In dual-port mode, the data must be delivered at the sample rate (up to 250 MSPS). In single-port mode, data must be delivered at twice the sample rate. Because the data inputs function only up to 250 MSPS, it is only practical to operate the DAC clock at up to 125 MHz in single-port mode. INPUT DATA TIMING With most DACs, signal-to-noise ratio (SNR) is a function of the relationship between the position of the clock edges and the point in time at which the input data changes. The AD9741/ AD9743/AD9745/AD9746/AD9747 are rising edge triggered and thus exhibit greater SNR sensitivity when the data transition is close to this edge. The specified minimum setup and hold times define a window of time, within each data period, where the data is sampled correctly. Generally, users should position data to arrive relative to the DAC clock and well beyond the minimum setup and minimum hold times. This becomes increasingly more important at increasingly higher sample rates. SINGLE-PORT MODE TIMING The single-port mode timing diagram is shown in Figure 28. CLKP/CLKN tDBS P1D<15:0> tDBH I1 Q1 I2 Q2 IQSEL Figure 28. Data Interface Timing, Single-Port Mode SPI PORT, RESET, AND PIN MODE In general, when the AD9741/AD9743/AD9745/AD9746/ AD9747 are powered up, an active high pulse applied to the RESET pin should follow. This insures the default state of all control register bits. In addition, once the RESET pin goes low, the SPI port can be activated, so CSB should be held high. Table 16. SPI Pin Functions (Pin Mode) The timing diagram for the dual-port mode is shown in Figure 27. Pin Name SCLK CLKP/CLKN tDCO SDIO P1D<15:0> I1 I2 I3 I4 P2D<15:0> Q1 Q2 Q3 Q4 06569-018 tDBH Figure 27. Data Interface Timing, Dual-Port Mode tDCO DCO For applications without a controller, the AD9741/AD9743/ AD9745/AD9746/AD9747 also support pin mode operation, which allows some functional options to be pin, selected without the use of the SPI port. Pin mode is enabled anytime the RESET pin is held high. In pin mode, the four SPI port pins take on secondary functions, as shown in Table 16. DUAL-PORT MODE TIMING tDBS Setup and hold times are referenced to the positive transition of the DAC clock. Data should arrive at the input pins such that the minimum setup and hold times are met. Note that the data clock output has a fixed time delay from the DAC clock and may be a more convenient signal to use to confirm timing. In single-port mode, data for both DACs is received on the Port 1 input bus. Ix and Qx data samples are interleaved and arrive twice as fast as in dual-port mode. Accompanying the data is the IQSEL input signal, which steers incoming data to its respective DAC. When IQSEL is high, data is steered to DAC1 and when IQSEL is low, data is steered to DAC2. IQSEL should coincide as well as be time-aligned with incoming data. In both dual-port and single-port modes, a data clock output (DCO) signal is available as a fixed time base with which to stimulate data from an FPGA. This output signal always operates at the sample rate. It may be inverted by asserting the INVDCO bit. DCO In Figure 27, data samples for DAC1 are labeled Ix and data samples for DAC2 are labeled Qx. Note that the differential DAC clock input is shown in a logical sense (CLKP/CLKN). The data clock output is labeled DCO. CSB SDO Rev. 0 | Page 22 of 28 Pin Mode Description ONEPORT (Register 0x02, Bit 6), bit value (1/0) equals pin state (high/low) DATTYPE (Register 0x02, Bit 7), bit value (1/0) equals pin state (high/low) Enable Mix Mode, if CSB is high, Register 0x0A is set to 0x05 putting both DAC1 and DAC2 into mix mode Enable full power-down, if SDO is high, Register 0x03 is set to 0xFF 06569-019 The AD9741/AD9743/AD9745/AD9746/AD9747 can operate in two data input modes: dual-port mode and single-port mode. For the default dual-port mode (ONEPORT = 0), each DAC receives data from a dedicated input port. In single-port mode (ONEPORT = 1), however, both DACs receive data from Port 1. In single-port mode, DAC1 and DAC2 data is interleaved and the IQSEL input is used to steer data to the correct DAC. AD9741/AD9743/AD9745/AD9746/AD9747 In pin mode, all register bits are reset to their default values with the exception of those that are controlled by the SPI pins. Note also that the RESET pin should be allowed to float and must be pulled low. Connect an external 10 k resistor to DVSS. This avoids unexpected behavior in noisy environments. DRIVING THE DAC CLOCK INPUT The DAC clock input requires a low jitter drive signal. It is a PMOS differential pair powered from the CVDD18 supply. Each pin can safely swing up to 800 mV p-p at a commonmode voltage of about 400 mV. Though these levels are not directly LVDS-compatible, CLKP and CLKN can be driven by an ac-coupled, dc-offset LVDS signal, as shown in Figure 29. It is important to use CVDD18 and CVSS for any clock bias circuit as noise that is coupled onto the clock from another power supply is multiplied by the DAC input signal and degrades performance. FULL-SCALE CURRENT GENERATION The full-scale currents on DAC1 and DAC2 are functions of the current drawn through an external resistor connected to the FSADJ pin (Pin 54). The required value for this resistor is 10 k. An internal amplifier sets the current through the resistor to force a voltage equal to the band gap voltage of 1.2 V. This develops a reference current in the resistor of 120 A. AD9747 0.1F 1.2V BANDGAP CLKP 50 0.1F VCM = 400mV 10k 06569-021 CLKN 0.1F Using a CMOS or TTL clock is also acceptable for lower sample rates. It can be routed through an LVDS translator and then ac-coupled as described previously, or alternatively, it can be transformer-coupled and clamped, as shown in Figure 30. 50 CLKP CLKN 50 BAV99ZXCT HIGH SPEED DUAL DIODE VCM = 400mV REFIO (Pin 55) should be bypassed to ground with a 0.1 F capacitor. The band gap voltage is present on this pin and can be buffered for use in external circuitry. The typical output impedance is near 5 k. If desired, an external reference can be connected to REFIO to overdrive the internal reference. IFS = Figure 30. TTL or CMOS DAC Clock Drive Circuit If a sine wave signal is available, it can be transformer-coupled directly to the DAC clock inputs, as shown in Figure 31. SINE WAVE INPUT DAC2 DAC2 GAIN Internal current mirrors provide a means for adjusting the DAC full-scale currents. The gain for DAC1 and DAC2 can be adjusted independently by writing to the DAC1FSC<9:0> and DAC2FSC<9:0> register bits. The default value of 0x01F9 for the DAC gain registers gives an IFS of 20 mA, where IFS equals 06569-022 0.1F DAC FULL SCALE REFERENCE CURRENT Figure 33. Reference Circuitry Figure 29. LVDS DAC Clock Drive Circuit TTL OR CMOS CLK INPUT DAC1 CURRENT SCALING FSADJ 50 LVDS_N_IN DAC1 GAIN REFIO 06569-024 LVDS_P_IN 1.2 V 3 x 72 + x DAC n FSC 10,000 16 The full-scale output current range is 8.6 mA to 31.7 mA for register values 0x000 to 0x3FF. CLKP 35 50 30 25 Figure 31. Sine Wave DAC Clock Drive Circuit The 400 mV common-mode bias voltage can be derived from the CVDD18 supply through a simple divider network, as shown in Figure 32. IFS (mA) VCM = 400mV CVDD18 5 1nF CVSS 06569-023 0.1F 15 10 1k 287 20 0 256 512 DAC GAIN CODE 768 Figure 34. IFS vs. DAC Gain Code Figure 32. DAC Clock VCM Circuit Rev. 0 | Page 23 of 28 1024 06569-025 VCM = 400mV 06569-034 CLKN AD9741/AD9743/AD9745/AD9746/AD9747 Each DAC output of the AD9741/AD9743/AD9745/AD9746/ AD9747 drives complementary current outputs IOUTP and IOUTN. IOUTP provides a near full-scale current output (IFS) when all bits are high. For example, DAC CODE = 2N - 1 where: N = 8-/10-/12-/14-/16-bits (for AD9741/AD9743/AD9745/ AD9746/AD9747 respectively), and IOUTN provides no current. The current output appearing at IOUTP and IOUTN is a function of both the input code and IFS and can be expressed as IOUTP = (DAC DATA/2N) x IFS N (1) N IOUTN = ((2 - 1) - DAC DATA)/2 x IFS (2) where DAC DATA = 0 to 2N - 1 (decimal representation). The two current outputs typically drive a resistive load directly or via a transformer. If dc coupling is required, IOUTP and IOUTN should be connected to matching resistive loads (RLOAD) that are tied to analog common (AVSS). The single-ended voltage output appearing at the IOUTP and IOUTN pins is VOUTP = IOUTP x RLOAD (3) VOUTN = IOUTN x RLOAD (4) Note that to achieve the maximum output compliance of 1 V at the nominal 20 mA output current, RLOAD must be set to 50 . Also note that the full-scale value of VOUTP and VOUTN should not exceed the specified output compliance range to maintain specified distortion and linearity performance. There are two distinct advantages to operating the AD9741/ AD9743/AD9745/AD9746/AD9747 differentially. First, differential operation helps cancel common-mode error sources associated with IOUTP and IOUTN, such as noise, distortion, and dc offsets. Second, the differential code dependent current and subsequent output voltage (VDIFF) is twice the value of the single-ended voltage output (VOUTP or VOUTN), providing 2x signal power to the load. VDIFF = (IOUTP - IOUTN) x RLOAD (5) ANALOG MODES OF OPERATION The AD9741/AD9743/AD9745/AD9746/AD9747 utilize a proprietary quad-switch architecture that lowers the distortion of the DAC output by eliminating a code dependent glitch that occurs with conventional dual-switch architectures. But whereas this architecture eliminates the code dependent glitches, it creates a constant glitch at a rate of 2 x fDAC. For communications systems and other applications requiring good frequency domain performance, this is seldom problematic. The quad-switch architecture also supports two additional modes of operation; mix mode and return-to-zero (RZ) mode. The waveforms of these two modes are shown in Figure 35. In mix mode, the output is inverted every other half clock cycle. This effectively chops the DAC output at the sample rate. This chopping has the effect of frequency shifting the sinc roll-off from dc to fDAC. Additionally, there is a second subtle effect on the output spectrum. The shifted spectrum is shaped by a second sinc function with a first null at 2 x fDAC. The reason for this shaping is that the data is not continuously varying at twice the clock rate, but is simply repeated. In RZ mode, the output is set to midscale on every other half clock cycle. The output is similar to the DAC output in normal mode except that the output pulses are half the width and half the area. Because the output pulses have half the width, the sinc function is scaled in frequency by 2 and has a first null at 2 x fDAC. Because the area of the pulses is half that of the pulses in normal mode, the output power is half the normal mode output power. INPUT DATA D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 DAC CLK 4-SWITCH DAC OUTPUT (fS MIX MODE) 4-SWITCH DAC OUTPUT (RETURN TO ZERO MODE) t t Figure 35. Mix Mode and RZ Mode DAC Waveforms The functions that shape the output spectrums for normal mode, mix mode, and RZ mode, are shown in Figure 36. Switching between the modes reshapes the sinc roll off inherent at the DAC output. This ability to change modes in the AD9741/ AD9743/AD9745/D9746/AD9747 makes the parts suitable for direct IF applications. The user can place a carrier anywhere in the first three Nyquist zones depending on the operating mode selected. The performance and maximum amplitude in all three zones are impacted by this sinc roll off depending on where the carrier is placed, as shown in Figure 36. Rev. 0 | Page 24 of 28 06569-026 DAC TRANSFER FUNCTION AD9741/AD9743/AD9745/AD9746/AD9747 QUADRATURE MODULATOR V+ 0 MIX RZ AD9747 AUX DAC1 OR DAC2 NORMAL QUAD MOD I OR Q INPUTS -20 AD9747 FS 1.5 2 POWER DISSIPATION Figure 36. Transfer Function for Each Analog Operating Mode AUXILIARY DACS Two auxiliary DACs are provided on the AD9741/AD9743/ AD9745/AD9746/AD9747. A functional diagram is shown in Figure 37. The auxiliary DACs are current output devices with two output pins, AUXP and AUXN. The active pin can be programmed to either source or sink current. When either sinking or sourcing, the full-scale current magnitude is 2 mA. The available compliance range at the auxiliary DAC outputs depends on whether the output is configured to a sink or source current. When sourcing current, the compliance voltage is 0 V to 1.6 V, but when sinking current, the output compliance voltage reduces to 0.8 V to 1.6 V. Either output can be used, but only one output of the auxiliary DAC (P or N) is active at any time. The inactive pin is always in a high impedance state (>100 k). Figure 39 shows the power dissipation and current draw of the AD9741/AD9743/AD9745/AD9746/AD9747. It shows that the devices have a quiescent power dissipation of about 190 mW. Most of this comes from the AVDD33 supply. Total power dissipation increases about 50% as the clock rate is increased to the maximum clock rate of 250 MHz. 350 310 fOUT = NYQUIST 270 fOUT = DC 230 190 0mA TO 2mA AUXP VBIAS 150 0 25 50 75 AUXN SINK OR SOURCE POSITIVE OR NEGATIVE 100 125 150 175 200 225 250 225 250 fDAC (MHz) 06569-035 0mA TO 2mA 25 TO 50 Figure 38. DAC DC Coupled to Quadrature Modulator with Passive DC Shift PTOTAL (mW) 0.5 06569-027 25 TO 50 -40 06569-029 OPTIONAL PASSIVE FILTERING DAC1 OR DAC2 -30 06569-030 T(f) (dB) -10 Figure 39. AD9747 Power Dissipation vs. fDAC 15 Figure 37. Auxiliary DAC Functional Diagram 12 9 AD9747 6 AD9741 3 0 0 25 50 75 100 125 150 175 200 fDAC (MHz) Figure 40. DVDD33 Current vs. fDAC Rev. 0 | Page 25 of 28 06569-031 IDVDD33 (mA) In a single side band transmitter application, the combination of the input referred dc offset voltage of the quadrature modulator and the DAC output offset voltage can result in local oscillator (LO) feedthrough at the modulator output, which degrades system performance. The auxiliary DACs can be used to remove the dc offset and the resulting LO feedthrough. The circuit configuration for using the auxiliary DACs for performing dc offset correction depends on the details of the DAC and modulator interface. An example of a dc-coupled configuration with low-pass filtering is outlined in the Power Dissipation section. AD9741/AD9743/AD9745/AD9746/AD9747 30 Figure 43 shows the power consumption for each power supply domain as well as the total power consumption. Individual bars within each group display the power in full active mode (blue) vs. power for five increasing levels of power-down. 350 AD9747 18 300 12 250 PDISS (mW) AD9741 0 0 25 50 75 100 125 150 175 200 225 250 fDAC (MHz) 06569-032 6 FULL ACTIVE DCO OFF AUX OFF DAC OFF CLK OFF BIAS OFF 200 150 100 Figure 41. DVDD18 Current vs. fDAC 50 15 0 11 9 7 5 AVDD33 DVDD18 CVDD18 DVDD33 TOT PWR Figure 43. Power Dissipation vs. Power-Down Mode 0 25 50 75 100 125 150 175 200 fDAC (MHz) 225 250 06569-033 ICVDD18 (mA) 13 06569-045 IDVDD18 (mA) 24 The overall power consumption is dominated by AVDD33 and significant power savings can be achieved simply by disabling the DAC outputs. Also, disabling the DAC outputs is a significant way to conserve power and still maintain a fast wake-up time. Full power-down disables all circuitry for minimum power consumption. Note, however, that even in full powerdown, there is a small power draw (25 mW) due to incoming data activity. To lower power consumption to near zero, all incoming data activity must be halted. Figure 42. CVDD18 Current vs. fDAC Rev. 0 | Page 26 of 28 AD9741/AD9743/AD9745/AD9746/AD9747 OUTLINE DIMENSIONS 10.00 BSC SQ 0.60 0.42 0.24 0.60 0.42 0.24 55 54 PIN 1 INDICATOR 0.50 BSC 18 19 37 36 0.80 MAX 0.65 TYP 8.50 REF 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.30 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4 EXPOSED PAD MUST BE SOLDERED TO PCB AND CONNECTED TO AVSS. 111507-A 12 MAX 4.70 BSC SQ EXPOSED PAD 0.50 0.40 0.30 SEATING PLANE PIN 1 INDICATOR (BOTTOM VIEW) 9.75 BSC SQ TOP VIEW 1.00 0.85 0.80 72 1 Figure 44. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 10 mm x 10 mm, Very Thin Quad (CP-72-1) Dimensions shown in millimeters ORDERING GUIDE Model AD9741BCPZ1 AD9741BCPZRL1 AD9743BCPZ1 AD9743BCPZRL1 AD9745BCPZ1 AD9745BCPZRL1 AD9746BCPZ1 AD9746BCPZRL1 AD9747BCPZ1 AD9747BCPZRL1 AD9741-EBZ1 AD9743-EBZ1 AD9745-EBZ1 AD9746-EBZ1 AD9747-EBZ1 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 72-Lead LFCSP_VQ 72-Lead LFCSP_VQ 72-Lead LFCSP_VQ 72-Lead LFCSP_VQ 72-Lead LFCSP_VQ 72-Lead LFCSP_VQ 72-Lead LFCSP_VQ 72-Lead LFCSP_VQ 72-Lead LFCSP_VQ 72-Lead LFCSP_VQ Evaluation Board Evaluation Board Evaluation Board Evaluation Board Evaluation Board Z = RoHS Compliant Part. Rev. 0 | Page 27 of 28 Package Option CP-72-1 CP-72-1 CP-72-1 CP-72-1 CP-72-1 CP-72-1 CP-72-1 CP-72-1 CP-72-1 CP-72-1 AD9741/AD9743/AD9745/AD9746/AD9747 NOTES (c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06569-0-5/07(0) Rev. 0 | Page 28 of 28