ANALOG DEVICES AN-318 APPLICATION NOTE ONE TECHNOLOGY WAY e P.O. BOX 9106 e NORWOOD, MASSACHUSETTS 02062-9106 617/329-4700 AD7528 Dual 8-Bit CMOS DAC Application Note by Paul Toomey and Bill Hunt INTRODUCTION The AD7528 is a monolithic dua! 8-bit CMOS DAC pack- aged in a 20-pin DiP. Each DAC has its own 8-bit data latch which loads data from a common 8-bit data bus (see Fig- ure 1). Since both DACs are fabricated on the same chip, precise matching and tracking between DACs is inherent. This property of the AD7528 dual DAC, along with the P.C. board space saving it allows, makes the AD7528 a unique and extremely useful device. qT 4 OAC A Figure 1. AD7528 Functional Diagram This note discusees the AD7528 applications circuits listed below. Several of these circuits rety on the DAC to DAC matching provided by the AD7528. All of the circuits benefit from the high pecking density the AD7528 allows, especiaily when used with dual and quad op-amps such as the AD644 or TLO74. Not discussed in this note ere basic details of AD7528 operation, consult the data sheet for this information. AD7828 APPLICATIONS DISCUSSED IN THIS NOTE 1. State-variabie filter (S.V.F.) with programmabie center frequency, selectivity and gain. 2. Programmable sine wave oscillator with linear control. 3. Function fitting sine wave synthesizer with amplitude control facility and programmabie phase shift. 4. Programmable voitage/current source, unipolar and bipolar circuits. 5. Programmable gain amplifier with no trimpots. 6. Programmable waveform generator for vector scan CRT displays. 7. AD7826 single-supply operation circuits for low iy budget applications requiring multiple analog outputs STATE VARIABLE FILTER WITH PROGRAMMABLE CENTER FREQUENCY, SELECTIVITY (Q) AND GAIN The state variable filter (or universal filter as it is often calied) is a convenient 2nd order filter biock. It provides simultaneous low-pass, high-pess and bendpass outputs. All filter perameters can be readily adjusted. Figure 2 shows a typical filter circuit with expressions for center frequency, QO and gain for the bendpass output. Lid ouTpuT CJ P Cd mt c ms re c Vou at we + aa nm > Low PASS OuTeUT ma n> STATE VARIABLE FILTER BANOPASS OUTPUT Figure 2. State Variable Filter Where f = frequency of Vin Ao =gainatf=f, fo Q = circuit Q factor, i.e., 3dB Bandwidth jwidth fo = resonant frequency. DIGITAL-TO-ANALOG CONVERTERS 8-113CIRCUIT EQUATIONS: Ct = C2, R3 = R4, R7 = RB C2 1000pF 1 oh er j+ fo =a ; eee an 8 R2 ohitg M0 ~ jy For Bandpees Output 2 fie o ours DAC EQUIVALENT RESISTANCE EQUALS 256 x (DAC LADDER RESISTANCE) on ) AD?628 f wOTES: 1X SK? aw aW 6 C3 1S A COMPENSATION CAPACITOR TO ELIMINATE AND GA VARIATIONS CAUSED SY AMPLIMGR GANG BANDUADTH LIMITATIONS eo SS WM OA ORS 06 REPLACED BY DAC 61 UITERMAL APB ~ 114i), OF-AMPS ARE +16 pes.087 BACB 2x apeu. COMPONENT VALUES SHOWN PROGRAMMABLE OATA2 RANGE 1G O = 0.3 TO 45, lo =0 te 1Skite. Figure 3. Digitally Controlled State Variable Filter Introducing the DACs as Control Elements: By replacing A1, R2 and R3, R4 with matched DAC pairs the fier parameters can be made programmable as shown in Figure 3. DAC Ail and DAC B1 control filter gain and Q, while DAC A2 and DAC B82 control center frequency (f,). For the component values shown the programmable Q range is from 0.3 to 4.5 and is independent of f, (see Figure 4). Center frequency (f,) is programmable from 0 to 15kHz (eee Figure 5) and is independent of Q. f, = 20nhe _ ow - t {, = tte 2s Figure 5. Filter f, Variation Programming The graph in Figure 6 shows how the circuit QO varies with DAC B1 code and Figure 7 shows how the center fre- quency varies with DAC 2 (A and B) code for the compo- nent values given in Figure 3. Gain variation alone is accomplished by changing DAC A1 cade. Unity gain oc- curs when the data in DAC A1 and DAC B11 latches is iden- tical. Since the AD7526s logic inputs are TTL or CMOS compatible, the DACs are readily interfaced to most microprocessors, (see data sheet for hookups) thus pro- viding an ideal microprocessor-to-filter interface. 8-114 DIGITAL-TO-ANALOG CONVERTERS L {\ o Pe eon a? NE mt 2 Cd a * a co Lid Lad OAC Bt HEPUT CORE, HEX Figure 6. Filter Q Variation with Code 2 a * td a co Lo F BAL ALAND BAC OROPUT CORE, HEX Figure 7. Fitter f, Variation with Code PROGRAMMABLE SINE WAVE OGCILLATOR WITH LINEAR CONTROL Frequency contro! of many oscillator circuits can be accomplished using two ganged potentiometers. How- ever, the two potentiometers must track precisely over their full temperature range if a linear response is re- quired. Figure 8 shows e high performance sine-wave os- cillator realized using a state-variabie filter. The frequency of oscillation is set by ganged potentiometers P1 and P2.Figure 9 shows the same circuit with P1 and P2 replaced by the AD7528 matched pairs. Al, Al, Al = ADE Figure 8. Sine Wave Oscillator Using a State Variable Filter Figure 9. Programmable Sine Wave Oscillator Using a State Variable Filter and a Dual DAC The equivalent resistance of each DAC, as seen by op- amps A2 and A3 varies with input code from infinity at code 00 Hex (0000 0000) to a minimum of ~ 11kf (DAC ladder resistance) at code FF HEX (1111 1111). a e o a od co 0 * OAC A AND DAC B INPUT CODE HEX! Figure 10. Frequency vs. DAC Code for Programmable Sine Wave Oscillator (Figure 9) Loading each DAC latch with the same code provides a linear code versus frequency relationship as shown in Fig- ure 10. The frequency of oscillation can be expressed as: N Output Frequency = 256 (2a) Hz Where R= DAC ladder resistance i.e. Var input resistance. C = isasshown in Figure9. N = decimal representation of digital input code. For example, N = 128 for input code 10000000. For the component values given in Figure 9, output fre- quency is variable from 0 to 15kHz. Output amplitude is controlled by the zener diode D1. Total harmonic distor- tion for the circuit shown is 53dB at low frequencies (1kHz) and 43dB at higher frequencies (14kHz). Note that a cosine output is also available at the output of op- amp Az2. FUNCTION FITTING SINE WAVE SYNTHESIZER In this application the multiplying capabilities of the two CMOS DACs are used to synthesize a sine wave based on a function fitting technique. This allows very low fre- quency, highly stable sine waves to be generated. Function Fitting: Function fitting is a technique for translating a mathemati- cal or empirical relationship from one medium (such as a mathematical formula) to another medium (usually a physically realizable device or system). This application uses the dual DAC to implement a one quadrant sin X ap- proximation in the form of the quadratic polynomial. Y = 1.828N 0.828N2 whereO<N<1andN = 2 x The graph of Figure 11 shows the relationship between sin X and its quadratic approximation given above. The 6 ow xo wt =a = wa Figure 11. Relationship Between Sin X and its Quadratic Approximation circuit of Figure 12 implements the function by ramping N up and down using an up/down counter, and switching the circuit output polarity. This generates sin X in four stages (see Figure 13). Circuit Operstion: (Figure 12) An input clock drives the up/down counter in real time. The counter is connected so that it counts up and down continuously, providing an output pulse at borrow every time it reaches the all zeros count. DIGITAL-TO-ANALOG CONVERTERS 8-115. four AT-A2, AD-A4 = ADEN IMU Figure 12. Function Fitting Sine Wave Generator DAC A produces a triangle waveform consisting of two ramps of opposite slope, each generated in 256 steps at op-amp Ai output. This is the N variable. DAC B is driven with the same digital word as DAC A. Its reference input is driven by op-amp A1, thus DAC B multi- plies the digital version of N by the analog version of N to produce an output from op-amp A2 of N? (negative sign is due to inversion through A2). Since the N and N? signals are of opposite polarity, the Y = 1.828N - 0.828N? expression is implemented by sum- ming N and N? signals in the correct ratios determined by RA and RB. The analog switch, in conjunction with op-amp A4, changes the circuit's output polarity at one-half the triangle wave frequency, thus producing both positive and negative haives of the sine wave. vy ee AT OUTPUT: X VARIABLE | A4 OUTPUT: COMPLETED SINE WAVE Figure 13. Sine Wave Synthesis Using Function Fitting Distortion: Distortion in the output sine wave is a function of the quadratic approximation fit to the sine curve. Errors in the values of R, and Ra will, therefore, contribute directly to distortion. If Ra is made adjustable over a small range, it can be trimmed to minimize distortion. Distortion was measured for the circuit of Figure 12 at 33dB and was constant over sine-wave frequency 0-2.5kHz. 8-116 DIGITAL-TO-ANALOG CONVERTERS The circuit of Figure 12 generates constant amplitude sine waves in the 0-2.5kHz frequency range. Output frequency is given by fout = fk 1024 It is possible to obtain rapid frequency sweeping by var- ing the input clock rate. The counter up/down output pro- vides a useful zero crossing pulse. By applying an ac sig- nal to the DAC A reference input, the output sine wave can be amplitude-modulated as shown in Figure 14. Figure 14. Amplitude Controi Using DAC A Reference input Output amplitude is directly controlled by the voltage level on DAC A reference input. Ac or dc signals may be used within the range +10 volts, 0 to 10kHz. Figure 14 shows the amplitude of a 1kHz sine wave being controlled by a 55Hz sine wave. Programmable Phase Two sine waves with 0 to 360programmablie phase re- lationship can be generated by running two of the circuits, shown in Figure 12, from the same input clock source. By allowing one circuit to start running from zero count a pre- set number of clock cycies before the other, a phase differ- ence between their output sine waves is introduced (see Figure 15). Since each complete cycle is generated by 1024 clock cy- cles, phase steps of 9360/1024 degrees are programmable. Note aiso that the phase difference is independent of out- put frequency.| me funcrion erTwa We =a a nnn prem le PRESET 2 meee ace ween mate |X N77 Figure 15. Programmable Phase Relationship PROGRAMMABLE VOLTAGE/CURRENT SOURCE USING DUAL DAC AD7528 The circuit in Figure 16 is that of a unipolar V/I source. A negative reference is required for a positive output voltage. The circuit provides; (a) Aprogrammabie output voltage N Vout = +VprerA a forN, = 0to 255. provided the current limit is not exceeded. (b) In the voltage mode, a programmable load current limit given by: R, 1 Ne loutimex)= VnerB - Ry fea 256 for Ng = Oto 255. p+ 1SV REFERENCE 17 3 PUT asi Rez oe rat 2 = foe 10000 | ae DACA at Wiveont ie, 2 ? 5 Ae | Raenee? st Vaal 20) ox oac 8 az , ono > s) aov7e2s 3% Own Or On a sm | 8 S Al, AZ ond AS. Ad = ADESS 180K NOTE: 01 SHOWN POR POSITIVE OUTPUT POLARITY. REVERSE 01 POR NOBATIVE OUTPUT VOLTAGE. Figure 16. Programmable Voitage/Current Source Vour = 0 to +10V, lour = Oto +10MA (c) A constant current feature by setting Na = 255 i.e., maximum output voltage capability, and limiting the load resistance value R, such that 255 loutimax) * Ri < 356 YrerA i = ~Ry 1 Ne with lout (mex) = VaerB Ra Rep 256 asin (b). A useful feature of the circuit is the possibility of load cur- rent readback in the voltage mode (or load voltage readback in the current mode). By monitoring point X in Figure 16, as the current limit value is reduced, a state change will take place when current limit is attained. The set current limit value will correspond to the load current. In the circuit DAC A with amplifier A1 and buffer A3 acts as a standard programmable voltage source when VacrA is held constant. The voltage drop across resistor Rc pro- vides a voitage proportional to load current with Re, act- ing as a current limit on amplifier A2. Amplifier A4 with resistors R, and Ro references the voitage across Rs? to R ground and also provides gain ), The output of A4 C2 LI Von OUT A @To 2 3 wee. een | 200 wesies - 12 aDresamy toanS wan . t 1 (st ov M hey(4 3 yer som D1: ol a NN 10% Al = ADEs A2A} = ADSO AAAS = ADE Figure 17. Programmable Voltage/Current Source with Bipolar Output DIGITAL-TO-ANALOG CONVERTERS 8-117is compared with a proportion x of VaerB Oe VaerA = VrerB) by amplifier A2. If Vouts > VeaerB sex a then current limit is required and the output of A2 via diode D1 draws load current to maintain a constant load current. N if Vouta < VaerB agg then the current limit is not required and amplifier A2 output is disconnected as diode D1 is re- versed biased. Figure 17 shows a similar circuit for bipolar operation, i.e., Oto + 10V atOto + 10mA. DUAL DAC PROGRAMMASLE GAIN AMPLIFIER WITH NO TRIMPOTS Aunique advantage of the matched DACs available in the AD7528 is utilized in the programmable gain/attenuation circuit shown in Figure 18. The equivalent resistance of each DAC from its reference input to its output is used to replace the input and feedback resistors in the standard inverting amplifier circuit. By loading DACs A and B with suitable codes, programmable gain/attenuation over the range 48dB to + 48dB can be achieved. In the circuit of Figure 18, the DAC equivaient resistances are given by: 256R 256R, pB RoacA = ZEA and Roac --K STANDARD CIRCUIT ne Ve ss ba Vour Vour = ~92-Ven NS rmoenencuT na pace Vour = ~ ff-Ve WHERE 1=NA= 255 ; 1S NO=< 208 Vn OF DACA a Figure 18. Dual DAC Programmable Gain Amplifier v WF vi +19 Oe 2 i= DAC A al he + bata oe 1 1 1 ADYS28 a ) wm 28 oace aa 1 OEs + s : DGND ORK TO pp mrTeRMUT pace REQUIRED Where: RipA and RipB are DAC A and DAC B R-2R ladder resistances respectively, Na and Ng are the DAC codes in decimal (1-255). The resultant gain expression for the circuit is Spur 256 RipB Na Ny SERA This simplifies to: Vout Rip8 - Na Vin Pup Ng But since DAC A and DAC B are a matched pair, RipA = RipB. simplifies the expression even further to give: Na 1=N,g3255 ot ~ ~Ne 15Ng = 255 Notice that DAC ladder resistance does not appear in the expression. Previous PGA circuits using DACs have al- ways had to be trimmed to accommodate the DAC ladder resistance which usually has a wide tolerance (typically 8k to 20k). This circuit does not suffer from this problem since RipA and R.p8 are matched to better than 1%. Notice also that the circuit has a constant input resistance of RipA. The two unused feedback resistors, RegA and RegB are also precisely matched and could be used to pro- vide other DAC code vs. gain relationships. PROGRAMMABLE WAVEFORM GENERATOR FOR VECTOR SCAN CRT DISPLAYS Figure 19 shows the dual DAC in a triangle/rectangle wave generator in which the period of each haif cycle can be programmed. Such a circuit is useful for vector scan CRT displays to generate variable rate sweep signals (depend- ing upon whether a long or short vector is to be drawn). DAC A determines the ramp rate for the positive going ramp of the triangle while DAC B determines the ramp rate for the negative going ramp. The integrator output voitage is sensed by comparators A4 and A5. When this voltage reaches + 10V or 10V the comparators drive the R-S flip-flop G1 and G2 which selects the output of the ap- propriate DAC via the double-pole ganged analog switch sw1,SW2. The switching arrangement shown has the advantage that high speed switches (such as CD 4016 or AD7519) can be used to change between the two DACs without in- troducing significant output glitches at the changeover. Al, A2 = ADEA $A = ADB Ad, AS = ADSI SW, SW2 = AD7612 OR ADTS19 +5V swe wn S ew 1 u & e t PUT WA + 4 TRANGLE ' tang i et ewe oh aL RECTANGLE OUTPUT -- Figure 19. Digitally Programmable Waveform GeneratorFurthermore, one DAC can be updated from the data bus and allowed to settle while the output of the other DAC is being used to generate the ramp signai. The output of flip- flop G1 and G2 automatically connects the unused DAC to the data bus for further data update if necessary. The output of the flip-flop can be used to drive the interrups of a microprocessor if required. Selecting Waveform Parameters: The period (t) of the waveforms generated by the circuit is given by: 1. 1 | t = 512RC lm + Ne where N, and Ng are the DAC A, DAC B codes in decimal (1-255) respectively. lf DAC A and DAC 8 latches contain the same codes, the expression simplifies to: 1024RC . Na Na i.e., output frequencyf = 7024RC Hz The mark-to-space ratio of the rectangle wave output is dependent on the ratio of Ng to Na t= N Markto Space Ratio = Ne A special case, exists when the code in either DAC is zero. in this case the circuit will stop oscillating as the integrator input voltage will be zero. If the all zeros condition can occur, it is advisable to connect a 10MQ resistor from the Veer terminal to the output terminal of each DAC, i.e, VaerA to OUT A and VaesB to OUT B. This provides suffi- cient bias current to keep the circuit oscillating, and does not affect frequency calculations significantly as the 10M resistor introduces onty 1/4 LSB of additional error into each DAC output. maa + 15 AD7S528 SINGLE SUPPLY OPERATION In jow budget digital designs requiring analog outputs, the cost of adding an extra power supply rail for the DAC circuits can be a limiting factor. The AD7528 in the single supply configurations shown below provides an ideal cost effective solution for such applications (especially where multiple analog outputs are required). Single Supply, Voltage Switching Mode: In this mode, the normal DAC R-2R ladder is inverted. The reference voltage is applied to the DAC OUT A or OUT B terminal and the output voltage is taken from the DAC VaerA or VeeeS terminal. For the DACs to retain their specified linearity, the reference voltage range must be restricted as follows: For Vpop = + 15V,Vagemax = +2.5V ForVpp = +5V,Vreemax = +0.5V Figure 20 shows a circuit for use with a + 15 volt power supply giving four separate 0 to + 10V outputs. The op- amps used have a Class A output configuration for small signal levels, thus allowing their outputs to go to zero volts for zero volts input. At higher signal levels, the out- puts convert to Class B. Single Supply, Current Steering Mode: This mode of operation is described in the AD7528 data sheet, and is suitable for single + 10 voit to + 15 volt sup- ply operation. This is achieved by biasing the AD7528 ana- log ground (AGND) +5 voits above the power supply ground. Unlike the previous circuits the available drive for the DAC switches is now Vpp 5 volts so the 5 voit specifi- cations apply for linearity. Figure 21 shows how a + 2 volt to +8 voit analog output may be obtained using two op- amps per DAC. The two DAC reference inputs are tied il a@hbuna ii ( fi 28a 2 one #55 z z E i Figure 20. Four Channel Analog Output Circuit DIGITAL-TO-ANALOG CONVERTERS 8-119Voo = +10V TO +15V Vourd = +2V TO +8V (For CODE 1119 1115 TO cese enee} bn Veur & = +2V TO +8V (POR DAC CODE 1119 1117 TO e008 cee) Figure 21. AD7528 Single Supply Operation with AGND Biased to +5 Volts together and a reference input voltage is obtained without a buffer amplifier by making use of the constant and matched impedances of the DAC A and DAC B reference inputs. Current flows through the two DAC R-2R ladders into R1; R1 is adjusted until VaccA and Vags8 inputs are at +2 voits. The adjustment is independent of either DAC code. Each analog output channel has a +2 to +8 volt range for DAC codes 1111 1111t0 0000 0000. 8-190 DIGITAL.TO.ANALOG CONVERTERS Reference Dan H. Sheingold, Nonlinear Circuits Handbook, avail- able from Analog Devices. D. P. Burton, Application Note Methods For Generating Complex Waveforms And Vectors Using Multiplying D/A Converters Analog Devices Publication Number: E671- 15-9/81. Application Guide to CMOS Multiplying D/A Converters, Analog Devices Publication Number: G479-15-8/78.