S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) S5K4B1FX 1/4" UXGA CMOS Image Sensor supporting SMIA 1.0 Preliminary Data Sheet (Rev. 0.20) SAMSUNG ELECTRONICS PROPRIETARY Copyright (c) 2006 Samsung Electronics, Inc. All Rights Reserved SAMSUNG PROPRIETARY 1/30 S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) Contents Features ..................................................................................................................................................................4 General Description.................................................................................................................................................4 Logical Symbol Diagram .........................................................................................................................................5 Module Pin Configuration ........................................................................................................................................6 Functional Description...........................................................................................................................................11 Power Up Sequence .............................................................................................................................................22 Power Down Sequence.........................................................................................................................................24 Internal Power-on Reset........................................................................................................................................26 Stand-By Sequence...............................................................................................................................................28 Electrical Characteristics .......................................................................................................................................29 SAMSUNG PROPRIETARY 2/30 S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) List of Figures Figure 1 : Logical Symbol Diagram ............................................................................................................................5 Figure 2 : Module Pin Description ..............................................................................................................................6 Figure 3 : Video Timing Overview...............................................................................................................................7 Figure 4 : CCI message type ......................................................................................................................................8 Figure 5 : CCI read operation .....................................................................................................................................9 Figure 6 : CCI write operation...................................................................................................................................10 Figure 7 : Function Block Diagram ........................................................................................................................... 11 Figure 8 : Addressable Pixel Array ...........................................................................................................................12 Figure 9 : Analog Gain Value ....................................................................................................................................16 Figure 10 : Clock tree structure ................................................................................................................................17 Figure 11 : Full Scaler Block Diagram ......................................................................................................................18 Figure 12 : Frame Format.........................................................................................................................................19 Figure 13 : PN9 Linear Feedback Shift Registers ....................................................................................................20 Figure 14 : CCP Timing Specifications .....................................................................................................................21 Figure 15 : Power-Up Sequence ..............................................................................................................................23 Figure 16 : Power-Down Sequence..........................................................................................................................25 Figure 17 : Power-on Reset Power-up and Supply Glitch/Brown-out Timing...........................................................27 Figure 18 : Stand-By Sequence................................................................................................................................28 List of Tables Table 1 : Power-Up Sequence Timing Constraints ...................................................................................................22 Table 2 : Power-Down Sequence Timing Constraints ..............................................................................................24 Table 3 : Internal Power-on Reset Cell Specifications..............................................................................................26 Table 4 : Absolute Maximum Rating .........................................................................................................................29 Table 5 : Operating Conditions .................................................................................................................................29 SAMSUNG PROPRIETARY 3/30 S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) FEATURES z z z z z z z z z z z z z z z z z z z z z SMIA 1.0 compliant Optical size: 1/4 inch Pixel size: 2.25 um Effective resolution: 1600 (H) x 1200 (V), UXGA Line progressive read out Vertical and horizontal flip mode Continuous frame capture mode Sub-sampled readout Output format: RAW 10-Bit and 8-Bit mode using DPCM/PCM compression Max. frame rate: 30fps @ UXGA (for all output format including RAW10) Digital gain control (X1~X8, 1/256 step) Color space conversion Image scaling down (to arbitrary number that is greater than or equal to 256x192) Built-in test pattern generation Standby mode for power saving CCI(I2C-compatible) bus control interface Operating temperature: -30C to +70C Supply voltage: 2.8V for analog 1.8V for digital Internal voltage regulator for 1.5V generation Internal PLL for high speed clock generation High speed SubLVDS data/clock or data/strobe signaling GENERAL DESCRIPTION The S5K4B1FX is a highly integrated UXGA camera chip which includes CMOS image sensor (CIS) and CCP2compliant image data interface. It is fabricated by SAMSUNG 0.13m CMOS image sensor process developed for imaging application to realize high-efficiency and low-power photo sensor. The sensor consists of 1600 x 1200 effective pixels which meet with 1/4 inch optical format. The CIS has on-chip 10-bit ADC arrays to digitize the pixel output and also on-chip Correlated Double Sampling (CDS) to reduce Fixed Pattern Noise (FPN) drastically. The image data interface performs data formatting, image compression, image scaling and serial transmission using SubLVDS. The host controller is able to access and control this device via CCI bus. The S5K4B1FX is suitable for low power camera module with 2.8V/1.8V power supply. SMIA 85 8.5 X 8.5 X 6.1 (mm) SAMSUNG PROPRIETARY 4/30 S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) LOGICAL SYMBOL DIAGRAM Figure 1 : Logical Symbol Diagram SAMSUNG PROPRIETARY 5/30 S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) MODULE PIN CONFIGURATION Figure 2 : Module Pin Description SAMSUNG PROPRIETARY 6/30 S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) I/O Timing Description Video Output Timing Figure 3 : Video Timing Overview SAMSUNG PROPRIETARY 7/30 S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) Control Interface Timing 1. Camera Control Interface (CCI) S5K4B1FX supports the Camera Control Interface (CCI), which is an I2C Fast-mode compatible interface for controlling the transmitter. The CCP2 receiver is always a master and CCP2 transmitter always a slave in the CCI bus. CCI is capable of handling several slaves in the bus, but multi-master mode is not supported. Typically no other devices than CCP2 receiver and transmitter are connected to the CCI bus. This makes a pure SW implementation possible. Typically the CCI is separate from the system I2C bus, but I2C compatibility ensures that it is also possible to connect the transmitter to system I2C bus. CCI is a subset of I2C protocol including the minimum combination of obligatory features for I2C slave device specified in the I2C specification. Therefore transmitters complying with the CCI specification can also be connected to system I2C bus. However, it has to be taken care that the I2C masters do not try to utilize those I2C features, which are not supported in transmitters complying with the CCI specification. Each transmitter conforming the CCI specification may have additional features implemented to support I2C. 1.1 Data transfer protocol The data protocol is according to I2C standard specified in I2C specification. 1.1.1 Message format The S5K4B1FX CCI supports 16-bit index with 8-bit data with basic I2C standard protocol; START condition, slave address with read/write bit, acknowledge from slave, and STOP condition. In read operation, data byte comes from slave till negative ack is asserted from master. The device address for the sensor is "0010_000b + 1bit R/W bit". (Write mode : 0010_0000b, Read mode : 0010_0001b) Figure 4 : CCI message type 1.1.2 Read / Write operation The S5K4B1FX CCI interface must be able to support four different read operations and two different write operations; single read from random location, sequential read from random location, single read from current location, sequential read from current location, single write to random location and sequential write starting from random location. The read/write operations are presented in the followings.The 16bit index in the slave device has to be auto incremented after each read/write operation. SAMSUNG PROPRIETARY 8/30 S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) Figure 5 : CCI read operation SAMSUNG PROPRIETARY 9/30 S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) Previous index value K S Slave Address 0 A 7 bits Sub Address Sub Address A Index M+1 Index M A / P A DATA A Index M (16bit) Single write to random location Previous index value K S Slave Address 0 A 7 bits Sub Address A Sub Address Index M (16bit) Index M+L-1 Index M A DATA A L byte DATA Sequential write starting from random location NOTES: 1. S: Start, P: Stop, RS: Restart A: Acknowledge, A: Negative acknowledge, 2. : From Master to Slave, : From Slave to Master Figure 6 : CCI write operation SAMSUNG PROPRIETARY 10/30 DATA Index M+L A / P A S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) FUNCTIONAL DESCRIPTION CCI slave SCL APS array Row driver Timing Generator XSHUTDOWN SDA Register Bank (1616 x 1216 : actual size of array) Ramp generator TST_DBLR VPAD2 Voltage Regulator REG_CAP CDS/ADC array 10 Data bus 10 D gain/ C matrix 10 Scaler 10 PCM/ DPCM 8/ 10 CCP2 formatter 8 EXTCLK PLL CLK divider Serializer/ D-STB encoder POR SubLVDS Driver SubLVDS Driver DATA+ DATACLK+ CLK- REF_R Figure 7 : Function Block Diagram SAMSUNG PROPRIETARY 11/30 S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) 1. Output Data Format 1-1. Pixel array addresses Addressable pixel array is defined as the pixel address range to be read. The Addressable pixel array can be assigned anywhere on the pixel array. The addressed region of the pixel array is controlled by x_start_addr, y_start_addr, x_end_addr and y_end_addr register. Figure 10 refers to a pictorial representation of the Addressable pixel array on the Physical pixel array. The limits for the above parameters are given by the x_addr_min, y_addr_min, x_addr_max, y_addr_max register. (x_addr_min, y_addr_min) (x_addr_start, y_addr_start) Addressed Pixel Array Region (x_addr_end, y_addr_end) (x_addr_max, y_addr_max) Figure 8 : Addressable Pixel Array 1-2. Mirror/Flip The pixel data are read out from left to right in horizontal direction and from top to bottom in vertical direction normally. By changing the mirror/flip mode, the read-out sequence can be reversed and the resulting image can be flipped like a mirror image. Pixel data are read out from right to left in horizontal mirror mode and from bottom to top in vertical flip mode. The horizontal mirror and the vertical flip mode can be programmed by image orientation register. The sensor module support 4 possible pixel readout order 1) standard readout 2) Horizontally mirrored readout 3) Vertical Flipped readout 4) Horizontally Mirrored and Vertically Flipped readout SAMSUNG PROPRIETARY 12/30 S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) Direction of Pixel Readout 0 1 2 3 4 5 6 7 0 G R G R G R G R 1 B G B G B G B G 2 G R G R G R G R 3 B G B G B G B G 4 G R G R G R G R 5 B G B G B G B G 6 G R G R G R G R 7 B G B G B G B G 0 1 2 3 4 5 6 7 0 Direction of Line Readout Direction of Line Readout Direction of Pixel Readout 1 2 3 4 5 6 7 1) Standard Readout Direction of Pixel Readout 7 6 5 4 3 2 1 0 0 R G R G R G R G 1 G B G B G B G B 2 R G R G R G R G 3 G B G B G B G B 4 R G R G R G R G 5 G B G B G B G B 6 R G R G R G R G 7 G B G B G B G B 7 6 5 4 3 2 1 0 0 Direction of Line Readout Direction of Line Readout Direction of Pixel Readout 1 2 3 4 5 6 7 2) Horizontally Mirrored Readout Direction of Pixel Readout 0 1 2 3 4 5 6 7 7 B G B G B G B G 6 G R G R G R G R 5 B G B G B G B G 4 G R G R G R G R 3 B G B G B G B G 2 G R G R G R G R 1 B G B G B G B G 0 G R G R G R G R 0 1 2 3 4 5 6 7 7 Direction of Line Readout Direction of Line Readout Direction of Pixel Readout 6 5 4 3 2 1 0 3) Vertically Flipped Readout SAMSUNG PROPRIETARY 13/30 S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) Direction of Pixel Readout 7 6 5 4 3 2 1 0 7 G B G B G B G B 6 R G R G R G R G 5 G B G B G B G B 4 R R G R G R G 3 G B G B G B G B 2 R G R G R G R G 1 G B G B G B G B 0 R G R G R G R G 0 1 2 3 4 5 6 7 7 Direction of Line Readout Direction of Line Readout Direction of Pixel Readout 6 5 4 3 2 1 0 4) Horizontally Mirrored and Vertically Flipped Readout 1-3. Sub-Sampled readout By programming the x and y odd and even increment register (x_even_inc, x_odd_inc, y_even_inc, y_odd_inc). the sensor can be configured to readout sub-sampled pixel data. 1 3 0 1 0 G 1 2 1 3 3 4 5 R G B G 4 G 5 6 1 7 3 8 9 R G R B G B G R G R G R B G B G B G 8 G R G R G R 9 B G B G B G 10 1 2 3 3 1 6 3 7 1 10 3 11 x_addr_start = 0 x_even_inc = 1 x_odd_inc = 3 SAMSUNG PROPRIETARY 14/30 y_addr_start = 0 y_even_inc = 1 y_odd_inc = 3 11 S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) 1-4. Frame Rate Control (Virtual Frame) The line rate and the frame rate can be changed by varying the size of virtual frame. The virtual frame's width and depth are controlled by line_length_pck and frame_length_lines register. The frame rate can be calculated by the following equation: Frame rate = 1 / (line_length_pck * frame_length_lines) * vt_pix_clk_freq_mhz For S5K4B1FX, the minimum line_length_pck is 1738(decimal) and other parameters can be set appropriately according to the above equation. 1-5. Integration Time Control (Electronic Shutter Control) The pixel integration time is controlled by shutter operation. In shutter operation, the amount of time, integration time, is determined by the column Step Integration Time Control Register (fine_integration_time) and line Step Integration Time Control Register(coarse_integration_time). The total integration time of sensor module can be calculated using the following formula. Total_integration_time = {(coarse_integration_time*pixel_period_per_line)+fine_integration_time}*pck_clk_period 1-6. Dark Level Compensation The data pedestal is the pixel value the sensor module produces when there is no light incident on the sensor module. The sensor module must have an internal calibration function, which ensures that data pedestal value remains constant with integration time, gain, and temperature and between different sensors. The host system should always use the data_pedestal register value to determine the sensor output black level. Register Name data_pedestal Type 16-bit unsigned integer RW Comment RO Static System 8-bit 10-bit Typical Data Pedestal 16 64 1-7. Image Format Format Bit stream False Sync. Protection (FSP) RAW8 P1[7:0] P2[7:0] P3[7:0] P4[7:0] P5[7:0] P : 1~255 RAW10 P1[9:2] P2[9:2] P3[9:2] P4[9:2] P4[1:0] P3[1:0] P2[1:0] P1[1:0] P : 4~1023, check every 5th byte SAMSUNG PROPRIETARY 15/30 S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) 2. Analog to Digital Converter (ADC) The image sensor has an on-chip ADC. Column parallel ADC scheme is used for low power analog processing. 2-1. Correlated Double Sampling (CDS) The analog output signal of each pixel includes some temporal random noise caused by the pixel reset action and some fixed pattern noise caused by the in-pixel amplifier offset deviation. To eliminate those noise components, a Correlated Double Sampling(CDS) circuit is used before converting to digital. The output signal sampled twice, once for the reset level and once for the actual signal level sampling. 2-2. Analog Gain Control The user can control the gain of pixel signal by Analog Gain Control Register (analogue_gain_code_global). According to SMIA 1.0 specification, the analog gain can be given by the following equation: Analog Gain = (m0 x + c0) / (m1 x + c1) S5K4B1FX specifies analog gain by coefficients of m0 = 0, c0 = 128, m1 = -1, c1 = 128. As a result, users can control analog gain as following equation: Analog Gain = 128 / (128 - analogue_gain_code_global[15:0]) 10 45 9 40 8 35 Analog gain value [dB] Analog gain value Separate channel gain is also supported in addition to global analog gain. Theoretically, maximum x128 gain can be obtained, but analog gain up to x16 is recommended for image quality. 7 6 5 4 3 2 30 25 20 15 10 5 1 0 0 16 32 48 64 80 96 112 0 16 Analogue_gain_code_global [code] 32 48 64 Figure 9 : Analog Gain Value (Gain 1x : 00h, Gain 2x : 40h, Gain 3x : 50h, Gain 4x : 60h, Gain 8x : 70h, Gain16x : 78h) SAMSUNG PROPRIETARY 16/30 80 96 Analogue_gain_code_global [code] 112 S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) 3. Image Scaling and Data Interface The S5K4B1FX is a high performance and low power UXGA CMOS image sensor with image scaling functions. It generates 10-bit raw data from 10-bit sensor with maximum frame rate of 30 fps at UXGA resolution and transmits the data in the forms of RAW10, RAW8 specified in SMIA CCP2 Specification 1.0. It performs image scaling functions for horizontal/full scaling. The host controller is able to access and control it through CCI bus interface (also specified in SMIA CCP2 Specification 1.0). 3-1. PLL and Clock Generator S5K4B1FX contains a Phase-Locked Loop(PLL) and a clock generator, which generates all the necessary video timing and output pixel clocks from the external clock input. By setting the divide-ratio for Pre PLL Clock Divider(pre_pll_clk_div) and PLL Multiplier(pll_multiplier) appropriately, users can get necessary PLL output Clock(pll_op_clk_freq_mhz). The minimum and maximum limits for the output clock frequencies and divideratios of the various clock dividers are fully described and limited by the Parameter Limit Registers (Read Only) from 0x1100 to 0x1177 address. The PLL can handle any ext_clk_freq_mhz in the range of 6.0MHz to 27MHz, and synthesize pll_op_clk_freq_mhz between 324MHz and 650MHz by 1 steps of pll_multiplier. For the proper PLL operation, pll_ip_clk_freq_mhz should be in the range of 1MHz to 6MHz. All PLL programming should be performed during software stand-by mode for the stable system operation. The overall clock tree structure is shown in Figure 12, and there are user-controllable divide-ratios in the red box. All necessary frequencies are synthesized by the following equations. pll_ip_clk_freq_mhz = ext_clk_freq_mhz / pre_pll_clk_div (pll_ip_clk_freq_mhz : 1MHz ~ 6MHz) pll_op_clk_freq_mhz = pll_ip_clk_freq_mhz * pll_multiplier (pll_op_clk_freq_mhz : 324MHz ~ 650MHz) vt_sys_clk_freq_mhz = pll_op_clk_freq_mhz / vt_sys_clk_div vt_pix_clk_freq_mhz = pll_op_clk_freq_mhz / (vt_sys_clk_div * vt_pix_clk_div) op_sys_clk_freq_mhz = pll_op_clk_freq_mhz / op_sys_clk_div op_pix_clk_freq_mhz = pll_op_clk_freq_mhz / (op_sys_clk_div * op_pix_clk_div) Clock Generator PLL Output Clock Video Timing System Clock Video Timing Pixel Clock pll_op_clk_freq_mhz vt_sys_clk_freq_mhz vt_pix_clk_freq_mhz Phase Locked Loop VT Sys Clock Divider PLL Input Clock VT Pixel Clock Divider pll_ip_clk_freq_mhz External Input Clock Pre PLL Clock Driver PLL multiplier 6 ~ 27 MHz vt_sys_clk_div vt_pix_clk_div 1,2,4,6,8 4,5,6,7,8,9,10 324 ~ 650 MHz pre_pll_clk_div pll_multiplier 1,2,4,6, ...,12 ...,26 54,56, ...,325 27,28, ...,650 Output Timing System Clock Output Timing Pixel Clock op_sys_clk_freq_mhz op_pix_clk_freq_mhz OP Sys Clock Divider OP Pixel Clock Divider op_sys_clk_div op_pix_clk_div 1,2,4,6,8 8,10 Figure 10 : Clock tree structure SAMSUNG PROPRIETARY 17/30 S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) 3-2. Scaler The image scaling function within the sensor module provides a flexible way of generating lower resolution full field of view image data, at a reduced data rates, for viewfinder and video applications. The scaler is able to scale the full resolution of the sensor module down to within 10% of a the target image size (the smallest output size is 256x192). This flexibility means that sensor modules can support a wide range of LCD viewfinder sizes and different codec resolutions To provide a wider range of data rate reduction options the full image scaler is able to reduce the data rates in both the horizontal and vertical directions. This is achieved by the use of a FIFO between video timing and output clock domains (Figure 13). Figure 11 : Full Scaler Block Diagram Clock divider setting restrictions are as follows when scaling mode is on: 2 op_sys_clk_div x op_pix_clk_div scale_m 1 , for full scale down vt_sys_clk_div x vt_pix_clk_div scale_n 1 op_sys_clk_div x op_pix_clk_div scale_m , for horizontal scaling only vt_sys_clk_div x vt_pix_clk_div scale_n For the proper scaler operation, the fifo_water_mark_pixels register value should be specified according to the scale_m as described below : fifo_water_mark_pixels = the horizontal width of visible pixels / scale_down factor + 10 where scale-down factor = scale_m / scale_n and decimal 10 is the marginal value for safe operation. For example, when `the horizontal width of visible pixels is 1608 and scale_m is 20', fifo_water_mark_pixels becomes 1296 ( 1608 / ( 20/16) + 10 1296 ). SAMSUNG PROPRIETARY 18/30 S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) 3-3. CCP2 Frame Format The frame format is specified by Frame Descriptors. There are 3 descriptors in S5K4B1FX, one for column, two for row. Each describes the visible column width, embedded data lines, visible row width. Figure 14 shows our default Frame Descriptor value. FS 2 Embedded Data Lines Total Number of Columns = 1616 LE LS LS Visible Column = 1616 LE 1616 Visible Cols 5H Checksum Visible Pixels 1616 x 1216 50H Descriptor 0 Total Number of Rows = 2 + 1216 = 1218 2 Visible Rows = 1216 2 Embedded Rows FE 6H 1H 0H 02H Descriptor 1 1208 Visible Cols 5H 4H C0H Descriptor 2 Figure 12 : Frame Format 3-4. Test Pattern Two types of full frame deterministic test patterns are defined. Most are Bayer test patterns more suitable for some tests than real image data and are injected early in the sensor data path. The only exception to this is a test pattern that is intended to test sensor-host link integrity, the data in this pattern is not Bayer data and it is injected just prior to CCP2 framing. Use of these full frame test patterns is controlled by the test_pattern_mode parameter. The following table shows all the defined parameter settings. Parameter Name test_pattern_mode Type 16-bit unsigned integer R/W RW Coding 0 - no pattern (default) 1 - solid color 2 - 100 % color bars 3 - fade to grey color bars 4 - PN9 (no embedded lines) 5 - 255 reserved 256-65535 - manufacturer specific Function Controls the output of the test pattern mode SAMSUNG PROPRIETARY 19/30 S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) 3-5. PN9 Code Generation The PN9 test pattern is included to ease testing of sensor-link integrity (measurement of bit error rate etc). PN9 9 5 linear feedback shift register has the polynomial X +X +1 in Fibonacci type notation (Figure 15). The reset value of PN9 is 0x1FF. Figure 13 : PN9 Linear Feedback Shift Registers 3-6. CCP2 and SubLVDS The CCP2 specification defines standard data transmission and control interfaces between transmitter and receiver. Data transmission interface (referred as CCP2) is unidirectional differential serial interface with data and clock/strobe signals. CCP2 defines two options for data transfer between transmitter and receiver. The first one is normal data and clock. The second one is based on signaling scheme called data-strobe, which is a method for data transfer not needing a continuous clock signal. The clock is reconstructed at the receiving end from the data and strobe signals. The physical layer of CCP2 is based on signaling scheme called SubLVDS, which is current mode differential low voltage signaling method modified from the IEEE 1596.3 LVDS standard for reduced power consumption. Electrical specifications for the SubLVDS I/O's can be found from chapter 9, SMIA1.0 Part 2: CCP2 specification. The use of data-strobe coding together with SubLVDS enables the use of high data rates with low EMI. CCP2 is classified in 3 classes according to the data rate and signaling method. This sensor complies with CCP2 Class 2 (up to 650Mbps, Data/Strobe mode). Maximum frame rates at raw 10 mode is 1600 X 1200 30 fps @ 650 Mbps data /strobe 800 X 600 60 fps @ 650 Mbps data /strobe 400 X 300 60 fps @ 650 Mbps data /strobe SAMSUNG PROPRIETARY 20/30 S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) t period CLK t Setup t Hold DATA t Setup(MIN) = t period /2 - 0.05* t period t Hold(MIN) = t period /2 - 0.05* t period t period t DSW DATA STROBE 0.98* t period < t DSW < 1.02* t period Figure 14 : CCP Timing Specifications SAMSUNG PROPRIETARY 21/30 S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) POWER UP SEQUENCE The digital and analogue supply voltages can be powered up in any order e.g. VDIG then VANA or VANA then VDIG. On power up : z If XSHUTDOWN is low when the power supplies are brought up then the sensor module will go into hardware standby mode. z If XSHUTDOWN is high when the power supplies are brought up then the sensor module will go into software standby mode In both cases the presence of an on-chip power-on reset cell ensures that the CCI register values are initialized correctly to their default values. The EXTCLK clock can either be initially low and then enabled during software standby mode or EXTCLK can be a free running clock. Table 1 : Power-Up Sequence Timing Constraints Constant VANA rising - VDIG rising Label t0 t1 VDIG rising - VANA rising VANA rising - XSHUTDOWN rising XSHUTDOWN rising - First I2C transaction Minimum No. of EXTCLK cycles prior to the first I2C transaction PLL start up/lock time Entering streaming mode - first frame start sequence (fixed part) Entering streaming mode - first frame start sequence (variable part) SAMSUNG PROPRIETARY 22/30 t2 t3 Min Max VANA and VDIG may rise in any order. The rising separation can vary from 0ns to indefinite 0.0 2400 - t4 2400 t5 t6 - t7 1 10 The delay is the coarse integration time value Units ns ns ns EXTCLK cycles EXTCLK cycles ms ms lines S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) Figure 15 : Power-Up Sequence SAMSUNG PROPRIETARY 23/30 S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) POWER DOWN SEQUENCE The digital and analogue supply voltages can be powered down in any order e.g. VDIG then VANA or VANA then VDIG. Similarly to the power-up sequence the EXTCLK: input clock may be either gated or continuous. If the CCI command to exit streaming is received while a frame of CCP2 data is being output then the sensor module must wait to the CCP2 frame end code before entering software standby mode. If the CCI command to exit streaming mode is received during the inter frame time then the sensor module must enter software standby mode immediately. Table 2 : Power-Down Sequence Timing Constraints Constant Label t0 Enter Software Standby CCI command - Device in Software Standby mode Minimum no of EXTCLK cycles after the last I2C transaction or CCP2 frame end Last I2C Transaction or CCP2 frame end - XSHUTDOWN falling XSHUTDOWN falling - VANA falling VANA falling - VDIG falling VDIG falling - VANA falling SAMSUNG PROPRIETARY 24/30 t1 t2 t3 t4 t5 Min Max If outputting a frame of CCP2 data waits to CCP2 frame end code before entering software standby, otherwise enter software standby mode immediately. 512 512 - 0.0 VANA and VDIG may fall in any order. The falling separation can vary from 0ns to Indefinite. Units EXTCLK cycles EXTCLK cycles ns ns ns S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) Figure 16 : Power-Down Sequence SAMSUNG PROPRIETARY 25/30 S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) INTERNAL POWER-ON RESET The sensor module should internally perform a power-on reset (POR) when the digital supply rises above a trigger level, V . trig_rising Similarly is the digital power supply falls below the trigger level, V trig_falling , then the power-on reset should activate. The host must be able to reset the sensor by turning the power supplies on and off. Table 3 : Internal Power-on Reset Cell Specifications Constraint VDIG rising crossing V - Internal reset Label t1 Min 7 Typ 10 Max 15 Units us being released VDIG falling crossing V - Internal reset t2 - 0.5 1 us which t3 0.4 0.5 - us is considered to be a reset when POR cell output high Minimum VDIG spike width below V which t4 0.5 1.0 - us is considered to be a reset when POR cell output low Minimum VDIG spike width above V which t5 - 50 - ns trig_rising trig_falling active Minimum VDIG spike width below V trig_falling trig_falling trig_rising is considered to be a supply is stable when POR cell output low. While the POR cell output is low all VDIG spikes above V that are less than t5 must be trig_rising ignored. VDIG rising trigger voltage V 1.15 1.4 1.55 V VDIG falling trigger voltage V 1.00 1.25 1.45 V SAMSUNG PROPRIETARY 26/30 trig_rising trig_falling S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) Figure 17 : Power-on Reset Power-up and Supply Glitch/Brown-out Timing SAMSUNG PROPRIETARY 27/30 S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) STAND-BY SEQUENCE Figure 18 : Stand-By Sequence SAMSUNG PROPRIETARY 28/30 S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) ELECTRICAL CHARACTERISTICS Table 4 : Absolute Maximum Rating Symbol VDIG(MAX) VANA(MAX) VIP(DIG) VCAP TSTR Description Digital Absolute Max (1) Analogue Absolute Max (2) Digital Input Voltages (3) VCAP Analogue Voltage Storage Temperature Min -0.3 -0.3 -0.3 -0.3 -40 Typical - Max 2.2 4 VANA+0.3 4.2 85 Units V V V V C Max 1.9 2.9 VANA 4.2 25 40 55 70 Units V V V V C C C C [Notes:] (1) Digital Supply 1.9V + 0.3V (2) Analogue Supply 2.9V + 1.1V (3) Digital Inputs: EXTCLK, XSHUTDOWN, SCL, SDA Table 5 : Operating Conditions Symbol VDIG VANA VIP(DIG) VCAP TTEST TOPT TOPR TFUNC Description Digital Absolute Max (1) Analogue Absolute Max (2) Digital Input Voltages (3) VCAP Analogue Voltage Test Temperature (4) Optimum Operating Temperature (5) Normal Operating Temperature (6) Functional Operating Temperature (7) Min 1.7 2.4 0 0 21 5 -25 -30 Typical 1.8 2.8 23 - [Notes:] (1) Digital Supply tolerances: 1.8V +/- 100mV (2) Analogue Supply Tolerances: Lower limit 2.5V -100mV, Upper Limit: 2.8V+100mV (3) Digital Inputs: EXTCLK, XSHUTDOWN, SCL, SDA (4) Test Temperature - image quality test conditions (5) Optimum Operating Temperature - no visible degradation in image quality (6) Normal Operating Temperature - camera produces acceptable images (7) Functional Operating Temperature - camera fully functional SAMSUNG PROPRIETARY 29/30 S5K4B1FX - 1/4 INCH UXGA CMOS IMAGE SENSOR PRELIMINARY DATA SHEET (REV. 0.10) IMPORTANT NOTICE The information furnished by Samsung Electronics in this document is believed to be accurate and reliable. However, no responsibility is assumed by Samsung Electronics for its use, nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any patents or patent rights of Samsung Electronics. Samsung Electronics reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current and complete. For More Information http://samsungelectronics.com/semiconductors/ Copyright (c) 2006 Samsung Electronics, Inc. All Rights Reserved SAMSUNG PROPRIETARY 30/30