APL78L05DC-TRG - Anpec Electronics Corp.

APL78L05/12

www.anpec.com.tw1

Three-Terminal Low Current Positive Voltage Regulator

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and

advise customers to obtain the latest version of relevant information to verify before placing orders.

Rev. A.11 - Jun., 2011

FeaturesGeneral Description

Pin Configuration

TO-92A (Top View)

These series of fixed-voltage monolithic integrated-cir-

cuit voltage regulators are designed for a wide range of

applications. These applications include on-card regula-

tion for elimination of noise and distribution problems

associated with single-point regulation. In addition, they

can be used with power-pass elements to make high-

current voltage regulators. Each of these regulators can

deliver up to 100mA of output current. The internal limit-

ing and thermal shutdown features of these regulators

make them essentially immune to overload. When used

as a replacement for a Zener diode-resistor combination,

an effective improvement in output impedance can be

obtained together with lower-bias current.

SOP-8 (Top View)

Applications

SOT-89 (Front View)

•Three-Terminal Regulators

•Maximum Input Voltage : 30V

•Output Voltages of 5V, 12V

•Output Current Up to 100mA

•No External Components

•Internal Thermal Overload Protection

•Internal Short-Circuit Limiting

•Output Voltage Offered in 4% Tolerance

•SOP-8, SOT-89, and TO-92/TO-92A Packages

•Lead Free and Green Devices Available

(RoHS Compliant)

•Battery-Powered Circuitry

•Post Regulator for Switching Power Supply1

VOUT

GND

VIN

GND

21 3

VOUT

TO-92 (Top View)

VIN

GND

VOUT

VIN

GND

VOUT

APL78L05/12

www.anpec.com.tw2Copyright  ANPEC Electronics Corp.

Rev. A.11 - Jun., 2011

Symbol

Parameter Rating Unit

VIN Input Voltage 30 VDC

TJ Operating Junction Temperature Range Control Section

Power Transistor

0 to 125

0 to 150 °C

TSTG Storage Temperature Range -65 to +150 °C

Absolute Maximum Ratings (Note 1)

Ordering and Marking Information

Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which

are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for

MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen

free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by

weight).

Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

Thermal Characteristics

Symbol

Parameter Typical Value Unit

θJA Thermal Resistance from Junction to Ambient in Free Air (Note 2) SOP-8

SOT-89/TO-92/TO-92A

160

180 °C/W

θJC Thermal Resistance from Junction to Case SOP-8

SOT-89/TO-92/TO-92A

80 °C/W

Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.

Package Code

E : TO-92/TO-92A K : SOP-8 D : SOT-

Operating Ambient Temperature Range

C : 0 to 70 oC

Handling Code

TR : Tape & Reel

TB : Tape & Box (only for TO-92A Bent Legs)

PB : Plastic & Box

Assembly Material

G : Halogen and Lead Free Device

APL78L05/12

Handling Code

Temperature Range

Package Code

APL78L05/12 D :APL78L05/12

XXXXX XXXXX - Date Code

APL

78L05/12

XXXXX XXXXX - Date Code

APL78L05/12 E :

Assembly Material

APL78L05/12 K : APL78L05/12

XXXXX XXXXX - Date Code

APL78L05/12

www.anpec.com.tw3Copyright  ANPEC Electronics Corp.

Rev. A.11 - Jun., 2011

Electrical Characteristics

VIN = 10V, IOUT = 40mA, TA = 25°C, CIN = 0.33µF, COUT = 0.1µF, unless otherwise specified.

APL78L05

Symbol

Parameter Test Conditions Min. Typ. Max.

Unit

Output Voltage 4.8 5.0 5.2

1.0mA≤IOUT≤40mA

7.0Vdc≤VIN≤20Vdc

VO Output Voltage (0° to +125°C)

VIN = 10V, 1.0mA≤IOUT≤40mA

4.75 5 5.25 Vdc

7.0Vdc≤VIN≤20Vdc - 29 150

Regline Line Regulation 8.0Vdc≤VIN≤20Vdc - 26 100 mV

1.0mA≤IOUT≤100mA - 9 60

Regload Load Regulation 1.0mA≤IOUT≤40mA - 5 30 mV

IB Quiescent Current - 2.8 6.0 mA

APL78L12

Symbol

Parameter Test Conditions Min. Typ. Max.

Unit

8.0Vdc≤VIN≤20Vdc - 0.15 1.5

∆ IB Quiescent Current Change 1.0mA≤IOUT≤40mA - 0.08 0.1 mA

VIN-VO Dropout Voltage IOUT = 100mA - 1.9 -

VO Output Voltage 11.5 12 12.5

1.0mA≤IOUT≤40mA

14Vdc≤VIN≤27Vdc

VO Output Voltage (0° to +125°C)

VIN = 19V, 1.0mA≤IOUT≤40mA

11.4 12 12.6

Vdc

Regline Line Regulation 14.5Vdc≤VIN≤27Vdc - - 250

1.0mA≤IOUT≤100mA - - 100

Regload Load Regulation 1.0mA≤IOUT≤40mA - - 50

IB Quiescent Current - - 6.5

16Vdc≤VIN≤27Vdc - - 1.5

∆ IB Quiescent Current Change 1.0mA ≤IOUT≤40mA - - -

VIN-VO Dropout Voltage IOUT = 100mA - 1.9 - Vdc

APL78L05/12

www.anpec.com.tw4Copyright  ANPEC Electronics Corp.

Rev. A.11 - Jun., 2011

2.2

2.4

2.6

2.8

3.0

025 50 75 100 125

0 2 4 6 8 10

0.5

1.5

2.5

3.5

0 5 10 15 20 25 30 35

1.25

1.5

1.75

2.25

025 50 75 100 125

Typical Operating Characteristics

Dropout Voltage vs. Junction Temperature

Dropout of Regulation is

defined as when

∆Vo=1% of Vo

IO=1mA

Quiescent Current vs. Ambient Temperature

Ambient Temperature (°C)

Quiescent Current (mA)

Quiescent Current vs. Input Voltage

Input Voltage (V)

Output Voltage vs. Input Voltage

Output Voltage (V)

Input Voltage (V)

IO=40mA

IO=100mA

Dropout Voltage (V)

Junction Temperature (°C)

IO=1mA

IO=40mA

IO=70mA

VIN=10V

IO=40mANo Load

APL78L05/12

www.anpec.com.tw5Copyright  ANPEC Electronics Corp.

Rev. A.11 - Jun., 2011

1.6

1.65

1.7

1.75

1.8

1.85

1.9

020 40 60 80 100

-80

-70

-60

-50

-40

-30

-20

-10

100k

100 1k 10k

0.5

1.5

2.5

020 40 60 80 100

Typical Operating Characteristics (Cont.)

Dropout Voltage vs. Output Current

Load-Transient Response

Time (20µs/div)

Quiescent Current vs. Output Current

Quiescent Current (mA)

Output Current (mA)

Dropout Voltage (V)

Output Current (mA)

IOUT=

10mA~80mA

VOUT(100mv/div)

COUT=0.1µF

PSRR vs. Frequency

PSRR (dB)

Frequency (Hz)

VIN=10V

IOUT=10mA

VIN=10V

Dropout of

Regulation is

defined as when

∆Vo=1% of Vo

VOUT(100mv/div)

COUT=0.1µF

IOUT=10mA~80mA

APL78L05/12

www.anpec.com.tw6Copyright  ANPEC Electronics Corp.

Rev. A.11 - Jun., 2011

0.01

0.1

020 40 60 80 100

4.995

5.005

5.01

5.015

5.02

025 50 75 100 125

100

300

500

700

900

1100

1300

25 50 75 100 125 150

Maximum Power Dissipation vs.

Ambient Temperature

TO-92 Type Package

No Heat Sink

Line Transient Response

VIN=9.5V~10.5V

COUT=0.1µF

IOUT=10mA

Time (100µs/div)

VOUT=10(mV/div)

Maximum Power Dissipation (mW)

Ambient Temperature (°C)

Output Voltage (V)

VIN=10V

IO=40mA

Output Voltage vs.

Ambient TemperatureRegion of Stable ESR vs. Output

Current

Output Current (mA)

COUTESR (Ω)

COUT=0.1µF

Stable Region

Untested

Typical Operating Characteristics (Cont.)

APL78L05/12

www.anpec.com.tw7Copyright  ANPEC Electronics Corp.

Rev. A.11 - Jun., 2011

Pin Description

NO.

SOP-8

TO-92

SOT-89

NAME

FUNCTION

1 1 1 V

OUT Output Voltage Output Pin.

2,3,6,7

2 2 GND

Ground. A common ground is required between the input and the output voltage.

4,5 - - NC No Internal Connection

8 3 3 VIN Power input pin of the device. The maximum Input Voltage can be 30V. It should be

bypassed with a 0.33µF (minimum) capacitor to the GND.

Typical Application Circuit

Note

a : A common ground is required between the input and the output voltage. The input voltage must remain typically 2V above the

output voltage even during the low point on the input ripple voltage.

b : CIN is required if regulator is located an appreciable distance from power supply filter.

c : COUT is not needed for stability; however, it improves transient response.

VOUT

APL78L05/12

COUT=

0.1µF

VIN

CIN=

0.33µF

APL78L05/12

www.anpec.com.tw8Copyright  ANPEC Electronics Corp.

Rev. A.11 - Jun., 2011

Application Information

Input

Constant

Current to

Grounded

Load

APL78L05

0.33µF

The APL78L05/12, series of fixed voltage regulators, are

designed with thermal overload protection that shuts down

the circuit when subjected to an excessive power overload

condition. In addition, the APL78L05/12 have the func-

tion of internal short circuit protection to limit the maxi-

mum current the circuit will pass.

In many low current applications, compensation capaci-

tors are not required. However, it is recommended that

the regulator input will be bypassed with a capacitor if the

regulator connects to the power supply filter with long

wire lengths, or if the output load capacitance is large. The

input bypass capacitor should be selected to provide

good high-frequency characteristics to insure stable

operation under all load conditions. If the value of the

capacitor is greater than 0.33µF, the capacitor with tan-

talum or mylar, or other capacitor having low internal im-

pedance at high frequencies should be chosen. The by-

pass capacitor should be mounted with the shortest pos-

sible leads directly across the regulators input terminals.

Good construction techniques should be used to mini-

mize ground loops and lead resistance drops since the

regulator has no external sense lead. Bypassing the out-

put is also recommended.

Figure 1. Current Regulator

MC1741

0.33µF

+20V

0.33µF

20V MPSU55

6.5 MPSA70

10K

+VO

-VO

APL78L05

The APL78L05 regulators can also be used as a cur-

rent source when connected as above. In order to mini-

mize dissipation, the APL78L05 is chosen in this

application. Resistor R determines the current as be-

low :

IO = + IB

5.0V

IB =3.8mA over line and load changes

For example, a 100mA current source would require R to

be a 50Ω, 1/2W resistor and the output voltage compli-

ance would be the input voltage less 7V.

Figure 2. ±15V Tracking Voltage Regulator

Figure 3. Positive and Negative Regulator

+VI

0.1µF

APL78LXX

0.33µF

APL79LXX

0.33µF0.1µF

+VO

-VO

-VI

APL78L05/12

www.anpec.com.tw9Copyright  ANPEC Electronics Corp.

Rev. A.11 - Jun., 2011

Package Information

SOP-8

SEE VIEW A

h X 45

A1A2

VIEW A

0.25

SEATING PLANE

GAUGE PLANE

Note: 1. Follow JEDEC MS-012 AA.

2. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.

3. Dimension “E” does not include inter-lead flash or protrusions.

Inter-lead flash and protrusions shall not exceed 10 mil per side.

LMIN. MAX.

1.75

0.10

0.17 0.25

0.25

MILLIMETERS

b0.31 0.51

SOP-8

0.25 0.50

0.40 1.27

MIN. MAX.

INCHES

0.069

0.004

0.012 0.020

0.007 0.010

0.010 0.020

0.016 0.050

0.010

1.27 BSC 0.050 BSC

A2 1.25 0.049

3.80

5.80

4.80

4.00

6.20

5.00 0.189 0.197

0.228 0.244

0.150 0.157

APL78L05/12

www.anpec.com.tw10Copyright  ANPEC Electronics Corp.

Rev. A.11 - Jun., 2011

Package Information

SOT-89

OMIN. MAX.

MILLIMETERS

SOT-89

MIN. MAX.

INCHES

1.60

0.44

0.35 0.44

4.40 4.60

1.62 1.83

0.56

2.13

B1 0.36 0.48

3.00 BSC

3.94 4.25

2.29 2.60

2.29

0.118 BSC

0.063

0.017

0.014 0.019

0.014 0.017

0.173 0.181

0.064 0.072

0.084

0.155 0.167

0.090 0.102

0.090

0.022

L0.89 0.035

1.50 BSC 0.059 BSC

1.40

1.20 0.047

0.055

Note : Follow JEDEC TO-243 AA.

APL78L05/12

www.anpec.com.tw11Copyright  ANPEC Electronics Corp.

Rev. A.11 - Jun., 2011

Package Information

TO-92

LMIN. MAX.

5.33

3.18 4.19

2.42 2.66

0.53

3.43

MILLIMETERS

D4.45 5.20

TO-92

12.70

2.03 2.66

MIN. MAX.

INCHES

0.210

0.175 0.205

0.125 0.165

0.095 0.105

0.135

0.500

0.080 0.105

4.32 0.170

0.021

0.055

1.15 1.39 0.045

0.41 0.016

Note : Follow JEDEC TO-92.

4.00 0.157

0.591

15.00

APL78L05/12

www.anpec.com.tw12Copyright  ANPEC Electronics Corp.

Rev. A.11 - Jun., 2011

Package Information

TO-92A

LMIN.MAX.

5.33

3.18 4.19

2.50 2.80

0.53

1.15

MILLIMETERS

D4.45 5.20

TO-92A

3.34

12.70

MIN.MAX.

INCHES

0.210

0.175 0.205

0.125 0.165

0.098 0.110

0.045

0.135

0.500

4.32 0.170

0.021

0.105

2.42 2.66 0.095

0.41 0.016

Note : Follow JEDEC TO-92A

1.39 0.055

0.157

4.00

1.70

2.03 2.66

0.067

0.080 0.105

0.130

3.30

APL78L05/12

www.anpec.com.tw13Copyright  ANPEC Electronics Corp.

Rev. A.11 - Jun., 2011

OD0

BA0

SECTION B-B

SECTION A-A

OD1

Carrier Tape & Reel Dimensions

Application

A H T1 C d D W E1 F

330.0±2.00

50 MIN.

12.4+2.00

-0.00

13.0+0.50

-0.20

1.5 MIN.

20.2 MIN.

12.0±0.30

1.75±0.10

5.5±0.05

P0 P1 P2 D0 D1 T A0 B0 K0

SOP-8

4.0±0.10

8.0±0.10

2.0±0.05

1.5+0.10

-0.00

1.5 MIN.

0.6+0.00

-0.40

6.40±0.20

5.20±0.20

2.10±0.20

Application

A H T1 C d D W E1 F

178.0±2.00

50 MIN.

12.4+2.00

-0.00

13.0+0.50

-0.20

1.5 MIN.

20.2 MIN.

12.0±0.30

1.75±0.10

5.50±0.05

P0 P1 P2 D0 D1 T A0 B0 K0

SOT-89

4.0±0.10

8.0±0.10

2.0±0.05

1.5+0.10

-0.00

1.5 MIN.

0.6+0.00

-0.40

4.80±0.20

4.50±0.20

1.80±0.20

(mm)

APL78L05/12

www.anpec.com.tw14Copyright  ANPEC Electronics Corp.

Rev. A.11 - Jun., 2011

Carrier Tape & Box Dimensions

Devices Per Unit

Package Type Unit Quantity

SOP-8 Tape & Reel 2500

SOT-89 Tape & Reel 1000

TO-92A Tape & Box 2000

TO-92 Plastic & Box 1000

Application

A0 D D1 D2 F1=F2 F1-F2 M H H1

4.32~5.33

4.0±0.2 0.36~0.53

4.45~5.20

2.5+0.2

-0.1 ±0.3 1.7~3.3 16±0.5 9±0.5

H2 H2A H3 H4 H5=H0+M

L L1 P P1

0.5 MAX

27.0 MAX

20.0 MAX

18.5±0.5

11.0 MAX

2.5 MIN

12.7±0.3

6.35±0.4

P2 T T1 T2 W W1 W2 W W1

TO-92A

50.8±0.5

0.55 MAX

1.42 MAX

0.36~0.68

18.0±0.2

6.0±0.2 ≦1 18.0±0.2

6.0±0.2

(mm)

APL78L05/12

www.anpec.com.tw15Copyright  ANPEC Electronics Corp.

Rev. A.11 - Jun., 2011

Taping Direction Information

SOT-89

USER DIRECTION OF FEED

SOP-8

USER DIRECTION OF FEED

APL78L05/12

www.anpec.com.tw16Copyright  ANPEC Electronics Corp.

Rev. A.11 - Jun., 2011

Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly

Preheat & Soak

Temperature min (Tsmin)

Temperature max (Tsmax)

Time (Tsmin to Tsmax) (ts)

100 °C

150 °C

60-120 seconds

150 °C

200 °C

60-120 seconds

Average ramp-up rate

(Tsmax to TP) 3 °C/second max. 3°C/second max.

Liquidous temperature (TL)

Time at liquidous (tL) 183 °C

60-150 seconds 217 °C

60-150 seconds

Peak package body Temperature

(Tp)* See Classification Temp in table 1 See Classification Temp in table 2

Time (tP)** within 5°C of the specified

classification temperature (Tc) 20** seconds 30** seconds

Average ramp-down rate (Tp to Tsmax)

6 °C/second max. 6 °C/second max.

Time 25°C to peak temperature 6 minutes max. 8 minutes max.

* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.

** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.

Classification Profile

Classification Reflow Profiles

APL78L05/12

www.anpec.com.tw17Copyright  ANPEC Electronics Corp.

Rev. A.11 - Jun., 2011

Customer Service

Anpec Electronics Corp.

Head Office :

No.6, Dusing 1st Road, SBIP,

Hsin-Chu, Taiwan, R.O.C.

Tel : 886-3-5642000

Fax : 886-3-5642050

Taipei Branch :

2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,

Sindian City, Taipei County 23146, Taiwan

Tel : 886-2-2910-3838

Fax : 886-2-2917-3838

Classification Reflow Profiles (Cont.)

Table 2. Pb-free Process – Classification Temperatures (Tc)

Package

Thickness Volume mm3

<350 Volume mm3

350-2000 Volume mm3

>2000

<1.6 mm 260 °C 260 °C 260 °C

1.6 mm – 2.5 mm 260 °C 250 °C 245 °C

≥2.5 mm 250 °C 245 °C 245 °C

Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)

Package

Thickness Volume mm3

<350 Volume mm3

≥350

<2.5 mm 235 °C 220 °C

≥2.5 mm 220 °C 220 °C

Reliability Test Program

Test item Method Description

SOLDERABILITY JESD-22, B102 5 Sec, 245°C

HOLT JESD-22, A108 1000 Hrs, Bias @ Tj=125°C

PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C

TCT JESD-22, A104 500 Cycles, -65°C~150°C

HBM MIL-STD-883-3015.7 VHBM≧2KV

MM JESD-22, A1 15 VMM≧200V

Latch-Up JESD 78 10ms, 1tr≧100mA