L6910 L6910A ADJUSTABLE STEP DOWN CONTROLLER WITH SYNCHRONOUS RECTIFICATION 1 2 3 Figure 1. Packages FEATURES OPERATING SUPPLY VOLTAGE FROM 5V TO 12V BUSES UP TO 1.3A GATE CURRENT CAPABILITY ADJUSTABLE OUTPUT VOLTAGE N-INVERTING E/A INPUT AVAILABLE 0.9V 1.5% VOLTAGE REFERENCE VOLTAGE MODE PWM CONTROL VERY FAST LOAD TRANSIENT RESPONSE 0% TO 100% DUTY CYCLE POWER GOOD OUTPUT OVERVOLTAGE PROTECTION HICCUP OVERCURRENT PROTECTION 200kHz INTERNAL OSCILLATOR OSCILLATOR EXTERNALLY ADJUSTABLE FROM 50kHz TO 1MHz SOFT START AND INHIBIT PACKAGES: SO-16 & HTSSOP16 APPLICATIONS SUPPLY FOR MEMORIES AND TERMINATIONS COMPUTER ADD-ON CARDS LOW VOLTAGE DISTRIBUTED DC-DC MAG-AMP REPLACEMENT DESCRIPTION The device is a pwm controller for high performance SO-16 (Narrow) HTSSOP16 (Exposed Pad) Table 1. Order Codes Part Number Package L6910 SO-16 L6910TR SO-16 in Tape & Reel L6910A HTSSOP16 L6910ATR HTSSOP16 in Tape & Reel dc-dc conversion from 3.3V, 5V and 12V buses. The output voltage is adjustable down to 0.9V; higher voltages can be obtained with an external voltage divider. High peak current gate drivers provide for fast switching to the external power section, and the output current can be in excess of 20A. The device assures protections against load overcurrent and overvoltage. An internal crowbar is also provided turning on the low side mosfet as long as the over-voltage is detected. In case of over-current detection, the soft start capacitor is discharged and the system works in HICCUP mode. Figure 2. Block Diagram Vin 5V to 12V VCC PGOOD OCSET MONITOR PROTECTION & REF VREF BOOT SS UGATE OSC OSC RT E/A + 300K EAREF - BOOT PWM - VO LGATE + PGND GND VFB COMP D03IN1509 May 2005 Rev. 9 1/29 L6910 - L6910A Table 2. Absolute Maximum Ratings Symbol Vcc VBOOTVPHASE Parameter Value Unit Vcc to GND, PGND 15 V Boot Voltage 15 V 15 V VHGATEVPHASE OCSET, LGATE, PHASE -0.3 to Vcc+0.3 V 7 V SS, FB, PGOOD, VREF, EAREF, RT 6.5 V Junction Temperature Range COMP -40 to 150 C Tstg Storage temperature range -40 to 150 C Ptot Maximum power dissipation at Tamb = 25C 1 W Tj Table 3. Thermal Data Symbol Rth j-amb Parameter Thermal Resistance Junction to Ambient SO-16 HTSSOP16 HTSSOP16 (*) Unit 120 110 50 C/W (*) Device soldered on 1 S2P PC board Figure 3. Pins Connection (Top view) VREF 1 16 N.C. VREF 1 16 VCC OSC 2 15 VCC OSC 2 15 LGATE OCSET 3 14 LGATE OCSET 3 14 PGND SS/INH 4 13 PGND SS/INH 4 13 BOOT COMP 5 12 BOOT N.C. 5 12 HGATE FB 6 11 HGATE COMP 6 11 PHASE GND 7 10 PHASE FB 7 10 PGOOD EAREF 8 9 PGOOD GND 8 9 EAREF D03IN1510 2/29 D03IN1511 L6910 - L6910A Table 4. Pins Function SO HTSSOP Name Description 1 1 VREF Internal 0.9V 1.5% reference is available for external regulators or for the internal error amplifier (connecting this pin to EAREF) if external reference is not available. A minimum 1nF capacitor is required. If the pin is forced to a voltage lower than 70%, the device enters the hiccup mode. 2 2 OSC Oscillator switching frequency pin. Connecting an external resistor (RT) from this pin to GND, the external frequency is increased according to the equation: 6 4.94 10 f OSC,RT = 200KHz + ------------------------R T ( K ) Connecting a resistor (RT) from this pin to Vcc (12V), the switching frequency is reduced according to the equation: 7 4.306 10 f OSC,RT = 200KHz - ----------------------------R T ( K ) If the pin is not connected, the switching frequency is 200KHz. The voltage at this pin is fixed at 1.23V. Forcing a 50A current into this pin, the built in oscillator stops to switch. In Over Voltage condition this pin goes over 3V until that conditon is removed. 3 3 OCSET A resistor connected from this pin and the upper Mos Drain sets the current limit protection. The internal 200A current generator sinks a constant current through the external resistor. The Over-Current threshold is due to the following equation: I OCSET R OCSET I P = --------------------------------------------R DSon 4 4 SS/INH The soft start time is programmed connecting an external capacitor from this pin and GND. The internal current generator forces through the capacitor 10A. This pin can be used to disable the device forcing a voltage lower than 0.4V 5 6 COMP This pin is connected to the error amplifier output and is used to compensate the voltage control feedback loop. 6 7 FB This pin is connected to the error amplifier inverting input and is used to compensate the voltage control feedback loop. Connected to the output resistor divider, if used, or directly to Vout, it manages also overvoltage conditions and the PGOOD signal 7 8 GND 8 9 EAREF 9 10 PGOOD This pin is an open collector output and it is pulled low if the output voltage is not within the above specified thresholds. If not used it may be left floating. 10 11 PHASE This pin is connected to the source of the upper mosfet and provides the return path for the high side driver. This pin monitors the drop across the upper mosfet for the current limit together with OCSET. 11 12 HGATE High side gate driver output. 12 13 BOOT Bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper mosfet. Connect through a capacitor to the PHASE pin and through a diode to Vcc (cathode vs. boot). 13 14 PGND Power ground pin. This pin has to be connected closely to the low side mosfet source in order to reduce the noise injection into the device 14 5 LGATE This pin is the lower mosfet gate driver output 15 16 VCC Device supply voltage. The operative supply voltage ranges is from 5V to 12V. DO NOT CONNECT VIN TO A VOLTAGE GREATER THAN VCC. 16 5 N.C. This pin is not internally bonded. It may be left floating or connected to GND. All the internal references are referred to this pin. Connect it to the PCB signal ground. Error amplifier non-inverting input. Connect to this pin an external reference (from 0.9V to 3V) for the PWM regulation or short it to VREF pin to use the internal reference. If this pin goes under 650mV (typ), the device shuts down. 3/29 L6910 - L6910A Table 5. Electrical Characteristics (Vcc = 12V, TJ =25C unless otherwise specified) Symbol Parameter Vcc SUPPLY CURRENT Icc Vcc Supply current POWER-ON Turn-On Vcc threshold Turn-Off Vcc threshold Test Condition OSC = open; SS to GND VOCSET = 4V VOCSET = 4V Min Typ Max Unit 4 7 9 mA 4.0 3.8 4.3 4.1 4.6 4.4 V V Rising VOCSET threshold Turn On EAREF threshold SOFT START AND INHIBIT Iss Soft start Current S.S. current in INH condition OSCILLATOR fOSC Initial Accuracy fOSC,RT Total Accuracy Vosc Ramp amplitude REFERENCE VOUT Output Voltage Accuracy 1.24 1.4 V 650 750 mV 6 10 35 14 60 A A OSC = OPEN OSC = OPEN; Tj = 0 to 125 180 170 200 220 230 KHz kHz 16 K < RT to GND < 200 K -15 15 % VOCSET = 4V SS = 2V SS = 0 to 0.4V 1.9 VOUT = VFB; VEAREF = VREF 0.886 0.900 0.913 0.886 0.900 0.913 V +2 % VREF Reference Voltage CREF = 1nF; IREF = 0 to 100A VREF Reference Voltage CREF = 1nF; TJ = 0 to 125C ERROR AMPLIFIER IEAREF N.I. bias current IFB VCM VCOMP GV EAREF Input Resistance I.I. bias current VEAREF = 3V A 10 Vs. GND VFB = 0V to 3V 300 0.01 0.5 k A 0.8 3 V Output Voltage 0.5 4 V Open Loop Voltage Gain 70 ILGATE High Side Sink Resistance Low Side Source Current RLGATE Low Side Sink Resistance Output Driver Dead Time PROTECTIONS IOCSET OCSET Current Source IOSC -2 V Common Mode Voltage GBWP Gain-Bandwidth Product SR Slew-Rate GATE DRIVERS IHGATE High Side Source Current RHGATE V COMP = 10pF VBOOT - VPHASE = 12V VHGATE - VPHASE = 6V 1 VBOOT - VPHASE = 12V Vcc = 12V; VLGATE = 6V 0.9 Vcc = 12V VOCSET = 4V 170 OSC Sourcing Current 1.3 A 4 1.1 A 3 210 ns 200 230 A 117 120 % 1.5 90 VFB Rising dB MHz V/s 2 PHASE connected to GND Over Voltage Trip (VFB / VEAREF) 85 10 10 VFB > OVP Trip 15 30 POWER GOOD Upper Threshold (VFB / VEAREF) VFB Rising 108 110 112 % Lower Threshold (VFB / VEAREF) VFB Falling 88 90 92 % Hysteresis (VFB / VEAREF) Upper and Lower threshold VPGOOD PGOOD Voltage Low IPGOOD Output Leakage Current 4/29 mA 2 % IPGOOD = -4mA 0.4 V VPGOOD = 6V 0.2 1 A L6910 - L6910A 4 DEVICE DESCRIPTION The device is an integrated circuit realized in BCD technology. The controller provides complete control logic and protection for a high performance step-down DC-DC converter. It is designed to drive N Channel Mosfets in a synchronous-rectified buck topology. The output voltage of the converter can be precisely regulated down to 900mV with a maximum tolerance of 1.5% when the internal reference is used (simply connecting together EAREF and VREF pins). The device allows also using an external reference (0.9V to 3V) for the regulation. The device provides voltage-mode control with fast transient response. It includes a 200kHz free-running oscillator that is adjustable from 50kHz to 1MHz. The error amplifier features a 10MHz gain-bandwidth product and 10V/s slew rate that permits to realize high converter bandwidth for fast transient performance. The PWM duty cycle can range from 0% to 100%. The device protects against over-current conditions entering in HICCUP mode. The device monitors the current by using the rDS(ON) of the upper MOSFET(s) that eliminates the need for a current sensing resistor. The device is available in SO16 narrow package. 4.1 Oscillator The switching frequency is internally fixed to 200kHz. The internal oscillator generates the triangular waveform for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the oscillator is typically 50A (Fsw = 200KHz) and may be varied using an external resistor (RT) connected between OSC pin and GND or VCC. Since the OSC pin is maintained at fixed voltage (typ. 1.235V), the frequency is varied proportionally to the current sunk (forced) from (into) the pin. In particular connecting RT vs. GND the frequency is increased (current is sunk from the pin), according to the following relationship: 6 4.94 10 f OSC,RT = 200KHz + ------------------------R T ( K ) Connecting RT to VCC = 12V or to VCC = 5V the frequency is reduced (current is forced into the pin), according to the following relationships: 7 4.306 10 f OSC,RT = 200KHz - ----------------------------R T ( K ) VCC = 12V 6 15 10 f OSC,RT = 200KHz - --------------------R T ( K ) VCC = 5V Switching frequency variation vs. RT are repeated in Fig. 4. Note that forcing a 50A current into this pin, the device stops switching because no current is delivered to the oscillator. Figure 4. 10000 Resistance [kOhm] 1000 100 10 RT to GND RT to VCC=12V RT to VCC=5V 10 100 1000 Frequency [kHz] 5/29 L6910 - L6910A 4.2 Reference A precise 1.5% 0.9V reference is available. This reference must be filtered with 1nF ceramic capacitor to avoid instability in the internal linear regulator. It is able to deliver up to 100A and may be used as reference for the device regulation and also for other devices. If forced under 70% of its nominal value, the device enters in Hiccup mode until this condition is removed. Through the EAREF pin the reference for the regulation is taken. This pin directly connects the non-inverting input of the error amplifier. An external reference (or the internal 0.9V 1.5%) may be used. The input for this pin can range from 0.9V to 3V. It has an internal pull-down (300k resistor) that forces the device shutdown if no reference is connected (pin floating). However the device is shut down if the voltage on the EAREF pin is lower than 650mV (typ). 4.3 Soft Start At start-up a ramp is generated charging the external capacitor CSS with an internal current generator. The initial value for this current is of 35A and speeds-up the charge of the capacitor up to 0.5V. After that it becames 10A until the final charge value of approximatively 4V. When the voltage across the soft start capacitor (VSS) reaches 0.5V the lower power MOS is turned on to discharge the output capacitor. As VSS reaches 1.1V (i.e. the oscillator triangular wave inferior limit) also the upper MOS begins to switch and the output voltage starts to increase. No switching activity is observable if SS is kept lower than 0.5V and both mosfets are off. If VCC and OCSET pins are not above their own turn-on thresholds and VEAREF is not above 650mV, the SoftStart will not take place, and the relative pin is internally shorted to GND. During normal operation, if any undervoltage is detected on one of the two supplies, the SS pin is internally shorted to GND and so the SS capacitor is rapidly discharged. Figure 5. Soft Start (with Reference Present) Vcc Turn-on threshold Vcc Vin Vin Turn-on threshold 1V Vss to GND 0.5V LGATE Vout Timing Diagram Acquisition: CH1 = PHASE; CH2 = Vout; CH3 = PGOOD; CH4 = Vss 4.4 Driver Section The driver capability on the high and low side drivers allows using different types of power MOS (also multiple MOS to reduce the RDSON), maintaining fast switching transition. The low-side mos driver is supplied directly by Vcc while the high-side driver is supplied by the BOOT pin. Adaptative dead time control is implemented to prevent cross-conduction and allow to use several kinds of mosfets. The upper mos turn-on is avoided if the lower gate is over about 200mV while the lower mos turn-on is 6/29 L6910 - L6910A avoided if the PHASE pin is over about 500mV. The lower mos is in any case turned-on after 200ns from the high side turn-off. The peak current is shown for both the upper (fig. 6) and the lower (fig. 7) driver at 5V and 12V. A 3.3nF capacitive load has been used in these measurements. For the lower driver, the source peak current is 1.1A @ VCC = 12V and 500mA @ VCC = 5V, and the sink peak current is 1.3A @ VCC = 12V and 500mA @ VCC = 5V. Similarly, for the upper driver, the source peak current is 1.3A @ Vboot-Vphase = 12V and 600mA @ VbootVphase = 5V, and the sink peak current is 1.3A @ Vboot-Vphase =12V and 550mA @ Vboot-Vphase = 5V. Figure 6. High Side Driver Peak Current. Vboot-Vphase = 12V (right) Vboot-Vphase = 5V (left) CH1 = High Side Gate CH4 = Gate Current Figure 7. Low Side Driver Peak Current. VCC = 12V (right) VCC = 5V (left) CH1 = Low Side Gate CH4 = Gate Current 4.5 Monitoring and Protections The output voltage is monitored by means of pin FB. If it is not within 10% (typ.) of the programmed value, the powergood output is forced low. The device provides overvoltage protection, when the voltage sensed on pin FB reaches a value 17% (typ.) greater than the reference the OSC pin is forced high (3V typ.) and the lower driver is turned on as long as the over-voltage is detected. 7/29 L6910 - L6910A Overcurrent protection is performed by the device comparing the drop across the high side MOS, due to the RDSON, with the voltage across the external resistor (ROCS) connected between the OCSET pin and drain of the upper MOS. Thus the overcurrent threshold (IP) can be calculated with the following relationship: R OCS I OCS I P = -------------------------------R dsON Where the typical value of IOCS is 200A. To calculate the ROCS value it must be considered the maximum RdsON (also the variation with temperature) and the minimum value of IOCS. To avoid undesirable trigger of overcurrent protection this relationship must be satisfied: I I P I OUTMAX + ----- = I PEAK 2 Where I is the inductance ripple current and IOUTMAX is the maximum output current. In case of over current detectionthe soft start capacitor is discharged with constant current (10A typ.) and when the SS pin reaches 0.5V the soft start phase is restarted. During the soft start the over-current protection is always active and if such kind of event occurs, the device turns off both mosfets, and the SS capacitor is discharged again (after reaching the upper threshold of about 4V). The system is now working in HICCUP mode, as shown in figure 8. After removing the cause of the over-current, the device restart working normally without power supplies turn off and on. Figure 8. Hiccup Mode Figure 9. Inductor Ripple Current vs. Vout 9 L=1.5H, Vin=12V Inductor Ripple [A] 8 7 L=2H, Vin=12V 6 L=3H, Vin=12V 5 4 L=1.5H, Vin=5V 3 L=2H, Vin=5V 2 L=3H, Vin=5V 1 0 0 .5 CH1 = SS; CH4 = Inductor current 1.5 2 .5 3 .5 Output V oltage [V ] 4.6 Inductor Design The inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain the ripple current IL between 20% and 30% of the maximum output current. The inductance value can be calculated with this relationship: V IN - V OUT V OUT L = ------------------------------ --------------f sw I L V IN Where fSW is the switching frequency, VIN is the input voltage and VOUT is the output voltage. Figure 9 shows the ripple current vs. the output voltage for different values of the inductor, with VIN = 5V and VIN = 12V. Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter response time to a load transient. If the compensation network is well designed, the device is able to open or close the duty cycle up to 100% or down to 0%. The response time is now the time required by the inductor to change its current from initial to final value. Since the inductor has not finished its charging time, the output current is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance required. 8/29 L6910 - L6910A The response time to a load transient is different for the application or the removal of the load: if during the application of the load the inductor is charged by a voltage equal to the difference between the input and the output voltage, during the removal it is discharged only by the output voltage. The following expressions give approximate response time for I load transient in case of enough fast compensation network response: L I t application = -----------------------------V IN - V OUT L I t removal = --------------V OUT The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst case is the response time after removal of the load with the minimum output voltage programmed and the maximum input voltage available. 4.7 Output Capacitor The output capacitor is a basic component for the fast response of the power supply. In fact, during load transient, for first few microseconds they supply the current to the load. The controller recognizes immediately the load transient and sets the duty cycle at 100%, but the current slope is limited by the inductor value. The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the ESL): V OUT = I OUT ESR A minimum capacitor value is required to sustain the current during the load transient without discharge it. The voltage drop due to the output capacitor discharge is given by the following equation: 2 I OUT L V OUT = --------------------------------------------------------------------------------------------2 C OUT ( V INMIN D MAX - V OUT ) Where DMAX is the maximum duty cycle value that is 100%. The lower is the ESR, the lower is the output drop during load transient and the lower is the output voltage static ripple. 4.8 Input Capacitor The input capacitor has to sustain the ripple current produced during the on time of the upper MOS, so it must have a low ESR to minimize the losses. The rms value of this ripple is: I rms = I OUT D ( 1 - D ) Where D is the duty cycle. The equation reaches its maximum value with D = 0.5. The losses in worst case are: 2 P = ESR I rms 4.9 Compensation Network Design The control loop is a voltage mode (figure 10). The output voltage is regulated to the input Reference voltage level (EAREF). The error amplifier output VCOMP is then compared with the oscillator triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. This wave is filtered by the output filter. The modulator transfer function is the small-signal transfer function of VOUT/VCOMP. This function has a double pole at frequency FLC depending on the L-Cout resonance and a zero at FESR depending on the output capacitor ESR. The DC Gain of the modulator is simply the input voltage VIN divided by the peak-to-peak oscillator voltage VOSC. 9/29 L6910 - L6910A Figure 10. Compensation Network VIN VOSC L VOUT ESR PWM COMPARATOR COUT C18 R5 C19 R3 C20 VCOMP -EAREF R4 D03IN1512 + The compensation network consists in the internal error amplifier and the impedance networks ZIN (R3, R4 and C20) and ZFB (R5, C18 and C19). The compensation network has to provide a closed loop transfer function with the highest 0dB crossing frequency to have fast response (but always lower than fsw/10) and the highest gain in DC conditions to minimize the load regulation. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45. Include worst-case component variations when determining phase margin. To locate poles and zeroes of the compensation networks, the following suggestions may be used: Modulator singularity frequencies: 1 LC = --------------------------L C OUT 1 ESR = -------------------------------ESR C OUT Compensation network singularity frequency: 1 P1 = ----------------------------------------------C18 C19 R5 ----------------------------- C18 + C19 1 Z1 = -----------------------R5 C19 1 P2 = -----------------------R4 C20 1 Z2 = ------------------------------------------( R3 + R4 ) C20 - Put the gain R5/R3 in order to obtain the desired converter bandwidth; - Place Z1 before the output filter resonance LC; - Place Z2 at the output filter resonance LC; - Place P1 at the output capacitor ESR zero ESR; - Place P2 at one half of the switching frequency; - Check the loop gain considering the error amplifier open loop gain. 10/29 L6910 - L6910A Figure 11. Asymptotic Bode Plot of Converter's Gain dB Error Amplifier R5/R3 1 LC 2 P1 P2 ESR Modulator Gain Compensation Network Gain Error Amplifier 5 Closed Loop Gain 15A DEMO BOARD DESCRIPTION The demo board shows the operation of the device in a general purpose application. This evaluation board allows voltage adjustability from 0.9V to 5V through the switches S2-S5 according to the reported table when the internal 0.9V reference is used (G1 closed). Output current in excess of 20A can be reached dependently on the kind of mosfet used: up to three SO8 mosfet may be used for both High side and Low side switches. External reference may be used for the regulation simply leaving open G1 and the switches S2-S5. The device may also be disabled with the switch S1. The VCC input rail supplies the device while the power conversion starts from the VIN input rail. The device is also able to operate with a single supply voltage; in this case the jumper G2 has to be closed and a 5V to 12V input can be directly connected to the VIN input. The four layers demo board's copper thickness is of 70m in order to minimize conduction losses considering the high current that the circuit is able to deliver.The PGOOD signal is used as a logic level and it's been pulled up to VIN because there's no other appropriate voltage available on the demo board. In case of input voltage higher than 7V (PGOOD Pin Maximum Absolute Rating) a 5V reference is required. Figure 12 shows the demo board's schematic circuit Figure 12. 15A Demo Board Schematic L1 F1 VIN GNDIN R7 G2 C1-C3 C14 C13 D1 VCC R6 VCC C17 GNDCC OCSET 12 Q1-3 3 11 C15 GND EAREF REFIN C16 GNDREFIN BOOT 15 10 7 14 8 13 UGATE L2 PHASE LGATE C411 D2 R2 PGND GNDOUT G1 VREF +VREF 9 1 PGOOD PWRGD R8 C12 GNDREF VOUT Q4-6 R9 SS C21 OSC 4 2 R1 C22 5 COMP 6 C19 VFB R5 VOUT R3 0.9 R4 C20 S2 S3 S4 S5 Open Open Open Open 1.2 ON Open Open Open R10 1.5 Open ON Open Open S3 R11 1.8 S4 SR12 2.5 Open Open ON Open S5 SR13 3.3 Open Open Open ON 5.0 Open Open ON C18 S1 S2 D03IN1513 ON ON Open Open ON 11/29 L6910 - L6910A Table 6. Part List Reference Description Manufacturer R1 N.C NEOHM R2 10K 5% 125mW NEOHM SMD 0805 R3 4.7K 5% 125mW NEOHM SMD 0805 R4 1KOhm 5% 125mW NEOHM SMD 0805 R5 2.7K 5% 125mW NEOHM SMD 0805 R6 10Ohm 5% 125mW NEOHM SMD 0805 R7 510Ohm 5% 125mW NEOHM SMD 0805 R8 N.C R9 0 Ohm SMD 0805 R10 14K 5% 125mW NEOHM SMD 0805 R11 6.98K 5% 125mW NEOHM SMD 0805 R12 2.61K 5% 125mW NEOHM SMD 0805 R13 1.74K 5 5% 125mW NEOHM SMD 0805 RADIAL 10X10.5 C1, C3 100F - 20V OSCON 20SA100M C9, C10 330F - 6.3V POSCAP 6TPB330M SMD7343 C12, C13, C15, C21 100nF KEMET SMD0805 C14 1nF KEMET SMD0805 C16 100nF KEMET C17 4.7F - 16V AUX SMA6032 C18 1.5nF KEMET SMD0805 C19 15nF KEMET SMD0805 C20 47nF KEMET SMD0805 C22 N.C L1 Short L2 3H (T50-52B Core, 7T AWG15) MICROMETALS Q2,Q3,Q4,Q6 STS11NF30L ST D1 1N4148 D2 STPS2L25U ST SMB U1 Device L6910 ST SO16Narrow F1 Short SWITCH DIP SWITCH 6 POS. SO8 SOT23 Table 7. Other Inductor Manufacturer Manufacturer WURTH ELEKTRONIK PANASONIC SUMIDA 12/29 Series Inductor Value (H) Saturation Current (A) 744318 1.8 to 2.7 16 to 20 ETQP6F1R8FA 1.8 20 CDEP134-2R7MC-H 2.7 15 L6910 - L6910A Figure 13. PCB and Components Layouts Component Side Internal Signal GND Layer Figure 14. PCB and Components Layouts Internal Power GND Layer Solder Side Figure 15. Efficiency vs Output Current 100 Efficiency (%) 95 Vo=3.3V 90 Vo=2.5V Vo=1.8V 85 Vo=1.5V Vo=1.2V Vin=Vcc=5V Fsw=200KHz 80 Vo=0.9V 75 1 3 5 7 9 11 13 15 17 Output Current (A) 13/29 L6910 - L6910A Figure 16. Efficiency vs Output Current 100 Efficiency (%) 95 Vo=5V Vo=3.3V 90 Vo=1.5V 85 Vo=1.8V 80 Vo=2.5V Vo=1.2V Vo=0.9V 75 70 65 Vin=Vcc=12V Fsw.=200KHZ 60 55 50 1 3 5 7Output Current 9 (A) 11 13 15 17 Output Current (A) 6 COMPONENTS SELECTION 6.1 Inductor Selection To select the right inductor value, the application conditions must be fixed. For example we can consider: Vin=12V Vout =3.3V Iout=15A Considering a ripple of approximately 25% to 30% of Iout, the inductor value will be L=3 H. An iron powder core (TO50-52B) with 7 windings has been chosen. 6.2 Output Capacitors 2 POSCAP capacitors, model 6TPB330M, have been chosen, with a maximum ERS equal to 40m each. Therefore, the resultant ESR is of 20m. Considering a current ripple of 4A, the output voltage ripple is: Vout = 4 * 0.02 = 80mV 6.3 Input Capacitors For IOUT = 15A and D = 0.5 (worst case for input current ripple), the RMS current of the input capacitor is equal to 7.5A. Two OSCON electrolytic capacitors 6SP680M, with a maximum ESR equal to 13m, have been chosen to sustain the ripple. Therefore, the resultant ESR is equal to 13m/2 = 6.5m. The losses, in worst case, are: P = ESR * I2rms = 366mW 6.4 Over-Current Protection The current limit can be set to approximately 20A. Substituting the demo board parameters in the relationship reported in the relative section, (IOSCMIN =170A; IP = 20A; RDSONMAX = 9m / 2=4.5m) it results that ROCS = 510 14/29 L6910 - L6910A 6.5 APPLICATION SUGGESTIONS FOR HIGHER CURRENTS For higher output currents, up to 20A, the following configuration can be used (with reference to the demo board schematic): Q1,Q2,Q3: STS11NF30L Q4,Q5,Q6: STS17NF3LL L: 2.5H Magnetic 77121A7 Core 7T 2x AWG16 In these conditions, the following performance have been achieved: Table 8. VIN (V) VOUT (V) IOUT (A) (%) VIN (V) VOUT (V) IOUT (A) (%) 5 1.2 20 81 12 1.2 20 80 5 1.5 20 83 12 1.5 20 83 5 1.8 20 85 12 1.8 20 85 5 2.5 20 89 12 2.5 20 88 5 3.3 20 91 12 3.3 20 91 12 5 20 93 For currents higher than 20A, bigger mosfets should be selected (e.g. STS25NH3LL) both for the high side and low side (depending on the duty cycle and input voltage). 7 6A DEMO BOARD DESCRIPTION A compact demo board has been realized to manage currents in the range of 5A-6A . The external power mosfets are included in a single SO8 package to save space and increase power density. Two separate rails are provided, for VCC and VIN. They can be connected together by shorting the jumper J1. The PGOOD signal is used as a logic level and it's been pulled up to VIN because there's no other appropriate voltage available on the demo board. In case of input voltage higher than 7V (PGOOD Pin Maximum Absolute Rating) a 5V reference is required. Figure 17. 6A Demo Board Schematic VIN R7 J1 GNDIN C7 D1 R6 VCC VCC 3 11 C5 GNDCC 10 GND 14 U1 L6910 4 OSC 13 2 EAREF 9 8 C8 1 5 R10 UGATE C1- C2 R8 LGATE PGND L1 Q1/Q1 PHASE 7 SS C9 C6 OCSET BOOT 12 15 VOUT R9 R11 Q2/Q1 D2 R2 C10 C3-4 GNDOUT PGOOD PWRGD VREF 6 VFB COMP R3 R5 C19 R4 C20 C18 R1 15/29 L6910 - L6910A Table 9. Part List Reference Description Manufacturer 2K7 Ohm 0805 5% 125mW NEOHM (Vout = 2.5V) 1K8 Ohm 0805 5% 125mW NEOHM (Vout = 3.3V) 1K Ohm 0805 5% 125mW NEOHM (Vout = 5V) Resistor R1 R2 10K 5% 125mW NEOHM SMD 0805 R3 4K7 5% 125mW NEOHM SMD 0805 R4 4K7 5% 125mW NEOHM SMD 0805 R5 2K7 5% 125mW NEOHM SMD 0805 R6 10 Ohm 5% 125mW NEOHM SMD 0805 R7 680 Ohm 5% 125mW NEOHM SMD 0805 R8 R9 2.2 Ohm 5% 125mW NEOHM SMD 0805 R10 N.C R11 N.C Capacitors C1,C2 10F 25V TOKIN C34Y5U1E106ZTE12 SMD7343 C3,C4 100F - 6.3V POSCAP 6TPB100M C5,C6,C9 100nF KEMET SMD0805 C7,C8 1nF KEMET SMD0805 C10 N.C C18 1.5nF KEMET SMD0805 C19 15nF KEMET SMD0805 C20 47nF KEMET SMD0805 Magnetics L1 7H (T50-52B Core, 12T AWG 21) MICROMETALS Transistor Q1 STS8DNF3LL ST Diodes D1 1N4148 D2 STPS2L25U ST SOT23 SMB Device L6910 ST SO16Narrow Device U1 Table 10. Other inductor manufacturer Manufacturer Series Inductor Value (H) Saturation Current (A) WURTH ELEKTRONIK 744 382 4.8 to 5.8 7.5 to 8 PANASONIC ETQP6F 4.6 to 6.4 9.3 to 7.9 CDEP134-H 6 to 8 7.2 to 9.6 DO3316P-472HC 4.7 5.4 DO3340P 10 to 22 8 to 5.5 DR125-8R2 8.2 7.8 SUMIDA COILCRAFT COILTRONICS 16/29 L6910 - L6910A Figure 18. PCB and Components Layouts Component Side Solder Side 7.1 Compact Demo Board Performances Figures 19, 20 show the measured efficiency versus load current for different values of output voltage. The measure has been done at 5V and 12V input. Output voltage has been changed modifying the value of R1 in the demo board as reported in the part list. Figure 19. Efficiency vs. Output Current 100 Efficiency (%) 95 90 Vo=3.3V Vo=2.5V 85 Vo=1.8V 80 Vo=1.5V Vin=Vcc=5V Fsw=200KHz 75 Vo=1.2V 70 1 2 3 4 5 6 7 8 Output Current (A) Figure 20. Efficiency vs. Output Current 95 Vo=5V Efficiency (%) 90 Vo=3.3V 85 Vo=2.5V 80 Vo=1.8V Vo=1.5V Vin=Vcc=12V Fsw=200KHz 75 Vo=1.2V 70 1 2 3 4 5 6 7 8 Output Current (A) 17/29 L6910 - L6910A 8 15A HTSSOP16 DEMO BOARD DESCRIPTION A specific Demo Board has been realized for the HTSSOP16 package. The features are the same of the 15A Demo Board previously described but thermal performance are improved. The PGOOD signal is used as a logic level and it's been pulled up to VIN because there's no other appropriate voltage available on the demo board. In case of input voltage higher than 7V (PGOOD Pin Maximum Absolute Rating) a 5V reference is required. Figure 21. 15A HTSSOP16 Demo Board Schematic L1 F1 VIN R7 G2 GNDIN C14 D1 BOOT R6 13 VCC VCC OCSET 3 UGATE C17 R14 12 16 C15 GNDCC C1- C3 C13 VOUT 11 GND 8 LGATE U1 L6910A SS 4 OSC L2 Q1-3 PHASE R16 R15 15 D2 Q4-6 PGND R2 C4 -11 C23 GNDOUT 14 2 PGOOD PWRGD 10 EAREF VREF 9 Ref IN 1 6 C16 C21 C12 R8 VFB R1 7 COMP GNDRef +Vref R5 C19 R3 C20 R4 C22 C18 S1 S2 R10 S3 R11 S4 R12 S5 R13 GNDref R9 Vout S2 S3 S4 S5 0.9 1.2 1.5 1.8 2.5 3.3 5.0 Open Open Open Open ON Open Open Open Open ON Open Open ON ON Open Open Open Open ON Open Open Open Open ON Open Open ON ON Table 11. Part List 18/29 Reference R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 C1,C3 Description N.C 10K 5% 125mW 4.7K 5% 125mW 1K Ohm 5% 125mW 2.7K 5% 125mW 10 Ohm 5% 125mW 560 Ohm 5% 125mW N.C 0 Ohm 14K 5% 125mW 6.98K 5% 125mW 2.61K 5% 125mW 1.74K 5% 125mW 0 Ohm 0 Ohm N.C 100uF 20V C9,C10 330uF - 6.3V Manufacturer NEOHM NEOHM NEOHM NEOHM NEOHM NEOHM SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 NEOHM NEOHM NEOHM NEOHM NEOHM NEOHM NEOHM SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 OSCON 20SA100M POSCAP 6TPB330M RADIAL 10X10.5 SMD7343 L6910 - L6910A Table 11. Part List (continued) Reference C12,C13, C15,C21,C16 C14 C17 C18 C19 C20 C22 C23 L1 L2 Q2,Q3,Q4,Q6 D1 D2 U1 F1 SWITCH Description 100nF Manufacturer KEMET SMD0805 1nF 4.7uF - 16V 1.5nF 15nF 47nF N.C N.C Short 3uH T50-52B Core, 7T AWG15 STS11NF30L 1N4148 STPS340U Device L6910 Short DIP SWITCH KEMET AVX KEMET KEMET KEMET SMD0805 SMA6032 SMD0805 SMD0805 SMD0805 MICROMETALS SO8 SOT23 SMB HTSSOP16 ST ST ST Table 12. Other inductor manufacturer Manufacturer WURTH ELEKTRONIK PANASONIC SUMIDA Series 744318 ETQP6F1R8FA CDEP134-2R7MC-H Inductor Value (H) 1.8 to 2.7 1.8 2.7 Saturation Current (A) 16 to 20 20 15 Figure 22. PCB and Components Layout Component Side Internal Signal GND Layer Internal Power GND Layer Solder Side 19/29 L6910 - L6910A 9 APPLICATION IDEA 1: DDR MEMORY AND TERMINATION SUPPLY Double Data Rate (DDR) Memories require a particular Power Management Architecture. This is due to the fact that the trace between the driving chipset and the memory input must be terminated with resistors. Since the Chipset driving the Memory has a push pull output buffer, the Termination voltage must be capable of sourcing and sinking current. Moreover, the Termination voltage must be equal to one half of the memory supply (the input of the memory is a differential stage requiring a reference bias midpoint) and in tracking with it. For DDRI the Memory Supply is 2.5V and the Termination voltage is 1.25V while, for DDRII, the Memory Supply is 1.8V and the Termination voltage is 0.9V. Fig. 23 shows a complete DDRI Memory and Termination Power Supply realized by using 2 x L6910. The 2.5V section is powering the memory while the 1.25V section is providing the termination voltage. The tracking between the two sections is realized by providing the EAREF voltage of the 1.25V section through a resistor divider connected to the 2.5V. Figure 23. Application idea : DDR Memory Supply VIN 12V BOOT OCSET 12 15 VCC 3 UGATE 11 STS11NF3LL GND 7 U1 14 L6910 13 DDR MEMORY PHASE 10 VDDQ LGATE VREF STS11NF3LL SS 4 OSC 2 EAREF PGOOD 9 8 PWRGD VREF 1 5 2.5V@15A PGND TERMINATION NETWORK 6 VFB BUS COMP VIN 12V BOOT VCC 11 10 GND 4 OSC U2 14 L6910 13 2 EAREF 9 8 1 5 CHIPSET PHASE LGATE PGND PGOOD VTT 1.25V@ +- 5A PWRGD VREF 6 VFB COMP R UGATE 7 SS R STS8DNF3LL OCSET 3 12 15 + The current required by the memory and the termination supply, depends on the memory type and size. The figure 24, 25 shows the efficiency of the L6910 for the termination section of the application shown in fig. 23, in sink and source mode. The figures show the efficiency values also when the input voltage is coming directly from the 12V rail. 20/29 L6910 - L6910A Figure 24. Efficiency vs Output Current Source Mode Figure 27. Efficiency vs Output Current Sink Mode 95 100 90 Vin=2.5V 85 Efficiency (%) Efficiency (%) 90 80 75 Vin=12V Vcc=12V Vout=1.25V Fsw=200KHz 70 65 Vin=1.8V 80 70 Vin=12V 60 Vcc=12V Vout=0.9V Fsw=200KHz 50 60 40 1 2 3 4 5 6 7 1 8 Output Current (A) 3 5 7 9 11 13 15 17 Output Current (A) Figure 25. Efficiency vs Output Current Sink Mode Figure 28. Efficiency vs Output Current Source Mode 95 100 85 Vout=2.5V 90 Efficiency (%) Efficiency (%) 90 Vin=2.5V 80 75 70 Vcc=12V Vout=1.25V Fsw=200KHz 65 Vin=12V 80 Vout=12V 70 Vcc=12V Vout=1.25V Fsw=200KHz 60 60 1 2 3 4 5 6 7 8 50 Output Current (A) 1 Figure 26. Efficiency vs Output Current Sink Mode 100 Efficiency (%) 90 80 Vin=12V 9 11 13 15 17 100 90 Vin=1.8V 80 Vin=12V 70 Vin=12V Vout=0.9V Fsw=200KHz 50 Vin=12V 1 70 Vcc=12V Vout=1.25V Fsw=200KHz 60 7 Figure 29. Efficiency vs Output Current Source Mode 60 Vin=2.5V 5 Output Current (A) Efficiency (%) For very big systems (e.g. servers), the DDR memory termination can require much higher currents, in the range of 10A-15A and more. Figures 26, 27 and 28, 29 show the efficiency of the L6910 in sink and source mode, up to 17A both for DDRI and DDRII memories.The measurements have been realized with the 15A demo board. (See pag.11 ) 3 3 5 7 9 11 13 15 17 Output Current (A) 50 1 3 5 7 9 11 13 Output Current (A) 15 17 21/29 L6910 - L6910A 10 APPLICATION IDEA 2: POSITIVE BUCK-BOOST REGULATOR 3V TO 13.2V INPUT / 5V 2.5A OUTPUT In some applications the input voltage changes in a very wide range while the output must be regulated to a fixed value. In this case a Buck-Boost topology can be required in order to keep the output voltage in regulation. The schematic below shows how to implement a Buck-Boost regulating 5V at the output from both 3.3V and 5V and 12V input buses. In a Buck-Boost topology the current is delivered to the output during the OFF phase only. So, for a given current limit, the maximum output current depends strongly on the duty cycle. Assuming a 100% efficiency and neglecting the current ripple across the inductor, the relationship betweent the current limit and the maximum output current is the following: I OMAX = I LIM ( 1 - D ) Where ILIM is the current limit and D is the duty cycle of the application. The worst case is with DMAX. Since, in a Buck-Boost application, D is given by the following formula: VO D = ---------------------V IN + V O The worst case is with VINMIN. Obviously, since the efficiency is lower than 100% and the ripple is usually not negligible, the maximum output current is always lower than the value calculated in the above formula Figure 30. Positive buck-boost regulator 3V to 13.2V input / 5V 2.5A Output Circuit VIN (3.3V-5V-12V BUSES) C3 R1 G1 GNDIN D1 C4 C6 VCC 3 11 10 GND SS OSC EAREF Q4 L1 VOUT ( 5V 2.5A ) PHASE 7 4 U1 L6910/A 2 8 C7 14 1 5 6 LGATE R2 D2 Q2 13 9 PGND C10 R6 Q3 C13-- 14 C13 GNDOUT PGOOD VREF C12 VFB COMP R5 C9 22/29 UGATE Q1 C5 GNDCC C8 12 15 C1- C2 OCSET BOOT R7 VCC (12V BUS) R3 R4 C11 L6910 - L6910A Table 13. Part List Reference Description Manufacturer R1 910 Ohm 5% 125mW NEOHM SMD 0805 R2 10K 5% 125mW NEOHM SMD 0805 R3 4.7K 5% 125mW NEOHM SMD 0805 R4 1K 5% 125mW NEOHM SMD 0805 R5 2.7K 5% 125mW NEOHM SMD 0805 R6 1K1 NEOHM SMD 0805 R7 10 Ohm 125mW NEOHM SMD 0805 C1,C2 100F - 20V OSCON 20SA100M RADIAL 10X10.5 C13,C14 330F - 6.3V POSCAP 6TPB330M SMD7343 C12,C5,C8 100nF KEMET SMD0805 C3 1nF KEMET SMD0805 C4 470nF KEMET SMD0805 C6 4.7F - 16V AUX SMA6032 C7 100nF KEMET C9 15nF KEMET SMD0805 C10 1.5nF KEMET SMD0805 C11 47nF KEMET SMD0805 G1 Open Jumper L1 2.5H (77121A7 Core, Double winding 7 AWG16) MAGNETICS Q1,Q2,Q3 STS11NF30L ST SO8 Q4 STS5P30L ST SO8 D1 1N4148 D2 STPS3L25U (STPS340U) ST SMB (D0144) U1 Device L6910 ST SO16 Narrow SOT23 Figure 31. Efficiency vs. Output Current 90 Vin=5V Efficiency (%) 85 80 Vin=12V 75 Vin=3.3V Vcc=5V Vout=5V Fsw=200KHz 70 65 1 1.5 2 2.5 3 3.5 Output Current (A) 23/29 L6910 - L6910A 11 APPLICATION IDEA 3: BUCK-BOOST REGULATOR 3V TO 5.5V INPUT/-5V 3A OUTPUT In applications where a negative output voltage is required, a standard Buck-Boost topology can be implemented. The considerations related to the maximum output current are the same of the "Positive Buck-Boost" (Application Idea 2). A particularity of this topology is that the device undergoes a voltage that is the sum of VIN and VOUT. So, converting 5V to -5V, the device undergoes 10V voltage. It must be checked that the sum of the input and output voltage is lower than the maximum operating input voltage of the device. Figure 32. buck-boost regulator 3V to 5.5V input / -5V 3A Output Circuit VIN (3V to 5.5V ) R1 G1 C3 C1- C2 GNDIN=GNDOUT D1 C4 BOOT R7 VCC VCC (5V) 15 OCSET 3 12 UGATE 10 PHASE 14 LGATE 13 PGND L1 Q1 C5 C6 GND GNDCC 11 GNDOUT 7 SS 4 OSC U1 L6910/A 2 EAREF 8 C7 5 C8 6 9 PGOOD 1 VREF C13 14 - VOUT (-5V 3A) C12 VFB COMP R5 C9 D2 Q2 R3 R4 C11 C10 R6 Table 14. Part List Reference Description Manufacturer R1 910 Ohm 5% 125mW NEOHM SMD 0805 R2 10K 5% 125mW NEOHM SMD 0805 R3 4.7K 5% 125mW NEOHM SMD 0805 R4 1K Ohm 5% 125mW NEOHM SMD 0805 R5 2.7K 5% 125mW NEOHM SMD 0805 R6 1K 5% 125mW NEOHM SMD 0805 R7 10 Ohm 5% 125mW NEOHM SMD 0805 C1,C2 100F - 20V OSCON 20SA100M RADIAL 10X10.5 C13,C14 330F - 6.3V POSCAP 6TPB330M SMD7343 C12,C4,C5,C8 100nF KEMET SMD0805 C3 1nF KEMET SMD0805 C6 4.7F - 16V AUX SMA6032 C7 100nF KEMET 24/29 L6910 - L6910A Table 14. Part List (continued) C9 15nF KEMET SMD0805 C10 1.5nF KEMET SMD0805 Reference Description Manufacturer C11 47nF KEMET G1 Open Jumper L1 2.5H (77121A7 Core, Double winding 7 AWG16) MAGNETICS Q1,Q2 STS11NF30L ST SO8 SMD0805 D1 1N4148 D2 STPS3L25U ( STPS340U) ST SMB (D0144) SOT23 U1 Device L6910 ST SO16 Narrow Figure 33. Efficiency vs. Output Current 94 92 Efficiency (%) Vin=5V 90 88 Vin=3.3V 86 Vcc=5V Vout= -5V Fsw=200KHz 84 82 1 1.5 2 2.5 3 Output Current (A) 25/29 L6910 - L6910A Figure 34. HTSSOP16 (Exposed pad) Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 1.2 0.047 A1 0.15 0.006 A2 0.8 b 1.05 0.031 0.19 0.3 0.007 0.012 c 0.09 0.2 0.003 0.008 D (*) 4.9 5.1 0.192 D1 1.7 E 6.2 6.4 6.6 E1 (*) 4.3 4.4 4.5 E2 1.5 e L L1 k aaa 1.0 5.0 0.041 0.197 0.200 0.244 0.252 0.260 0.169 0.173 0.177 0.067 0.059 0.65 0.45 0.039 OUTLINE AND MECHANICAL DATA 0.6 0.026 0.75 0.018 1.0 0.024 0.029 0.039 0 (min), 8 (max) 0.10 0.004 (*) Dimensions D and E1 does not include mold flash or protusions. Mold flash or protusions shall not exeed 0.15mm per side. HTSSOP16 (Exposed Pad) 7419276 26/29 L6910 - L6910A Figure 35. SO-16 (Narrow) Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. A a1 MAX. MIN. TYP. 1.75 0.1 0.25 a2 MAX. 0.069 0.004 0.009 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 c1 D(1) E (typ.) 9.8 10 0.386 0.394 5.8 6.2 0.228 0.244 1.27 e3 F (1) 0.020 45 e 0.050 8.89 3.8 0.350 4.0 0.150 0.157 G 4.60 5.30 0.181 0.208 L 0.4 1.27 0.150 0.050 M S OUTLINE AND MECHANICAL DATA 0.62 0.024 8 (max.) SO16 (Narrow) (1) "D" and "F" do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (.006inc.) 0016020 D 27/29 L6910 - L6910A Table 1. Revision History Date Revision January 2004 7 Migration from ST-Press to EDOCS dms. August 2004 8 Changed any figures and textes; add. the section "15A HTSSOP16 Demo Board Description". Changed the style-look following the new "Corporate Technical Pubblications Design Guide" rules; and figs 23, 30, 32 May 2005 9 Changed the figure 30. 28/29 Description of Changes L6910 - L6910A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 29/29