PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 1©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb SYNCBURST™
SRAM
MT58L1MY18D, MT58V1MV18D,
MT58L512Y32D, MT58V512V32D,
MT58L512Y36D, MT58V512V36D
3.3V VDD, 3.3V or 2.5V I/O; 2.5V VDD, 2.5V I/O
Features
• Fast clock and OE# access times
• Single 3.3V
±5 percent or 2.5V ±5 percent
power supply
• Separate 3.3V
±5 percent or 2.5V ±5 percent
isolated
output buffer supply (VDDQ)
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Individual byte write control and global write
• Three chip enables for simple depth expansion and
address pipelining
• Clock-controlled and registered addresses, data
I/Os, and control signals
• Internally self-timed WRITE cycle
• Burst control (interleaved or linear burst)
• Low capacitive bus loading
Part Number Example:
MT58L512Y36DT-10
General Description
The Micron® SyncBurst™ SRAM family employs
high-speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
Micron’s 18Mb SyncBurst SRAMs integrate a 1 Meg x
18, 512K x 32, or 512K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single-clock
input (CLK). The synchronous inputs include all
addresses, all data inputs, active LOW chip enable
Options TQFP
Marking
• Timing (Access/Cycle/MHz)
3.1ns/5ns/200 MHz
3.5ns/6ns/166 MHz
4.2ns/7.5ns/133 MHz
5ns/10ns/100 MHz
-5
-6
-7.5
-10
• Configurations
3.3V VDD, 3.3V or 2.5V I/O
1 Meg x 18
512K x 32
512K x 36
MT58L1MY18D
MT58L512Y32D
MT58L512Y36D
2.5V VDD, 2.5V I/O
1 Meg x 18
512K x 32
512K x 36
MT58V1MV18D
MT58V512V32D
MT58V512V36D
•Packages
100-pin TQFP
165-ball, 13mm x 15mm FBGA
T
F1
NOTE:
1. A Part Marking Guide for the FBGA devices can be found
on Micron’s Web site—http://www.micron.com/number-
guide.
• Operating Temperature Range
Commercial (0ºC £ TA £ +70ºC
Industrial (-40ºC
£
T
A
£
+85ºC)
None
IT2
2. Contact factory for availability of Industrial Temperature
devices.
Figure 1: 100-Pin TQFP
JEDEC-Standard MS-026 BHA (LQFP)
Figure 2: 165-Ball FBGA
JEDEC-Standard MO-216 (Var. CAB-1)
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 2©2003 Micron Technology, Inc.
(CE#), two additional chip enables for easy depth
expansion (CE2, CE2#), burst control inputs (ADSC#,
ADSP#, ADV#), byte write enables (BWx#), and global
write (GW#).
Asynchronous inputs include the output enable
(OE#), clock (CLK) and snooze enable (ZZ). There is
also a burst mode input (MODE) that selects between
interleaved and linear burst modes. The data out (Q) is
enabled by OE#. WRITE cycles can be from one to two
bytes wide (x18) or from one to four bytes wide (x32/
x36), as controlled by the write control inputs.
Burst operation can be initiated with either address
status processor (ADSP#) or address status controller
(ADSC#) inputs. Subsequent burst addresses can be
internally generated as controlled by the burst
advance input (ADV#).
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed write
cycles. Individual byte enables allow individual bytes
to be written. During WRITE cycles on the x18 device,
BWa# controls DQa pins/balls and DQPa; BWb# con-
trols DQb pins/balls and DQPb. During WRITE cycles
on the x32 and x36 devices, BWa# controls DQa pins/
balls and DQPa; BWb# controls DQb pins/balls and
DQPb; BWc# controls DQc pins/balls and DQPc; BWd#
controls DQd pins/balls and DQPd. GW# LOW causes
all bytes to be written. Parity bits are only available on
the x18 and x36 versions.
This device incorporates an additional pipelined
enable register which delays turning off the output
buffer an additional cycle when a deselect is executed.
This feature allows depth expansion without penaliz-
ing system performance.
The device is ideally suited for Pentium
®
and
PowerPC pipelined systems and systems that benefit
from a very wide, high-speed data bus. The device is
also ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-
wide applications.
Please refer to Micron’s Web site (www.micron.com/
sramds) for the latest data sheet.
Dual Voltage I/O
The 3.3V VDD device is tested for 3.3V and 2.5V I/O
function. The 2.5V VDD device is tested for only 2.5V
I/O function.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 3©2003 Micron Technology, Inc.
Figure 3: Functional Block Diagram
1 Meg x 18
Figure 4: Functional Block Diagram
512K x 32/36
NOTE:
Functional block diagrams illustrate simplified device operation. See truth tables, pin/ball description, and tim-
ing diagrams for detailed information.
SA0, SA1, SAs ADDRESS
REGISTER
ADV#
CLK
BINARY
COUNTER AND
LOGIC
CLR
Q1
Q0
ADSC#
20 20 18 20
BWb#
BWa#
CE#
BYTE “b”
WRITE REGISTER
BYTE “a”
WRITE REGISTER
ENABLE
REGISTER
SA0'
SA1'
OE#
SENSE
AMPS
1 Meg x 9 x 2
MEMORY
ARRAY
ADSP#
2SA0-SA1
MODE
CE2
CE2#
GW#
BWE#
PIPELINED
ENABLE
DQs
DQPa
DQPb
2
OUTPUT
REGISTERS
INPUT
REGISTERS
E
BYTE “b”
WRITE DRIVER
BYTE “a”
WRITE DRIVER
OUTPUT
BUFFERS
9
9
9
9
18 18 18 18
18
ADDRESS
REGISTER
ADV#
CLK BINARY
COUNTER
CLR
Q1
Q0
ADSP#
ADSC#
MODE
19 19 17 19
BWd#
BWc#
BWb#
BWa#
BWE#
GW#
CE#
CE2
CE2#
OE#
BYTE “d”
WRITE REGISTER
BYTE “c”
WRITE REGISTER
BYTE “b”
WRITE REGISTER
BYTE “a”
WRITE REGISTER
ENABLE
REGISTER PIPELINED
ENABLE
DQs
DQPa
DQPb
DQPc
DQPd
4
OUTPUT
REGISTERS
SENSE
AMPS
512K x 8 x 4
(x32)
512K x 9 x 4
(x36)
MEMORY
ARRAY
OUTPUT
BUFFERS
E
BYTE “a”
WRITE DRIVER
BYTE “b”
WRITE DRIVER
BYTE “c”
WRITE DRIVER
BYTE “d”
WRITE DRIVER
INPUT
REGISTERS
SA0, SA1, SAs
SA0'
9
9
9
9
9
9
36 36 36 36
36
9
9
SA1'
SA0-SA1
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 4©2003 Micron Technology, Inc.
Figure 5:
Pin Layout (Top View)
100-Pin TQFP
NOTE:
1. No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version.
2. Pins 39 and 38 are reserved for address expansion; 36Mb and 72Mb, respectively.
SA
SA
ADV#
ADSP#
ADSC#
OE# (G#)
BWE#
GW#
CLK
VSS
VDD
CE2#
BWa#
BWb#
NC
NC
CE2
CE#
SA
SA
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SA
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
SA
SA
SA
SA
SA
SA
SA
SA
SA
VDD
VSS
DNU2
DNU2
SA0
SA1
SA
SA
SA
SA
MODE
(LBO#)
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
NC
VDD
NC
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
VSS
VDDQ
NC
NC
NC
x18
SA
SA
ADV#
ADSP#
ADSC#
OE# (G#)
BWE#
GW#
CLK
VSS
VDD
CE2#
BWa#
BWb#
BWc#
BWd#
CE2
CE#
SA
SA
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NF/DQPb1
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
NF/DQPa1
SA
SA
SA
SA
SA
SA
SA
SA
SA
VDD
VSS
DNU2
DNU2
SA0
SA1
SA
SA
SA
SA
MODE
(LBO#)
NF/DQPc1
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
NF/DQPd1
x32/x36
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 5©2003 Micron Technology, Inc.
Table 1: TQFP Pin Descriptions
SYMBOL TYPE DESCRIPTION
ADSC# Input Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst,
causing a new external address to be registered. A READ or WRITE is performed using the
new address if CE# is LOW. ADSC# is also used to place the chip into power-down state when
CE# is HIGH.
ADSP# Input Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst,
causing a new external address to be registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent upon CE#, CE2, and CE2#.
ADSP# is ignored if CE# is HIGH. Power-down state is entered if CE2 is LOW or CE2# is HIGH.
ADV# Input Synchronous Address Advance: This active LOW input is used to advance the internal burst
counter, controlling burst access after the external address is loaded. A HIGH on this pin
effectively causes wait states to be generated (no address advance). To ensure use of correct
address during a WRITE cycle, ADV# must be HIGH at the rising edge of the first clock after an
ADSP# cycle is initiated.
BWa#
BWb#
BWc#
BWd#
Input Synchronous Byte Write: These active LOW inputs allow individual bytes to be written when a
WRITE cycle is active and must meet the setup and hold times around the rising edge of CLK.
BWs need to be asserted on the same cycle as the address. To enable the BW’s functionality,
the byte write enable (BWE#) input must be asserted LOW. BWa# controls DQa pins; BWb#
controls DQb pins; BWc# controls DQc pins; and BWd# controls DQa pins.
BWE# Input Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the
setup and hold times around the rising edge of CLK.
CE# Input Synchronous Chip Enable: This active LOW input is used to enable the device and conditions
the internal use of ADSP#. CE# is sampled only when a new external address is loaded.
CE2# Input Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled
only when a new external address is loaded.
CE2 Input Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled
only when a new external address is loaded.
CLK Input Clock: This signal registers the address, data, chip enable, byte write enables, and burst
control inputs on its rising edge. All synchronous inputs must meet setup and hold times
around the clock’s rising edge.
GW# Input Global Write: This active LOW input allows a full 18-, 32-, or 36-bit WRITE to occur
independent of the BWE# and BWx# lines and must meet the setup and hold times around
the rising edge of CLK.
MODE
(LBO#)
Input Mode: This input selects the burst sequence. A LOW on this pin selects “linear burst.” NC or
HIGH on this pin selects “interleaved burst.” Do not alter input state while device is
operating. LBO# is the JEDEC-standard term for MODE.
OE# (G#) Input Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. G# is
the JEDEC-standard term for OE#.
SA0
SA1
SA
Input Synchronous Address Inputs: These inputs are registered and must meet the setup and hold
times around the rising edge of CLK.
ZZ Input Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power
standby mode in which all data in the memory array is retained. When ZZ is active, all other
inputs are ignored. This pin has an internal pull-down and can be left unconnected.
DQa
DQb
DQc
DQd
Input/
Output
SRAM Data I/Os: For the x18 version, byte “a” is associated with DQa pins; byte “b” is
associated with DQb pins. For the x32 and x36 versions, byte “a” is associated with DQa pins;
byte “b” is associated with DQb pins; byte “c” is associated with DQc pins; byte “d” is
associated with DQd pins. Input data must meet setup and hold times around the rising edge
of CLK.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 6©2003 Micron Technology, Inc.
NF/DQPa
NF/DQPb
NF/DQPc
NF/DQPd
NF
I/O
No Function/Parity Data I/Os: On the x32 version, these pins are No Function (NF). On the x18
version, byte “a” parity is DQPa; byte “b” parity is DQPb. On the x36 version, byte “a” parity
is DQPa; byte “b” parity is DQPb; byte “c” parity is DQPc; byte “d” parity is DQPd.
VDD Supply Power Supply: See DC Electrical Characteristics and Operating Conditions for range.
VDDQ Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for
range.
VSS Supply Ground: GND.
DNU – Do Not Use: These pins are internally connected to the die. They may be left floating or
connected to ground to improve package heat dissipation.
NC – No Connect: These pins are not internally connected to the die. They may be left floating,
driven by signals, or connected to ground to improve package heat dissipation.
NF – No Function: These pins are internally connected to the die and have the capacitance of an
input pin. They may be left floating, driven by signals, or connected to ground to improve
package heat dissipation.
Table 1: TQFP Pin Descriptions (continued)
SYMBOL TYPE DESCRIPTION
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 7©2003 Micron Technology, Inc.
Figure 6: Ball Layout (Top View)
165-Ball FBGA
x18 x32/x36
NOTE:
1. No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version.
2. Balls 2P and 2R are reserved for address expansion; 36Mb and 72Mb, respectively.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
CE#
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
SA
SA
SA
SA
NC
DQb
DQb
DQb
DQb
VSS
NC
NC
NC
NC
NC
NC2
NC2
NC
NC
NC
NC
NC
NC
NC
VDD
DQb
DQb
DQb
DQb
DQPb
NC
MODE
(LBO#)
BWb#
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
SA
SA
NC
BWa#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
TMS
CE2#
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
SA1
SA0
BWE#
GW#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TD0
TCK
ADSC#
OE# (G#)
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
SA
SA
ADV#
ADSP#
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
SA
SA
SA
SA
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
SA
SA
SA
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
SA
SA
TOP VIEW
3456789
10 11
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
CE#
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
SA
SA
SA
SA
NC
DQc
DQc
DQc
DQc
VSS
DQd
DQd
DQd
DQd
NC
NC2
NC2
NC
NC
NF/DQPc1
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
NF/DQPd1
NC
MODE
(LBO#)
BWc#
BWd#
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
SA
SA
BWb#
BWa#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
TMS
CE2#
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
SA1
SA0
BWE#
GW#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TD0
TCK
ADSC#
OE# (G#)
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
SA
SA
ADV#
ADSP#
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
SA
SA
SA
SA
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
SA
SA
NC
NC
NF/DQPb1
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
NF/DQPa1
SA
SA
TOP VIEW
3456789
10 11
1
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 8©2003 Micron Technology, Inc.
Table 2: FBGA Ball Descriptions
SYMBOL TYPE DESCRIPTION
ADSC# Input Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst,
causing a new external address to be registered. A READ or WRITE is performed using the
new address if CE# is LOW. ADSC# is also used to place the chip into power-down state when
CE# is HIGH.
ADSP# Input Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst,
causing a new external address to be registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent upon CE#, CE2, and CE2#.
ADSP# is ignored if CE# is HIGH. Power-down state is entered if CE2 is LOW or CE2# is HIGH.
ADV# Input Synchronous Address Advance: This active LOW input is used to advance the internal burst
counter, controlling burst access after the external address is loaded. A HIGH on ADV#
effectively causes wait states to be generated (no address advance). To ensure use of correct
address during a WRITE cycle, ADV# must be HIGH at the rising edge of the first clock after an
ADSP# cycle is initiated.
BWa#
BWb#
BWc#
BWd#
Input Synchronous Byte Write: These active LOW inputs allow individual bytes to be written when a
WRITE cycle is active and must meet the setup and hold times around the rising edge of CLK.
BWs need to be asserted on the same cycle as the address. To enable the BW’s functionality,
the byte write enable (BWE#) input must be asserted LOW. BWa# controls DQa balls; BWb#
controls DQb balls; BWc# controls DQc balls; and BWd# controls DQa balls.
BWE# Input Byte Write Enable: This active LOW input permits byte write operations and must meet the
setup and hold times around the rising edge of CLK.
CE# Input Synchronous Chip Enable: This active LOW input is used to enable the device and conditions
the internal use of ADSP#. CE# is sampled only when a new external address is loaded.
CE2# Input Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled
only when a new external address is loaded.
CE2 Input Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled
only when a new external address is loaded.
CLK Input Clock: This signal registers the address, data, chip enable, byte write enables, and burst
control inputs on its rising edge. All synchronous inputs must meet setup and hold times
around the clock’s rising edge.
GW# Input Global Write: This active LOW input allows a full 18-, 32-, or 36-bit WRITE to occur
independent of the BWE# and BWx# lines and must meet the setup and hold times around
the rising edge of CLK.
MODE
(LB0#)
Input Mode: This input selects the burst sequence. A low on this ball selects “linear burst.” NC or
HIGH on this input selects “interleaved burst.” Do not alter input state while device is
operating. LBO# is the JEDEC-standard term for MODE.
OE# (G#) Input Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. G# is
the JEDEC-standard term for OE#.
SA0
SA1
SA
Input Synchronous Address Inputs: These inputs are registered and must meet the setup and hold
times around the rising edge of CLK.
TMS
TDI
TCK
Input IEEE 1149.1 Test Inputs: JEDEC-standard 3.3V and 2.5V I/O levels. These balls may be left as No
Connects if the JTAG function is not used in the circuit.
ZZ Input Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power
standby mode in which all data in the memory array is retained. When ZZ is active, all other
inputs are ignored. This ball has an internal pull-down and can be left unconnected.
DQa
DQb
DQc
DQd
Input/
Output
SRAM Data I/Os: For the x18 version, byte “a” is associated DQa balls; byte “b” is associated
with DQb balls. For the x32 and x36 versions, byte “a” is associated with DQa balls; byte “b”
is associated with DQbs; byte “c” is associated with DQc balls; byte “d” is associated with DQd
balls. Input data must meet setup and hold times around the rising edge of CLK.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 9©2003 Micron Technology, Inc.
NF/DQPa
NF/DQPb
NF/DQPc
NF/DQPd
NF
I/O
No Function/Parity Data I/Os: On the x32 version, these are No Function (NF). On the x18
version, byte “a” parity is DQPa; byte “b” parity is DQPb. On the x36 version, byte “a” parity
is DQPa; byte “b” parity is DQPb; byte “c” parity is DQPc; byte “d” parity is DQPd.
TDO Output IEEE 1149.1 Test Output: JEDEC-standard 3.3V and 2.5V I/O levels.
VDD Supply Power Supply: See DC Electrical Characteristics and Operating Conditions for range.
VDDQ Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for
range.
VSS Supply Ground: GND.
NC – No Connect: These balls are not internally connected to the die. They may be left floating,
driven by signals, or connected to ground to improve package heat dissipation.
NF – No Function: These balls are internally connected to the die and have the capacitance of an
input pin. They may be left floating, driven by signals, or connected to ground to improve
package heat dissipation.
Table 2: FBGA Ball Descriptions (continued)
SYMBOL TYPE DESCRIPTION
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 10 ©2003 Micron Technology, Inc.
NOTE:
Using BWE# and BWa# through BWd#, any one or more bytes may be written.
NOTE:
Using BWE# and BWa# through BWd#, any one or more bytes may be written.
Table 3: Interleaved Burst Address Table (Mode = NC or HIGH)
FIRST ADDRESS
(EXTERNAL)
SECOND ADDRESS
(INTERNAL)
THIRD ADDRESS
(INTERNAL)
FOURTH ADDRESS
(INTERNAL)
X...X00 X...X01 X...X10 X...X11
X...X01 X...X00 X...X11 X...X10
X...X10 X...X11 X...X00 X...X01
X...X11 X...X10 X...X01 X...X00
Table 4: Linear Burst Address Table (Mode = LOW)
FIRST ADDRESS
(EXTERNAL)
SECOND ADDRESS
(INTERNAL)
THIRD ADDRESS
(INTERNAL)
FOURTH ADDRESS
(INTERNAL)
X...X00 X...X01 X...X10 X...X11
X...X01 X...X10 X...X11 X...X00
X...X10 X...X11 X...X00 X...X01
X...X11 X...X00 X...X01 X...X10
Table 5: Partial Truth Table for WRITE Commands (x18)
FUNCTION GW# BWE# BWa# BWb#
READ HHXX
READ HLHH
WRITE Byte “a” HLLH
WRITE Byte “b” HLHL
WRITE All Bytes HLLL
WRITE All Bytes LXXX
Table 6: Partial Truth Table for WRITE Commands (x32/x36)
FUNCTION GW# BWE# BWa# BWb# BWc# BWd#
READ HHXXXX
READ HLHHHH
WRITE Byte “a” HL LHHH
WRITE All Bytes HLLLLL
WRITE All Bytes LXXXXX
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 11 ©2003 Micron Technology, Inc.
NOTE:
1. X means “Don’t Care.” # means active LOW. H means logic HIGH. L means logic LOW.
2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc#, or BWd#), and BWE# are LOW
or GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH.
3. BWa# enables writes to DQa pins/balls and DQPa. BWb# enables writes to DQb pins/balls and DQPb. BWc# enables
writes to DQc pins/balls and DQPc. BWd# enables writes to DQd pins/balls and DQPd. DQPa and DQPb are only avail-
able on the x18 and x36 versions. DQPc and DQPd are only available on the x36 version.
4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held
HIGH throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP# LOW always initiates an internal READ at the L–H edge of CLK. A WRITE is performed by setting one or more
byte write enable signals and BWE# LOW or GW# LOW for the subsequent L–H edge of CLK. Refer to WRITE timing
diagram for clarification.
Table 7: Truth Table
Notes 1–8
OPERATION
ADDRESS
USED CE# CE2# CE2 ZZ ADSP# ADSC# ADV# WRITE# OE# CLK DQ
DESELECT Cycle,
Power-Down
None H X X L X L X X X L–H High-Z
DESELECT Cycle,
Power-Down
None L X L L L X X X X L–H High-Z
DESELECT Cycle,
Power-Down
None L H X L L X X X X L–H High-Z
DESELECT Cycle,
Power-Down
None L X L L H L X X X L–H High-Z
DESELECT Cycle,
Power-Down
None L H X L H L X X X L–H High-Z
SNOOZE MODE,
Power-Down
None X X X H X X X X X X High-Z
READ Cycle, Begin Burst External L L H L L X X X L L–H Q
READ Cycle, Begin Burst External L L H L L X X X H L–H High-Z
WRITE Cycle, Begin Burst External L L H L H L X L X L–H D
READ Cycle, Begin Burst External L L H L H L X H L L–H Q
READ Cycle, Begin Burst External L L H L H L X H H L–H High-Z
READ Cycle, Continue Burst Next XXXL H H L H LL–HQ
READ Cycle, Continue Burst Next X X X L H H L H H L–H High-Z
READ Cycle, Continue Burst Next H X X L X H L H L L–H Q
READ Cycle, Continue Burst Next H X X L X H L H H L–H High-Z
WRITE Cycle,
Continue Burst
Next XXXL H H L L XL–HD
WRITE Cycle,
Continue Burst
Next H X X L X H L L X L–H D
READ Cycle, Suspend Burst Current X X X L H H H H L L–H Q
READ Cycle, Suspend Burst Current X X X L H H H H H L–H High-Z
READ Cycle, Suspend Burst Current H X X L X H H H L L–H Q
READ Cycle, Suspend Burst Current H X X L X H H H H L–H High-Z
WRITE Cycle, Suspend Burst Current X X X L H H H L X L–H D
WRITE Cycle, Suspend Burst Current H X X L X H H L X L–H D
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 12 ©2003 Micron Technology, Inc.
Absolute Maximum Ratings
3.3V VDD
Voltage on VDD Supply
Relative to VSS .......................................-0.5V to +4.6V
Voltage on VDDQ Supply
Relative to VSS .......................................-0.5V to +4.6V
VIN (DQx) ....................................... -0.5V to VDDQ + 0.5V
VIN (inputs) ....................................... -0.5V to VDD + 0.5V
Storage Temperature (TQFP).................-55ºC to +150ºC
Storage Temperature (FBGA).................-55ºC to +125ºC
Junction Temperature .......................................... +150ºC
Short Circuit Output Current ...............................100mA
2.5V VDD
Voltage on VDD Supply
Relative to VSS .......................................-0.3V to +3.6V
Voltage on VDDQ Supply
Relative to VSS .......................................-0.3V to +3.6V
VIN (DQx) ....................................... -0.3V to VDDQ + 0.3V
VIN (inputs) ....................................... -0.3V to VDD + 0.3V
Storage Temperature (TQFP).................-55ºC to +150ºC
Storage Temperature (FBGA).................-55ºC to +125ºC
Junction Temperature .......................................... +150ºC
Short Circuit Output Current ...............................100mA
Stresses greater than those listed may cause perma-
nent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the opera-
tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Maximum Junction Temperature depends upon
package type, cycle time, loading, ambient tempera-
ture, and airflow.
Table 8: 3.3V VDD, 3.3V I/O DC Electrical Characteristics and Operating Conditions
Notes appear following parameter tables on page 17; 0ºC £ TA £ +70ºC; VDD and VDDQ = 3.3V ±0.165V unless otherwise
noted
DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES
Input High (Logic 1) Voltage VIH 2.0 VDD + 0.3 V 1, 2
Input Low (Logic 0) Voltage VIL -0.3 0.8 V 1, 2
Input Leakage Current 0V £ VIN £ VDD ILI-1.0 1.0 µA 4
Output Leakage Current Output(s) disabled,
0V £ VIN £ VDD
ILO-1.0 1.0 µA
Output High Voltage IOH = -4.0mA VOH 2.4 – V 1
Output Low Voltage IOL = 8.0mA VOL –0.4V 1
Supply Voltage VDD 3.135 3.465 V 1
Isolated Output Buffer Supply VDDQ3.135 VDD V1, 5
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 13 ©2003 Micron Technology, Inc.
Table 9: 3.3V VDD, 2.5V I/O DC Electrical Characteristics and Operating Conditions
Notes appear following parameter tables on page 17; 0ºC £ TA £ +70ºC; VDD = 3.3V ±0.165V and VDDQ = 2.5V ±0.125V unless
otherwise noted
DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES
Input High (Logic 1) Voltage Data bus (DQx) VIHQ 1.7 VDDQ + 0.3 V 1, 2
Inputs VIH 1.7 VDD + 0.3 V 1, 2
Input Low (Logic 0) Voltage VIL -0.3 0.7 V 1, 2
Input Leakage Current 0V £ VIN £ VDD ILI-1.0 1.0 µA 4
Output Leakage Current Output(s) disabled,
0V £ VIN £ VDDQ (DQx)
ILO -1.0 1.0 µA
Output High Voltage IOH = -2.0mA VOH 1.7 – V 1
IOH = -1.0mA VOH 2.0 – V 1
Output Low Voltage IOL = 2.0mA VOL – 0.7V1
IOL = 1.0mA VOL –0.4 V1
Supply Voltage VDD 3.135 3.465 V 1
Isolated Output Buffer Supply VDDQ 2.375 2.625 V 1, 5
Table 10: 2.5V VDD, 2.5V I/O DC Electrical Characteristics and Operating Conditions
Notes appear following parameter tables on page 17; 0ºC £ TA £ +70ºC; VDD and VDDQ = 2.5V ±0.125V unless otherwise
noted
DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES
Input High (Logic 1) Voltage Data bus (DQx) VIHQ1.7VDDQ + 0.3 V 1, 3
Inputs VIH 1.7 VDD + 0.3 V 1, 3
Input Low (Logic 0) Voltage VIL -0.3 0.7 V 1, 3
Input Leakage Current 0V £ VIN £ VDD ILI-1.0 1.0 µA 4
Output Leakage Current Output(s) disabled,
0V £ VIN £ VDDQ (DQx)
ILO -1.0 1.0 µA
Output High Voltage IOL = 2.0mA VOL 1.7 – V 1
IOH = -1.0mA VOH 2.0 – V 1
Output Low Voltage IOL = 2.0mA VOL – 0.7V1
IOL = 1.0mA VOL –0.4 V1
Supply Voltage VDD 2.375 2.625 V 1
Isolated Output Buffer Supply VDDQ 2.375 2.625 V 1, 5
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 14 ©2003 Micron Technology, Inc.
Table 11: TQFP Capacitance
Note 6; notes appear following parameter tables on page 17
Table 12: FBGA Capacitance
Note 6; notes appear following parameter tables on page 17
Table 13: TQFP Thermal Resistance
Note 6; notes appear following parameter tables on page 17
Table 14: FBGA Thermal Resistance
Note 6; notes appear following parameter tables on page 17
DESCRIPTION CONDITIONS SYMBOL TYP MAX UNITS
Control Input Capacitance
TA = 25ºC; f = 1 MHz;
VDD = 3.3V
CI4.2 5 pF
Input/Output Capacitance (DQ) CO3.5 4 pF
Address Input Capacitance CA45 pF
Clock Capacitance CCK 4.2 5 pF
DESCRIPTION CONDITIONS SYMBOL TYP MAX UNITS
Control Input Capacitance
TA = 25ºC; f = 1 MHz;
VDD = 3.3V
CI45pF
Input/Output Capacitance (DQ) CO44.5pF
Address Input Capacitance CA45 pF
Clock Capacitance CCK 55.5pF
DESCRIPTION CONDITIONS SYMBOL TYP UNITS
Junction to Ambient
(Airflow of 1m/s, two-layer board) Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
qJA 28.9 ºC/W
Thermal Resistance
Junction to Case (Top) qJC 4.2 ºC/W
DESCRIPTION CONDITIONS SYMBOL TYP UNITS
Junction to Ambient
(Airflow of 1m/s, two-layer board) Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
qJA 32 ºC/W
Junction to Case (Top) qJC 1.7 ºC/W
Junction to Board (Bottom) qJB 10.4 ºC/W
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 15 ©2003 Micron Technology, Inc.
Table 15: 3.3V VDD, IDD Operating Conditions and Maximum Limits
(1 Meg x 18 and 512K x 36)
Notes appear following parameter tables on page 17; 0ºC £ TA £ +70ºC; VDD and VDDQ = 3.3V ±0.165V unless otherwise
noted
Table 16: 2.5V VDD, IDD Operating Conditions and Maximum Limits
(1 Meg x 18 and 512K x 36)
Notes appear following parameter tables on page 17; 0ºC £ TA £ +70ºC; VDD and VDDQ = 2.5V ±0.125V unless otherwise
noted
MAX
DESCRIPTION CONDITIONS SYMBOL TYP -5 -6 -7.5 -10 UNITS NOTES
Power Supply
Current:
Operating
Device selected; All inputs £ VIL or
³ VIH; Cycle time ³ tKC (MIN);
VDD = MAX; Outputs open
IDD 300 420 380 340 300 mA 7, 8, 9
Power Supply
Current: Idle
Device selected; VDD = MAX;
ADSC#, ADSP#, ADV#, GW#,
BWx# ³ VIH; All inputs £ VSS + 0.2
or ³ VDD - 0.2; Cycle time ³
tKC (MIN); Outputs open
IDD1120 180 170 160 150 mA 7, 8, 9
CMOS Standby Device deselected; VDD = MAX;
All inputs £ VSS + 0.2 or
³ VDD - 0.2; All inputs static;
CLK frequency = 0
ISB28 30303030mA8, 9
Clock Running Device deselected; VDD = MAX;
ADSC#, ADSP#, ADV#, GW#,
BWx# ³ VIH; All inputs £ VSS + 0.2
or ³ VDD - 0.2;
Cycle time ³ tKC (MIN)
ISB4120 180 170 160 150 mA 8, 9
Snooze Mode ZZ ³ VIH ISB2Z 8 30303030mA 9
MAX
DESCRIPTION CONDITIONS SYMBOL TYP -5 -6 -7.5 -10 UNITS NOTES
Power Supply
Current:
Operating
Device selected; All inputs £ VIL or
³ VIH; Cycle time ³ tKC (MIN);
VDD = MAX; Outputs open
IDD 230 350 300 260 230 mA 7, 8, 10
Power Supply
Current: Idle
Device selected; VDD = MAX;
ADSC#, ADSP#, ADV#, GW#,
BWx# ³ VIH; All inputs £ VSS + 0.2
or ³ VDD - 0.2; Cycle time ³
tKC (MIN); Outputs open
IDD190 150 130 110 90 mA 7, 8, 10
CMOS Standby Device deselected; VDD = MAX;
All inputs £ VSS + 0.2 or
³ VDD - 0.2; All inputs static;
CLK frequency = 0
ISB2830303030mA8, 10
Clock Running Device deselected; VDD = MAX;
ADSC#, ADSP#, ADV#, GW#,
BWx# ³ VIH; All inputs £ VSS + 0.2
or ³ VDD - 0.2;
Cycle time ³ tKC (MIN)
ISB490 150 130 110 90 mA 8, 10
Snooze Mode ZZ ³ VIH ISB2Z 830303030mA 10
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 16 ©2003 Micron Technology, Inc.
Table 17: AC Electrical Characteristics and Recommended Operating Conditions
Note 11; notes appear following parameter tables on page 17; 0ºC £ TA £ +70ºC; TJ £ 95ºC (commercial); TJ £ 110ºC
(industrial); VDD = 3.3V ±0.165V unless otherwise noted
DESCRIPTION SYM
-5 -6 -7.5 -10
UNITS NOTESMIN MAX MIN MAX MIN MAX MIN MAX
Clock
Clock cycle time tKC 5.0 6.0 7.5 10 ns
Clock frequency fKF 200 166 133 100 MHz
Clock HIGH time tKH 2.0 2.3 2.5 3.0 ns 12
Clock LOW time tKL 2.0 2.3 2.5 3.0 ns 12
Output Times
Clock to output valid tKQ 3.1 3.5 4.0 5.0 ns
Clock to output invalid tKQX 1.0 1.5 1.5 1.5 ns 13
Clock to output in Low-Z tKQLZ 0 0 0 0 ns 6, 13, 14,
Clock to output in High-Z tKQHZ 3.1 3.5 4.2 5.0 ns 6, 13, 14
OE# to output valid tOEQ 3.1 3.5 4.0 5.0 ns 15
OE# to output in Low-Z tOELZ 0 0 0 0 ns 6, 13, 14
OE# to output in High-Z tOEHZ 3.0 3.0 3.5 4.5 ns 6, 13, 14
Setup Times
Address tAS 1.4 1.5 1.5 2.0 ns 16, 17
Address status
(ADSC#, ADSP#)
tADSS 1.4 1.5 1.5 2.0 ns 16, 17
Address advance (ADV#) tAAS 1.4 1.5 1.5 2.0 ns 16, 17
Write signals
(BWa#-BWd#, GW#, BWE#)
tWS 1.4 1.5 1.5 2.0 ns 16, 17
Data-in tDS 1.4 1.5 1.5 2.0 ns 16, 17
Chip enable (CE#) tCES 1.4 1.5 1.5 2.0 ns 16, 17
Hold Times
Address tAH 0.4 0.5 0.5 0.5 ns 16, 17
Address status (ADSC#, ADSP#) tADSH 0.4 0.5 0.5 0.5 ns 16, 17
Address advance (ADV#) tAAH 0.4 0.5 0.5 0.5 ns 16, 17
Write signals
(BWa#-BWd#, GW#, BWE#)
tWH 0.4 0.5 0.5 0.5 ns 16, 17
Data-in tDH 0.4 0.5 0.5 0.5 ns 16, 17
Chip enable (CE#) tCEH 0.4 0.5 0.5 0.5 ns 16, 17
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 17 ©2003 Micron Technology, Inc.
Notes
1. All voltages referenced to VSS (GND).
2. For 3.3V VDD:
Overshoot: VIH £ +4.6V for t £ tKC/2 for I £ 20mA
Undershoot: VIL ³ -0.7V for t £ tKC/2 for I £ 20mA
Power-up: VIH £ +3.6V and VDD £ 3.135V for t £
200ms
3. For 2.5V VDD:
Overshoot: VIH £ +3.6V for t £ tKC/2 for I £ 20mA
Undershoot:VIL ³ -0.5V for t £ tKC/2 for I £ 20mA
Power-up: VIH £ +2.65V and VDD £ 2.375V for t £
200ms
4. The MODE and ZZ pins/balls have an internal
pull-up/pull-down and input leakage = ±10µA.
5. VDDQ should never exceed VDD. VDD and VDDQ
can be connected together.
6. This parameter is sampled.
7. IDD is specified with no output current and
increases with faster cycle times. IDDQ increases
with faster cycle times and greater output loading.
8. “Device deselected” means device is in power-
down mode as defined in the truth table. “Device
selected” means device is active (not in power-
down mode).
9. Typical values are measured at 3.3V, 25ºC, and
10ns cycle time.
10. Typical values are measured at 2.5V, 25ºC, and
10ns cycle time.
11. Test conditions as specified with the output load-
ing shown in Figures 11 and 12 for 3.3V I/O and
Figures 13 and 14 for 2.5V I/O unless otherwise
noted.
12. Measured as HIGH above VIH and LOW below VIL.
13. This parameter is measured with the output load-
ing shown in Figure 12 for 3.3V I/O and Figure 14
for 2.5V I/O.
14. Refer to Technical Note TN-58-09, “Synchronous
SRAM Bus Contention Design Considerations,”
for a more thorough discussion of these parame-
ters.
15. OE# is a “Don’t Care” when a byte write enable is
sampled LOW.
16. A WRITE cycle is defined by at least one byte write
(BWa#–BWd#) being LOW, the byte write enable
(BWE#) active, and ADSC# LOW for the required
setup and hold times. A READ cycle is defined by
the byte write enable (BWE#) being HIGH or
ADSP# LOW for the required setup and hold
times.
17. This is a synchronous device. All addresses must
meet the specified setup and hold times when
either ADSC# or ADSP# is LOW and chip is
enabled. All other synchronous inputs must meet
the setup and hold times with stable logic levels
for all rising edges of CLK when the chip is
enabled. To remain enabled, chip enable must be
valid at each rising edge when either ADSC# or
ADSP# is LOW.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 18 ©2003 Micron Technology, Inc.
Figure 7:
READ Timing
NOTE:
1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following
A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause Q
to be driven until after the following clock rising edge. (This note applies to whole diagram.)
4. Outputs are disabled within two clock cycles after deselect.
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A1
tCEH
tCES
GW#, BWE#,
BWa#-BWd#
QHigh-Z
tKQLZ tKQX
tKQ
ADV#
tOEHZ
tKQ
Single READ BURST READ
tOEQ
tOELZ tKQHZ
Burst wraps around
to its initial state
tAAH
tAAS
tWH
tWS
tADSH
tADSS
Q(A2) Q(A2 + 1) Q(A2 + 2)
Q(A1) Q(A2) Q(A2 + 1) Q(A3)Q(A2 + 3)
A2 A3
(NOTE 1)
Deselect
cycle
(NOTE 3)
Burst continued with
new base address
(NOTE 4)
ADV# suspends burst
DON’T CARE UNDEFINED
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 19 ©2003 Micron Technology, Inc.
Figure 8:
WRITE Timing
NOTE:
1. D(A2) refers to output from address A2. D(A2 + 1) refers to output from the next internal burst address following
A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/
output data contention for the time period prior to the byte write enable inputs being sampled.
4. ADV# must be HIGH to permit a WRITE to the loaded address.
5. Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa#, and BWb# LOW for x18 device; or
GW# HIGH and BWE#, BWa#–BWd# LOW for x32 and x36 devices.
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A1
tCEH
tCES
BWE#,
BWa#-BWd#
Q
High-Z
ADV#
BURST READ BURST WRITE
D(A2) D(A2 + 1) D(A2 + 1) D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)
A2 A3
D
Extended BURST WRITE
D(A2 + 2)
Single WRITE
tADSH
tADSS
tADSH
tADSS
tOEHZ
tAAH
tAAS
tWH
tWS
tDH
tDS
(NOTE 3)
(NOTE 1)
(NOTE 4)
GW#
tWH
tWS
(NOTE 5)
Byte write signals are ignored for first cycle when
ADSP# initiates burst
ADSC# extends burst
ADV# suspends burst
DON’T CARE UNDEFINED
D(A1)
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 20 ©2003 Micron Technology, Inc.
Figure 9:
READ/WRITE Timing
NOTE:
1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following
A4.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC#, or ADV# cycle is performed.
(This note applies to whole diagram.)
4. GW# is HIGH.
5. Back-to-back READs may be controlled by either ADSP# or ADSC#.
6. This undefined READ will follow any WRITE cycle which is transitioned to a Read, Deselect, or Snooze.
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A2
tCEH
tCES
QHigh-Z
ADV#
Single WRITE
D(A3)
A4 A5 A6
D(A5) D(A6)
D
BURST READBack-to-Back READs
High-Z
Q(A2)Q(A1) Q(A4) Q(A4+1) Q(A4+2)
tWH
tWS
Q(A4+3)
tOEHZ
tDH
tDS
tOELZ
(NOTE 5)
(NOTE 1)
tKQLZ
tKQ
Back-to-Back
WRITEs
A1
BWE#,
BWa#-BWd#
(NOTE 4)
A3
DON’T CARE UNDEFINED
(NOTE 6)
(NOTE 3)
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 21 ©2003 Micron Technology, Inc.
SNOOZE MODE
SNOOZE MODE is a low-current, power-down
mode in which the device is deselected and current is
reduced to ISB2Z. The duration of SNOOZE MODE is
dictated by the length of time ZZ is in a HIGH state.
After the device enters SNOOZE MODE, all inputs
except ZZ become gated inputs and are ignored.
ZZ is an asynchronous, active HIGH input that
causes the device to enter SNOOZE MODE. When ZZ
becomes a logic HIGH, ISB2Z is guaranteed after the
setup time tZZ is met. Any READ or WRITE operation
pending when the device enters SNOOZE MODE is not
guaranteed to complete successfully. Therefore,
SNOOZE MODE must not be initiated until valid pend-
ing operations are completed.
NOTE:
1. This parameter is sampled.
Figure 10:
SNOOZE MODE Waveform
Table 18: SNOOZE MODE Electrical Characteristics
DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES
Current during SNOOZE MODE ZZ ³ VIH ISB2Z30 mA
ZZ active to input ignored tZZ 2(tKC) ns 1
ZZ inactive to input sampled tRZZ 2(tKC) ns 1
ZZ active to snooze current tZZI 2(tKC) ns 1
ZZ inactive to exit snooze current tRZZI 0ns1
tZZ
ISUPPLY
CLK
ZZ
tRZZ
ALL INPUTS
(except ZZ)
DON’T CARE
IISB2Z
tZZI
tRZZI
Outputs (Q) High-Z
DESELECT or READ Only
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 22 ©2003 Micron Technology, Inc.
3.3V VDD, 3.3V I/O AC Test Conditions
Input pulse levels ....................VIH = (VDD/2.2) + 1.5V
................................................... VIL = (VDD/2.2) - 1.5V
Input rise and fall times......................................... 1ns
Input timing reference levels ........................ VDD/2.2
Output reference levels................................VDDQ/2.2
Output load ..............................See Figures 11 and 12
3.3V VDD, 2.5V I/O AC Test Conditions
Input pulse levels ................VIH = (VDD/2.64) + 1.25V
............................................... VIL = (VDD/2.64) - 1.25V
Input rise and fall times......................................... 1ns
Input timing reference levels ...................... VDD/2.64
Output reference levels...................................VDDQ/2
Output load ..............................See Figures 13 and 14
3.3V I/O Output Load Equivalents
Figure 11:
Figure 12:
2.5V VDD, 2.5V I/O AC Test Conditions
Input pulse levels .................... VIH = (VDD/2) + 1.25V
....................................................VIL = (VDD/2) - 1.25V
Input rise and fall times......................................... 1ns
Input timing reference levels ........................... VDD/2
Output reference levels.................................. VDDQ/2
Output load...............................See Figures 13 and 14
2.5V I/O Output Load Equivalents
Figure 13:
Figure 14:
NOTE:
For Figures 11 and 13, 30pF = distributive test jig capacitance.
Q
VT = VDDQ/2.2
30pF
Z = 50Ω
O
50Ω
Q
351
317
5pF
+3.3V
Q
VT = VDDQ/2
30pF
Z = 50Ω
O
50Ω
Q
225Ω
225Ω
5pF
+2.5V
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 23 ©2003 Micron Technology, Inc.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The SRAM incorporates a serial boundary scan test
access port (TAP). This port operates in accordance
with IEEE Standard 1149.1-1990 but does not have the
set of functions required for full 1149.1 compliance.
These functions from the IEEE specification are
excluded because their inclusion places an added
delay in the critical speed path of the SRAM. Note that
the TAP controller functions in a manner that does not
conflict with the operation of other devices using
1149.1 fully compliant TAPs. The TAP operates using
JEDEC-standard 3.3V or 2.5V I/O logic levels.
The SRAM contains a TAP controller, instruction
register, boundary scan register, bypass register, and
ID register.
Disabling the JTAG Feature
These balls can be left floating (unconnected), if the
JTAG function is not to be implemented. Upon power-
up, the device will come up in a reset state which will
not interfere with the operation of the device.
Figure 15:
TAP Controller State Diagram
NOTE:
The 0/1 next to each state represents the value
of TMS at the rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller.
All inputs are captured on the rising edge of TCK. All
outputs are driven from the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP
controller and is sampled on the rising edge of TCK. It
is allowable to leave this ball unconnected if the TAP is
not used. The ball is pulled up internally, resulting in a
logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information
into the registers and can be connected to the input of
any of the registers. The register between TDI and TDO
is chosen by the instruction that is loaded into the TAP
instruction register. For information on loading the
instruction register, see Figure 15. TDI is internally
pulled up and can be unconnected if the TAP is unused
in an application. TDI is connected to the most signifi-
cant bit (MSB) of any register. (See Figure 16.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-
out from the registers. The output is active depending
upon the current state of the TAP state machine. (See
Figure 15.) The output changes on the falling edge of
TCK. TDO is connected to the least significant bit
(LSB) of any register. (See Figure 16.)
Figure 16:
TAP Controller Block Diagram
NOTE:
X = 74 for all configurations.
TEST-LOGIC
RESET
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
CAPTURE-DR
SHIFT-DR
CAPTURE-IR
SHIFT-IR
EXIT1-DR
PAUSE-DR
EXIT1-IR
PAUSE-IR
EXIT2-DR
UPDATE-DR
EXIT2-IR
UPDATE-IR
1
1
1
0
1 1
0 0
1 1
1
0
0
0
0 0
0
0
0 0
1
0
1
1
0
1
0
1
1
1
1 0
Bypass Register
0
Instruction Register
012
Identification Register
012293031 ...
Boundary Scan Register*
012..x ...
Selection
Circuitry
Selection
Circuitry
TCK
TMS TAP CONTROLLER
TDI TDO
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 24 ©2003 Micron Technology, Inc.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (VDD) for
five rising edges of TCK. This RESET does not affect the
operation of the SRAM and may be performed while
the SRAM is operating.
At power-up, the TAP is reset internally to ensure
that TDO comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO
balls and allow data to be scanned into and out of the
SRAM test circuitry. Only one register can be selected
at a time through the instruction register. Data is seri-
ally loaded into the TDI ball on the rising edge of TCK.
Data is output on the TDO ball on the falling edge of
TCK.
Instruction Register
Three-bit instructions can be serially loaded into
the instruction register. This register is loaded when it
is placed between the TDI and TDO balls as shown in
Figure 16. Upon power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded
with the IDCODE instruction if the controller is placed
in a reset state as described in the previous section.
When the TAP controller is in the Capture-IR state,
the two least significant bits are loaded with a binary
“01” pattern to allow for fault isolation of the board-
level serial test data path.
Bypass Register
To save time when serially shifting data through reg-
isters, it is sometimes advantageous to skip certain
chips. The bypass register is a single-bit register that
can be placed between the TDI and TDO balls. This
allows data to be shifted through the SRAM with mini-
mal delay. The bypass register is set LOW (Vss) when
the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the
input and bidirectional balls on the SRAM. The SRAM
has a 75-bit-long register.
The boundary scan register is loaded with the con-
tents of the RAM I/O ring when the TAP controller is in
the Capture-DR state and is then placed between the
TDI and TDO balls when the controller is moved to the
Shift-DR state. The EXTEST, SAMPLE/PRELOAD and
SAMPLE Z instructions can be used to capture the
contents of the I/O ring.
The Boundary Scan Order tables show the order in
which the bits are connected. Each bit corresponds to
one of the bumps on the SRAM package. The MSB of
the register is connected to TDI, and the LSB is con-
nected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-
bit code during the Capture-DR state when the
IDCODE command is loaded in the instruction regis-
ter. The IDCODE is hardwired into the SRAM and can
be shifted out when the TAP controller is in the Shift-
DR state. The ID register has a vendor code and other
information described in the Identification Register
Definitions table.
TAP Instruction Set
Overview
Eight different instructions are possible with the
three-bit instruction register. All combinations are
listed in the Instruction Codes table. Three of these
instructions are listed as RESERVED and should not be
used. The other five instructions are described in detail
below.
The TAP controller used in this SRAM is not fully
compliant to the 1149.1 convention because some of
the mandatory 1149.1 instructions are not fully imple-
mented. The TAP controller cannot be used to load
address, data or control signals into the SRAM and
cannot preload the I/O buffers. The SRAM does not
implement the 1149.1 commands EXTEST or INTEST
or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the I/O ring when these
instructions are executed.
Instructions are loaded into the TAP controller dur-
ing the Shift-IR state when the instruction register is
placed between TDI and TDO. During this state,
instructions are shifted through the instruction regis-
ter through the TDI and TDO balls. To execute the
instruction once it is shifted in, the TAP controller
needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is
to be executed whenever the instruction register is
loaded with all 0s. EXTEST is not implemented in this
SRAM TAP controller, and therefore this device is not
compliant to 1149.1.
The TAP controller does recognize an all-0 instruc-
tion. When an EXTEST instruction is loaded into the
instruction register, the SRAM responds as if a SAM-
PLE/PRELOAD instruction has been loaded. There is
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 25 ©2003 Micron Technology, Inc.
one difference between the two instructions. Unlike
the SAMPLE/PRELOAD instruction, EXTEST places
the SRAM outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific,
32-bit code to be loaded into the instruction register. It
also places the instruction register between the TDI
and TDO balls and allows the IDCODE to be shifted
out of the device when the TAP controller enters the
Shift-DR state. The IDCODE instruction is loaded into
the instruction register upon power-up or whenever
the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary
scan register to be connected between the TDI and
TDO balls when the TAP controller is in a Shift-DR
state. It also places all SRAM outputs into a High-Z
state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruc-
tion. The PRELOAD portion of this instruction is not
implemented, so the device TAP controller is not fully
1149.1-compliant.
When the SAMPLE/PRELOAD instruction is loaded
into the instruction register and the TAP controller is in
the Capture-DR state, a snapshot of data on the inputs
and bidirectional balls is captured in the boundary
scan register.
The user must be aware that the TAP controller
clock can only operate at a frequency up to 10 MHz,
while the SRAM clock operates more than an order of
magnitude faster. Because there is a large difference in
the clock frequencies, it is possible that during the
Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not
harm the device, but there is no guarantee as to the
value that will be captured. Repeatable results may not
be possible.
To guarantee that the boundary scan register will
capture the correct value of a signal, the SRAM signal
must be stabilized long enough to meet the TAP con-
troller’s capture setup plus hold time (tCS plus t
CH).
The SRAM clock input might not be captured correctly
if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and
simply ignore the value of the CLK captured in the
boundary scan register.
Once the data is captured, it is possible to shift out
the data by putting the TAP into the Shift-DR state.
This places the boundary scan register between the
TDI and TDO balls.
Note that since the PRELOAD part of the command
is not implemented, putting the TAP to the Update-DR
state while performing a SAMPLE/PRELOAD instruc-
tion will have the same effect as the Pause-DR com-
mand.
BYPASS
When the BYPASS instruction is loaded in the
instruction register and the TAP is placed in a Shift-DR
state, the bypass register is placed between the TDI
and TDO balls. The advantage of the BYPASS instruc-
tion is that it shortens the boundary scan path when
multiple devices are connected together on a board.
Reserved
These instructions are not implemented but are
reserved for future use. Do not use these instructions.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 26 ©2003 Micron Technology, Inc.
Figure 17:
TAP Timing
NOTE:
1. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
2. Test conditions are specified using the load in Figures 18 and 19.
tTLTH
Test Clock
(TCK)
123456
Test Mode Select
(TMS)
tTHTL
Test Data-Out
(TDO)
tTHTH
Test Data-In
(TDI)
tTHMX
tMVTH
tTHDX
tDVTH
tTLOX
tTLOV
DON’T CARE UNDEFINED
Table 19: TAP AC Electrical Characteristics
Notes 1, 2; 0ºC £ TA £ +70ºC; VDD = 3.3V ±0.165V or 2.5V ±0.125V
DESCRIPTION SYMBOL MIN MAX UNITS
Clock
Clock cycle time tTHTH 100 ns
Clock frequency fTF 10 MHz
Clock HIGH time tTHTL 40 ns
Clock LOW time tTLTH 40 ns
Output Times
TCK LOW to TDO unknown tTLOX 0ns
TCK LOW to TDO valid tTLOV 20 ns
TDI valid to TCK HIGH tDVTH 10 ns
TCK HIGH to TDI invalid tTHDX 10 ns
Setup Times
TMS setup tMVTH 10 ns
Capture setup tCS 10 ns
Hold Times
TMS hold tTHMX 10 ns
Capture hold tCH 10 ns
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 27 ©2003 Micron Technology, Inc.
3.3V TAP AC Test Conditions
Input pulse levels ........................................... VSS to 3.0V
Input rise and fall times ..............................................1ns
Input timing reference levels.................................... 1.5V
Output reference levels............................................. 1.5V
Test load termination supply voltage ...................... 1.5V
Figure 18:
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Test Conditions
Input pulse levels............................................ VSS to 2.5V
Input rise and fall times ............................................. 1ns
Input timing reference levels.................................. 1.25V
Output reference levels ........................................... 1.25V
Test load termination supply voltage .................... 1.25V
Figure 19:
2.5V TAP AC Output Load Equivalent
NOTE:
1. All voltages referenced to VSS (GND).
2. TAP control balls only. For boundary scan ball specifications, please refer to the I/O DC Electrical Characteristics and
Operation Conditions tables.
TDO
1.5V
20pF
Z = 50Ω
O
50Ω
TDO
1.25V
20pF
Z = 50Ω
O
50Ω
Table 20: 3.3V VDD, TAP DC Electrical Characteristics and Operating Conditions
0ºC £ TA £ +70ºC; VDD = 3.3V ±0.165V unless otherwise noted
DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES
Input High (Logic 1) Voltage VIH 2.0 VDD + 0.3 V 1, 2
Input Low (Logic 0) Voltage VIL -0.3 0.8 V 1, 2
Input Leakage Current 0V £ VIN £ VDD ILI-10 10 µA 2
Output Leakage Current Output(s) disabled,
0V £ VIN £ VDD (TDO)
ILO-10 10 µA 2
Output Low Voltage IOLC = 100µA VOL1 0.7 V 1, 2
IOLT = 2mA VOL2 0.8 V 1, 2
Output High Voltage IOHC = -100µA VOH1 2.9 V 1, 2
IOHT = -2mA VOH2 2.0 V 1, 2
Table 21: 2.5V VDD, TAP DC Electrical Characteristics and Operating Conditions
0ºC £ TA £ +70ºC; VDD = 2.5V ±0.125V unless otherwise noted
DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES
Input High (Logic 1) Voltage VIH 1.7 VDD + 0.3 V 1, 2
Input Low (Logic 0) Voltage VIL -0.3 0.7 V 1, 2
Input Leakage Current 0V £ VIN £ VDD ILI-10 10 µA 2
Output Leakage Current Output(s) disabled,
0V £ VIN £ VDD (TDO)
ILO-10 10 µA 2
Output Low Voltage IOLC = 100µA VOL1 0.2 V 1, 2
IOLT = 2mA VOL2 0.7 V 1, 2
Output High Voltage IOHC = -100µA VOH1 2.1 V 1, 2
IOHT = -2mA VOH2 1.7 V 1, 2
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 28 ©2003 Micron Technology, Inc.
Table 22: Identification Register Definitions
INSTRUCTION FIELD
BIT
CONFIGURATION DESCRIPTION
Revision Number
(31:28)
0000 Reserved for version number.
Device Depth
(27:23)
00111
00110
Defines depth of 1Mb.
Degines depth of 512K.
Device Width
(22:18)
00011
00100
Defines width of x18 bits.
Defines width of x32 or x36 bits.
Micron Device ID
(17:12)
xxxxxx Reserved for future use.
Micron JEDEC ID Code
(11:1)
00000101100 Allows unique identification of SRAM vendor.
ID Register Presence
Indicator (0)
1Indicates the presence of an ID register.
Table 23: Scan Register Sizes
REGISTER NAME BIT SIZE
Instruction 3
Bypass 1
ID 32
Boundary Scan: x18, x32, x36 75
Table 24: Instruction Codes
INSTRUCTION CODE DESCRIPTION
EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1-compliant.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 29 ©2003 Micron Technology, Inc.
Table 25: 165-Ball FBGA Boundary Scan Order (x18)
BIT# SIGNAL NAME BALL ID BIT# SIGNAL NAME BALL ID
1 MODE (LB0#) 1R 39 CLK 6B
2SA 6N 40 NC 11B
3SA 11P 41 NC 1A
4SA 8R 42 CE2# 6A
5SA 8P 43 BWa# 5B
6SA 9R 44 NC 5A
7SA 9P 45 BWb# 4A
8SA 10R 46 NC 4B
9SA 10P 47 CE2 3B
10 SA 11R 48 CE# 3A
11 ZZ 11H 49 SA 2A
12 NC 11N 50 SA 2B
13 NC 11M 51 NC 1B
14 NC 11L 52 NC 1C
15 NC 11K 53 NC 1D
16 NC 11J 54 NC 1E
17 DQa 10M 55 NC 1F
18 DQa 10L 56 NC 1G
19 DQa 10K 57 DQb 2D
20 DQa 10J 58 DQb 2E
21 DQa 11G 59 DQb 2F
22 DQa 11F 60 DQb 2G
23 DQa 11E 61 DQb 1J
24 DQa 11D 62 DQb 1K
25 DQPa 11C 63 DQb 1L
26 NC 10F 64 DQb 1M
27 NC 10E 65 DQPb 1N
28 NC 10D 66 NC 2K
29 NC 10G 67 NC 2L
30 SA 11A 68 NC 2M
31 SA 10B 69 NC 2J
32 SA 10A 70 SA 3P
33 ADV# 9A 71 SA 3R
34 ADSP# 9B 72 SA 4P
35 ADSC# 8A 73 SA 4R
36 OE# (G#) 8B 74 SA1 6P
37 BWE# 7A 75 SA0 6R
38 GW# 7B
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 30 ©2003 Micron Technology, Inc.
Table 26: 165-Ball FBGA Boundary Scan Order (x32)
BIT# SIGNAL NAME BALL ID BIT# SIGNAL NAME BALL ID
1 MODE (LB0#) 1R 39 CLK 6B
2SA 6N 40 NC 11B
3SA 11P 41 NC 1A
4SA 8R 42 CE2# 6A
5SA 8P 43 BWa# 5B
6SA 9R 44 BWb# 5A
7SA 9P 45 BWc# 4A
8SA 10R 46 BWd# 4B
9SA 10P 47 CE2 3B
10 SA 11R 48 CE# 3A
11 ZZ 11H 49 SA 2A
12 NF 11N 50 SA 2B
13 DQa 11M 51 NC 1B
14 DQa 11L 52 NF 1C
15 DQa 11K 53 DQc 1D
16 DQa 11J 54 DQc 1E
17 DQa 10M 55 DQc 1F
18 DQa 10L 56 DQc 1G
19 DQa 10K 57 DQc 2D
20 DQa 10J 58 DQc 2E
21 DQb 11G 59 DQc 2F
22 DQb 11F 60 DQc 2G
23 DQb 11E 61 DQd 1J
24 DQb 11D 62 DQd 1K
25 DQb 10G 63 DQd 1L
26 DQb 10F 64 DQd 1M
27 DQb 10E 65 DQd 2J
28 DQb 10D 66 DQd 2K
29 NF 11C 67 DQd 2L
30 NC 11A 68 DQd 2M
31 SA 10B 69 NF 1N
32 SA 10A 70 SA 3P
33 ADV# 9A 71 SA 3R
34 ADSP# 9B 72 SA 4P
35 ADSC# 8A 73 SA 4R
36 OE# (G#) 8B 74 SA1 6P
37 BWE# 7A 75 SA0 6R
38 GW# 7B
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 31 ©2003 Micron Technology, Inc.
Table 27: 165-Ball FBGA Boundary Scan Order (x36)
BIT# SIGNAL NAME BALL ID BIT# SIGNAL NAME BALL ID
1 MODE (LB0#) 1R 39 CLK 6B
2SA 6N 40 NC 11B
3SA 11P 41 NC 1A
4SA 8R 42 CE2# 6A
5SA 8P 43 BWa# 5B
6SA 9R 44 BWb# 5A
7SA 9P 45 BWc# 4A
8SA 10R 46 BWd# 4B
9SA 10P 47 CE2 3B
10 SA 11R 48 CE# 3A
11 ZZ 11H 49 SA 2A
12 DQPa 11N 50 SA 2B
13 DQa 11M 51 NC 1B
14 DQa 11L 52 DQPc 1C
15 DQa 11K 53 DQc 1D
16 DQa 11J 54 DQc 1E
17 DQa 10M 55 DQc 1F
18 DQa 10L 56 DQc 1G
19 DQa 10K 57 DQc 2D
20 DQa 10J 58 DQc 2E
21 DQb 11G 59 DQc 2F
22 DQb 11F 60 DQc 2G
23 DQb 11E 61 DQd 1J
24 DQb 11D 62 DQd 1K
25 DQb 10G 63 DQd 1L
26 DQb 10F 64 DQd 1M
27 DQb 10E 65 DQd 2J
28 DQb 10D 66 DQd 2K
29 DQPb 11C 67 DQd 2L
30 NC 11A 68 DQd 2M
31 SA 10B 69 DQPd 1N
32 SA 10A 70 SA 3P
33 ADV# 9A 71 SA 3R
34 ADSP# 9B 72 SA 4P
35 ADSC# 8A 73 SA 4R
36 OE# (G#) 8B 74 SA1 6P
37 BWE# 7A 75 SA0 6R
38 GW# 7B
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 32 ©2003 Micron Technology, Inc.
Figure 20:
100-Pin Plastic TQFP (JEDEC LQFP)
NOTE:
1. All dimensions in millimeters or typical where noted.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
14.00 ±0.10
1.40 ±0.05
16.00 ±0.20
0.10 +0.10
-0.05
0.15 +0.03
-0.02
22.10 +0.10
-0.20
0.32 +0.06
-0.10
20.10 ±0.10
0.65 TYP
0.625
1.60 MAX
DETAIL A
SEE DETAIL A
0.60 ±0.15
1.00 TYP
GAGE PLANE
0.25
0.10
PIN #1 ID
MAX
MIN
--------------
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo, and SyncBurst are trademarks and/or service marks of Micron Technology, Inc.
Pentium is a registered trademark of Intel Corporation.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 33 ©2003 Micron Technology, Inc.
Figure 21:
165-Ball FBGA
NOTE:
1. All dimensions in millimeters or typical where noted.
Data Sheet Designation
No Marking: This data sheet contains minimum and maximum limits specified over the complete power
supply and temperature range for production devices. Although considered final, these specifications are sub-
ject to change, as further product development and data characterization sometimes occur.
10.00
14.00
15.00 ±0.10
1.00
TYP
1.00
TYP
5.00 ±0.05
13.00 ±0.10
PIN A1 ID
PIN A1 ID
BALL A1
MOLD COMPOUND: EPOXY NOVOLAC
SUBSTRATE: PLASTIC LAMINATE
6.50 ±0.05
7.00 ±0.05
7.50 ±0.05
1.20 MAX
SOLDER BALL MATERIAL: EUTECTIC 62% Sn, 36% Pb, 2% Ag
SOLDER BALL PAD: Ø .33mm
SOLDER BALL DIAMETER REFERS
TO POST REFLOW CONDITION. THE
PRE-REFLOW DIAMETER IS Ø 0.40
SEATING PLANE
0.85 ±0.075
0.12 C
C
165X Ø 0.45
BALL A11
MAX
MIN
--------------
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03 34 ©2003 Micron Technology, Inc.
Document Revision History
• Rev D; Pub. 2/03..........................................................................................................................................................2/03
Changed designation from Preliminary to Production
• Rev C; Pub. 12/02 ......................................................................................................................................................12/02
Added TJ specifications to the AC Electrical Characteristics table
Corrected Boundary Scan errors
Updated TQFP and FBGA Thermal Resistance values
Corrected grammatical errors
• Rev B; Pub. 11/02 ......................................................................................................................................................11/02
Changed designation from ADVANCE to PRELIMINARY
Corrected grammatical errors
• New ADVANCE data sheet for 0.16µm process; Rev. A, Pub. 6 /02 .........................................................................6/02
