18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM 18Mb SYNCBURSTTM SRAM MT58L1MY18D, MT58V1MV18D, MT58L512Y32D, MT58V512V32D, MT58L512Y36D, MT58V512V36D 3.3V VDD, 3.3V or 2.5V I/O; 2.5V VDD, 2.5V I/O Features * Fast clock and OE# access times * Single 3.3V 5 percent or 2.5V 5 percent power supply * Separate 3.3V 5 percent or 2.5V 5 percent isolated output buffer supply (VDDQ) * SNOOZE MODE for reduced-power standby * Common data inputs and data outputs * Individual byte write control and global write * Three chip enables for simple depth expansion and address pipelining * Clock-controlled and registered addresses, data I/Os, and control signals * Internally self-timed WRITE cycle * Burst control (interleaved or linear burst) * Low capacitive bus loading Figure 1: 100-Pin TQFP JEDEC-Standard MS-026 BHA (LQFP) TQFP Marking Options * Timing (Access/Cycle/MHz) 3.1ns/5ns/200 MHz 3.5ns/6ns/166 MHz 4.2ns/7.5ns/133 MHz 5ns/10ns/100 MHz * Configurations 3.3V VDD, 3.3V or 2.5V I/O 1 Meg x 18 512K x 32 512K x 36 2.5V VDD, 2.5V I/O 1 Meg x 18 512K x 32 512K x 36 * Packages 100-pin TQFP 165-ball, 13mm x 15mm FBGA * Operating Temperature Range Commercial (0C TA +70C Industrial (-40C TA +85C) Figure 2: 165-Ball FBGA JEDEC-Standard MO-216 (Var. CAB-1) -5 -6 -7.5 -10 MT58L1MY18D MT58L512Y32D MT58L512Y36D MT58V1MV18D MT58V512V32D MT58V512V36D Part Number Example: MT58L512Y36DT-10 T F1 General Description The Micron(R) SyncBurstTM SRAM family employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process. Micron's 18Mb SyncBurst SRAMs integrate a 1 Meg x 18, 512K x 32, or 512K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable None IT2 NOTE: 1. A Part Marking Guide for the FBGA devices can be found on Micron's Web site--http://www.micron.com/numberguide. 2. Contact factory for availability of Industrial Temperature devices. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 1 (c)2003 Micron Technology, Inc. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM (CE#), two additional chip enables for easy depth expansion (CE2, CE2#), burst control inputs (ADSC#, ADSP#, ADV#), byte write enables (BWx#), and global write (GW#). Asynchronous inputs include the output enable (OE#), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. The data out (Q) is enabled by OE#. WRITE cycles can be from one to two bytes wide (x18) or from one to four bytes wide (x32/ x36), as controlled by the write control inputs. Burst operation can be initiated with either address status processor (ADSP#) or address status controller (ADSC#) inputs. Subsequent burst addresses can be internally generated as controlled by the burst advance input (ADV#). Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed write cycles. Individual byte enables allow individual bytes to be written. During WRITE cycles on the x18 device, BWa# controls DQa pins/balls and DQPa; BWb# controls DQb pins/balls and DQPb. During WRITE cycles on the x32 and x36 devices, BWa# controls DQa pins/ 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 balls and DQPa; BWb# controls DQb pins/balls and DQPb; BWc# controls DQc pins/balls and DQPc; BWd# controls DQd pins/balls and DQPd. GW# LOW causes all bytes to be written. Parity bits are only available on the x18 and x36 versions. This device incorporates an additional pipelined enable register which delays turning off the output buffer an additional cycle when a deselect is executed. This feature allows depth expansion without penalizing system performance. The device is ideally suited for Pentium(R) and PowerPC pipelined systems and systems that benefit from a very wide, high-speed data bus. The device is also ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bitwide applications. Please refer to Micron's Web site (www.micron.com/ sramds) for the latest data sheet. Dual Voltage I/O The 3.3V VDD device is tested for 3.3V and 2.5V I/O function. The 2.5V VDD device is tested for only 2.5V I/O function. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM Figure 3: Functional Block Diagram 1 Meg x 18 20 SA0, SA1, SAs 18 20 ADDRESS REGISTER 2 MODE SA0-SA1 SA1' BINARY Q1 COUNTER AND LOGIC CLR Q0 ADV# CLK 20 SA0' ADSC# ADSP# BYTE "b" WRITE REGISTER BWb# 9 9 BYTE "a" WRITE REGISTER BWa# BYTE "b" WRITE DRIVER BYTE "a" WRITE DRIVER 9 1 Meg x 9 x 2 MEMORY ARRAY 18 SENSE AMPS 18 OUTPUT 18 REGISTERS OUTPUT BUFFERS 18 E 9 DQs DQPa DQPb BWE# GW# INPUT REGISTERS 18 ENABLE REGISTER CE# CE2 CE2# PIPELINED ENABLE 2 OE# Figure 4: Functional Block Diagram 512K x 32/36 19 SA0, SA1, SAs ADDRESS REGISTER 17 19 19 SA0-SA1 MODE SA1' Q1 BINARY COUNTER SA0' CLR Q0 ADV# CLK ADSC# ADSP# BWd# BYTE "d" WRITE REGISTER 9 BYTE "d" WRITE DRIVER 9 BWc# BYTE "c" WRITE REGISTER 9 BYTE "c" WRITE DRIVER 9 BWb# BWa# BWE# GW# CE# CE2 CE2# OE# 512K x 9 x 4 (x36) BYTE "b" WRITE REGISTER 9 BYTE "b" WRITE DRIVER 9 BYTE "a" WRITE REGISTER 9 BYTE "a" WRITE DRIVER 9 ENABLE REGISTER 512K x 8 x 4 (x32) 36 SENSE AMPS 36 OUTPUT REGISTERS 36 MEMORY ARRAY 36 PIPELINED ENABLE OUTPUT BUFFERS E 36 DQs DQPa DQPb DQPc DQPd INPUT REGISTERS 4 NOTE: Functional block diagrams illustrate simplified device operation. See truth tables, pin/ball description, and timing diagrams for detailed information. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM SA NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC Figure 5: Pin Layout (Top View) 100-Pin TQFP SA SA ADV# ADSP# ADSC# OE# (G#) BWE# GW# CLK VSS VDD CE2# BWa# BWb# NC NC CE2 CE# SA SA 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SA SA ADV# ADSP# ADSC# OE# (G#) BWE# GW# CLK VSS VDD CE2# BWa# BWb# BWc# BWd# CE2 CE# SA SA 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NF/DQPb1 DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa NF/DQPa1 NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC x18 SA SA SA SA SA SA SA SA SA VDD VSS DNU2 DNU2 SA0 SA1 SA SA SA SA MODE (LBO#) NF/DQPc1 DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd NF/DQPd1 x32/x36 SA SA SA SA SA SA SA SA SA VDD VSS DNU2 DNU2 SA0 SA1 SA SA SA SA MODE (LBO#) NOTE: 1. No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version. 2. Pins 39 and 38 are reserved for address expansion; 36Mb and 72Mb, respectively. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM Table 1: TQFP Pin Descriptions SYMBOL TYPE DESCRIPTION ADSC# Input ADSP# Input ADV# Input BWa# BWb# BWc# BWd# Input BWE# Input CE# Input CE2# Input CE2 Input CLK Input GW# Input MODE (LBO#) Input OE# (G#) Input SA0 SA1 SA ZZ Input Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ or WRITE is performed using the new address if CE# is LOW. ADSC# is also used to place the chip into power-down state when CE# is HIGH. Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ is performed using the new address, independent of the byte write enables and ADSC#, but dependent upon CE#, CE2, and CE2#. ADSP# is ignored if CE# is HIGH. Power-down state is entered if CE2 is LOW or CE2# is HIGH. Synchronous Address Advance: This active LOW input is used to advance the internal burst counter, controlling burst access after the external address is loaded. A HIGH on this pin effectively causes wait states to be generated (no address advance). To ensure use of correct address during a WRITE cycle, ADV# must be HIGH at the rising edge of the first clock after an ADSP# cycle is initiated. Synchronous Byte Write: These active LOW inputs allow individual bytes to be written when a WRITE cycle is active and must meet the setup and hold times around the rising edge of CLK. BWs need to be asserted on the same cycle as the address. To enable the BW's functionality, the byte write enable (BWE#) input must be asserted LOW. BWa# controls DQa pins; BWb# controls DQb pins; BWc# controls DQc pins; and BWd# controls DQa pins. Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the internal use of ADSP#. CE# is sampled only when a new external address is loaded. Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded. Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded. Clock: This signal registers the address, data, chip enable, byte write enables, and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. Global Write: This active LOW input allows a full 18-, 32-, or 36-bit WRITE to occur independent of the BWE# and BWx# lines and must meet the setup and hold times around the rising edge of CLK. Mode: This input selects the burst sequence. A LOW on this pin selects "linear burst." NC or HIGH on this pin selects "interleaved burst." Do not alter input state while device is operating. LBO# is the JEDEC-standard term for MODE. Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. G# is the JEDEC-standard term for OE#. Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. DQa DQb DQc DQd Input Input/ Output Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored. This pin has an internal pull-down and can be left unconnected. SRAM Data I/Os: For the x18 version, byte "a" is associated with DQa pins; byte "b" is associated with DQb pins. For the x32 and x36 versions, byte "a" is associated with DQa pins; byte "b" is associated with DQb pins; byte "c" is associated with DQc pins; byte "d" is associated with DQd pins. Input data must meet setup and hold times around the rising edge of CLK. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM Table 1: TQFP Pin Descriptions (continued) SYMBOL TYPE DESCRIPTION NF/DQPa NF/DQPb NF/DQPc NF/DQPd VDD VDDQ NF I/O No Function/Parity Data I/Os: On the x32 version, these pins are No Function (NF). On the x18 version, byte "a" parity is DQPa; byte "b" parity is DQPb. On the x36 version, byte "a" parity is DQPa; byte "b" parity is DQPb; byte "c" parity is DQPc; byte "d" parity is DQPd. Supply Supply VSS DNU Supply - NC - NF - Power Supply: See DC Electrical Characteristics and Operating Conditions for range. Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range. Ground: GND. Do Not Use: These pins are internally connected to the die. They may be left floating or connected to ground to improve package heat dissipation. No Connect: These pins are not internally connected to the die. They may be left floating, driven by signals, or connected to ground to improve package heat dissipation. No Function: These pins are internally connected to the die and have the capacitance of an input pin. They may be left floating, driven by signals, or connected to ground to improve package heat dissipation. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM Figure 6: Ball Layout (Top View) 165-Ball FBGA x18 x32/x36 10 11 BWE# ADSC# ADV# SA SA GW# OE# (G#) ADSP# SA NC VSS VSS VDDQ NC DQPa VSS VSS VDD VDDQ NC DQa VSS VSS VSS VDD VDDQ NC DQa VDD VSS VSS VSS VDD VDDQ NC DQa VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa VSS NC VDD VSS VSS VSS VDD NC NC ZZ DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQPb NC VDDQ VSS NC SA VSS VSS VDDQ NC NC NC NC2 SA SA TDI SA1 TD0 SA SA SA SA MODE (LBO#) NC2 SA SA TMS SA0 TCK SA SA SA SA 1 2 3 4 5 6 NC SA CE# BWb# NC CE2# NC SA CE2 NC BWa# CLK NC NC VDDQ VSS VSS VSS NC DQb VDDQ VDD VSS NC DQb VDDQ VDD NC DQb VDDQ NC DQb VDD 7 8 9 A A B VSS VSS VDD VDDQ DQb DQb VSS VSS VSS VDD VDDQ DQb DQb VDD VSS VSS VSS VDD VDDQ DQb DQb VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb VSS NC VDD VSS VSS VSS VDD NC NC ZZ DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa NF/DQPd1 NC VDDQ VSS NC SA VSS VSS VDDQ NC NF/DQPa1 NC NC2 SA SA TDI SA1 TD0 SA SA SA SA MODE (LBO#) NC2 SA SA TMS SA0 TCK SA SA SA SA CE2 BWd# BWa# CLK NF/DQPc1 NC VDDQ VSS VSS VSS DQc DQc VDDQ VDD VSS DQc DQc VDDQ VDD DQc DQc VDDQ DQc DQc VDD B C D E F G H J K L M N P R NF/DQPb1 SA M N P NC NC A L M N VDDQ CE2# K L M VSS BWc# BWb# J K L VSS CE# 9 H J K NC SA 8 G H J SA NC 7 F G H GW# OE# (G#) ADSP# 6 E F G NC 5 D E F SA 4 C D E BWE# ADSC# ADV# 3 B C D 11 2 A B C 10 1 N P R P R R TOP VIEW TOP VIEW NOTE: 1. No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version. 2. Balls 2P and 2R are reserved for address expansion; 36Mb and 72Mb, respectively. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM Table 2: FBGA Ball Descriptions SYMBOL TYPE DESCRIPTION ADSC# Input ADSP# Input ADV# Input BWa# BWb# BWc# BWd# Input BWE# Input CE# Input CE2# Input CE2 Input CLK Input GW# Input MODE (LB0#) Input OE# (G#) Input SA0 SA1 SA TMS TDI TCK ZZ Input Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ or WRITE is performed using the new address if CE# is LOW. ADSC# is also used to place the chip into power-down state when CE# is HIGH. Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ is performed using the new address, independent of the byte write enables and ADSC#, but dependent upon CE#, CE2, and CE2#. ADSP# is ignored if CE# is HIGH. Power-down state is entered if CE2 is LOW or CE2# is HIGH. Synchronous Address Advance: This active LOW input is used to advance the internal burst counter, controlling burst access after the external address is loaded. A HIGH on ADV# effectively causes wait states to be generated (no address advance). To ensure use of correct address during a WRITE cycle, ADV# must be HIGH at the rising edge of the first clock after an ADSP# cycle is initiated. Synchronous Byte Write: These active LOW inputs allow individual bytes to be written when a WRITE cycle is active and must meet the setup and hold times around the rising edge of CLK. BWs need to be asserted on the same cycle as the address. To enable the BW's functionality, the byte write enable (BWE#) input must be asserted LOW. BWa# controls DQa balls; BWb# controls DQb balls; BWc# controls DQc balls; and BWd# controls DQa balls. Byte Write Enable: This active LOW input permits byte write operations and must meet the setup and hold times around the rising edge of CLK. Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the internal use of ADSP#. CE# is sampled only when a new external address is loaded. Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded. Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded. Clock: This signal registers the address, data, chip enable, byte write enables, and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. Global Write: This active LOW input allows a full 18-, 32-, or 36-bit WRITE to occur independent of the BWE# and BWx# lines and must meet the setup and hold times around the rising edge of CLK. Mode: This input selects the burst sequence. A low on this ball selects "linear burst." NC or HIGH on this input selects "interleaved burst." Do not alter input state while device is operating. LBO# is the JEDEC-standard term for MODE. Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. G# is the JEDEC-standard term for OE#. Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. DQa DQb DQc DQd Input IEEE 1149.1 Test Inputs: JEDEC-standard 3.3V and 2.5V I/O levels. These balls may be left as No Connects if the JTAG function is not used in the circuit. Input Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored. This ball has an internal pull-down and can be left unconnected. SRAM Data I/Os: For the x18 version, byte "a" is associated DQa balls; byte "b" is associated with DQb balls. For the x32 and x36 versions, byte "a" is associated with DQa balls; byte "b" is associated with DQbs; byte "c" is associated with DQc balls; byte "d" is associated with DQd balls. Input data must meet setup and hold times around the rising edge of CLK. Input/ Output 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM Table 2: FBGA Ball Descriptions (continued) SYMBOL TYPE DESCRIPTION NF/DQPa NF/DQPb NF/DQPc NF/DQPd TDO VDD VDDQ NF I/O No Function/Parity Data I/Os: On the x32 version, these are No Function (NF). On the x18 version, byte "a" parity is DQPa; byte "b" parity is DQPb. On the x36 version, byte "a" parity is DQPa; byte "b" parity is DQPb; byte "c" parity is DQPc; byte "d" parity is DQPd. Output Supply Supply VSS NC Supply - NF - IEEE 1149.1 Test Output: JEDEC-standard 3.3V and 2.5V I/O levels. Power Supply: See DC Electrical Characteristics and Operating Conditions for range. Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range. Ground: GND. No Connect: These balls are not internally connected to the die. They may be left floating, driven by signals, or connected to ground to improve package heat dissipation. No Function: These balls are internally connected to the die and have the capacitance of an input pin. They may be left floating, driven by signals, or connected to ground to improve package heat dissipation. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM Table 3: Interleaved Burst Address Table (Mode = NC or HIGH) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 X...X01 X...X00 X...X11 X...X10 X...X10 X...X11 X...X00 X...X01 X...X11 X...X10 X...X01 X...X00 Table 4: Linear Burst Address Table (Mode = LOW) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 X...X01 X...X10 X...X11 X...X00 X...X10 X...X11 X...X00 X...X01 X...X11 X...X00 X...X01 X...X10 Table 5: Partial Truth Table for WRITE Commands (x18) FUNCTION READ READ WRITE Byte "a" WRITE Byte "b" WRITE All Bytes WRITE All Bytes GW# BWE# BWa# BWb# H H H H H L H L L L L X X H L H L X X H H L L X NOTE: Using BWE# and BWa# through BWd#, any one or more bytes may be written. Table 6: Partial Truth Table for WRITE Commands (x32/x36) FUNCTION READ READ WRITE Byte "a" WRITE All Bytes WRITE All Bytes GW# BWE# BWa# BWb# BWc# BWd# H H H H L H L L L X X H L L X X H H L X X H H L X X H H L X NOTE: Using BWE# and BWa# through BWd#, any one or more bytes may be written. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM Table 7: Truth Table Notes 1-8 OPERATION DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down SNOOZE MODE, Power-Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst ADDRESS USED CE# CE2# CE2 ZZ ADSP# ADSC# ADV# WRITE# OE# CLK DQ None H X X L X L X X X L-H High-Z None L X L L L X X X X L-H High-Z None L H X L L X X X X L-H High-Z None L X L L H L X X X L-H High-Z None L H X L H L X X X L-H High-Z None X X X H X X X X X X High-Z External External External External External Next Next Next Next Next L L L L L X X H H X L L L L L X X X X X H H H H H X X X X X L L L L L L L L L L L L H H H H H X X H X X L L L H H H H H X X X X X L L L L L X X L H H H H H H L L H X L H L H L H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H Q High-Z D Q High-Z Q High-Z Q High-Z D Next H X X L X H L L X L-H D Current Current Current Current Current Current X X H H X H X X X X X X X X X X X X L L L L L L H H X X H X H H H H H H H H H H H H H H H H L L L H L H X X L-H L-H L-H L-H L-H L-H Q High-Z Q High-Z D D NOTE: 1. X means "Don't Care." # means active LOW. H means logic HIGH. L means logic LOW. 2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc#, or BWd#), and BWE# are LOW or GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH. 3. BWa# enables writes to DQa pins/balls and DQPa. BWb# enables writes to DQb pins/balls and DQPb. BWc# enables writes to DQc pins/balls and DQPc. BWd# enables writes to DQd pins/balls and DQPd. DQPa and DQPb are only available on the x18 and x36 versions. DQPc and DQPd are only available on the x36 version. 4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held HIGH throughout the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM Absolute Maximum Ratings 3.3V VDD Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Maximum Junction Temperature depends upon package type, cycle time, loading, ambient temperature, and airflow. Voltage on VDD Supply Relative to VSS ....................................... -0.5V to +4.6V Voltage on VDDQ Supply Relative to VSS ....................................... -0.5V to +4.6V VIN (DQx) ....................................... -0.5V to VDDQ + 0.5V VIN (inputs) ....................................... -0.5V to VDD + 0.5V Storage Temperature (TQFP).................-55C to +150C Storage Temperature (FBGA).................-55C to +125C Junction Temperature .......................................... +150C Short Circuit Output Current ...............................100mA 2.5V VDD Voltage on VDD Supply Relative to VSS ....................................... -0.3V to +3.6V Voltage on VDDQ Supply Relative to VSS ....................................... -0.3V to +3.6V VIN (DQx) ....................................... -0.3V to VDDQ + 0.3V VIN (inputs) ....................................... -0.3V to VDD + 0.3V Storage Temperature (TQFP).................-55C to +150C Storage Temperature (FBGA).................-55C to +125C Junction Temperature .......................................... +150C Short Circuit Output Current ...............................100mA Table 8: 3.3V VDD, 3.3V I/O DC Electrical Characteristics and Operating Conditions Notes appear following parameter tables on page 17; 0C TA +70C; VDD and VDDQ = 3.3V 0.165V unless otherwise noted DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage Isolated Output Buffer Supply 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 CONDITIONS SYMBOL MIN MAX UNITS NOTES VIH VIL ILI ILO 2.0 -0.3 -1.0 -1.0 VDD + 0.3 0.8 1.0 1.0 V V A A 1, 2 1, 2 4 VOH VOL VDD VDDQ 2.4 - 3.135 3.135 - 0.4 3.465 VDD V V V V 1 1 1 1, 5 0V VIN VDD Output(s) disabled, 0V VIN VDD IOH = -4.0mA IOL = 8.0mA 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM Table 9: 3.3V VDD, 2.5V I/O DC Electrical Characteristics and Operating Conditions Notes appear following parameter tables on page 17; 0C TA +70C; VDD = 3.3V 0.165V and VDDQ = 2.5V 0.125V unless otherwise noted DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage CONDITIONS SYMBOL MIN MAX UNITS NOTES Data bus (DQx) Inputs VIHQ VIH VIL ILI ILO 1.7 1.7 -0.3 -1.0 -1.0 VDDQ + 0.3 VDD + 0.3 0.7 1.0 1.0 V V V A A 1, 2 1, 2 1, 2 4 VOH VOH VOL VOL VDD VDDQ 1.7 2.0 - - 3.135 2.375 - - 0.7 0.4 3.465 2.625 V V V V V V 1 1 1 1 1 1, 5 0V VIN VDD Output(s) disabled, 0V VIN VDDQ (DQx) IOH = -2.0mA IOH = -1.0mA IOL = 2.0mA IOL = 1.0mA Supply Voltage Isolated Output Buffer Supply Table 10: 2.5V VDD, 2.5V I/O DC Electrical Characteristics and Operating Conditions Notes appear following parameter tables on page 17; 0C TA +70C; VDD and VDDQ = 2.5V 0.125V unless otherwise noted DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage CONDITIONS SYMBOL MIN MAX UNITS NOTES Data bus (DQx) Inputs VIHQ VIH VIL ILI ILO 1.7 1.7 -0.3 -1.0 -1.0 VDDQ + 0.3 VDD + 0.3 0.7 1.0 1.0 V V V A A 1, 3 1, 3 1, 3 4 VOL VOH VOL VOL VDD VDDQ 1.7 2.0 - - 2.375 2.375 - - 0.7 0.4 2.625 2.625 V V V V V V 1 1 1 1 1 1, 5 0V VIN VDD Output(s) disabled, 0V VIN VDDQ (DQx) IOL = 2.0mA IOH = -1.0mA IOL = 2.0mA IOL = 1.0mA Supply Voltage Isolated Output Buffer Supply 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM Table 11: TQFP Capacitance Note 6; notes appear following parameter tables on page 17 DESCRIPTION Control Input Capacitance Input/Output Capacitance (DQ) Address Input Capacitance Clock Capacitance CONDITIONS SYMBOL TYP MAX UNITS TA = 25C; f = 1 MHz; VDD = 3.3V CI CO CA CCK 4.2 3.5 4 4.2 5 4 5 5 pF pF pF pF CONDITIONS SYMBOL TYP MAX UNITS TA = 25C; f = 1 MHz; VDD = 3.3V CI CO CA CCK 4 4 4 5 5 4.5 5 5.5 pF pF pF pF Table 12: FBGA Capacitance Note 6; notes appear following parameter tables on page 17 DESCRIPTION Control Input Capacitance Input/Output Capacitance (DQ) Address Input Capacitance Clock Capacitance Table 13: TQFP Thermal Resistance Note 6; notes appear following parameter tables on page 17 DESCRIPTION Junction to Ambient (Airflow of 1m/s, two-layer board) Thermal Resistance Junction to Case (Top) CONDITIONS SYMBOL TYP UNITS Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. qJA 28.9 C/W qJC 4.2 C/W SYMBOL TYP UNITS qJA 32 C/W qJC 1.7 C/W qJB 10.4 C/W Table 14: FBGA Thermal Resistance Note 6; notes appear following parameter tables on page 17 DESCRIPTION Junction to Ambient (Airflow of 1m/s, two-layer board) Junction to Case (Top) Junction to Board (Bottom) 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 CONDITIONS Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM Table 15: 3.3V VDD, IDD Operating Conditions and Maximum Limits (1 Meg x 18 and 512K x 36) Notes appear following parameter tables on page 17; 0C TA +70C; VDD and VDDQ = 3.3V 0.165V unless otherwise noted MAX DESCRIPTION CONDITIONS Power Supply Current: Operating Power Supply Current: Idle Device selected; All inputs VIL or VIH; Cycle time tKC (MIN); VDD = MAX; Outputs open Device selected; VDD = MAX; ADSC#, ADSP#, ADV#, GW#, BWx# VIH; All inputs VSS + 0.2 or VDD - 0.2; Cycle time tKC (MIN); Outputs open Device deselected; VDD = MAX; All inputs VSS + 0.2 or VDD - 0.2; All inputs static; CLK frequency = 0 Device deselected; VDD = MAX; ADSC#, ADSP#, ADV#, GW#, BWx# VIH; All inputs VSS + 0.2 or VDD - 0.2; Cycle time tKC (MIN) ZZ VIH CMOS Standby Clock Running Snooze Mode SYMBOL TYP -5 -6 -7.5 -10 UNITS NOTES IDD 300 420 380 340 300 mA 7, 8, 9 IDD1 120 180 170 160 150 mA 7, 8, 9 ISB2 8 30 30 30 30 mA 8, 9 ISB4 120 180 170 160 150 mA 8, 9 ISB2Z 8 30 30 30 30 mA 9 Table 16: 2.5V VDD, IDD Operating Conditions and Maximum Limits (1 Meg x 18 and 512K x 36) Notes appear following parameter tables on page 17; 0C TA +70C; VDD and VDDQ = 2.5V 0.125V unless otherwise noted MAX DESCRIPTION CONDITIONS Power Supply Current: Operating Power Supply Current: Idle Device selected; All inputs VIL or VIH; Cycle time tKC (MIN); VDD = MAX; Outputs open Device selected; VDD = MAX; ADSC#, ADSP#, ADV#, GW#, BWx# VIH; All inputs VSS + 0.2 or VDD - 0.2; Cycle time tKC (MIN); Outputs open Device deselected; VDD = MAX; All inputs VSS + 0.2 or VDD - 0.2; All inputs static; CLK frequency = 0 Device deselected; VDD = MAX; ADSC#, ADSP#, ADV#, GW#, BWx# VIH; All inputs VSS + 0.2 or VDD - 0.2; Cycle time tKC (MIN) ZZ VIH CMOS Standby Clock Running Snooze Mode 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 SYMBOL TYP -5 -6 -7.5 -10 UNITS NOTES IDD 230 350 300 260 230 mA 7, 8, 10 IDD1 90 150 130 110 90 mA 7, 8, 10 ISB2 8 30 30 30 30 mA 8, 10 ISB4 90 150 130 110 90 mA 8, 10 ISB2Z 8 30 30 30 30 mA 10 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM Table 17: AC Electrical Characteristics and Recommended Operating Conditions Note 11; notes appear following parameter tables on page 17; 0C TA +70C; TJ 95C (commercial); TJ 110C (industrial); VDD = 3.3V 0.165V unless otherwise noted -5 DESCRIPTION SYM MIN Clock Clock cycle time tKC 5.0 -6 MAX MIN -7.5 MAX 6.0 200 MIN -10 MAX 7.5 166 MIN MAX UNITS 10 133 NOTES ns 100 MHz Clock frequency fKF Clock HIGH time tKH 2.0 2.3 2.5 3.0 ns 12 Clock LOW time tKL 2.0 2.3 2.5 3.0 ns 12 Output Times Clock to output valid 3.1 tKQ 3.5 4.0 5.0 ns Clock to output invalid tKQX 1.0 1.5 1.5 1.5 ns 13 Clock to output in Low-Z tKQLZ 0 0 0 0 ns 6, 13, 14, Clock to output in High-Z tKQHZ 5.0 ns 6, 13, 14 5.0 ns 15 ns 6, 13, 14 ns 6, 13, 14 OE# to output valid tOEQ OE# to output in Low-Z tOELZ OE# to output in High-Z tOEHZ Setup Times Address 3.1 3.5 3.1 0 4.2 3.5 0 3.0 4.0 0 3.0 0 3.5 4.5 tAS 1.4 1.5 1.5 2.0 ns 16, 17 tADSS 1.4 1.5 1.5 2.0 ns 16, 17 tAAS 1.4 1.5 1.5 2.0 ns 16, 17 Write signals (BWa#-BWd#, GW#, BWE#) Data-in tWS 1.4 1.5 1.5 2.0 ns 16, 17 tDS 1.4 1.5 1.5 2.0 ns 16, 17 Chip enable (CE#) tCES 1.4 1.5 1.5 2.0 ns 16, 17 Hold Times Address tAH 0.4 0.5 0.5 0.5 ns 16, 17 tADSH 0.4 0.5 0.5 0.5 ns 16, 17 Address advance (ADV#) tAAH 0.4 0.5 0.5 0.5 ns 16, 17 Write signals (BWa#-BWd#, GW#, BWE#) Data-in tWH 0.4 0.5 0.5 0.5 ns 16, 17 tDH 0.4 0.5 0.5 0.5 ns 16, 17 Chip enable (CE#) tCEH 0.4 0.5 0.5 0.5 ns 16, 17 Address status (ADSC#, ADSP#) Address advance (ADV#) Address status (ADSC#, ADSP#) 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM Notes 1. All voltages referenced to VSS (GND). 2. For 3.3V VDD: Overshoot: VIH +4.6V for t tKC/2 for I 20mA Undershoot: VIL -0.7V for t tKC/2 for I 20mA Power-up: VIH +3.6V and VDD 3.135V for t 200ms 3. For 2.5V VDD: Overshoot: VIH +3.6V for t tKC/2 for I 20mA Undershoot:VIL -0.5V for t tKC/2 for I 20mA Power-up: VIH +2.65V and VDD 2.375V for t 200ms 4. The MODE and ZZ pins/balls have an internal pull-up/pull-down and input leakage = 10A. 5. VDDQ should never exceed VDD. VDD and VDDQ can be connected together. 6. This parameter is sampled. 7. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and greater output loading. 8. "Device deselected" means device is in powerdown mode as defined in the truth table. "Device selected" means device is active (not in powerdown mode). 9. Typical values are measured at 3.3V, 25C, and 10ns cycle time. 10. Typical values are measured at 2.5V, 25C, and 10ns cycle time. 11. Test conditions as specified with the output loading shown in Figures 11 and 12 for 3.3V I/O and 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 12. 13. 14. 15. 16. 17. 17 Figures 13 and 14 for 2.5V I/O unless otherwise noted. Measured as HIGH above VIH and LOW below VIL. This parameter is measured with the output loading shown in Figure 12 for 3.3V I/O and Figure 14 for 2.5V I/O. Refer to Technical Note TN-58-09, "Synchronous SRAM Bus Contention Design Considerations," for a more thorough discussion of these parameters. OE# is a "Don't Care" when a byte write enable is sampled LOW. A WRITE cycle is defined by at least one byte write (BWa#-BWd#) being LOW, the byte write enable (BWE#) active, and ADSC# LOW for the required setup and hold times. A READ cycle is defined by the byte write enable (BWE#) being HIGH or ADSP# LOW for the required setup and hold times. This is a synchronous device. All addresses must meet the specified setup and hold times when either ADSC# or ADSP# is LOW and chip is enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of CLK when the chip is enabled. To remain enabled, chip enable must be valid at each rising edge when either ADSC# or ADSP# is LOW. Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM Figure 7: READ Timing tKC CLK tKH tKL tADSS tADSH ADSP# tADSS tADSH ADSC# tAS ADDRESS tAH A1 A2 tWS A3 Burst continued with new base address tWH GW#, BWE#, BWa#-BWd# tCES Deselect (NOTE 4) cycle tCEH CE# (NOTE 2) tAAS tAAH ADV# ADV# suspends burst OE# (NOTE 3) t KQLZ Q High-Z t OEHZ Q(A1) tOEQ tKQ t OELZ tKQX Q(A2) t KQHZ Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A3) t KQ (NOTE 1) Single READ BURST READ Burst wraps around to its initial state DON'T CARE UNDEFINED NOTE: 1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2. 2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause Q to be driven until after the following clock rising edge. (This note applies to whole diagram.) 4. Outputs are disabled within two clock cycles after deselect. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM Figure 8: WRITE Timing t KC CLK tKH tKL tADSS tADSH ADSP# ADSC# extends burst tADSS tADSH tADSS tADSH ADSC# tAS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP# initiates burst tWS tWH BWE#, BWa#-BWd# (NOTE 5) tWS tWH GW# tCES tCEH CE# (NOTE 2) tAAS tAAH ADV# ADV# suspends burst (NOTE 4) OE# (NOTE 3) tDS D tDH D(A1) High-Z tOEHZ D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) (NOTE 1) Q BURST READ Single WRITE BURST WRITE Extended BURST WRITE DON'T CARE UNDEFINED NOTE: 1. D(A2) refers to output from address A2. D(A2 + 1) refers to output from the next internal burst address following A2. 2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/ output data contention for the time period prior to the byte write enable inputs being sampled. 4. ADV# must be HIGH to permit a WRITE to the loaded address. 5. Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa#, and BWb# LOW for x18 device; or GW# HIGH and BWE#, BWa#-BWd# LOW for x32 and x36 devices. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM Figure 9: READ/WRITE Timing tKC CLK tKL tKH tADSS tADSH ADSP# ADSC# tAS ADDRESS BWE#, BWa#-BWd# (NOTE 4) A1 tAH A3 A2 tCES A4 tWS tWH tDS tDH A5 A6 D(A5) D(A6) tCEH CE# (NOTE 2) ADV# OE# tKQ D tOELZ High-Z tKQLZ Q (NOTE 3) High-Z Q(A1) Back-to-Back READs tOEHZ D(A3) (NOTE 6) Q(A2) (NOTE 1) Q(A4) Single WRITE Q(A4+1) BURST READ (NOTE 5) Q(A4+2) Q(A4+3) Back-to-Back WRITEs DON'T CARE UNDEFINED NOTE: 1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4. 2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC#, or ADV# cycle is performed. (This note applies to whole diagram.) 4. GW# is HIGH. 5. Back-to-back READs may be controlled by either ADSP# or ADSC#. 6. This undefined READ will follow any WRITE cycle which is transitioned to a Read, Deselect, or Snooze. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM SNOOZE MODE SNOOZE MODE is a low-current, power-down mode in which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time ZZ is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become gated inputs and are ignored. ZZ is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When ZZ becomes a logic HIGH, ISB2Z is guaranteed after the setup time tZZ is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed. Table 18: SNOOZE MODE Electrical Characteristics DESCRIPTION Current during SNOOZE MODE ZZ active to input ignored CONDITIONS SYMBOL ZZ VIH ZZ inactive to input sampled MAX UNITS ISB2Z 30 tZZ 2(tKC) mA ns 1 ns 1 ns 1 ns 1 tRZZ MIN 2(tKC) tZZI ZZ active to snooze current tRZZI ZZ inactive to exit snooze current 2(tKC) 0 NOTES NOTE: 1. This parameter is sampled. Figure 10: SNOOZE MODE Waveform CLK t ZZ ZZ I t RZZ t ZZI SUPPLY I ISB2Z t RZZI ALL INPUTS (except ZZ) DESELECT or READ Only Outputs (Q) High-Z DON'T CARE 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM 2.5V VDD, 2.5V I/O AC Test Conditions 3.3V VDD, 3.3V I/O AC Test Conditions Input pulse levels ....................VIH = (VDD/2.2) + 1.5V ................................................... VIL = (VDD/2.2) - 1.5V Input rise and fall times......................................... 1ns Input timing reference levels ........................ VDD/2.2 Output reference levels................................VDDQ/2.2 Output load .............................. See Figures 11 and 12 Input pulse levels .................... VIH = (VDD/2) + 1.25V .................................................... VIL = (VDD/2) - 1.25V Input rise and fall times......................................... 1ns Input timing reference levels ........................... VDD/2 Output reference levels.................................. VDDQ/2 Output load............................... See Figures 13 and 14 3.3V VDD, 2.5V I/O AC Test Conditions Input pulse levels ................VIH = (VDD/2.64) + 1.25V ............................................... VIL = (VDD/2.64) - 1.25V Input rise and fall times......................................... 1ns Input timing reference levels ...................... VDD/2.64 Output reference levels...................................VDDQ/2 Output load .............................. See Figures 13 and 14 3.3V I/O Output Load Equivalents 2.5V I/O Output Load Equivalents Figure 11: Figure 13: VT = VDDQ/2.2 VT = VDDQ/2 50 50 Q Z O= 50 Q 30pF Z O= 50 Figure 12: Figure 14: +3.3V 317 +2.5V Q 351 30pF 225 5pF Q 225 5pF NOTE: For Figures 11 and 13, 30pF = distributive test jig capacitance. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM IEEE 1149.1 Serial Boundary Scan (JTAG) Test Access Port (TAP) Test Clock (TCK) The SRAM incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels. The SRAM contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test MODE SELECT (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see Figure 15. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Figure 16.) Disabling the JTAG Feature These balls can be left floating (unconnected), if the JTAG function is not to be implemented. Upon powerup, the device will come up in a reset state which will not interfere with the operation of the device. Figure 15: TAP Controller State Diagram 1 Test Data-Out (TDO) TEST-LOGIC RESET The TDO output ball is used to serially clock dataout from the registers. The output is active depending upon the current state of the TAP state machine. (See Figure 15.) The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Figure 16.) 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 1 SELECT IR-SCAN 0 1 1 0 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 1 0 Figure 16: TAP Controller Block Diagram 1 EXIT1-DR 1 EXIT1-IR 0 1 0 PAUSE-DR 0 PAUSE-IR 0 0 Bypass Register 1 0 1 EXIT2-DR 0 2 1 0 EXIT2-IR 1 Selection Circuitry TDI 1 Instruction Register 31 30 29 . UPDATE-DR 1 0 UPDATE-IR 1 . Selection Circuitry TDO . 2 1 0 Identification Register 0 x . . . . . 2 1 0 Boundary Scan Register* NOTE: The 0/1 next to each state represents the value of TMS at the rising edge of TCK. TCK TAP CONTROLLER TMS NOTE: X = 74 for all configurations. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM Performing a TAP Reset The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. A reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. Identification (ID) Register The ID register is loaded with a vendor-specific, 32bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the ShiftDR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. TAP Instruction Set Overview Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in Figure 16. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the boardlevel serial test data path. Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals into the SRAM and cannot preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the I/O ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (Vss) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The SRAM has a 75-bit-long register. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold time (tCS plus tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls. Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1-compliant. When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM Figure 17: TAP Timing 1 2 Test Clock (TCK) 3 tTHTL tMVTH tTHMX tDVTH tTHDX t TLTH 4 5 6 tTHTH Test Mode Select (TMS) Test Data-In (TDI) tTLOV tTLOX Test Data-Out (TDO) DON'T CARE UNDEFINED Table 19: TAP AC Electrical Characteristics Notes 1, 2; 0C TA +70C; VDD = 3.3V 0.165V or 2.5V 0.125V DESCRIPTION SYMBOL MIN Clock cycle time tTHTH 100 MAX UNITS Clock ns 10 MHz Clock frequency fTF Clock HIGH time tTHTL 40 ns Clock LOW time tTLTH 40 ns tTLOX 0 ns Output Times TCK LOW to TDO unknown 20 ns TCK LOW to TDO valid tTLOV TDI valid to TCK HIGH tDVTH 10 ns TCK HIGH to TDI invalid tTHDX 10 ns tMVTH 10 ns tCS 10 ns Setup Times TMS setup Capture setup Hold Times TMS hold Capture hold tTHMX 10 ns tCH 10 ns NOTE: 1. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 2. Test conditions are specified using the load in Figures 18 and 19. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels ........................................... VSS to 3.0V Input rise and fall times ..............................................1ns Input timing reference levels.................................... 1.5V Output reference levels ............................................. 1.5V Test load termination supply voltage ...................... 1.5V Input pulse levels............................................ VSS to 2.5V Input rise and fall times ............................................. 1ns Input timing reference levels.................................. 1.25V Output reference levels ........................................... 1.25V Test load termination supply voltage .................... 1.25V Figure 18: 3.3V TAP AC Output Load Equivalent Figure 19: 2.5V TAP AC Output Load Equivalent 1.5V 1.25V 50 50 TDO TDO Z O= 50 Z O= 50 20pF 20pF Table 20: 3.3V VDD, TAP DC Electrical Characteristics and Operating Conditions 0C TA +70C; VDD = 3.3V 0.165V unless otherwise noted DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage CONDITIONS 0V VIN VDD Output(s) disabled, 0V VIN VDD (TDO) IOLC = 100A IOLT = 2mA IOHC = -100A IOHT = -2mA SYMBOL MIN MAX UNITS NOTES VIH VIL ILI ILO 2.0 -0.3 -10 -10 VDD + 0.3 0.8 10 10 V V A A 1, 2 1, 2 2 2 0.7 0.8 V V V V 1, 2 1, 2 1, 2 1, 2 VOL1 VOL2 VOH1 VOH2 2.9 2.0 Table 21: 2.5V VDD, TAP DC Electrical Characteristics and Operating Conditions 0C TA +70C; VDD = 2.5V 0.125V unless otherwise noted DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage CONDITIONS 0V VIN VDD Output(s) disabled, 0V VIN VDD (TDO) IOLC = 100A IOLT = 2mA IOHC = -100A IOHT = -2mA SYMBOL MIN MAX UNITS NOTES VIH VIL ILI ILO 1.7 -0.3 -10 -10 VDD + 0.3 0.7 10 10 V V A A 1, 2 1, 2 2 2 0.2 0.7 V V V V 1, 2 1, 2 1, 2 1, 2 VOL1 VOL2 VOH1 VOH2 2.1 1.7 NOTE: 1. All voltages referenced to VSS (GND). 2. TAP control balls only. For boundary scan ball specifications, please refer to the I/O DC Electrical Characteristics and Operation Conditions tables. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM Table 22: Identification Register Definitions BIT CONFIGURATION DESCRIPTION INSTRUCTION FIELD 0000 Revision Number (31:28) Device Depth (27:23) Device Width (22:18) Micron Device ID (17:12) Micron JEDEC ID Code (11:1) ID Register Presence Indicator (0) 00111 00110 00011 00100 xxxxxx 00000101100 1 Reserved for version number. Defines depth of 1Mb. Degines depth of 512K. Defines width of x18 bits. Defines width of x32 or x36 bits. Reserved for future use. Allows unique identification of SRAM vendor. Indicates the presence of an ID register. Table 23: Scan Register Sizes REGISTER NAME BIT SIZE 3 1 32 75 Instruction Bypass ID Boundary Scan: x18, x32, x36 Table 24: Instruction Codes INSTRUCTION CODE EXTEST 000 IDCODE 001 SAMPLE Z 010 RESERVED SAMPLE/PRELOAD 011 100 RESERVED RESERVED BYPASS 101 110 111 DESCRIPTION Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM Table 25: 165-Ball FBGA Boundary Scan Order (x18) BIT# SIGNAL NAME BALL ID BIT# SIGNAL NAME BALL ID 1 MODE (LB0#) 1R 39 CLK 6B 2 SA 6N 40 NC 11B 3 SA 11P 41 NC 1A 4 SA 8R 42 CE2# 6A 5 SA 8P 43 BWa# 5B 6 SA 9R 44 NC 5A 7 SA 9P 45 BWb# 4A 8 SA 10R 46 NC 4B 9 SA 10P 47 CE2 3B 10 SA 11R 48 CE# 3A 11 ZZ 11H 49 SA 2A 12 NC 11N 50 SA 2B 13 NC 11M 51 NC 1B 14 NC 11L 52 NC 1C 15 NC 11K 53 NC 1D 16 NC 11J 54 NC 1E 17 DQa 10M 55 NC 1F 18 DQa 10L 56 NC 1G 19 DQa 10K 57 DQb 2D 20 DQa 10J 58 DQb 2E 21 DQa 11G 59 DQb 2F 22 DQa 11F 60 DQb 2G 23 DQa 11E 61 DQb 1J 24 DQa 11D 62 DQb 1K 25 DQPa 11C 63 DQb 1L 26 NC 10F 64 DQb 1M 27 NC 10E 65 DQPb 1N 28 NC 10D 66 NC 2K 29 NC 10G 67 NC 2L 30 SA 11A 68 NC 2M 31 SA 10B 69 NC 2J 32 SA 10A 70 SA 3P 33 ADV# 9A 71 SA 3R 34 ADSP# 9B 72 SA 4P 35 ADSC# 8A 73 SA 4R 36 OE# (G#) 8B 74 SA1 6P 37 BWE# 7A 75 SA0 6R 38 GW# 7B 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM Table 26: 165-Ball FBGA Boundary Scan Order (x32) BIT# SIGNAL NAME BALL ID BIT# SIGNAL NAME BALL ID 1 MODE (LB0#) 1R 39 CLK 6B 2 SA 6N 40 NC 11B 3 SA 11P 41 NC 1A 4 SA 8R 42 CE2# 6A 5 SA 8P 43 BWa# 5B 6 SA 9R 44 BWb# 5A 7 SA 9P 45 BWc# 4A 8 SA 10R 46 BWd# 4B 9 SA 10P 47 CE2 3B 10 SA 11R 48 CE# 3A 11 ZZ 11H 49 SA 2A 12 NF 11N 50 SA 2B 13 DQa 11M 51 NC 1B 14 DQa 11L 52 NF 1C 15 DQa 11K 53 DQc 1D 16 DQa 11J 54 DQc 1E 17 DQa 10M 55 DQc 1F 18 DQa 10L 56 DQc 1G 19 DQa 10K 57 DQc 2D 2E 20 DQa 10J 58 DQc 21 DQb 11G 59 DQc 2F 22 DQb 11F 60 DQc 2G 23 DQb 11E 61 DQd 1J 24 DQb 11D 62 DQd 1K 25 DQb 10G 63 DQd 1L 1M 26 DQb 10F 64 DQd 27 DQb 10E 65 DQd 2J 28 DQb 10D 66 DQd 2K 29 NF 11C 67 DQd 2L 30 NC 11A 68 DQd 2M 31 SA 10B 69 NF 1N 32 SA 10A 70 SA 3P 33 ADV# 9A 71 SA 3R 34 ADSP# 9B 72 SA 4P 35 ADSC# 8A 73 SA 4R 36 OE# (G#) 8B 74 SA1 6P 37 BWE# 7A 75 SA0 6R 38 GW# 7B 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 30 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM Table 27: 165-Ball FBGA Boundary Scan Order (x36) BIT# SIGNAL NAME BALL ID BIT# SIGNAL NAME BALL ID 1 MODE (LB0#) 1R 39 CLK 6B 2 SA 6N 40 NC 11B 3 SA 11P 41 NC 1A 4 SA 8R 42 CE2# 6A 5 SA 8P 43 BWa# 5B 6 SA 9R 44 BWb# 5A 7 SA 9P 45 BWc# 4A 8 SA 10R 46 BWd# 4B 9 SA 10P 47 CE2 3B 10 SA 11R 48 CE# 3A 11 ZZ 11H 49 SA 2A 12 DQPa 11N 50 SA 2B 13 DQa 11M 51 NC 1B 14 DQa 11L 52 DQPc 1C 15 DQa 11K 53 DQc 1D 16 DQa 11J 54 DQc 1E 17 DQa 10M 55 DQc 1F 18 DQa 10L 56 DQc 1G 19 DQa 10K 57 DQc 2D 2E 20 DQa 10J 58 DQc 21 DQb 11G 59 DQc 2F 22 DQb 11F 60 DQc 2G 23 DQb 11E 61 DQd 1J 24 DQb 11D 62 DQd 1K 25 DQb 10G 63 DQd 1L 1M 26 DQb 10F 64 DQd 27 DQb 10E 65 DQd 2J 28 DQb 10D 66 DQd 2K 29 DQPb 11C 67 DQd 2L 30 NC 11A 68 DQd 2M 31 SA 10B 69 DQPd 1N 32 SA 10A 70 SA 3P 33 ADV# 9A 71 SA 3R 34 ADSP# 9B 72 SA 4P 35 ADSC# 8A 73 SA 4R 36 OE# (G#) 8B 74 SA1 6P 37 BWE# 7A 75 SA0 6R 38 GW# 7B 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM Figure 20: 100-Pin Plastic TQFP (JEDEC LQFP) +0.10 22.10 -0.20 20.10 0.10 0.65 TYP 0.32 +0.06 -0.10 0.625 SEE DETAIL A 14.00 0.10 16.00 0.20 PIN #1 ID 0.15 +0.03 -0.02 1.40 0.05 GAGE PLANE 1.60 MAX 0.10 0.10 +0.10 -0.05 0.60 0.15 1.00 TYP 0.25 DETAIL A NOTE: 1. All dimensions in millimeters MAX -------------MIN or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM Figure 21: 165-Ball FBGA 0.85 0.075 0.12 C SEATING PLANE C BALL A11 165X O 0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS O 0.40 10.00 BALL A1 PIN A1 ID 1.00 TYP 1.20 MAX PIN A1 ID 7.50 0.05 14.00 15.00 0.10 7.00 0.05 1.00 TYP MOLD COMPOUND: EPOXY NOVOLAC 6.50 0.05 SUBSTRATE: PLASTIC LAMINATE 5.00 0.05 SOLDER BALL MATERIAL: EUTECTIC 62% Sn, 36% Pb, 2% Ag SOLDER BALL PAD: O .33mm 13.00 0.10 NOTE: 1. All dimensions in millimeters MAX -------------MIN or typical where noted. Data Sheet Designation No Marking: This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo, and SyncBurst are trademarks and/or service marks of Micron Technology, Inc. Pentium is a registered trademark of Intel Corporation. 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. 18Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM Document Revision History * Rev D; Pub. 2/03..........................................................................................................................................................2/03 Changed designation from Preliminary to Production * Rev C; Pub. 12/02 ......................................................................................................................................................12/02 Added TJ specifications to the AC Electrical Characteristics table Corrected Boundary Scan errors Updated TQFP and FBGA Thermal Resistance values Corrected grammatical errors * Rev B; Pub. 11/02 ......................................................................................................................................................11/02 Changed designation from ADVANCE to PRELIMINARY Corrected grammatical errors * New ADVANCE data sheet for 0.16m process; Rev. A, Pub. 6 /02 .........................................................................6/02 18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM MT58L1MY18D_16_D.fm - Rev. D, Pub 2/03 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc.