ORT82G5 - Agere Systems, Inc. - Datasheet.Company

Preliminary Product Brief

Jan u ary 2001

ORCA® ORT82G5

1.25/2.5/3.125 Gbits/s Backplane Interface FPSC

Introduction

Lucent Technologies Microelectronics Group has

developed a next generation FPSC intended f or high-

speed serial backplane data transmission. Built on

the Series 4 reconfigurable embedded system-on-

chips (SoC) architecture, the ORT82G5 is made up

of backplane transceivers containing eight channels,

each operating at up to 3.125 Gbits/s (2.5 Gbits/s

data rate), with a full-duplex synchronous interface

with built-in clock and data recovery (CDR), along

with up to 600k usable FPGA system gates. The

CDR circuitry is a macrocell available from Lucent's

Smart Silicon macro library, and has already been

implemented in numerous applications including

ASICs, standard products, and FPSCs to create

interfaces for SONET/SDH, STS-48/STM-16, STS-

192/STM-64, and 10 gigabit Ethernet applications.

With the addition of protocol and access logic such

as protocol-independent framers, asynchronous

transfer mode (ATM) framers, packet-o ver-SONET

(POS) interfaces, and framers for HDLC for Internet

protocol (IP), designers can build a configurable

interface retaining proven backplane driver/receiver

technology. Designers can also use the device to

drive high-speed data transfer across buses within a

system that are not SONET/SDH based. For exam-

ple, designers can build a 20 Gbits/s bridge for

10 Gbits/s Ethernet, the high-speed SERDES inter-

faces can comprise two XAUI interfaces with config-

urable back-end interfaces such as XGMII or POS-

PHY4. The ORT82G5 can also be used to provide a

full 10 Gbits/s backplane data connection with pro-

tection between a line card and switch fabric.

The ORT82G5 offers a clockless high-speed inter-

face for interdevice communication on a board or

across a backplane. The built-in clock recov ery of the

ORT82G5 allows for higher system performance,

easier-to-design clock domains in a multiboard sys-

tem, and fewer signals on the backplane. Network

designers will benefit from the backplane transceiver

as a network termination device. The backplane

transceiver offers SONET data scrambling/descram-

bling, or 8b/10b data encoding/decoding and stream-

lined SONET framing, transport overhead handling,

plus the programmable logic to terminate the network

into proprietary systems. For non-SONET applica-

tions, all SONET functionality is hidden from the user

and no prior networking knowledge is required.

Table 1. ORCA ORT82G5 Famil y—Available FPGA Logic

† The embedded core and interface are not included in the above gate counts. The usable gate counts range from a logic-only gate count

to a gate count assuming 20% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as

108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIO

groups are counted as 16 gates (three FFs, fast-capture latch, output logic, CLK, and I/O buffers). PFUs used as RAM are counted at

four gat es per bit, with each PFU capable of implem enting a 32 x 4 RAM (or 512 gates) per PFU. Embedded block RAM (EBR) is

counted as four gates per bit plus each block has an additional 25k gates. 7k gates are used for each PLL and 50k gates for the embed-

ded system bus and microprocessor interface logic. Both the EBR and PLLs are conservatively utilized in the gate count calculations.

Device PFU

Rows PFU

Columns Total

PFUs User I/O LUTs EBR

Blocks EBR Bits

(k) Usable†

Gates (k)

ORT82G5 46 44 2024 536 16,192 16 147 530—970

22 Lucent Technologies Inc.

Preliminary Product Brief

January 20 01

ORCA ORT82G5 FPSC

Embedded Function Features

■High speed SERDES programmable serial data

rates of 622 Mbits/s, 1.25 Gbits/s, 2.5 Gbits/s, and

3.125 Gbits/s.

■Asynchronous operation per receive channel (sepa-

rate PLL per channel).

■Transmit pre-emphasis (programmab le) for improved

data eyes to determine if a link is active.

■Receiver energy detector.

■8-bit (SONET) or (8b/10b) parallel internal bus for

data processing in FPGA logic.

■1.5 V internal operation, 1.5 V/1.8 V I/O support.

■Provides a 10 Gbits/s backplane interf ace to switch

fabric with protection.

■3.125 Gbits/s SERDES compliant with XAUI serial

data specification for 10 Gbit Ethernet applications.

■Compliant to Infiband 1.0 physical lay er specification.

■Compliant to fibre-channel physical layer specifica-

tion.

■Allows wide range of applications for SONET net-

work termination, as well as generic data moving for

high-speed backplane data transfer.

■No knowledge of SONET/SDH needed in generic

applications. Simply supply data (100 MHz—

156.25 MHz clock) and a frame pulse.

■High-speed interface (HSI) function for clock/data

recov ery serial backplane data transfer without e xter-

nal clocks.

■Eight-channel HSI function provides 2.5 Gbits/s

serial user data interface per channel for a total chip

bandwidth of 20 Gbits/s (full duplex).

■Low-power CML buffers.

■Programmable STS-12, and STS-48 framing.

■Independent STS-12 and STS-48 data streams per

quad channels.

■Powerdown option of HSI receiver on a per-channel

basis.

■Selectable 8b/10b coder/decoder or SONET scram-

bler/descrambler.

■HSI automatically recovers from loss-of-clock once

its reference clock returns to normal operating state.

■Frame alignment across multiple ORT82G5 devices

for work/protect switching at STS-768/STM256 and

above rates.

■Most XAUI features for 10 Gbit Ethernet are embed-

ded including:

— Serial management interface

— Elastic store buffers for clock domain transfer to/

from XGMII or XAUI interfaces.

■In-band mana gem ent and co nfi guration thr oug h

transport overhead extraction/insertion.

■Supports transparent mode where the only insertion

is A1/A2 framing bytes.

■Built-in boundry scan (IEEE * 1149.1 JTAG ) .

■FIFOs align incoming data across all eight channels

(two groups of four channels or four groups of two

channels). Optional ability to bypass alignment

FIFOs for asynchronous operation between chan-

nels.

■1 + 1 protection supports STS-192/STM-64/STS-48

redundancy by either software or hardware control

for protection switching applications. STS-768 and

above rates are supported through multiple devices.

■Programmable STM framer bypass mode.

■Programmable inverted data framing per channel.

Intellectual Property Features

Programmable logic provides a variety of yet-to-be

standardized interf ace functions, including the following

Lucent ME IP core functions:

■10 Gbits/s Ethernet as defined by IEEE 802.3ae:

— XGMII for interf acing to 10 Gbits/s Ethernet

MACs. XGMII is a 156 MHz double data rate par-

allel short reach (typically less than 2") intercon-

nect interface.

— X59 + X19 + X1 scrambl er/descramb ler for

10 Gbits/s Ethern et.

— 64b/66b encoders/decoders for 10 Gbits/s Ether-

net.

■POS-PHY interface for 10 Gbits/s SONET/SDH and

O TN systems and some 10 Gbits/s Ethernet systems

to allow easy integration of Infiniband, fibre-channel,

and 10 Gbits/s Ethernet in data over fibre applica-

tions.

*IEEE is a registered trademark of The Institute of Electrical and

Electronics Engineers, Inc.

Lucent Technologies Inc. 3

Preliminary Product Brief

January 20 01 ORCA ORT82G5 FPSC

Programmable Features

■High-performance programmable logic:

— 0.13 µm 7-level metal technology.

— Internal performance of >250 MHz.

— Over 600k usable system gates.

— Meets multiple I/O interface standards.

— 1.5 V operation (30% less power than 1.8 V oper-

ation) translates to greater performance.

■Traditional I/O selections:

— LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V) I/Os.

— Per pin-selectable I/O clamping diodes provide

3.3 V PCI compliance.

— Individually programmable drive capability:

24 mA sink/12 mA source, 12 mA sink/6 mA

source, or 6 mA sink/3 mA source.

— Two slew rates supported (fast & slew-limited).

— Fast-capture input latch and input flip-flop

(FF)/latch for reduced input setup time and zero

hold time.

— Fast open-drain drive capability.

— Capability to register 3-state enable signal.

— Off-chip clock drive capability.

— Two-input function generator in output path.

■New programmable high-speed I/O:

— Single-ended: GTL, GTL+, PECL, SSTL3/2

(class I & II), HSTL (Class I, III, IV), ZBT, and

DDR.

— Double-ended: LVDS, bused-LVDS, and LVPECL.

— Customer defined: ability to substitute arbitrary

standard cell I/O to meet fast moving standards.

■New capability to (de)multiplex I/O signals:

— New DDR on both input and output at rates up to

311 MHz (622 MHz effective rate).

— New 2x and 4x downlink and uplink capability per

I/O (i.e., 50 MHz internal to 200 MHz I/O).

■Enhanced twin-quad programmable function unit

(PFU):

— Eight 16-bit look-up tables (LUTs) per PFU.

— Nine user registers per PFU, one following each

LUT, and organized to allow two nibbles to act

independently, plus one ex tra for arithmetic opera-

tions.

— New register control in each PFU has two inde-

pendent programmable clocks, clock enables ,

local set/reset, and data selects.

— New LUT structure allows fle xible combinations of

LUT4, LUT5, ne w LUT6, 4 → 1 MUX, new

8 → 1 MUX, and ripple mode arithmetic functions

in the same PFU.

— 32 x 4 RAM per PFU, configurable as single- or

dual-port. Create large, fast RAM/ROM blocks

(128 x 8 in only eight PFUs) using the SLIC

decoder s as ban k drivers.

— Soft-w ir ed LUT s (SWL ) al lo w fast ca scad ing of up

to three levels of LUT logic in a single PFU

through fast internal routing which reduces rout-

ing congestion and improves speed.

— Flexible fast access to PFU inputs from routing.

— Fast-carry logic and routing to all four adjacent

PFUs for nibble-wide, byte-wide, or longer arith-

metic functions, with the option to register the

PFU ca rry-o ut.

■Abundant high-sp eed buffered and nonbuffer ed ro ut-

ing resources provide 2x average speed improve-

ments over previous architectures.

■Hierarchical routing optimized for both local and glo-

bal routing with dedicated routing resources. This

results in faster routing times with predictable and

efficient performance.

■SLIC provides eight 3-statable buffers, up to a 10-bit

decoder, and PAL*-like and-or-invert (AOI) in each

programmable logic cell.

■Improved built-in clock management with program-

mable phase-locked loops (PPLLs) provides opti-

mum clock modification and conditioning for phase,

frequency, and duty cycle from 20 MHz up to 200

MHz.

■New 200 MHz embedded quad-port RAM blocks, 2

read ports, 2 write ports, and 2 sets of byte lane

enables. Each embedded RAM block can be config-

ured as:

— 1—512 x 18 (quad-port, two read/two write) with

optional built in arbitration.

— 1—256 x 36 (dual-port, one read/one write).

— 1—1k x 9 (dual-port, one read/one write).

— 2—512 x 9 (dual-port, one read/one write for

each).

— 2 RAMS with arbitrary number of words whose

sum is 512 or less by 18 (dual-port, one read/one

write).

— Supports joining of RAM blocks.

— Two 16 x 8-bit content addressable memory

(CAM) su pport.

— FIFO 512 x 18, 256 x 36, 1k x 9, or dual 512 x 9.

— Constant multiply (8 x 16 or 16 x 8).

— Dual variable multiply (8 x 8).

■Embedded 32-bit internal system bus plus 4-bit par-

ity interconnects FPGA logic, microprocessor inter-

face (MPI), embedded RAM blocks, and embedded

standard cell blocks with 100 MHz bus performance.

Included are built-in system registers that act as the

control and status center for the device.

* PAL is a trademark of Advanced Micro Devices , Inc.

44 Lucent Technologies Inc.

Preliminary Product Brief

January 20 01

ORCA ORT82G5 FPSC

Programmable Features (continued)

■Built-in testability:

— Full boundary scan (IEEE 1149.1 and Draft

1149.2 JTAG) .

— Programming and readback through boundary

scan port compliant to IEEE Draft 1532:D1.7.

— TS_ALL testability function to 3-state all I/O pins.

— New temperature-sensing diode.

■Improved built-in clock management with program-

mable phase-locked loops (PPLLs) provide optimum

clock modification and conditioning for phase, fre-

quency, and duty cycle from 20 MHz up to 420 MHz.

■New cycle stealing capability allows a typical 15% to

40% internal speed improvement after final place

and route. This f eature also enables compliance with

many setup/hold and clock to out I/O specifications

and may provide reduced ground bounce for output

buses by allowing flexible delays of switching output

buffers.

Programmable Logic System Features

■PCI local bus compliant fo r FPGA I/O s.

■Improved PowerPC*860 and PowerPC II high-speed

synchronous microprocessor interface can be used

for configuration, readback, device control, and

device status, as well as for a general-purpose inter-

face to the FPGA logic, RAMs, and embedded stan-

dard cell blocks. Glueless interface to synchronous

PowerPC processors with user-configurable address

space provided.

■Ne w embedded AMBA † specification 2.0 AHB sys-

tem bus (ARM† proce ssor) f aci litat es comm unicat ion

among the microprocessor interface, configuration

logic, embedded block RAM, FPGA logic, and

embedd ed standar d cel l blocks.

■New network PLLs meet ITU-T G.811 specifications

and provide clock conditio ning fo r DS-1/E -1 a nd

STS-3/STM-1 applications.

■Flexible general purpose PPLLs offer clock multiply

(up to 8x), divide (down to 1/8x), phase shift, delay

compe nsati on, and duty cycl e adju stm ent co mbi ned .

*PowerPC is a registered trademark of Inter nationa l Business

Mac hine s, In c.

†AMBA is a trademark, and ARM is a registered trademark of

Advanced RISC Machines Limited.

■Variable size bused readback of configuration data

capability with the built-in microprocessor interface

and system bus.

■Internal, 3-state, and bidirectional buses with simple

control provided by the SLIC.

■New clock routing structures for global and local

clocking significantly increases speed and reduces

skew (<200 ps for OR4E4).

■New local clock routing structures allow creation of

localized clock trees.

■Ne w doub le-data rate (DDR) and zero-bus turn-

around (ZBT) memory interfaces support the latest

high-speed memory interfaces.

■New 2x/4x uplink and downlink I/O capabi li ti es int er-

face high-speed external I/Os to reduced speed

internal logic.

■ORCA Foundry 2000 development system software.

Supported by industry-standard.

■CAE tools f or design entry, synthesis, simulation, and

timing analysis.

■Meets universal test and operations PHY interface

for ATM (UTOPIA) Levels 1, 2, and 3; as well as

POS-PHY3. Also meets proposed specifications for

UTOPIA Level 4 for and POS_PHY4 10 Gbits/s inter-

faces.

■Meet s POS-PHY3 (2.5 Gbits/s) and POS-PHY4

(10 Gbits/s) interface standards for packet-over-

SONET as defined by the Saturn group.

■Two new edge clock routing structures allow up to

seven high-speed clocks on each edge of the device

for improved setup/hold and clock to out perfor-

mance.

Lucent Technologies Inc. 5

Preliminary Product Brief

January 20 01 ORCA ORT82G5 FPSC

Block Diagrams

1023(F)

Figure 1. ORT82G5 Block Diagram

1024(F)

Figure 2. 10Gb Ethernet: Serial LAN

STANDARD

ORCA

SERIES 4

FPGA LOGIC

8-bit/10-bit

ENCODER

8-bit/10-bit

DECODER

CLOCK/DATA

RECOVERY

BYTE-

WIDE

DATA

CML

8 FULL-

2.5 Gbits/s

FPGA I/Os

DATA

DUPLEX

SERIAL

CHANNELS

2.5 Gbits/s

DATA

I/Os

PSUDO-

SONET

FRAMER

• POINTER MOVERS

• SCRAMBLING

• FIFO ALIGNMENT

• SELECTED TOH

LUCENT

ORT82G5

FPSC

LUCENT

10GbE

XAUI

TRANSPONDER

XGMII/

PARALLEL

10GMII

GbE

MAC

4 x 3.125

Gbits/s

4 x 3.125

Gbits/s

XAUI

16 x 644

Mbits/s

16 x 644

Mbits/s

10.3125

Gbits/s

LAN

32 x 156 M H z x 2

= 10 Gbits/s

32 x 156 M H z x 2

= 10 Gbits/s

4 CONTROL

TXCLK

4 CONTROL

RXCLK

8b/10b

DECODER (x4) 8b/10b

ENCODER (x4)

8b/10b

DECODER (x4)

8b/10b

ENCODER (x4)

64/66b

ENCODER (x4) 64/66b

ENCODER (x4)

3.125 Gbits/s

SER 3.125 Gbits/s

DE-SER

3.125 Gbits/s

SER

3.125 Gbits/s

DE-SER

OPTICS

OIF SERDES MUX/deMUX CDR

6Lucent Technologies Inc.

Preliminary Product Brief

January 20 01

ORCA ORT82G5 FPSC

Block Diagrams (continued)

1025(F)

Figure 3. 10G Application with Prote ction

LINE CARD

PROTECT LINE CARD

SWITCH CARD

PROTECT SWITCH CARD

BACKPLANE

10G

FRAMER

10G

NETWORK

PROCESSOR

10G

NETWORK

PROCESSOR

POS-

PHY4

POS-

PHY4

ORT82G5

ORT82G5 SWITCH

INTERFACE

SWITCH

INTERFACE

CSIX,

ETC.

CSIX,

ETC.

Lucent Technologies Inc. 7

Preliminary Product Brief

January 20 01 ORCA ORT82G5 FPSC

Ordering Information

Table 2. Device Options

Software Ordering Information

Implementing a design in an ORT82G5 requires the ORCA Foundry Development System and an OR T82G5

FPSC Design Kit. For ordering information please visit:

http://www.lucent.com/micro/netcom/ipkits

Device Parameter Value

ORT82G5 Voltage 1.5 V core

3.3 V/2.5 V/1.8 V/1.5 V I/O

Package 680-pin PBGAM

600-pin and 792-pin LBGA

Lucent Technologies Inc. reserves the right to make changes to the product(s) or infor mation contained herein without notice. No liability is assumed as a result of their use or application. No

rights under any patent accompany the sale of any such product(s) or information. ORCA is a registered trademark of Lucent Technologies Inc. Foundry is a trademark of Xilinx, Inc.

Printed in U.S.A.

Jan uary 2001

PB01-047NCIP (Replaces PB01-020 NCIP)

For additional information, contact y our Microelectronics Group Account Manager or the following:

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