_______________General Description
The MAX132 is a CMOS, 18-bit plus sign, serial-output,
analog-to-digital converter (ADC). Multi-slope integra-
tion provides high-resolution conversions in less time
than standard integrating ADCs, allowing operation up
to 100 conversions per second. Low conversion noise
provides guaranteed operation with ±512mV full-scale
input range (2µV/LSB). A simple 4-wire serial interface
connects easily to all common microprocessors, and
twos-complement output coding simplifies bipolar mea-
surements. Typical supply current is only 60µA and is
reduced to 1µA in sleep mode. Four serially pro-
grammed digital outputs can be used to control an
external multiplexer or programmable-gain amplifier.
The MAX132 comes in 24-pin narrow DIP and wide SO
packages, and is available in commercial and extend-
ed temperature grades.
High resolution, compact size, and low power make this
device ideal for data loggers, weigh scales, data-acqui-
sition systems, and panel meters.
________________________Applications
Remote Data Acquisition
Battery-Powered Instruments
Industrial Process Control
Transducer-Signal Measurement
Pressure, Flow, Temperature, Voltage
Current, Resistance, Weight
____________________________Features
♦Low Supply Current:
60µA (Normal Operation)
1µA (Sleep-Mode Operation)
♦±0.006% FSR Accuracy at 16 Conv/sec
♦Low Noise: 15µVRMS
♦Serial I/O Interface with Programmed Output for
Mux and PGA
♦Performs up to 100 Conv/sec
♦±2pA Input Current
♦50Hz/60Hz Rejection
MAX132
±18-Bit ADC with Serial Interface
________________________________________________________________
Maxim Integrated Products
1
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
V+
BUF OUT
INT OUT
INT IN
SCLK
DOUT
DIN
CS
TOP VIEW
CREF-
CREF+
REF+
REF-
P1
P0
OSC1
OSC2
16
15
14
13
9
10
11
12
AGND
IN LO
IN HI
V-
DGND
EOC
P3
P2
DIP/SO
MAX132
__________________Pin Configuration
MAX132
CREF- CREF+
CS 602k
SCLK
DOUT
DIN
EOC
P0
P1
P2
P3
-5V
±512mV INPUT
BUF OUT
INT OUT
INT IN 4.7nF
REF+
REF-
AGND
IN LO
IN HI
V-
V+
DGND
OSC2OSC1
+5V
________________Functional Diagram
Call toll free 1-800-998-8800 for free samples or literature.
19-0009; Rev 2; 8/95
PART
MAX132CNG
MAX132CWG
MAX132C/D 0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP. RANGE PIN-PACKAGE
24 Narrow Plastic DIP
24 Wide SO
Dice*
EVALUATION KIT MANUAL
FOLLOWS DATA SHEET
______________Ordering Information
* Contact factory for dice specifications.
** Contact factory for availability and processing to MIL-STD-883.
MAX132ENG
MAX132EWG
MAX132MRG -55°C to +125°C
-40°C to +85°C
-40°C to +85°C 24 Narrow Plastic DIP
24 Wide SO
24 Narrow CERDIP**
MAX132
±18-Bit ADC with Serial Interface
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V+ = 5V, V- = -5V, DGND = AGND = IN LO = REF- = 0V, REF+ = 545mV, RINT = 602kΩ, CINT = 0.0047µF, CREF = 0.1µF,
fCLK = 32,768Hz, 60Hz mode, TA= TMIN to TMAX, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage
V+ to DGND..............................................-0.3V < V+ < +6.0V
V- to DGND ................................................+0.3V < V- < -9.0V
V+ to V-............................................................................+15V
Analog Input Voltage (any input).....................................V+ to V-
Digital Input Voltage .....................(DGND - 0.3V) to (V+ + 0.3V)
Continuous Power Dissipation
Narrow Plastic DIP (derate 8.70mW/°C above +70°C)....478mW
Wide SO (derate 11.76mW/°C above +70°C)..............647mW
Narrow CERDIP (derate 12.50mW/°C above +70°C) ..688mW
Operating Temperature Ranges
MAX132C_ _ .......................................................0°C to +70°C
MAX132E_ _ ....................................................-40°C to +85°C
MAX132MRG.................................................-55°C to +125°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10sec).............................+300°C
Bits
±18Resolution
UNITSMIN TYP MAXPARAMETER
(Note 1)
CONDITIONS
VIN HI = 0V % of FSR
±0.0168
0 ±0.0076
Zero Error
fCLK = 32.768Hz
(Note 4)
ms63 ±0.032
Rollover Error
(Notes 2, 3)
% of FSR
0 ±0.010 % of FSR±0.0015 ±0.006Integral Nonlinearity
IN HI = IN LO V±3.0
Input Voltage Range
Common-Mode Range
(Note 3) ppm/°C±5Scale Factor Temp. Coefficient (Note 3) ppm/°C±0.15 ±1.5 µV15RMS Noise
Zero-Reading Drift
mV±512
Conversion Time
VIN HI = 400mV, V- = -5.0V,
4.5V ≤V+ ≤5.5V ±0.003 ±0.0168 % of FSR
±0.003 ±0.0061
Positive Supply Rejection
Digital input = 0V or V+
Digital input = 0V or V+ µA110
µA-25 -60Digital Ground Supply Current
Positive Sleep-Mode Current
Digital input = 0V or V+
Digital input = 0V or V+ µA-35 -65 µA60 125Positive Supply Current
Negative Supply Current
Digital input = 0V or V+ µA-1 -10Negative Sleep-Mode Current
V-5.5 -4.5 V4.5 5.5Positive Supply Voltage
Negative Supply Voltage
TA= +25°C
TA= TMIN to TMAX
TA= +25°C
TA= +25°C
TA= TMIN to TMAX
IN HI to IN LO, for specified accuracy
% of FSR
±0.25 ±0.50
Common-Mode Rejection Ratio IN HI = IN LO ±0.009 ±0.032VCM = ±500mV
VCM = ±3.0V
pA
±12 ±250
Leakage Current IN HI, IN LO ±2 ±10TA= +25°C
TA= TMIN to TMAX
TA= +25°C
TA= TMIN to TMAX
TA= TMIN to TMAX
TA= +25°C
VIN HI = 400mV, V- = 5.0V,
-5.5V ≤V- ≤-4.5V ±0.003 ±0.0168 % of FSR
±0.003 ±0.0061
Negative Supply Rejection
Digital input = 0V or V+ µA0±2
Digital Ground Sleep-Mode
Current
TA= +25°C % of FSR±3.1Read-Zero 50Hz/60Hz Range
ACCURACY
POWER REQUIREMENTS
MAX132
±18-Bit ADC with Serial Interface
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 5V, V- = -5V, DGND = AGND = IN LO = REF- = 0V, REF+ = 545mV, RINT = 602kΩ, CINT = 0.0047µF, CREF = 0.1µF,
fCLK = 32,768Hz, 60Hz mode, TA= TMIN to TMAX, unless otherwise noted.)
INTERFACE TIMING
(Test Circuit of Figure 1, Figure 2, V+ = 5V, V- = -5V, DGND = AGND = 0V, TA= +25°C, unless otherwise noted.) (Note 3)
Note 1: ±18-bit accuracy achieved by averaging multiple conversions.
Note 2: Maximum deviation from best straight-line fit.
Note 3: Guaranteed by design, not tested.
Note 4: Difference in reading for equal positive and negative inputs near full scale.
DOUT, IOUT = -100µA
DOUT, IOUT = -1mA
CS, DIN, SCLK, and DOUT when three-stated
CS, DIN, SCLK, and DOUT when three-stated
Referred to DGND, 4.5V ≤V+ ≤5.5V, CS, DIN, SCLK
EOC, P0–P3, IOUT = -100µA
DOUT, IOUT = 1.6mA
EOC, P0–P3, IOUT = 100µA
Referred to DGND, 4.5V ≤V+ ≤5.5V, CS, DIN, SCLK
CONDITIONS
4.0 4.5
3.5 4.3
pF5CIN
Input Capacitance nA±10 ±500IIN
Input Current V0.8VIL
Input Low
V
4.0 4.7
VOH
Output High
0.1 0.4 V
0.1 0.4
VOL
Output Low
V2.4VIH
Input High
UNITSMIN TYP MAXSYMBOLPARAMETER
CONDITIONS ns500t1
CS Lead Time
µs1t5
CS High Pulse Width ns300t4
SCLK Low Time ns400t3
SCLK High Time ns400t2
CS Lag Time
UNITSMIN TYP MAXSYMBOLPARAMETER
See Figure 4
See Figure 3
ns0t6
DIN to SCLK Setup Time
ns320t10
DOUT Disable Time to Three-State ns60t9
Data Valid ns320t8
DOUT Access Time from Three-State ns200t7
DIN to SCLK Hold Time
ns230 350t12
Delay to P0–P3 Low ns230 350t11
Delay to P0–P3 High
DIGITAL SECTION
MAX132
±18-Bit ADC with Serial Interface
4 _______________________________________________________________________________________
__________________________________________Typical Operating Characteristics
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0.05
0
ERROR vs. COMMON-MODE
INPUT VOLTAGE (VIN LO–AGND)
MAX132-01
COMMON-MODE VOLTAGE (V)
-3 -2 -1 0 1 2 3 4-4
ERROR (% OF FSR)
IN HI = IN LO
00 0.5 1.5
50Hz/60Hz READ-ZERO OFFSET
vs. VREF
1.5
3.5
MAX132-02
VREF (V)
READ-ZERO OFFSET (% OF FSR)
1.0 2.0
2.5
4.0
1.0
0.5
3.0
2.0
4.5
60Hz MODE
50Hz MODE
0-40 -20 20
50Hz/60Hz READ-ZERO OFFSET
vs. TEMPERATURE
0.6
1.4
MAX132-03
TEMPERATURE (°C)
0 40 60 80 100
1.0
1.6
0.4
0.2
1.2
0.8
READ-ZERO OFFSET (% OF FSR)
60Hz MODE, VREF = 545mV
50Hz MODE, VREF = 655mV
-40 0 50 150
SUPPLY CURRENT
vs. CRYSTAL FREQUENCY
20
100
MAX132-04
CRYSTAL FREQUENCY (kHz)
SUPPLY CURRENT (µA)
100 200 250 300 350
60
120
0
-20
80
40
140
V-
V+
0.10
0.08
0.06
0.04
0.02
0
FULL-SCALE ROLLOVER ERROR
vs. VREF
MAX132-05
VREF (V)
0 0.5 1.0 1.5 2.52.0
ROLLOVER ERROR (% OF FSA)
0
5
10
15
20
NOISE vs. NUMBER
OF SAMPLES AVERAGED
MAX132-06
NUMBER OF SAMPLES AVERAGED
0102030 5040
NOISE (µVRMS)
______________________________________________________________Pin Description
Oscillator Output 2 is normally connected to a 32,768Hz crystal. Do not connect with external clock source.OSC25
Serial Clock Input. On SCLK’s rising edge, data is shifted into the internal shift register through DIN. On
SCLK’s falling edge, data is clocked out of DOUT.
SCLK4
Serial Data Out, D7 first bit out. Data is clocked out at the falling edge of SCLK. High impedance when CSis high.DOUT3
User-programmable output bit 1—programmed through the serial port.P18 User-programmable output bit 0—programmed through the serial port.P07 Oscillator Input 1 is normally connected to a 32,768Hz crystal, or may be connected to an external clock.OSC16
Serial Data In, D7 first bit in. Data is clocked into the register on the rising edge of SCLK.DIN2
PIN
CHIP SELECT Input has 3 functions: 1) When low, selects IC for communication; 2) on rising edge, loads
input shift register data into one of the command registers; 3) on falling edge, loads data from one of the
output registers into the output shift register. When CS is high, DOUT is high impedance.
CS1
FUNCTIONNAME
MAX132
±18-Bit ADC with Serial Interface
_______________________________________________________________________________________ 5
MAX132
CREF- CREF+
1
20
CS 602k
4SCLK
3DOUT
2DIN
11 EOC
7P0
8P1
9P2
10 P3
23
19
22
21
-5V
512mV INPUT
18
17
65
15pF 15pF
BUF OUT
INT OUT
INT IN 4.7nF
32,768Hz
REF+
REF- 16
15
AGND
IN LO 14
IN HI 13
12
V-
24
V+
DGND
OSC2OSC1
0.1µF
120k
100k
40.2k
2.5V
MAX872
+5V
Figure 1. Test and Typical Application Circuit
_________________________________________________Pin Description (continued)
End of Conversion Output goes high at end of conversion.EOC11
Positive Supply, nominally +5VV+24
User-programmable output bit 3—programmed through the serial port.P310
Negative Reference Capacitor connectionCREF-20 Positive Reference Capacitor connectionCREF+19 Positive Reference InputREF+18 Negative Reference InputREF-17 Analog GroundAGND16 Negative Analog InputIN LO15
Buffer-Amplifier Output drives the integrator resistor.BUF OUT23
User-programmable output bit 2—programmed through the serial port.P29
PIN
Integrator Output. To minimize noise, this pin should drive the capacitor’s outside foil (negative end).INT OUT22 Integrator Input. Connect the integration capacitor between INT IN and INT OUT.INT IN21
FUNCTIONNAME
Positive Analog InputIN HI14 Negative Supply, nominally -5VV-13 Digital Ground—power-supply returnDGND12
____________Functional Description
The MAX132 integrates the input voltage for a fixed
period of time, then deintegrates a known reference
voltage and measures the time required to reach zero.
Good line rejection is achieved by setting the (input)
integration time equal to one 50Hz or 60Hz period. The
MAX132 has a 50Hz/60Hz mode selection bit that sets
the integration time to 655/545 clock periods, respec-
tively, so that 50Hz/60Hz rejection is obtained with a
32,768Hz crystal. The MAX132 is tested and guaran-
teed at a 16 conv/sec throughput rate. Figure 1 shows
the basic MAX132 application circuit, with component
values selected for 16 conv/sec .
For applications that don’t require 50Hz/60Hz rejection,
the MAX132 will operate up to 100 conv/sec at reduced
accuracy (typically 0.012% FSR nonlinearity, or ±13
bits). In these applications, the 50Hz mode is recom-
mended because of its longer (655 count) integration
time. See
Increased Speed
section.
__________Analog Design Procedure
Input Voltage Range
and Input Protection
The recommended analog full-scale input range is
±512mV. Performance is tested and guaranteed at
±512mV full scale, corresponding to a 2µV/LSB resolu-
tion at 18 bits. Resolution is defined as follows:
which corresponds to 2µV/LSB resolution at 18 bits.
Consult the
Typical Operating Characteristics
for Noise
vs. Number of Samples Averaged and other important
operating parameters. Note how accuracy depends on
common-mode input voltage (common mode is defined
here as |VIN LO - AGND|). For optimum performance,
set the analog input full-scale between ±470mV and
MAX132
±18-Bit ADC with Serial Interface
6 _______________________________________________________________________________________
Re / ( ) / ,solution Volts LSB V FS
IN
[]
=262144
3k
3k
DOUT DOUT
a. High-Z to VOH (t8) b. High-Z to VOL (t8)
DGND DGND
+5V
CLCL
Figure 3. Load Circuits for Access Time
3k
3k
DOUT DOUT
a. VOH to High-Z (t10) b. VOL to High-Z (t10)
DGND DGND
+5V
10pF 10pF
Figure 4. Load Circuits for Disable Time to Three-State
DIN
t2
t4
t1
t3
t9t10
t6
t8
t7
t11, t12
t5
SCLK
CS
DOUT
P0–P3
MSB IN B6–B1 LSB IN
LSB OUTB6–B1MSB OUT
Figure 2. Serial-Mode Timing
MAX132
±18-Bit ADC with Serial Interface
_______________________________________________________________________________________ 7
±660mV for 60Hz mode operation or between ±390mV
and ±550mV for 50Hz mode operation. The pseudo-
differential input voltage is applied across pins 14 and
15 (IN HI, IN LO), and can range to within 2V of either
supply rail.
The inputs IN HI and IN LO lead directly to CMOS tran-
sistor gates, yielding extremely high input impedances
that are useful when converting signals from a high
input source impedance, such as a sensor. Input cur-
rents are only 2pA typical at +25°C. Figure 6 shows an
RC filter at the input to optimize noise performance.
Fault protection is accomplished by the 100kΩseries
resistance. Internal protection diodes, which clamp the
analog inputs from V+ to V-, allow the channel input
pins to swing from (V- - 0.3V) to (V+ + 0.3V) without
damage. However, if the analog input voltage at the
pins IN HI or IN LO exceed the supplies, limit the cur-
rent into the device to less than 1mA, as excessive cur-
rent will damage the device.
Reference Voltage Selection
The reference voltage sets the analog input voltage
range. For the nominal ±512mV full-scale input range, a
545mV reference voltage is used for the 60Hz mode
and a 655mV reference voltage is used in the 50Hz mode.
The reference voltage can be calculated as follows:
The recommended reference voltage range is 500mV
to 700mV. The MAX132 is tested with the nominal
545mV reference voltage in 60Hz mode. Use amplifiers
or attenuators (resistor dividers) to scale other full-scale
input signal ranges to the recommended ±512mV full-
scale range.
References outside the recommended range may be
used with a degradation of linearity. A reference volt-
age from 200mV to 500mV will result in a lower signal-
to-noise ratio; a reference voltage from 700mV to 2V will
increase the rollover error.
The MAX872 2.50V reference, with its 10µA supply cur-
rent, is ideally suited for the MAX132. Figure 7 shows
how 2.50V can be divided to obtain the desired refer-
ence voltage. The reference input accepts voltages
anywhere within the converter’s power-supply range;
however, for best performance, neither REF+ nor REF-
should come within 2V of the supplies.
MAX132
IN LO
AGND
IN HI
DE+
DE+
REF+CREF+ CREF REF- CREF- INT IN INT OUT
INTEGRATOR
COMPARATOR 1
COMPARATOR 2
DE-
BUFFER
8pF
64pF
Z1+ x 8
CINT
RINT
BUFFER
DE-
TO
DIGITAL
SECTION
INT
REST
INT
INT
X8
DE DE
Figure 5. Analog Section Block Diagram
60 545 512
262144
50 655 512
262144
Hz Mode V counts V
or
Hz Mode V counts V
REF IN FS
REF IN FS
:
( ) () )
,
:
( ) () )
,
()
()
=
=
MAX132
±18-Bit ADC with Serial Interface
8 _______________________________________________________________________________________
Differential Reference Inputs
and Rollover Error
The main source of rollover voltage error is due to
common-mode voltages. This error is caused by the
reference capacitor losing or gaining charge to stray
capacitance. A positive signal with a large common-
mode voltage can cause the reference capacitor to
gain charge (increase voltage). In contrast, the refer-
ence capacitor will lose charge (decrease voltage)
when deintegrating a negative input signal. Rollover
error is a direct result of the difference in reference to
positive or negative input voltages. With the recom-
mended reference capacitor types, the worst-case
rollover error is 0.01% of full-scale. Connect REF- to
AGND to minimize rollover error. As outlined in the ref-
erence section, reference voltages below 500mV also
contribute to rollover errors.
Oscillator Circuit
The internal oscillator is typically driven by a crystal, as
shown in Figure 8, or by an external clock. If an exter-
nal clock is used, connect the clock to OSC1 and leave
OSC2 floating. The duty-cycle can vary from 20% to
80%. The typical threshold voltage is approximately 2V.
For proper start-up, a full +5V CMOS-logic swing is
required.
The oscillator frequency sets the conversion rate. Use
32,768Hz for applications that require 50Hz or 60Hz
line rejection. This frequency yields 16 conv/sec. The
same clock frequency can be used to reject both line
frequencies because the MAX132 integrates for a dif-
ferent number of clock cycles in its 50Hz and 60Hz
modes. In each case, the MAX132 integrates for a sin-
gle complete line cycle (20ms for the 50Hz mode,
16.67ms for the 60Hz mode). Refer to the
Increased
Speed
section for operation at higher conversion rates.
External Components
The MAX132 requires an integrator resistor (RINT) and
capacitor (CINT), a reference capacitor (CREF), and a
crystal. All MAX132 tests are performed with a
32,768Hz crystal frequency. The crystal frequency, ref-
erence voltage, and integrator current determine the
values of RINT and CINT.
Crystal
Figure 8 shows the internal oscillator drive circuitry used
with external crystals. The two external capacitors provide
DC bias at start-up. The 15pF capacitors shown are typical
values. The actual capacitance will vary, depending on the
crystal manufacturer’s recommendation and board layout.
150k
15pF15pF
5pF5pF 1M
+5V
65
OSC1 OSC2
MAX132
Figure 8. MAX132 Internal Oscillator Drive Circuitry
MAX132
V+
+5V
-5V
IN HI
IN LO
15
14
24
13
+545mV
100k
0.1µF
±512mV
16 18
17 AGND
REF- REF+
V-
Figure 6. MAX132 Input Circuit
REF+
REF-
1µF
120k
100k
40.2k
2.5V
MAX872
+5V
Figure 7. Dividing MAX872 to Generate the MAX132’s
Reference Voltage
MAX132
±18-Bit ADC with Serial Interface
_______________________________________________________________________________________ 9
Note: Capacitor values are for a 3.0V integrator swing.
Manufactures of miniature quartz resonators include:
Epson of America
C-2 (through-hole), MC-306 (SMD)
Phone: (310) 787-6300; Fax: (310) 782-5320
Integrator Resistor
The integrator resistor sets the maximum integrator out-
put current for the integrate phase. A 602kΩlow-noise,
metal-film integrator resistor is recommended for use
with reference voltages between 545mV and 655mV.
Best linearity is achieved when the integration current
(IINT) does not exceed 2.5µA. For other reference volt-
ages, select RINT as follows:
Integrator Capacitor
The oscillator frequency, integrator resistor, and inte-
grator capacitor set the maximum integrator output volt-
age swing for full-scale reading. The integrator voltage
swing is about 3V and should not come within 2V of
either supply rail to avoid saturation. A 602kΩintegrator
resistor and a 4.7nF integrator capacitor are recom-
mended with a clock frequency of 32,768Hz. If different
clock frequencies are used, select CINT using the fol-
lowing equations:
The integrator capacitor’s dielectric absorption directly
affects integral nonlinearity. High-quality metal-film
capacitors are recommended in the following order of
preference: polypropylene, polystyrene, polycarbon-
ate, and polyester (Mylar). The polyester capacitor will
generate some integral nonlinearity.
To minimize noise, INT OUT should drive the outside
foil (negative end) of the capacitor. Manufacturers of
polypropylene capacitors include Sprague (715P),
Panasonic (ECQ-P), Roderstein (KP1835), Wima (FKP),
and CSF Thompson (PL/PS).
Reference Capacitor
The reference capacitor must be small enough to fully
charge from a discharged state on power-up in reason-
able time, and large enough so the charge does not
droop excessively during a conversion. The reference
capacitor is normally 0.1µF for all oscillator frequencies.
For applications that require a physically smaller capaci-
tor, the equation below will maintain CREF proportionality:
The reference capacitor must have low leakage, since
it stores the reference voltage while floating during the
deintegrate phase. Any leakage or charge loss during
this phase changes the scale factor and will cause an
error. Appropriate metal-film capacitors recommended
for their low-leakage characteristics1are (in this order):
polypropylene (up to +105°C, large size), teflon (suit-
able for use up to +125°C, large size), polystyrene,
polycarbonate, and polyester.
At temperatures above +85°C, capacitor leakage may
affect accuracy. In such cases, increasing the value of
CREF up to 50% and more will help at the expense of
longer start-up time at power-on. The start-up time is
proportional to CREF and can be estimated by:
Table 1. Crystal Frequencies and
Integrator Capacitors for 50Hz to 60Hz
Operation
Conv/sec
16
32
48
64
80
96
Crystal
Freq.
(Hz)
32,768
65,536
98, 304
131,072
163,840
196,608
CINT/60Hz
(pF)
4700
2700
1800
CINT/50Hz
(pF)
6800
3300
2000
1200
1000
820
1500
1200
1000
Resistor
(kΩ)
602
602
602
602
602
602
RV
AI A
and
IV
R
INT REF
INT
INT REF
INT
. .
=<<
=
25 05µµ
t
f
for Hz e
or
tffor Hz e
INT OSC
INT OSC
, mod
, mod
=
=
545 60
655 50
Cf
REF OSC
.
=
0 0033
tCFxxk
START UP REF−= () µ10 100 Ω
1Pease, R.A., “Understanding Capacitor Soakage to Optimize
Analog Systems,”
EDN
, October 13, 1982, p.125.
CVt
RV where V V V
and
INT IN FS INT
INT SWING SWING
() ()
() ( )
, . ;
()
=<<135
MAX132
±18-Bit ADC with Serial Interface
10 ______________________________________________________________________________________
___________________Digital Interface
Serial data at DIN is sent in 8-bit packets and is shifted
into the internal 8-bit shift register with each rising edge
of SCLK. The data is then latched into either command
input register 0 or command input register 1, as deter-
mined by the LSB of the data sent, and is latched on
the rising edge of CHIP SELECT (CS) Data is clocked
out of the selected output register on each falling edge
of SCLK. D7(MSB) must be the first data bit to be shift-
ed in and is the first bit to be shifted out.
Output data is shifted out at the same time command
data is shifted in. Command data must be clocked in
on the previous 8-bit read-write cycle to receive con-
version data in the present cycle.
Since there is no internal power-on reset, initialize the
MAX132 immediately after power-up to insure correct
operation.
Table 2 defines each bit of five registers: the two com-
mand input registers, output register 0, output register
1, and the status output register.
Command Input Register 0
Register-Set Bits
Data bits D1 and D2 of command register 0 (RS1 and
RS0) determine the data to be read on the data bus.
These bits select which register outputs data to the bus.
Table 3 defines the bit values that determine which reg-
ister is read on the next cycle (Figure 9).
Read-Zero Bit
The read-zero bit allows the ADC to calibrate on com-
mand for zero offset. The read-zero bit, when set to 1,
internally shorts the inputs; when a start-conversion
command is given, the zero error is converted. Subtract
the results from the standard external measurement
conversion when the read-zero conversion ends. If the
read-zero bit is set to 0, the converter measures the
voltage between IN Hl and IN LO once a start bit is
given. Take a new zero reading periodically and when-
ever the ambient temperature, the reference voltage, or
the common-mode input voltage are changed.
START,
READ STATUS
CYCLE 1
REGISTER
INSTRUCTION
(DATA IN)
OUTPUT DATA OUTPUT STATUS
REGISTER
(EOC, POLARITY, B2–B0)
READ HIGHER
BITS
CYCLE 2
REGISTER 1
( B11–B18)
READ LOWER
BITS
CYCLE 3
REGISTER 0
( B3–B10)
START,
READ STATUS
CYCLE 4
Figure 9. Instruction and Data Sequencing
RS1
0
0
1
RS0
0
1
0
DEFINITIONS
Selects Register 0; output for data bits B3–B10
Selects Register 1; output for data bits B11–B18
Selects Register 2; output status for data bits
B0–B2, polarity, sleep, integrating, EOC, and
collision bit
1 1 Invalid data
Command Input
Register 0
Command Input
Register 1
REGISTER
“1”
“0”
Start
Convert
Returns to
0 at EOC
Set P3
Output
Output Register 0
RS1 = 0, RS0 = 0
Output Register 1
RS1 = 0, RS0 = 1
“1”
50Hz
60Hz
Set P2
Output
B10
B18
MSB
Collision
B9
B17
EOC
Sleep
Awake
Set P1
Output
B8
B16
Integrating
Input
Table 3. Register Set-Bit Definitions
Table 2. Register Map of Input and Output Data
Read Zero
Read VIN
Set P0
Output
Don’t Care
Don’t Care
Don’t Care
RS0*
Don’t Care
B7
B15
Sleep
B6
B14
-Polarity
RS1*
Don’t Care
B5
B13
B4
B12
DATA BIT
0
1
B3
B11
Output Status
Register
RS1 = 1, RS0 = 0 “0” No Collision Converting Not
Integrating Awake +Polarity B2 B1 B0
LSB
*Note: Refer to Table 3.
D7 D6 D5 D4 D3 D2 D1 D0
MAX132
±18-Bit ADC with Serial Interface
______________________________________________________________________________________ 11
Averaging 2 or 3 read-zero measurements provides the
most accurate read-zero value. Perform a read-zero
sequence whenever a large change in the input voltage
is expected.
Sleep Bit
When the sleep bit is set to 1, (bit D5 in command input
register 0), the low-power sleep mode starts when EOC
returns high. In sleep mode, the supply current is typi-
cally 1µA and the oscillator shuts down. The interface
remains active and data can be read. When exiting
sleep mode, the analog circuitry needs time to stabilize
before the next conversion starts. Accomplish this by
writing a dummy instruction to emerge from sleep
mode, and wait at least one conversion cycle before
writing a start instruction.
50Hz/60Hz
With a 32,768Hz crystal, the 50Hz/60Hz bit sets the
integrate period equal to one line cycle for 50Hz/60Hz
environments. When D6 (in command input register 0)
is set to 0, the integrate count is an integer multiple of
60Hz (32,768Hz/60Hz = 546 counts). When D6 is set to
1, the integrate input count is an integer multiple of
50Hz (32,768Hz/50Hz = 655 counts). Achieve the
greatest AC rejection by adjusting the integration peri-
od for 50Hz or 60Hz.
Start Conversion Bit
The start conversion bit (D7) in command input register
0 initiates a conversion when set to 1. The MAX132
immediately starts a conversion, stops at conversion
end, and then waits for the next start-bit command. A
start instruction is needed to initiate each conversion.
To initiate a continuous data stream, write a separate
start command for each conversion in three ways:
1) Wait longer than a known conversion time and then
write another start command.
2) Poll either the EOC status register bit or the EOC
line to determine conversion end and start time for
the next conversion. EOC becomes 1 at conversion
end at count 0000 of the conversion counter (Figure
10).
3) Set the start bit to 1 before a conversion end. The
internal conversion counter is then checked for its
count. If the count is 0000 (EOC = 1), a new conver-
sion starts and the conversion counter is set to
0001. The start bit resets to 0 after 5 clock cycles.
The MAX132 will not check the start bit again until
the conversion counter returns to a 0000 count. This
means a start command can be given any time after
0005 internal conversion count; the next conversion
starts when the counter returns to 0000.
DE-1 DE-2 DE-3 DE-4X8-1 X8-2 X8-3 ZERO INT
ZERO INT
INT OUT
50Hz mode
INTEGRATE
264
545
655 38 145
679
MAX
545
MAX
SOFT
OVERRANGE
AREA
(SEE TEXT)
40 147 47 30
0001
0000 0111
INT START
RESET 60Hz
60Hz mode
659 667
CHOP 16001346 1638 1783 1823 1970 2017 2047 0000
RESET EVENTS
INTERNAL CONVERSION DATA LATCH LATCH
EOC
Figure 10. Conversion Timing (Negative Input Shown)
MAX132
±18-Bit ADC with Serial Interface
12 ______________________________________________________________________________________
Command Input Register 1
User-Programmable Output Bits P0 to P3
Command input register 1 always has data bit D0 = 1.
Data bits D4 to D7 of command register 1 control the
states of the user-programmable output pins P0 to P3,
respectively (Table 2). These four outputs can be used
to control an external multiplexer, programmable gain
amplifier, or other devices.
Output Registers
Output data is the sum of system offset (read zero) plus
the results of the external input voltage measurement.
Register 0
Register 0 contains the low-byte (bits B3–B10) conver-
sion data. New data is available after EOC goes high.
Access register 0 by setting RS0 and RS1 to 0.
Register 1
Register 1 contains the high-byte (bits B11–B18) data.
Data is in a twos-complement format‚ where the polarity
bit is a 1 for negative polarity data. Access register 1
by setting control bits RS0 = 1 and RS1 = 0 when writ-
ing to the command input register.
Status Register
Bits B0–B2
The B0, B1, and B2 bits are located in the status regis-
ter. At the end of each conversion these bits are updat-
ed and read back from the status register. For full
18-bit resolution, use bits B0–B2. Average multiple
results to increase accuracy. The polarity bit informa-
tion is necessary to determine if the reading is not in
overrange (Tables 4 and 5).
Integrate Bit
The integrate (INT) bit is set to 1 at the beginning of the
integration phase and becomes 0 at the end. Poll INT
to determine the earliest time the input can be changed
without affecting the conversion.
End-of-Conversion Bit
The end-of-conversion (EOC) bit signals conversion sta-
tus. If EOC is 1, the conversion is complete and the ADC
waits in zero-integrate mode at time = 0000 for the next
start instruction. A conversion cycle has 2048 counts.
EOC becomes 1 at count 0000 and 0 at count 0001.
Collision Bit
The collision bit warns the microprocessor (µP) that the
register’s data was changed during the read cycle. A
collision occurs if the internal result latches on the falling
edge of CS, causing the collision bit to be set to 1 on the
rising edge of the next CS. This occurs because these
two pulses are asynchronous. Once the status register is
Table 4. Overrange Values for
Resolution Used
Table 5. Output Values for 16-Bit
Resolution (Offset Corrected)
Bits
Used
B18–B3
B18–B2
B18–B1
Resolution
Bits
±15
±16
±17
B18–B0 ±18
Soft Overrange
Start Value
34,880
69,760
139,520
Hard Overrange
Maximum Value
43,805
87,610
175,220
279,040 350,440
Input
+640mV
+576mV
+545mV
Hexadecimal
Reading
+A000
+9000
+8840
Decimal
Counts
+40960*
+36864*
+34880*
+512mV
Comment
+8000
Positive Reference
Voltage
+32768 Positive Full Scale
+448mV
+384mV
+320mV
+7000
+6000
+5000
+28672
+24576
+20480
+256mV +4000 +16384
+192mV
+128mV
+15µV
+3000
+2000
+0001
+12288
+8192
+1
0 +0000 0
-15µV
-64mV
-128mV
-FFFF
-F000
-E000
-1
-4096
-8192
-192mV -D000 -12288
-256mV
-320mV
-384mV
-C000
-B000
-A000
-16384
-20480
-24576
-448mV -9000 -28672
-512mV
-545mV
-576mV
-8000
-77C0
-7000
-32768
-34880*
-36864*
-640mV
Negative Full Scale
-6000
Negative Reference
Voltage
-40960*
+64mV +1000 +4096
* Soft Overrange Operation
Note: The MAX132 exhibits additional errors when operating
in the soft overrange area. Operation in this region is not
included in the specifications. The soft overrange values listed
in Table 5 do not include error correction.
MAX132
±18-Bit ADC with Serial Interface
______________________________________________________________________________________ 13
read, the collision bit is automatically reset to 0. To deter-
mine collision status, read the status register collision bit
before and after reading output registers 0 and 1.
Collisions will not occur if a conversion’s read cycle is
completed before the next conversion begins.
Sequence Counter and Results Counter
A binary sequencing counter controls the conversion
phase’s sequencing (or timing). In integrate phase,
both start and stop occur at preset counts. The deinte-
gration phases start at predetermined counts, but are
terminated when the comparator detects zero crossing
at the integrator output.
The results counter accumulates counts during all dein-
tegrate phases. It is an up/down binary counter, with
the count direction determined by the deintegration
polarity. In the first deintegrate phase, the results
counter counts by 512. Since the second deintegrate
phase deintegrates a residual voltage multiplied by 8,
the results counter increments or decrements by 64
during this phase. It increments or decrements by 8
during the third deintegrate phase, and by 1 during the
fourth deintegrate phase. The results counter content
transfers to the results register at each conversion end.
Overrange Indication
B18 is not strictly an overrange bit. This 19th bit is nec-
essary to exploit the converter’s full range, and to
ensure that a full 18-bit result can be achieved after a
zero reading has been deducted.
The actual overrange value is a function of the number
of bits of resolution used. Table 4 lists the overrange
values for different resolutions.
The MAX132 has two overrange levels (Figure 10 and
Table 4). The first level is a soft overrange that is set by
the user. Overrange is arbitrarily set at a value, prefer-
ably less than the 279,040 (including any zero offset)
raw counts soft limit. A nonlinearity step of about 64
counts occurs at raw count 279,040 and again at
330,240 counts.
The second level is a hard overrange with a maximum
value of 350,440 counts. Attempts to deintegrate values
greater than this will result in a value of ±350,440 counts.
____Multislope Conversion Phases
Multislope conversion allows 350,440 counts with a clock
frequency of only 32.768kHz. After zero-crossing, the
main comparator (with some delay) sends a signal to the
digital control section, which then terminates the deinte-
grate period by issuing commands to the analog switch-
es. This action entails further delay because the
commands must be synchronous with the clock. As a
result, the delay between zero-crossing and switch actu-
ation can exceed one clock cycle. A “residue” voltage
that represents unwanted extra counts in the conversion
result is left on the capacitor, while the integrator’s output
continues past the zero crossing.
Dual-slope converters ignore this residue voltage error.
However, the multislope MAX132 inverts, amplifies, and
deintegrates the residue, canceling the extra counts by
driving an up/down counter in the opposite direction.
This process of measuring and accounting for the residue
can be repeated for the successively smaller errors
remaining after each deintegration. (Deintegration is sim-
ply an integration of VREF, with polarity chosen so the inte-
grator output ramps toward zero.) The MAX132, for
example, executes three cycles in which the residue is
inverted, multiplied by eight, and deintegrated (Figure 10).
Integrate Phase
The MAX132 integrates the input signal by connecting
the integrator’s noninverting input to IN LO, and the
buffer input to IN Hl. The integration period is 545
counts for 60Hz mode and 655 counts for 50Hz
Deintegrate Phase
The integrator capacitor’s voltage polarity at the end of
integrate phase determines the polarity of the first dein-
tegration phase. The first deintegration phase ends
when the comparator detects that the integration
capacitor has been discharged. The MAX132 then
goes into a rest phase, where both the buffer input and
the integrator’s noninverting input are connected to
AGND, integrating the system offset.
Near the end of the maximum allowable deintegration
period, the integrator capacitor voltage polarity is again
sampled, resulting in either a positive or negative dein-
tegrate cycle.
Rest Phase
A rest phase follows each deintegrate phase. The rest
phase starts when the integrator crosses zero and ends
when the maximum count for that deintegration phase
has been reached.
First Times-Eight Phase
When the zero crossing is detected at the end of the
deintegrate phase, deintegration continues until the
next clock cycle. This causes the integrator to over-
shoot zero crossing slightly, leaving a small residual
voltage on the integration capacitor. The first times-
eight (X8) phase inverts and multiplies this residual by
a factor of 8.
MAX132
Second Deintegrate Phase
The second deintegrate phase deintegrates residual
voltage on the integration capacitor that has been
through the X8 phase. Since the voltage across the
integration capacitor has been multiplied by 8, each
deintegration clock cycle corresponds to 1/8 of one
clock cycle during the first deintegration.
Additional Times-Eight
and Deintegrate Phases
At the end of the second and third deintegration phas-
es, the device performs a X8 multiplication of the resid-
ual voltage left on the integration capacitor. After each
of these X8 multiplications, a deintegration occurs,
resulting in a second, third, and fourth deintegration
phase. Each time the residual voltage on the integration
capacitor is multiplied by 8, the following deintegration
has 8 times finer resolution.
Zero-Integrate Phase
The zero-integrate phase zeros out the integrator to
prepare for the next integration (Figure 10). This phase
occurs at the beginning and end of each conversion. At
power-up, or in the hold mode prior to a conversion, the
MAX132 continues to zero integrate until a conversion
starts. When a conversion starts in 60Hz mode, another
111 clocks of zero integrate are completed before the
beginning of a conversion. In 50Hz mode, only one
additional zero integrate is performed before the con-
version starts. An additional 20 clocks of zero integrate
occur at each conversion end.
__________Applications Information
Extended Delays Between Conversions
An extended delay between conversions can degrade
the subsequent conversion result due to capacitor
droop and internal offset/common-mode voltages. The
initial reading may be off by 4 to 6 counts in a ±15-bit
configuration. When the delay between conversions
exceeds 2 seconds (either because of a slower conver-
sion rate or the use of sleep mode), it is recommended
that the first reading after this delay be discarded.
Increased Speed
The MAX132 is tested with a 32,768Hz clock frequen-
cy, which results in 16 conv/sec. Up to 96 conv/sec
may be achieved with higher clock frequencies and
some changes in component values, as shown in Table
1. Operation at higher conversion rates reduces accu-
racy, and care must be taken to get the best results.
Although either the 50Hz or 60Hz mode can be used,
complete rejection of 50Hz or 60Hz normal-mode noise
at conversion rates above 16 conv/sec is impossible.
Use the 50Hz mode when operating at more than 16
conv/sec, irrespective of the local line frequency. The
50Hz mode uses a slightly longer integration time than
the 60Hz mode, and generally gives lower-noise perfor-
mance.
Table 1 lists the crystal frequencies and integrating
capacitor values for the 50Hz and 60Hz modes for vari-
ous conversion rates, although the 50Hz mode is rec-
ommended for clock rates above 32,768Hz.
The raw data can be used where highest accuracy is
not required, and the least significant bits can be
ignored. At 96 conv/sec, the accuracy is 13 bits.
Improvements in accuracy can be gained by averaging
both the data and the zero readings, although data
averaging compromises the converter’s speed perfor-
mance.
To maximize throughput, take zero readings only when
necessary, i.e., when the common-mode voltage
changes. It is not normally necessary to take a zero read-
ing after every data reading‚ as an excessive number of
zero readings reduces the converter’s effective speed.
Noise Reduction
To minimize noise, each supply must be bypassed to
GND with a 0.1µF capacitor. A ground plane should
also be placed under the analog circuitry. Use the RC
network at the inputs as shown in Figure 6. Also refer to
the section “Noise Reduction Techniques” in the notes
for the MAX132 evaluation kit. To minimize the coupling
effects of stray capacitance, keep digital lines as far
from analog components and lines as possible. Also,
connect the integrator capacitor’s outside foil to the INT
OUT pin to minimize stray capacitive coupling. If possi-
ble, keep the digital interface inactive while the
MAX132 is converting.
Ratiometric Measurements
Figure 11 shows an application to measure tempera-
ture ratiometrically with an RTD sensor. The voltage
drops across the RTD sensor and the 250Ωreference
resistor are generated by the same current source. The
voltage of the sensor (VS) is fed directly into the differ-
ential inputs, and the voltage drop across the reference
resistor (VR) is brought into the differential reference
inputs. The relationship of these voltages is ratiometric
and unaffected by the actual current. The MAX132’s
output is proportional to VSdivided by VR, independent
±18-Bit ADC with Serial Interface
14 ______________________________________________________________________________________
MAX132
±18-Bit ADC with Serial Interface
______________________________________________________________________________________ 15
MAX132
RW2
RW1
V- V+
DGND
IN
GND
AGND
RW1, RW2 WIRE RESISTANCE
4.096V 1
13
CS
VS
250Ω
0.1%
2k
600k
0.1µF10µF
2
DIN
3DOUT
4SCLK
11 EOC
7PG0
8PG1
VR9PG2
10 PG3
14 IN HI
15
23
24
-5V +5V
22
21
19
20
18
17
5
6
12 16
IN LO
BUF OUT
INT OUT
OUT
INT IN 4.7nF
32,768Hz
CREF+
CHIP SELECT
DATA IN
DATA OUT
SERIAL-
DATA
INTERFACE
CLOCK
RTD
PT100
CREF-
REF+ IN
REF- IN
OSC2
OSC1
IC2
MAX872
IC1
0.1µF
0.1µF
10µF
+5V
Figure 11. Ratiometric Configuration Using the Differential Reference Inputs
SPI is a trademark of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.
of the overall accuracy of the current source. The cur-
rent source delivers 2mA, resulting in about 500mV
across the 250Ωresistor—suitable to fit the MAX132’s
±512mV full-scale range. Note that the accuracy of the
reference resistor (0.1%) sets the circuit’s accuracy.
The power consumption of the RTD sensor is small
(0.5mW), minimizing errors caused by self-heating.
Interfacing to a µP Parallel Port
Figure 12 shows a high-level software subroutine for
reading output/status data and writing command data
to the MAX132. It provides an algorithm for serial com-
munication when the µP port does not have a prede-
fined serial interface protocol (i.e., SPI™ or Microwire™).
The routine sends command data (TxByte) to the
MAX132 while concurrently collecting the MAX132’s
output register data (selected by the previous write
cycle). Note that a write is required before each read to
change the next output register to be read, and that
the subroutine must be repeated three times to read
the output status register, Output Register 0, and
Output Register 1.
MAX132
±18-Bit ADC with Serial Interface
16 ______________________________________________________________________________________
___________________Chip Topography
INT IN
SCLK
PG2 EOC DGND IN HI AGND
PG3 V- IN LO
0.186"
(4.72mm)
0.144"
(3.66mm)
DOUT DINCS V+ BUF OUT
INT OUT
OSC2
OSC1
PG0
PG1
CREF-
CREF+
REF+
REF-
TRANSISTOR COUNT: 2799
SUBSTRATE CONNECTED TO V+
Figure 12. MAX132 Read/Write Algorithm
WAIT UNTIL EOC PIN IS HIGH
CLEAR SCLK
CLEAR CS
SET CS
RETURN RxByte
WRITE DIN132 FROM TxByte’s MSB
SET SCLK
READ DOUT132 INTO RxByte’s LSB
CLEAR SCLK
SHIFT RxByte LEFT
SHIFT TxByte LEFT
REPEAT 8 TIMES
