SN54LVC646A, SN74LVC646A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCAS302G - JANUARY 1993 - REVISED JUNE1998 D D D D D D description The SN54LVC646A octal bus transceiver and register is designed for 2.7-V to 3.6-V VCC operation and the SN74LVC646A octal bus transceiver and register is designed for 1.65-V to 3.6-V VCC operation. These devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that are performed with the 'LVC646A. SN74LVC646A . . . DB, DW, OR PW PACKAGE (TOP VIEW) CLKAB SAB DIR A1 A2 A3 A4 A5 A6 A7 A8 GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC CLKBA SBA OE B1 B2 B3 B4 B5 B6 B7 B8 SN54LVC646A . . . FK PACKAGE (TOP VIEW) DIR SAB CLKAB NC VCC CLKBA SBA D EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25C Power Off Disables Outputs, Permitting Live Insertion Support Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) ESD Protection Exceeds 2000 V Per MIL-STD-833, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW) Packages, and Ceramic Chip Carriers (FK) A1 A2 A3 NC A4 A5 A6 5 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 4 3 19 11 12 13 14 15 16 17 18 OE B1 B2 NC B3 B4 B5 A7 A8 GND NC B8 B7 B6 D NC - No internal connection Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port is stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when OE is low. In the isolation mode (OE high), A data is stored in one register and B data can be stored in the other register. When an output function is disabled, the input function is still enabled and can be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN54LVC646A, SN74LVC646A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCAS302G - JANUARY 1993 - REVISED JUNE1998 description (continued) Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54LVC646A is characterized for operation over the full military temperature range of -55C to 125C. The SN74LVC646A is characterized for operation from -40C to 85C. FUNCTION TABLE INPUTS DATA I/O OE DIR CLKAB CLKBA SAB SBA A1-A8 B1-B8 X X X X X Input Unspecified OPERATION OR FUNCTION X X X X X Unspecified Input Store A, B unspecified Store B, A unspecified H X X X Input Input Store A and B data H X H or L H or L X X Input disabled Input disabled Isolation, hold storage L L X X X L Output Input Real-time B data to A bus L L X H or L X H Output Input Stored B data to A bus L H X X L X Input Output Real-time A data to B bus L H H or L X H X Input Output Stored A data to B bus The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions always are enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54LVC646A, SN74LVC646A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS 21 OE L 3 DIR L 1 23 CLKAB CLKBA X X 2 SAB X BUS B BUS A BUS A BUS B SCAS302G - JANUARY 1993 - REVISED JUNE1998 22 SBA L 21 OE L 3 DIR H 3 DIR X X X 1 23 CLKAB CLKBA X X 2 SAB L 2 SAB X X X 22 SBA X BUS B BUS A BUS A 21 OE X X H 23 CLKBA X REAL-TIME TRANSFER BUS A TO BUS B BUS B REAL-TIME TRANSFER BUS B TO BUS A 1 CLKAB X 22 SBA X X X STORAGE FROM A, B, OR A AND B 21 OE L L 3 DIR L H 1 CLKAB X H or L 23 CLKBA H or L X 2 SAB X H 22 SBA H X TRANSFER STORED DATA TO A AND/OR B Figure 1. Bus-Management Functions POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN54LVC646A, SN74LVC646A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCAS302G - JANUARY 1993 - REVISED JUNE1998 logic symbol OE DIR CLKBA SBA CLKAB SAB A1 21 3 23 22 1 G3 3 EN1 [BA] 3 EN2 [AB] C4 G5 C6 2 G7 1 4 1 7 1 A3 A4 A5 A6 A7 A8 B1 1 2 7 5 19 6 18 7 17 8 16 9 15 10 14 11 13 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, and PW packages. 4 20 5 1 6D A2 4D 5 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 B2 B3 B4 B5 B6 B7 B8 SN54LVC646A, SN74LVC646A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCAS302G - JANUARY 1993 - REVISED JUNE1998 logic diagram (positive logic) OE DIR CLKBA SBA CLKAB SAB 21 3 23 22 1 2 One of Eight Channels 1D C1 A1 4 20 B1 1D C1 To Seven Other Channels Pin numbers shown are for the DB, DW, and PW packages. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SN54LVC646A, SN74LVC646A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCAS302G - JANUARY 1993 - REVISED JUNE1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Input voltage range, VI: (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) SN54LVC646A VCC Supply voltage VIH High-level input voltage Operating Data retention only VIL Low-level input voltage VI Input voltage VO Output voltage IOH High level output current High-level IOL Low level output current Low-level t/v Input transition rise or fall rate MAX MIN MAX 2 3.6 1.65 3.6 1.5 1.5 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V SN74LVC646A MIN 0.65xVCC 1.7 2 V V 2 0.35xVCC 0.7 VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V UNIT 0.8 V 0.8 0 5.5 0 5.5 V High or low state 0 0 VCC 5.5 0 3 state VCC 5.5 V 0 VCC = 1.65 V VCC = 2.3 V -4 -8 VCC = 2.7 V VCC = 3 V -12 -12 -24 -24 VCC = 1.65 V VCC = 2.3 V mA 4 8 VCC = 2.7 V VCC = 3 V 12 12 24 0 10 mA 24 0 10 ns/V TA Operating free-air temperature -55 125 -40 85 C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54LVC646A, SN74LVC646A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCAS302G - JANUARY 1993 - REVISED JUNE1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS 2.7 V to 3.6 V IOH = -4 mA IOH = -8 mA Control inputs 2.2 3V 2.4 2.4 3V 2.2 2.2 0.2 2.7 V to 3.6 V 0.2 0.45 0.7 IOL = 12 mA IOL = 24 mA 2.7 V 0.4 0.4 3V 0.55 0.55 VI = 0 to 5.5 V 3.6 V 5 5 A VO = 0 to 5.5 V VI = VCC or GND 3.6 V VI 5.5 V IO = 0 VI = VCC or GND 36V 3.6 2.7 V to 3.6 V V 10 A 15 10 A 10 10 10 10 500 500 0 3.6 V One input at VCC - 0.6 V, Other inputs at VCC or GND Control inputs 2.2 2.3 V VI or VO = 5.5 V Ci V 1.7 2.7 V 1.65 V IOZ ICC 1.2 IOL = 4 mA IOL = 8 mA Ioff ICC VCC-0.2 1.65 V to 3.6 V IOL = 100 A UNIT VCC-0.2 2.3 V IOH = -24 mA II MIN 1.65 V IOH = -12 12 mA VOL SN74LVC646A TYP MAX MIN 1.65 V to 3.6 V IOH = -100 100 A VOH SN54LVC646A TYP MAX VCC A A 3.3 V 4.5 4.5 pF Cio A or B ports VO = VCC or GND 3.3 V All typical values are at VCC = 3.3 V, TA = 25C. For I/O ports, the parameter IOZ includes the input leakage current. This applies in the disabled state only. 7.5 7.5 pF timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 4) SN54LVC646A VCC = 2.7 V MIN fclock tw Clock frequency MAX VCC = 3.3 V 0.3 V MIN 150 UNIT MAX 150 MHz Pulse duration 3.3 3.3 ns tsu Setup time, data before CLK 1.6 1.5 ns th Hold time, data after CLK 1.7 1.7 ns POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SN54LVC646A, SN74LVC646A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCAS302G - JANUARY 1993 - REVISED JUNE1998 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 2 through 4) SN74LVC646A VCC = 1.8 V 0.15 V MIN fclock tw Clock frequency tsu VCC = 2.5 V 0.2 V MAX MIN MAX VCC = 2.7 V MIN MAX VCC = 3.3 V 0.3 V MIN 150 UNIT MAX 150 MHz Pulse duration 3.3 3.3 ns Setup time, data before CLK 1.6 1.5 ns 1.7 1.7 ns th Hold time, data after CLK This information was not available at the time of publication. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 4) SN54LVC646A FROM (INPUT) PARAMETER TO (OUTPUT) VCC = 2.7 V MIN fmax MAX 150 A or B tpd B or A CLK A or B SBA or SAB VCC = 3.3 V 0.3 V MIN UNIT MAX 150 MHz 7.9 1 7.4 8.8 1 8.4 9.9 1 8.6 ns ten OE A 10.2 1 8.2 ns tdis OE A 8.9 1 7.5 ns ten DIR B 10.4 1 8.3 ns tdis DIR B 8.7 1 7.9 ns switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 2 through 4) SN74LVC646A PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 1.8 V 0.15 V MIN fmax A or B tpd MAX CLK SBA or SAB B or A A or B VCC = 2.5 V 0.2 V MIN MIN MAX 150 VCC = 3.3 V 0.3 V MIN UNIT MAX 150 MHz 7.9 1.4 7.4 8.8 1.3 8.4 9.9 1.4 8.6 ns ten OE A 10.2 1 8.2 ns tdis OE A 8.9 1 7.5 ns ten DIR B 10.4 1.2 8.3 ns DIR B 8.7 1.1 7.9 ns tdis This information was not available at the time of publication. 8 MAX VCC = 2.7 V POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54LVC646A, SN74LVC646A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCAS302G - JANUARY 1993 - REVISED JUNE1998 operating characteristics, TA = 25C TEST CONDITIONS PARAMETER Cpd Power dissipation capacitance per transceiver Outputs enabled Outputs disabled f = 10 MHz VCC = 1.8 V 0.15 V VCC = 2.5 V 0.2 V VCC = 3.3 V 0.3 V TYP TYP TYP 75 9 UNIT pF This information was not available at the time of publication. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 SN54LVC646A, SN74LVC646A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCAS302G - JANUARY 1993 - REVISED JUNE1998 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V 0.15 V 2 x VCC S1 1k From Output Under Test Open GND CL = 30 pF (see Note A) 1k TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC Open LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at Open (see Note B) VOL + 0.15 V VOL tPHZ tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 x VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input VCC/2 VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54LVC646A, SN74LVC646A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCAS302G - JANUARY 1993 - REVISED JUNE1998 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V 2 x VCC S1 500 From Output Under Test Open GND CL = 30 pF (see Note A) 500 TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 x VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input VCC/2 VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 SN54LVC646A, SN74LVC646A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCAS302G - JANUARY 1993 - REVISED JUNE1998 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V 0.3 V 6V S1 500 From Output Under Test Open GND CL = 50 pF (see Note A) 500 TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 0V 0V VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V 0V tPLH tPHL VOH 1.5 V 2.7 V Output Control (low-level enabling) 1.5 V 1.5 V VOL tPLZ 3V Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) 1.5 V 0V tPZL 2.7 V Output Input 1.5 V 1.5 V tsu Input 1.5 V 1.5 V tPZH VOL + 0.3 V VOL tPHZ 1.5 V VOH - 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 4. Load Circuit and Voltage Waveforms 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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