fax id: 5209 CY7B131 CY7B141 Features * 0.8-micron BiCMOS for high performance Automatic power-down TTL compatible Capable of withstanding greater than 2001V electro- static discharge Fully asynchronous operation Master CY7B131 easily expands data bus width to 16 or more bits using slave CY7B141 BUSY output flag on CY7B131; BUSY input on CY7B141 * INT flag for port-to-port communication Functional Description The CY7B131 and CY7B141 are high-speed BiCMOS 1K by 8 dual-port static RAMS. Two ports are provided to permit in- dependent access to any location in memory. The CY7B131 1Kx8 Dual-Port Static RAM can be utilized as either a standalone 8-bit dual-port static RAM or as a MASTER dual-port RAM in conjunction with the CY7B141 SLAVE dual-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requir- ing shared or buffered data such as cache memory for DSP, bit-slice, or multiprocessor designs. Each port has independent control pins; chip enable (CE), write enable (RAW), and output enable (OE). BUSY flags are provided on each port. In addition, an interrupt flag (INT) is provided on each port. BUSY signals that the port is trying to access the same location currently being accessed by the oth- er port. The INT is an interrupt flag indicating that data has been placed in a unique location (3FF for the right port and 3FE for the left port). An automatic power-down feature is controlled independently on each port by the chip enable (CE) pins. The CY7B131/CY7B141 are available in 52-lead PLCC. Logic Block Diagram RAN R/Wr CE, CER OE, OER Ag. Aor Ag. Agr VoL COLUMN COLUMN Vor - vo ~ Or. 0 VO7R BUSY,!1] BUSY,l"] ATL ROW MEMORY ROW ATR SELECT ARRAY SELECT Ao Aor Aor ARBITRATION LOGIC (7B131 ONLY) Aor AND INTERRUPTLOGIC TNT [2] INTR?2! B131-1 Notes: 1. CY7B131 (Master): BUSY is an open drain output and requires a pull-up resistor. CY7B141 (Slave): BUSY is an input. 2. Open drain outputs; pull-up resistor required. www.DataSheet4U.com Cypress Semiconductor Corporation > 3901 North First Street CA 95134 + 408-943-2600 June 1995 Revised August 1995 SanJose CY7B131 CY7B141 Pin Configuration 52-Lead PLCC Top View asvebewsed Bes 765 4 3 2 1 5251 50 4948 47 __ AL 46[] OER Aat 4517] Aor Ast 44] Air Aae 430] Aor AsL 420] Asr Ag 73131 410] Aar An 7B144 40] Asp Ast 391] Aer AaL 33f) Azz VOoL 371) Aer VOqL 36] Aor VOo. 35X01 NC VOsL 0 3411 VO7p 21 22 23 24 25 26 27 28 29 30 31 32 33 a qcoeoeece ae - SPST HS TTH STFS OM Selection Guide 7B131-15 7B131-20 7B141-15 7B141-20 Maximum Access Time (ns) 15 20 Maximum Operating Current (mA) ComI/Ind 260 240/300 Maximum Standby Current (mA) ComI/Ind 110 100/105 Maximum Ratings Output Current into Outputs (LOW).......... ee 20 mA . . . . . Static Disch Voltage ooo... eee eeeceeee rete te ere 2001V (Above which the useful life may be impaired. For user guide- (pet MIL-STD 283, Merhod 3015) * lines, not tested.) Latch-Up C A Storage Temperature soccccccecsssssssessssssseee 65C to +150C atch-Up Current... ieee >200 m Ambient Temperature with Operating Range Power Applied .............cccccccceesesseestteeeetees 5C to 125C Supply Voltage to Ground Potential Ambient (Pin 52 to Pin 26) ... vctsstsisistisss uses -0.5V to 7.0V Range Temperature Vec DC Voltage hepled to > Outputs Commercial 0C to +70C 5V + 10% in High Z Stat . bitter 0.5V to 7.0V eng Ne industrial 40C to +85C BV + 10% DC Input Voltage voce eeeeteseeteeeetesereeeesteneteeeeeneees -3.5V to +7.0V www.DataSheet4U.comCY7B131 CY7B141 Electrical Characteristics Over the Operating Range! 7B131-15 7B131-20 7B141-15 7B141-20 Parameter Description Test Conditions Min. | Max. | Min. | Max. | Unit Vou Output HIGH Voltage Voc = Min., loy =-4.0 mA 2.4 2.4 Vv Voi Output LOW Voltage Io, = 4.0 mA 0.4 0.4 Vv lo, = 16.0 mal] 0.5 0.5 Vin Input HIGH Voltage 2.2 2.2 Vv Vit Input LOW Voltage 0.8 0.8 Vv lix Input Load Current GND <V\< Voc -10 | +10 | -10 | +10 HA loz Output Leakage GND <Vo<Vec. -10 | +10 | -10 |} +10 HA Current Output Disabled loc Voc Operating CE = Vip Outputs Open, Com! 260 240 | mA Supply Current f = fax Ind 300 Ispy Standby Current Both Ports, |CE, and CER > Vin, Com! 110 100 | mA TTL Inputs f = fax Ind 105 Igpo Standby Current One Port, |CE, or CER > Vin, Com! 165 155 | mA TTL Inputs Active Fort Outputs Open, Ind 180 f = fax Igp3 Standby Current Both Ports, |Both Ports CE, and Com! 15 15 mA GMOS Inputs CER2> Voc -0.2V, Ind 30 Vin > Vec -0.2Vor Vins 0.2V, f=0 Ispq Standby Current One Port, | One Port CE, or Com! 160 150 | mA CMOS Inputs CER> Vcc - 0.2V, Ind 170 Vin > Voc -02Vor Vin < 0.2V, Active Port Outputs Open, f =fvax?! Capacitance"! Parameter Description Test Conditions Max. Unit c Input Capacitance Ta = 25C, f = 1 MHz, 10 F IN p p Veo = 5.0V p Court Output Capacitance 10 pF Notes: 3. See the last page of this specification for Group A subgroup testing information. 4. BUSY and INT pins only. 5. At f=fyax, address and data inputs are cycling at the maximum frequency of read cycle of 1/,, and using AC Test Waveforms input levels of GND to 3V. 6. Tested initially and after any design or process changes that may affect these parameters.CY7B131 CY7B141 AC Test Loads and Waveforms] 5V Sy R1 8930, Sy R1 8930, OUTPU OUTPU 2810 / f BUSY 30 pF $ R2 5 pF = Re OR | 1 | J 3470 INT INCLUDING + INCLUDING 4 L 30 pF JIG AND ~ - JIG AND ~ - = aise SCOPE a) SCOPE (b) BIS68 - BUSY Output Load (CY7B136ONLY) ALL INPUT PULSES 90% Equivalent to: THE VENIN EQUIVALENT 2500. QUTPUTo_~w0 1.4 Switching Characteristics Over the Operating Rangel: 71 7B131-15 7B131-20 7B141-15 7B141-20 Parameter Description Min. Max. Min. Max. Unit READ CYCLE tre Read Cycle Time 15 20 ns taa Address to Data Valid!l 15 20 ns toHA Data Hold from Address Change 3 3 ns tace CE LOW to Data Valid! 15 20 ns tpor OE LOW to Data Valid!l 10 13 ns tLZ0E OE LOW to Low Zl 3 3 ns tHZz0E OE HIGH to High Z/ 14] 10 13 ns tLZcE TE LOW to Low ZI 3 3 ns tzcE CE HIGH to High ZI: 10] 10 13 ns tpy CE LOW to Power-Up 9) 0 ns tpp CE HIGH to Power-Down 15 20 ns Notes: 7. Testconditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified loflon, and 30-pF load capacitance. 8. AC test conditions use Voy = 1.6V and Vo, = 1.4V. 9. Atany given temperature and voltage condition for any given device, tyzck Is less than t_zce and tyzo. is less than t_zog. 10. tizce. tLawe: tHzo0E: 1Lz08, tHzce. 4nd tyzwe are tested with CL = 5pF as in part (b) of AC Test Loads. Transition is measured +500 mV from steady-state voltage.CY7B131 CY7B141 Switching Characteristics Over the Operating Range 71 (Continued) 7B131-15 7B131-20 7B141-15 7B141-20 Parameter Description Min. | Max. Min. Max. Unit WRITE CYCLE!" twe Write Cycle Time 15 20 ns toce CE LOW to Write End 12 15 ns taw Address Set-Up to Write End 12 15 ns tHa Address Hold from Write End 2 2 ns tsa Address Set-Up to Write Start 0 0) ns tpwe RWW Pulse Width 42 15 ns tsp Data Set-Up to Write End 10 13 ns tub Data Hold from Write End 0 0 ns tuzwe R/W LOW to High Z 10 13 ns tLzwe R/W HIGH to Low Z 3 3 ns BUSY/INTERRUPT TIMING tBLA BUSY LOW from Address Match 15 20 ns tBHA BUSY HIGH from Address Mismatchl'2] 15 20 ns taLc BUSY LOW from CE LOW 15 20 ns tpHc BUSY HIGH from CE HIGHI!"2] 15 20 ns tps Port Set Up for Priority ns twp!!!) R/W LOW after BUSY LOW ns tw R/W HIGH after BUSY HIGH 13 20 ns tgpp BUSY HIGH to Valid Data 15 20 ns tppp Write Data Valid to Read Data Valid!"4] 25 30 ns twop Write Pulse to Data Delayl!'4] 30 40 ns INTERRUPT TIMING twins RW to INTERRUPT Set Time 15 20 ns teins CE to INTERRUPT Set Time 15 20 ns tins Address to INTERRUPT Set Time 15 20 ns toInR OE to INTERRUPT Reset Timel!'@! 15 20 ns tEINR CE to INTERRUPT Reset Timel!4] 15 20 ns tinr Address to INTERRUPT Reset Timel!@] 15 20 ns Notes: 11. The internal write time of the memory is defined by the overlap of CE LOW and RAW LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write. 12. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state. 13. CY7B141 only. 14. For information on port-to-port delay through RAM cells, from writing port to reading port, refer to the Read Timing with Port-to-Port Delay timing diagram.CY7B131 =a CYPRESS Switching Waveforms Read Cycle No. 1 (Either PortAddress Access)!'. 161 >! tac ADDRESS me +* tonn >} tAA DATA OUT PREVIOUS DATA vaLioK XK KK KK DATA VALID B131- 5 Read Cycle No. 2 (Either PortCE/OE)!'5. 17] ce J _ tacE e- tHZCE o> N Ze tHZOE {*<_~ bor tLZ0E p<- tzce DATA OUT SEEKER DATA VALID s teu < tpp loc Isp B131- 6 Read Cycle No. 3 (Read with BUSY Master: CY7B131) ADDRESS R/We Dinr ADDRES_ Notes: 15. R/Wis HIGH for read cycle. __ __ 16. Device is continuously selected, CE = V)_ and OE = Vi. 17. Address valid prior to or coincident with CE transition LOW. tre ADDRESS MATCH tPWE ADDRESS MATCHCY7B131 CY7B141 Switching Waveforms (Continued) Write Cycle No. 1 (OE Three-States Data I/Os Either Port)!": 18] two ADDRESS XK mK NN LILA taw tae Isa =__ tpwe RW NX Ok x 4-$ tsp te tip if x CE Y, DATAIN DATA VALID lA ~& tHZ0E HIGH IMPEDANCE Dout B131- 8 Write Cycle No. 2 (R/E Three-States Data /Os Either Port)!"!: 19] ADDRESS CE R/W tsp tHD DATAW DATA VALID _ tlzwe TON NN NN NN ON NN NN OS HIGH IMPEDANCE STITT. Dut PYLZZZLZLLLLL LLL LH oS B131- 9 Notes: 18. If OE is LOW during a RW controlled write cycle, the write pulse width must be the larger of tpye or tyzwe + tgp to allow the data I/O pins to enter high impedance and for data to be placed on the bus for the required tgp. 19. Ifthe CE LOW transition occurs simultaneously with or after the RAW LOW transition, the outputs remain in a high-impedance state.CY7B131 CY7B141 Switching Waveforms (Continued) Read Timing with Port-to-Port Delay (CE, =CER=LOW, BUSY=HIGH for the Writing Port) tee two ADDRES MATCH * RWe r bwe y iN / sp ~pobee pe HD DATAINR * fe VALID x ADDRESS , x MATCH tppp | DATAouTL VALID ju_ tw B131-10 Write Timing with Port-toPort Delay (CE_=CEpR=LOW) hw two ADDRESS p MATCH Ke NO MATCH R/Wr towe +, tgp tub DATAIN3 x VALID ADDRESS \ L > 4 MATCH xK DATAIN. VALID RAW tgp 3 tup t towe __y let BUSY) rm BHA eta, B131-11CY7B131 CY7B141 Switching Waveforms (Continued) Busy Timing Diagram No. 1 (CE Arbitration) CE, Valid First: ADDRESS 1.2 x ADDRESS MATCH x CE. tps > fa gl tBLc < tBHC BUSY, B131-12 CE R Valid First: ADDRESS, R x ADDRESS MATCH x CER tps > EL tBLc < tBHC BUSY, B131-13 Busy Timing Diagram No. 2 (Address Arbitration) Left Address Valid First: taootwo_ ADDRESS , * ADDRESS MATCH WK ADDRESS MISMATCH x a tps ADDRESS p x BLA eet BHA BUSY, B131-14 Right Address Valid First: tac ortwc -e ADDRESS R ADDRESS MATCH WK ADDRESS MISMATCH x ~< tps ADDRESS , x BLA eet BHA BUSY, B131-15CY7B131 : CY7B141 =a CYPRESS Switching Waveforms (Continued) Busy Timing Diagram No.3 (Write with BUSY, Slave: CY7B141) CE \ rate tpWE RAV Too Sf \ )) twa wo BUSY B131-16 Intercept Timing Diagrams Left Side Sets INT two ADDRESS WRITE 3FF tINS B131-17 Right Side Clears INT tre FS ADDRESSpR READ 3FF _ fe tHA tinR > CER K tEINR ats ILI IIL LLL ory WANNA AK f ml < tolnR > INTR A Bisi-18 Right Side Sets INT, two ADDRESSR x* WRITE 3FE KX x __ tng ta o-oo CE p _ tens * RW R WT r< tsa twins INTL \ \ B131-19 10CY7B131 CY7B141 Intercept Timing Diagrams (Continued) Left Side Sets INTp ADDRESS, f THA tre READ 3FE tINR Vf CEL yy tEINR am. SIZZL LL LL LZ oO NIL Architecture The CY7B131 (master) and CY7B141 (slave) are 1024-byte deep dual-port RAMs, with two independent sets of address signals, common I/O data signals, and control signals. By con- vention, the two ports are called the left port and the right port. The subscript R or L on the signal name identifies the port. The upper two memory locations (3FF, 3FE) are special loca- tions and may be used as mailboxes for passing messages between the ports. Location 3FF is the mailbox for the right port and location 3FE is the mailbox for the left port. When one port writes to the other ports mailbox, an interrupt is gen- erated to the owner of the mailbox. When the owner reads the mailbox, the interrupt is reset. The address and control signals provide independent, asyn- chronous, random access to any location in the memory. It is possible that both ports may attempt to access the same mem- ory location at the same time. If this contention occurs, a circuit in the master called an arbiter decides which port temporarily owns the memory location. The losing port receives a BUSY signal, which notifies it that the memory location is owned by the other port and that the operation it attempted to perform may not be successful. The two BUSY signals are outputs from the master and inputs to the slave. Contention, Arbitration and Resolution The Significance of BUSY When contention occurs, the arbiter decides which port wins (owns) the memory location and which port loses. The deci- sion is on a first-come-first-served basis. In order for conten- tion to occur, both ports must address the same memory loca- tion and have their respective chip enables active. If one port precedes the other by an amount of time greater than or equal totPS (port set-up for priority;equal to five nanoseconds) it is guaranteed to win the arbitration. If contention occurs within the tPS interval, it is not possible to predict which port will win, but one will win and the other will lose. There are two ports and each may be either reading or writing, and each may win or lose, so there are eight combinations. They are listed in Table 1 and identified as cases one through EL ASAD SW OOD 11 toINR ~~ / B131-20 eight. In cases one and two, both ports are reading, the losing port receives a BUSY, the read is allowed to occur, and the data read by both ports is valid. In case three, the left port wins and reads valid data, and the write attempted by the right port is inhibited. In cases four and five, when the winning port is writing, the write is completed, but the data read by the losing port may be invalid. Case six is similar to case three; the right port successfully reads and the write attempt by the left port is inhibited. In cases seven and eight the winning port success- fully writes and the attempted write by the losing port is inhib- ited. In cases four and five, where the losing port is reading, if the port signals are asynchronous to each other, the data read may be the old data, the new data, or some random combina- tion of the two sets of data. In cases seven and eight the losing port is prevented from writing. The commonality between these four cases is that the losing port receives a busy signal, which tells it that either (1) the operation it attempted was not successful, or (2) that the data it read may not be valid. In either situation, the operation should be repeated after the busy signal becomes inactive. Flow-Through Operation The CY7B131/141 have a flow-through architecture that facil- itates repeating (actually extending) an operation when a BUSY is received by a losing port. The BUSY signal should be interpreted as a NOT READY. Ifa BUSY to a port is active, the port should wait for BUSY to go inactive, and then extend the operation it was performing for another cycle. The timing diagram titled, Read Timing with Port-to-Port Delay illus- trates the case where the right port is writing to an address and the left port reads the same address. The data that the right port has just written flows through to the left, and is valid either twop after the falling edge of the write strobe of the left port, or tppp after the data being written becomes stable. The timing diagram titled, Write Timing with Port-to-Port De- lay illustrates the case where the right port is writing to an address and the left port wants to write to the same address. If the left port extends its write strobe for a minimum time of tpwe after the BUSY signal to it goes inactive, its write will be successful; it writes over the data just written by the right port.CY7B131 Data Bus Width Expansion Using Slaves One master and as many slaves as necessary may be con- nected in parallel to expand the data bus width in byte incre- ments. Two masters must not be connected in parallel because, if the time interval between which they address the same location is less than tpg, both could end up waiting for the other to release the BUSY to it. Therefore, only one master must arbitrate, and it can drive as many slaves as required. The write strobe to the slaves must be delayed an amount of time equal to at least tg),a. This insures that the slave is not inadvertently written to before the outcome of the arbitration is determined. 12 CY7B141 Table 1. Operation. Operation Port Winning Case L R Port Result 1 R R L Both Read 2 R R R Both Read 3 R W L L Reads OK, R Write Inhibited 4 R W R R Writes OK L Data May Be Invalid 5 W R L L writes OK R Data May Be Invalid 6 W R R R Reads OK L Write Inhibited 7 W W L L Writes OK R Write Inhibited 8 W W R R Writes OK L Write InhibitedCY7B131 CY7B141 Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 14 Isp 1.2 5 on ~ = 1.0 8 G a "og Gy a N N 06 ed a = <x = 04 hs 5 z 2 0.2 lec 0.0 4.0 4.5 5.0 55 6.0 SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.10 s Ta= 25C 3 a a Ni 1.05 V4 N | | =z =z S S| S g g 21.00 N Zz 0.95 4.0 45 5.0 55 6.0 SUPPLYVOLTAGE (V) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 1.0 We 5 0.75 N s 3 /\_|: 0.50 <t FE rs 9 / a 0.25 / 0.0 aa 10 20 30 4. SUPPLY VOLTAGE (V) 5.0 NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.2 T lec 1.0] 0.8;- 'ses 0.6 Voc = 5.0V Vin= 5.0V 0.4 0.2 0.6 55 25 125 AMBIENT TEMPERATURE (C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 1.2 14 LZ 1.0 J Vec = 5.0V 0.9 TL 0.8 -55 25 125 AMBIENT TEMPERATURE (C) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 20.0 near 15.0 ws 10.0 7 Veco = 45V 5.0 Ta= 25C 0 | | 0 200 400 600 800 1000 CAPACITANCE (pF) 13 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE =a oe Oo nN Bf oO oO Oo 60 40 20 OUTPUT SOURCE CURRENT (mA) 2.0 3.0 40 50 o 1.0 OUTPUT VOLTAGE(V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE AW y a oO ice) oO 70 / Voc = 5.0V / Ta= 25C _/ | | 10 20 30 40 50 OUTPUT VOLTAGE (V) 60 OUTPUT SINK CURRENT (mA) 50 0.0 NORMALIZED Iccvs. CYCLE TIME 1.25 T Vec = 5.0V Ta= 25C Vin = 0.5V cc Lf ~ 0.75 NORMALIZED | | 20 30 40 CYCLE FREQUENCY (MHz) Le 0.50 10 50CY7B131 CY7B141 Ordering Information Speed Package Operating (ns) Ordering Code Name Package Type Range 15 CY7B131-15JC J69 52-Lead Plastic Leaded Chip Carrier Commercial 20 CY7B131-20JC J69 52-Lead Plastic Leaded Chip Carrier Commercial CY7B131-20Jl J69 52-Lead Plastic Leaded Chip Carrier Industrial Document #: 38-00466 Package Diagram 52-Lead Plastic Leaded Chip Carrier J69 DIMENSIONS IN INCHES MIN. MAX, 0.785, 0.793 0.750 0.756 0.023 L 0.020 MIN. 0,090 0.130 Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.