5-A H-Bridge for DC-Motor Applications TLE 5206-2 Preliminary Data Overview Features * * * * * * * * * * * * Delivers up to 5 A continuous 6 A peak current Optimized for DC motor management applications Operates at supply voltages up to 40 V Very low RDS ON; typ. 200 m @ 25 C per switch Output full short circuit protected Overtemperature protection with hysteresis and diagnosis Short circuit and open load diagnosis with open drain error flag Undervoltage lockout CMOS/TTL compatible inputs with hysteresis No crossover current Internal freewheeling diodes Wide temperature range; - 40 C < Tj < 150 C Type Ordering Code Package TLE 5206-2 Q67000-A9290 P-TO220-7-11 TLE 5206-2GP Q67006-A9239 P-DSO-20-10 TLE 5206-2G Q67006-A9323 P-TO263-7-1 TLE 5206-2S Q67000-A9326 P-TO220-7-12 P-TO220-7-11 P-DSO-20-10 P-TO263-7-1 Description The TLE 5206-2 is an integrated power H-bridge with DMOS output stages for driving DC-Motors. The part is built using the SIEMENS multi-technology process SPT(R) which allows bipolar and CMOS control circuitry plus DMOS power devices to exist on the same P-TO220-7-12 monolithic structure. Operation modes forward (cw), reverse (ccw), brake high and brake low are invoked from just two control pins with TTL/CMOS compatible levels. The combination of an extremely low RDS ON and the use of a power IC package with low thermal resistance and high thermal capacity helps to minimize system power dissipation. A blocking capacitor at the supply voltage is the only external circuitry due to the integrated freewheeling diodes. Semiconductor Group 1 1998-04-29 TLE 5206-2 TLE 5206-2 1 2 3 4 5 TLE 5206-2GP 6 7 GND N.C. N.C. N.C. N.C. VS Q1 EF 1 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 GND N.C. N.C. N.C. N.C. VS Q2 N.C. 2 GND AEP01680 TLE 5206-2S EF OUT1 GND IN1 VS IN2 OUT2 AEP01990 TLE 5206-2G 1 2 3 4 5 6 1 2 7 3 4 5 6 7 OUT1 IN1 IN2 OUT2 EF GND V S AEP01991 OUT1 EF IN1 IN2 GND OUT2 VS AEP02513 Figure 1 Pin Configuration (top view) Semiconductor Group 2 1998-04-29 TLE 5206-2 Pin Definitions and Functions Pin No. P-TO220 Pin No. P-DSO Symbol Function 1 7 OUT1 Output of channel 1; Short-circuit protected; integrated freewheeling diodes for inductive loads. 2 8 EF Error flag; TTL/CMOS compatible output for error detection; (open drain) 3 9 IN1 Control input 1; TTL/CMOS compatible 4 1, 10, 11, 20 GND Ground; internally connected to tab 5 12 IN2 Control input 2; TTL/CMOS compatible 6 6, 15 VS Supply voltage; block to GND 7 14 OUT2 Output of channel 2; Short-circuit protected; integrated freewheeling diodes for inductive loads. - 2, 3, 4, 5, N.C. 16, 17, 18, 19 Semiconductor Group Not connected 3 1998-04-29 TLE 5206-2 VS EF 6 2 Error Flag Diagnosis and Protection Circuit 1 IN1 IN2 IN 1 2 OUT 1 2 0 0 1 1 0 1 0 1 0 0 1 1 3 5 1 0 1 0 1 7 OUT1 OUT2 Diagnosis and Protection Circuit 2 4 GND Figure 2 AEB02405 Block Diagram Circuit Description Input Circuit The control inputs consist of TTL/CMOS-compatible schmitt-triggers with hysteresis. Buffer amplifiers are driven by this stages. Output Stages The output stages consist of a DMOS H-bridge. Integrated circuits protect the outputs against short-circuit to ground and to the supply voltage. Positive and negative voltage spikes, which occur when switching inductive loads, are limited by integrated freewheeling diodes. A monitoring circuit for each output transistor detects whether the particular transitor is active and in this case prevents the corresponding source transistor (sink transistor) from conducting in sink operation (source operation). Therefore no crossover currents can occur. Semiconductor Group 4 1998-04-29 TLE 5206-2 Input Logic Truth Table Functional Truth Table IN1 IN2 OUT1 OUT2 Comments L L L L Brake; both low side transistors turned-ON L H L H Motor turns counterclockwise H L H L Motor turns clockwise H H H H Brake; both high side transistors turned-ON Notes for Output Stage Symbol Value L Low side transistor is turned-ON High side transistor is turned-OFF H High side transistor is turned-ON Low side transistor is turned-OFF Semiconductor Group 5 1998-04-29 TLE 5206-2 Monitoring Functions Undervoltage lockout (UVLO): When VS reaches the switch on voltage VS ON the IC becomes active with a hysteresis. All output transistors are switched off if the supply voltage VS drops below the switch off value VS OFF. Protective Function Various errors like short-circuit to + VS, ground or across the load are detected. All faults result in turn-OFF of the output stages after a delay of 50 s and setting of the error flag EF to ground. Changing the inputs resets the error flag. a. Output Shorted to Ground Detection If a high side transistor is switched on and its output is shorted to ground, the output current is internally limited. After a delay of 50 s all outputs will be switched-OFF and the error flag is set. b. Output Shorted to + VS Detection If a low side transistor is switched on and its output is shorted to the supply voltage, the output current is internally limited. After a delay of 50 s all outputs will be switched-OFF and the error flag is set. c. Overload Detection An internal circuit detects if the current through the low side transistor exceeds the trippoint ISDL. In this case all outputs are turned off after 50 s and the error flag is set. d. Overtemperature Protection At a junction temperature higher than 150 C the thermal shutdown turns-OFF, all four output stages commonly and the error flag is set with a delay. Semiconductor Group 6 1998-04-29 TLE 5206-2 Diagnosis Various errors as listed in the table "Diagnosis" are detected. Short circuits and overload result in turning off the output stages after a delay (tdoff for short circuit) and setting the error flag simultaneously [EF = L]. Changing the inputs to a state where the fault is not detectable resets the error flag (input toggling) with the exception of short circuit from OUT1 to OUT2 (load short circuit). Flag IN1 IN2 OUT1 OUT2 EF Remarks Short circuit from OUT1 to OUT2 Short circuit from OUT1 to GND Short circuit from OUT2 to GND Short circuit from OUT1 to VS Short circuit from OUT2 to VS Overtemperature or undervoltage IN: 0 = Logic LOW 1 = Logic HIGH OUT: 0 0 1 1 0 1 0 1 L X X H L X X H 1 0 0 1 Not detectable 0 0 1 1 0 1 0 1 GND GND GND GND L X L X 1 1 0 0 Not detectable Not detectable 0 0 1 1 0 1 0 1 L L X X GND GND GND GND 1 0 1 0 Not detectable 0 0 1 1 0 1 0 1 VS VS VS VS X H X H 0 0 1 1 0 0 1 1 0 1 0 1 X X H H VS VS VS VS 0 1 0 1 0 0 1 1 0 1 0 1 Z Z Z Z Z Z Z Z 0 0 0 0 Z = Output in tristate condition L = Output in sink condition EF: Not detectable Not detectable Not detectable Not detectable Not detectable Not detectable 1 = No error 0 = Error H = Output in source condition X = Voltage level undefined For Open circuit detection, use the TLE 5205-2. Semiconductor Group 7 1998-04-29 TLE 5206-2 Electrical Characteristics Absolute Maximum Ratings - 40 C < Tj < 150 C Parameter Symbol Limit Values Unit Remarks min. max. - 0.3 40 V - -1 40 V - 0.3 7 V t < 0.5 s; IS > - 5 A 0 V < VS < 40 V - 0.3 7 V - Voltages Supply voltage Logic input voltage Diagnostics output voltage VS VIN1, 2 VEF Currents of DMOS-Transistors and Freewheeling Diodes Output current (cont.) Output current (peak) Output current (peak) IOUT1, 2 IOUT1, 2 IOUT1, 2 -5 5 A - -6 6 A - - A tp < 100 ms; T = 1 s tp < 50 s; T = 1 s; internally limitted; see overcurrent Temperatures Tj Tstg - 40 150 C - - 50 150 C - Junction case RthjC - 3 K/W P-TO220-7-11/12, P-TO263-7-1 Junction ambient RthjA - 65 K/W P-TO220-7-11/12 - 75 K/W P-TO263-7-1 - 5 K/W P-DSO-20-10 - 50 K/W P-DSO-20-10 Junction temperature Storage temperature Thermal Resistances Junction case Junction ambient RthjC RthjA Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. Semiconductor Group 8 1998-04-29 TLE 5206-2 Operating Range Parameter Symbol Limit Values Unit min. Supply voltage VS Remarks max. VUV ON 40 After VS rising above V VUV ON - 0.3 VUV ON V VUV OFF V Outputs in tristate condition - 0.3 7 V - - 40 150 C - Supply voltage increasing - 0.3 Supply voltage decreasing Logic input voltage Junction temperature VIN1, 2 Tj Electrical Characteristics 6 V < VS < 18 V; IN1 = IN2 = HIGH IOUT1, 2 = 0 A (No load); - 40 C < Tj < 150 C; unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max. IS - - 10 mA IN1 = IN2 = LOW; VS = 13.2 V VUV ON VUV OFF VUV HY - 5 6 V 3.5 4.4 - V 0.2 0.6 - V VS increasing VS decreasing VUV ON - VUV OFF Current Consumption Quiescent current Under Voltage Lockout UV-Switch-ON voltage UV-Switch-OFF voltage UV-ON/OFF-Hysteresis Semiconductor Group 9 1998-04-29 TLE 5206-2 Electrical Characteristics (cont'd) 6 V < VS < 18 V; IN1 = IN2 = HIGH IOUT1, 2 = 0 A (No load); - 40 C < Tj < 150 C; unless otherwise specified Parameter Symbol Limit Values min. Unit Test Condition typ. max. 200 400 m 6 V < VS < 18 V Tj = 25 C - 650 m 6 V < VS < 18 V 350 500 m - 800 m 200 400 m - 650 m 400 600 m - 1000 m VS ON < VS 6 V Tj = 25 C VS ON < VS 6 V 6 V < VS < 18 V Tj = 25 C 6 V < VS < 18 V VS ON < VS 6 V Tj = 25 C VS ON < VS 6 V Outputs OUT1, 2 Static Drain-Source-On Resistance Source IOUT = - 3 A Sink RDS ON H - RDS ON L - IOUT = 3 A Note: Values of RDS ON for VS ON < VS 6 V are guaranteed by design. Overcurrent Source shutdown trippoint - ISDH 6 9 - A - Sink shutdown trippoint ISDL tdSD 6 9 - A - 25 50 80 s - Source current - ISCH - - 20 A Sink current ISCL - - 15 A t < tdSD t < tdSD Shutdown delay time Short Circuit Semiconductor Group 10 1998-04-29 TLE 5206-2 Electrical Characteristics (cont'd) 6 V < VS < 18 V; IN1 = IN2 = HIGH IOUT1, 2 = 0 A (No load); - 40 C < Tj < 150 C; unless otherwise specified Parameter Symbol Limit Values min. typ. Unit Test Condition max. Output Delay Times (device active for t > 1 ms) Source ON td ON H - 7.5 20 s IOUT = - 3 A resistive load Sink ON td ON L - 7.5 20 s IOUT = 3 A resistive load Source OFF td OFF H - 5 20 s IOUT = - 3 A resistive load Sink OFF td OFF L - 5 20 s IOUT = 3 A resistive load Output Switching Times (device active for t > 1 ms) Source ON tON H - 15 30 s IOUT = - 3 A resistive load Sink ON tON L - 5 10 s IOUT = 3 A resistive load Source OFF tOFF H - 2 5 s IOUT = - 3 A resistive load Source OFF tOFF L - 2 5 s IOUT = 3 A resistive load Clamp Diodes Forward Voltage High-side Low-side VFH VFL - 1 1.5 V - 1.1 1.5 V IF = 3 A IF = 3 A ILKH ILKL - 200 - - A OUT1 = VS - 200 A OUT2 = GND Leakage Current Source Sink Semiconductor Group - 11 1998-04-29 TLE 5206-2 Electrical Characteristics (cont'd) 6 V < VS < 18 V; IN1 = IN2 = HIGH IOUT1, 2 = 0 A (No load); - 40 C < Tj < 150 C; unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max. VINH VINL VINHY IINH IINL 2.8 - - V - - - 1.2 V - 0.4 0.8 1.2 V - -2 - 2 A - 10 -4 0 A VIN = 5 V VIN = 0 V VEFL IEFL - 0.2 0.5 V - - 10 A IEF = 3 mA VEF = 7 V Thermal shutdown junction temperature TjSD 150 175 200 C - Thermal switch-on junction temperature TjSO 120 - 170 C - Temperature hysteresis T - 30 - K - Logic Control Inputs IN 1, 2 H-input voltage threshold L-input voltage Hysteresis of input voltage H-input current L-input current Error Flag Output EF Low output voltage Leakage current Thermal Shutdown Semiconductor Group 12 1998-04-29 TLE 5206-2 FU ; S EF IN1 V EF IN2 V IN1 6 2 3 5 EF VS IN1 TLE 5206-2 IN2 V IN2 4700 F 63 V 470 nF OUT1 OUT2 1 OUT1 7 OUT2 R Load VS GND V OUT1 V OUT2 4 FL AES02406 Figure 3 Test Circuit IOUT Semiconductor Group Overcurrent Short Circuit Open Circuit ISD ISC IOC 13 1998-04-29 TLE 5206-2 VIN V 5 t r = t f <_ 100 ns 50% t 0 OUT Source t dONH t dOFFH A 3 90% 50% 10% 0 OUT Sink A 3 90% 50% 10% t ONH t OFFH t OFFL t ONL 90% 50% 10% 0 t 90% 50% 10% t dOFFL t t dONL AET01994 Figure 4 Switching Time Definitions +5V +V S 2 k 2 P 100 F 6 3 5 EF VS IN1 TLE 5206-2 IN2 OUT1 1 100 nF OUT2 7 M N =3A BL = 6 A GND 4 AES02407 Figure 5 Application Circuit Semiconductor Group 14 1998-04-29 TLE 5206-2 Application Modes 1. Simple CW/CCW-Control For low-cost application simple CW/CCW-Control without any speed regulation is recommended. A low-speed two-line interface is sufficient for the brake low, clockwise, counter clockwise and brake high command. 2. Sign/Magnitude Control For this mode two ports with PWM capability are necessary. Motor turns clockwise (current flows from OUT1 to OUT2; means: OUT1 is switched HIGH continuously and OUT2 is PWM controlled. To achieve motor counter clockwise turning change input signals to: IN1 = PWM; IN2 = H. IN2 PWM Motor speed =0 = 0.1 = 0.5 = 0.9 =1 Fastest High Medium Low t Brake to Zero V OUT1 - V OUT2 VS Motor Short Circuit 0 t AED02408 Figure 6 Input/Output Diagram for CW Operation (IN1 = H) 3. Locked Anti-Phase Control The most important advantage to drive a motor in locked anti-phase mode is: Only one variable duty cycle signal is necessary in which is encoded both direction- and amplitude information. So the interface is very simple: A PWM input driven by a dedicated PWM port from P. Semiconductor Group 15 1998-04-29 TLE 5206-2 IN1, 2 SCH SDH OUT1, 2 R Short x SCH VOUT1, 2 t dSD V FL EF AED01997 Figure 7 Timing Diagram for Output Shorted to Ground IN1, 2 SCL SDL OUT1, 2 VOUT1, 2 VS R Short x SCL V FU t dSD EF AED01998 Figure 8 Timing Diagram for Output Shorted to VS Semiconductor Group 16 1998-04-29 TLE 5206-2 Diagrams Quiescent Current IS (active) versus Junction Temperature Tj AED02398 7 S Static Drain-Source ON-Resistance versus Junction Temperature Tj AED02399 0.6 mA R ON 6 0.5 5 0.4 Low Side Transistor V S = 18 V 4 0.3 0.2 3 VS =6V 2 1 -50 0 50 100 High Side Transistor 0.1 0 -50 C 150 0 50 100 Tj Tj Input Switching Thresholds VINH, L versus Junction Temperature Tj Clamp Diode Forward Voltage VF versus Junction Temperature Tj AED02400 3.0 V INH, L C 150 AED02401 1.3 VF V INH 1.2 2.5 High Side Transistor 1.1 2.0 V INL 1.5 1.0 1.0 0.9 0.5 0.8 0 -50 0 50 100 0.7 -50 C 150 0 50 100 C 150 Tj Tj Semiconductor Group Low Side Transistor 17 1998-04-29 TLE 5206-2 Overcurrent Shutdown Threshold ISD versus Junction Temperature Tj AED02402 12 SD 10 Low Side Transistor 8 High Side Transistor 6 4 2 0 -50 0 50 100 C 150 Tj Error-Flag Saturation Output Voltage VEF versus Junction Temperature Tj AED02403 0.6 V EF 0.5 0.4 0.3 0.2 0.1 0 -50 0 Semiconductor Group 50 100 C 150 Tj 18 1998-04-29 TLE 5206-2 Package Outlines P-TO220-7-11 (Plastic Transistor Single Outline Package) 10 0.2 A 9.8 0.15 0...0.15 3.7 0.3 10.2 0.3 0.05 0.25 0.5 0.1 2.4 7x 0.6 0.1 1.27 9.25 0.2 1.27 0.1 8.6 0.3 C 1) 4.4 2.8 0.2 1) 13.4 15.65 0.3 17 0.3 8.5 1) 3.7 -0.15 3.9 0.4 M A C 8.4 0.4 Typical All metal surfaces tin plated, except area of cut. GPT09083 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". Semiconductor Group 19 Dimensions in mm 1998-04-29 TLE 5206-2 B 5 3 0.02 0.25 +0.0 7 - 1.3 1.2 -0.3 11 0.15 1) 2.8 3.5 max. 0 +0.15 3.25 0.1 P-DSO-20-10 (Plastic Dual Small Outline Package) 15.74 0.1 1.27 0.4 Index Marking 0.1 6.3 +0.13 0.25 M 20 11 1 1 x 45 10 A 20x 14.2 0.3 Heatsink 0.95 0.15 0.25 M B 15.9 0.15 1) A 1) Does not include plastic or metal protrusion of 0.15 max. per side Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 20 GPS05791 Dimensions in mm 1998-04-29 TLE 5206-2 P-TO263-7-1 Option E3180 (Plastic Transistor Single Outline Package) 10 0.2 4.4 9.8 0.15 1.27 0.1 B 0.1 0.05 2.4 2.7 0.3 4.7 0.5 8 1) 9.25 0.2 (15) 10.3 A 8.5 1) 0...0.15 7x0.6 0.1 0.5 0.1 6x1.27 8 max. 1) M A B Typical All metal surfaces tin plated, except area of cut. Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 21 0.1 GPT09114 0.25 Dimensions in mm 1998-04-29 TLE 5206-2 P-TO220-7-12 (Plastic Transistor Single Outline Package) 10 0.2 A 9.8 0.15 B 0...0.15 13 0.5 0.05 0.5 0.1 7x 0.6 0.1 1.27 9.25 0.2 1.27 0.1 110.5 C 1) 4.4 2.8 0.2 1) 13.4 17 0.3 15.65 0.3 8.5 1) 3.7 -0.15 2.4 0.25 M A B C Typical All metal surfaces tin plated, except area of cut. GPT09084 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". Semiconductor Group 22 Dimensions in mm 1998-04-29