APPLICATIONCIRCUIT
PGND
ROUT−
PVDD
PVDD
RHPIN
RLINEIN
RIN
VDD
VDD
LIN
LLINEIN
LHPIN
LOUT−
1ROUT+
SE/BTL
HP/LINE
VOLUME
SEDIFF
SEMAX
AGND
BYPASS
FADE
SHUTDOWN
LOUT+
PGND
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
17
18
19
20
21
22
23
24
CS
Ci
Ci
Ci
Ci
Ci
Ci
CS
CS
RightHP
AudioSource
PowerSupply
RightLine
AudioSource
LeftLine
AudioSource
LeftHP
AudioSource
PowerSupply
VDD
100kW
100kW
CC
InFromDAC
or
Potentiometer
(DCVoltage)
C(BYP)
SystemControl
CC
Right
Speaker
Left
Speaker
Headphones
1kW
1kW
S001
DCVOLUMECONTROL
Volume[Pin21] − V
Gain − dB
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
10
20
VolumeUp
VolumeDown
VDD =5.0V
BTLOutput
R =NoLoad
L
GAIN(BTL)
vs
VOLUMEVOLTAGE
TPA6013A4
www.ti.com
SLOS635 –NOVEMBER 2009
3-W STEREO AUDIO POWER AMPLIFIER
WITH ADVANCED DC VOLUME CONTROL
Check for Samples :TPA6013A4
1FEATURES DESCRIPTION
2• Advanced 32-Steps DC Volume Control
– Steps from –40 to 18 dB The TPA6013A4 is a stereo audio power amplifier
that drives 3 W/channel of continuous RMS power
– Fade Mode into a 3-Ωload. Advanced dc volume control
– Maximum Volume Setting for SE Mode minimizes external components and allows BTL
– Adjustable SE Volume Control (speaker) volume control and SE (headphone)
Referenced to BTL Volume Control volume control. Notebook and pocket PCs benefit
from the integrated feature set that minimizes
• 3 W Into 3-ΩSpeakers external components without sacrificing functionality.
• Stereo Input MUX To simplify design, the speaker volume level is
• Headphone Mode adjusted by applying a dc voltage to the VOLUME
• Pin-to-pin compatible with TPA6011A4 and terminal. Likewise, the delta between speaker volume
TPA6012A4 and headphone volume can be adjusted by applying
a dc voltage to the SEDIFF terminal. To avoid an
• 24-pin PowerPAD™ Package (PWP) unexpected high volume level through the
headphones, a third terminal, SEMAX, limits the
APPLICATIONS headphone volume level when a dc voltage is
• Notebook PC applied. Finally, to ensure a smooth transition
• LCD Monitors between active and shutdown modes, a fade mode
• Pocket PC ramps the volume up and down.
Figure 1. Application Circuit and DC Volume Control
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPA6013A4
SLOS635 –NOVEMBER 2009
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE OPTIONS
PACKAGE
TA24-PIN TSSOP (PWP) (1)
–40°C to 85°C TPA6013A4PWP
(1) The PWP package is available taped and reeled. To order a taped
and reeled part, add the suffix R to the part number
(e.g., TPA6013A4PWPR).
LEAD (PB-FREE) ORDERING INFORMATION
ORDERABLE DEVICE STATUS (1) ECO-STATUS (2)
TPA6013A4PWPG4 Active Pb-Free
and Green
TPA6013A4PWPRG4 Active
(1) The marketing status values are defined as follows:
(a) ACTIVE: This device recommended for new designs.
(b) LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
(c) NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using
this part in a new design.
(d) PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
(e) OBSOLETE: TI has discontinued production of the device.
(2) Eco-Status Information – Additional details including specific material content can be accessed at www.ti.com/leadfree
(a) N/A: Not yet available Lead (Pb)-Free, for estimated conversion dates go to www.ti.com/leadfree.
(b) Pb-Free: TI defines "Lead (Pb)-Free" or "Pb-Free" to mean RoHS compatible, including a lead concentration that does not exceed
0.1% of total product weight, and, if designed to be soldered, suitable for use in specified lead-free soldering processes.
(c) Green: TI devices "Green" to mean Lead (Pb)-Free and in addition, uses package materials that do not contain halogens, including
bromine (Br), or antimony (Sb) above 0.1% of total product weight.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
VSS Supply voltage, VDD, PVDD –0.3 V to 6 V
VIInput voltage –0.3 V to VDD+0.3 V
Continuous total power dissipation See Dissipation Rating Table
TAOperating free-air temperature range –40°C to 85°C
TJOperating junction temperature range –40°C to 150°C
Tstg Storage temperature range –65°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
TA≤25°C DERATING FACTOR TA= 70°C TA= 85°C
PACKAGE POWER RATING ABOVE TA= 25°C POWER RATING POWER RATING
PWP 2.7 mW 21.8 mW/°C 1.7 W 1.4 W
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SLOS635 –NOVEMBER 2009
RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT
VSS Supply voltage, VDD, PVDD 4.0 5.5 V
SE/BTL, HP/LINE, FADE 0.8 × VDD V
VIH High-level input voltage SHUTDOWN 2 V
SE/BTL, HP/LINE, FADE 0.6 × VDD V
VIL Low-level input voltage SHUTDOWN 0.8 V
TAOperating free-air temperature –40 85 °C
ELECTRICAL CHARACTERISTICS
TA= 25°C, VDD = PVDD = 5.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD = 5.5 V, Gain = 0 dB, SE/BTL = 0 V 2 30 mV
| VOO | Output offset voltage (measured differentially) VDD = 5.5 V, Gain = 18 dB, SE/BTL = 0 V 2.6 50 mV
PSRR Power supply rejection ratio VDD = PVDD = 4.0 V to 5.5 V, Gain = 0 dB –80 dB
High-level input current (SE/BTL, FADE, HP/LINE, VDD = PVDD = 5.5 V,
| IIH | 1 μA
SHUTDOWN, SEDIFF, SEMAX, VOLUME) VI= VDD = PVDD
Low-level input current (SE/BTL, FADE, HP/LINE,
| IIL | VDD = PVDD = 5.5 V, VI= 0 V 1 μA
SHUTDOWN, SEDIFF, SEMAX, VOLUME) VDD = PVDD = 5 V, SE/BTL = 0 V, 6.7 9.0
SHUTDOWN = 2 V
IDD Supply current, no load mA
VDD = PVDD = 5 V, SE/BTL= 5 V, 4.5 6
SHUTDOWN = 2 V
VDD = 5 V = PVDD, SE/BTL = 0 V,
IDD Supply current, max power into a 3-Ωload SHUTDOWN = 2 V, RL= 3Ω, 1.5 ARMS
PO= 2 W, stereo
IDD(SD) Supply current, shutdown mode SHUTDOWN = 0.0 V 10 25 μA
OPERATING CHARACTERISTICS
TA= 25°C, VDD = PVDD = 5 V, RL= 3 Ω, Gain = 6 dB, Stereo (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
THD = 1%, f = 1 kHz, RL= 16 Ω(SE) 195 mW
THD = 10%, f = 1 kHz, RL= 16 Ω(SE) 235 mW
POOutput power THD = 1%, f = 1 kHz, RL= 3 Ω(BTL) 2.0 W
THD = 10%, f = 1 kHz, VDD = 5.5 V, RL=3 Ω(BTL) 3.2
THD+N Total harmonic distortion + noise PO= 0.9 W, RL= 8 Ω(BTL), f = 20 Hz to 20 kHz <0.1%
PO= 0.1 W, RL= 16 Ω(SE), f = 20 Hz to 20 kHz 0.03%
VOH High-level output voltage RL= 8 Ω, Measured between output and VDD = 5.5 V 700 mV
RL= 8 Ω, Measured between output and GND,
VOL Low-level output voltage 400 mV
VDD = 5.5 V
V(Bypass) Bypass voltage (Nominally VDD/2) Measured at pin 17, No load, VDD = 5.5 V 2.65 2.75 2.85 V
BTL (4Ω) –66 dB
Supply ripple rejection ratio f = 1 kHz, Gain = 0 dB, C(BYP) = 1 µF SE (32Ω) –60 dB
BTL 110 dB
Crosstalk SE 102 dB
f = 20 Hz to 20 kHz, Gain = 0 dB,
Noise output voltage BTL 36 µVRMS
C(BYP) = 1 µF
ZIInput impedance (see Figure 17) VOLUME = 5 V 12 kΩ
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 3
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1
2
3
4
5
6
7
8
9
11
10
12
24
23
22
21
20
19
18
17
16
14
15
13
PWP Package
(TopView)
P0110-01
PGND
ROUT−
PVDD
PVDD
RHPIN
RLINEIN
RIN
VDD
LIN
LLINEIN
LHPIN
LOUT−
ROUT+
SE/BTL
HP/LINE
VOLUME
SEDIFF
SEMAX
AGND
BYPASS
FADE
SHUTDOWN
LOUT+
PGND
TPA6013A4
SLOS635 –NOVEMBER 2009
www.ti.com
PIN Functions
PIN I/O DESCRIPTION
NAME NO.
PGND 1, 13 – Power ground
LOUT– 12 O Left channel negative audio output
PVDD 3, 11 – Supply voltage terminal for power stage
LHPIN 10 I Left channel headphone input, selected when HP/LINE is held high
LLINEIN 9 I Left channel line input, selected when HP/LINE is held low
LIN 8 I Common left channel input for fully differential input. AC ground for single-ended inputs.
VDD 7 – Supply voltage terminal
RIN 6 I Common right channel input for fully differential input. AC ground for single-ended inputs.
RLINEIN 5 I Right channel line input, selected when HP/LINE is held low
RHPIN 4 I Right channel headphone input, selected when HP/LINE is held high
ROUT– 2 O Right channel negative audio output
ROUT+ 24 O Right channel positive audio output
SHUTDOWN 15 I Places the amplifier in shutdown mode if a TTL logic low is placed on this terminal
Places the amplifier in fade mode if a logic low is placed on this terminal; normal operation if a logic
FADE 16 I high is placed on this terminal
BYPASS 17 I Tap to voltage divider for internal mid-supply bias generator used for analog reference
AGND 18 – Analog power supply ground
SEMAX 19 I Sets the maximum volume for single ended operation. DC voltage range is 0 to VDD.
SEDIFF 20 I Sets the difference between BTL volume and SE volume. DC voltage range is 0 to VDD.
VOLUME 21 I Terminal for dc volume control. DC voltage range is 0 to VDD.
Input MUX control. When logic high, RHPIN and LHPIN inputs are selected. When logic low, RLINEIN
HP/LINE 22 I and LLINEIN inputs are selected.
Output MUX control. When this terminal is high, SE outputs are selected. When this terminal is low,
SE/BTL 23 I BTL outputs are selected.
LOUT+ 14 O Left channel positive audio output.
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Power
Management
32-Step
Volume
Control
MUX
Control
R
MUX
RHPIN
ROUT+
SHUTDOWN
ROUT-
PVDD
PGND
VDD
BYPASS
AGND
LOUT+
LOUT-
RLINEIN
RIN
HP/LINE
VOLUME
SEDIFF
SEMAX
FADE
_
+
HP/LINE
_
+
_
+
BYP
_
+
BYP
BYP EN SE/BTL
L
MUX _
+
HP/LINE
_
+
_
+
BYP
_
+
BYP
BYP EN SE/BTL
SE/BTL
LHPIN
LLINEIN
LIN
TPA6013A4
www.ti.com
SLOS635 –NOVEMBER 2009
FUNCTIONAL BLOCK DIAGRAM
NOTE: All resistor wipers are adjusted with 32-step volume control.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 5
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SLOS635 –NOVEMBER 2009
www.ti.com
Table 1. DC Volume Control (BTL Mode, VDD = 5 V)(1)
VOLUME (PIN 21) GAIN OF AMPLIFIER
(Typ) (2)
FROM (V) TO (V)
0.00 0.26 –85
0.33 0.37 –40
0.44 0.48 –34
0.56 0.59 –31
0.67 0.70 –28
0.78 0.82 –25
0.89 0.93 –22
1.01 1.04 –19
1.12 1.16 –16
1.23 1.27 –13
1.35 1.38 –10
1.46 1.49 –7
1.57 1.60 –4
1.68 1.72 –2
1.79 1.83 –0
1.91 1.94 2
2.02 2.06 4
2.13 2.17 6
2.25 2.28 8
2.36 2.39 10
2.47 2.50 11
2.58 2.61 12
2.70 2.73 13
2.81 2.83 14
2.92 2.95 14.5
3.04 3.06 15
3.15 3.17 15.5
3.26 3.29 16
3.38 3.40 16.5
3.49 3.51 17
3.60 3.63 17.5
3.71 5.00 18
(1) For other values of VDD, scale the voltage values in the table by a factor of VDD/5.
(2) Tested in production. Remaining gain steps are specified by design.
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SLOS635 –NOVEMBER 2009
Table 2. DC Volume Control (SE Mode, VDD = 5 V)(1)
SE_VOLUME = VOLUME - SEDIFF or SEMAX GAIN OF AMPLIFIER
(Typ)
FROM (V) TO (V)
0.00 0.26 –85(2)
0.33 0.37 –46
0.44 0.48 –40
0.56 0.59 –37
0.67 0.70 –34
0.78 0.82 –31
0.89 0.93 –28
1.01 1.04 –25
1.12 1.16 –22
1.23 1.27 –19
1.35 1.38 –16
1.46 1.49 –13
1.57 1.60 –10
1.68 1.72 –8
1.79 1.83 –6(2)
1.91 1.94 –4
2.02 2.06 –2
2.13 2.17 0(2)
2.25 2.28 2
2.36 2.39 4
2.47 2.50 5
2.58 2.61 6 (2)
2.70 2.73 7
2.81 2.83 8
2.92 2.95 8.5
3.04 3.06 9
3.15 3.17 9.5
3.26 3.29 10
3.38 3.40 10.5
3.49 3.51 11
3.60 3.63 11.5
3.71 5.00 12
(1) For other values of VDD, scale the voltage values in the table by a factor of VDD/5.
(2) Tested in production. Remaining gain steps are specified by design.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 7
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f − Frequency − Hz
THD+N − Total Harmonic Distortion + Noise − %
20 100 1k 10k 20k
0.001
0.01
0.1
1
10 PO = 500 mW
PO = 1 W
PO = 1.5 W
VDD = 5.0 V
RL = 3 Ω
LINEIN Input − BTL Output
Gain = 6 dB
f − Frequency − Hz
THD+N − Total Harmonic Distortion + Noise − %
20 100 1k 10k 20k
0.001
0.01
0.1
1
10 PO = 250 mW
PO = 1 W
PO = 1.5 W
VDD = 5.0 V
RL = 4 Ω
LINEIN Input − BTL Output
Gain = 6 dB
TPA6013A4
SLOS635 –NOVEMBER 2009
www.ti.com
TYPICAL CHARACTERISTICS
Test conditions (unless otherwise noted) for typical operating performance:
VDD = 5.0 V, CIN = 1 µF, CBYPASS = 1 µF, TA= 27°C, SHUTDOWN = VDD
Table of Graphs
Gain (BTL) vs Volume voltage Figure 1
vs Frequency Figure 2,Figure 3,Figure 4
THD+N Total harmonic distortion plus noise (BTL) vs Output power Figure 7,Figure 8,Figure 9
vs Frequency Figure 5,Figure 6
THD+N Total harmonic distortion plus noise (SE) vs Output power Figure 10
vs Output voltage Figure 11
PDTotal power dissipation (BTL) vs Total output power Figure 12
PDTotal power dissipation (SE) vs Total output power Figure 13
Crosstalk (BTL) vs Frequency Figure 14
Crosstalk (SE) vs Frequency Figure 15
Inter-channel crosstalk vs Frequency Figure 16
Input impedance vs Gain Figure 17
PSRR Power supply rejection ratio (BTL) vs Frequency Figure 18
PSRR Power supply rejection ratio (SE) vs Frequency Figure 19
IDD Supply current (BTL) vs Total output power Figure 20
IDD Supply current (SE) vs Total output power Figure 21
TOTAL HARMONIC DISTORTION + NOISE (BTL) TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs vs
FREQUENCY FREQUENCY
Figure 2. Figure 3.
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f − Frequency − Hz
THD+N − Total Harmonic Distortion + Noise − %
20 100 1k 10k 20k
0.001
0.01
0.1
1
10 PO = 250 mW
PO = 500 mW
PO = 900 mW
VDD = 5.0 V
RL = 8 Ω
LINEIN Input − BTL Output
Gain = 6 dB
f − Frequency − Hz
THD+N − Total Harmonic Distortion + Noise − %
20 100 1k 10k 20k
0.001
0.01
0.1
1
10 PO = 10 mW
PO = 40 mW
PO = 80 mW
VDD = 5.0 V
RL = 32 Ω
HPIN Input − SE Output
Gain = 0 dB
f − Frequency − Hz
THD+N − Total Harmonic Distortion + Noise − %
20 100 1k 10k 20k
0.001
0.01
0.1
1
10 VO = 500 mVRMS
VO = 1.0 VRMS
VO = 1.75 VRMS
VDD = 5.0 V
RL = 10 kΩ
HPIN Input − SE Output
Gain = 0 dB
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
1m 10m 100m 1 4
0.01
0.1
1
10
100 VDD = 4.5 V
VDD = 5.0 V
VDD = 5.5 V
RL = 3 Ω
LINEIN Input − BTL Output
Gain = 6 dB
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
1m 10m 100m 1 3
0.01
0.1
1
10
100 VDD = 4.5 V
VDD = 5.0 V
VDD = 5.5 V
RL = 4 Ω
LINEIN Input − BTL Output
Gain = 6 dB
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
1m 10m 100m 1 2
0.01
0.1
1
10
100 VDD = 4.5 V
VDD = 5.0 V
VDD = 5.5 V
RL = 8 Ω
LINEIN Input − BTL Output
Gain = 6 dB
TPA6013A4
www.ti.com
SLOS635 –NOVEMBER 2009
TOTAL HARMONIC DISTORTION + NOISE (BTL) TOTAL HARMONIC DISTORTION + NOISE (SE)
vs vs
FREQUENCY FREQUENCY
Figure 4. Figure 5.
TOTAL HARMONIC DISTORTION + NOISE (SE) TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs vs
FREQUENCY OUTPUT POWER
Figure 6. Figure 7.
TOTAL HARMONIC DISTORTION + NOISE (BTL) TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs vs
OUTPUT POWER OUTPUT POWER
Figure 8. Figure 9.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 9
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PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
100u 1m 10m 100m 300m
0.01
0.1
1
10
100 RL = 16 Ω
RL = 32 Ω
VDD = 5.0 V
HPIN Input − SE Output
Gain = 0 dB
VO − Output Voltage − VRMS
THD+N − Total Harmonic Distortion + Noise − %
0.0 500.0m 1.0 1.5 2.0
0.001
0.01
0.1
1
10
100 VDD = 5.0 V
RL = 10 kΩ
HPIN Input − SE Output
Gain = 0 dB
PO − Total Output Power − W
PD − Total Power Dissipation − W
0 100m 200m 300m 400m 500m
0
25m
50m
75m
100m
125m
150m
175m
200m
RL = 16 Ω
RL = 32 Ω
VDD = 5.0 V
HPIN Input
SE Output
Gain = 0 dB
PO − Total Output Power − W
PD − Total Power Dissipation − W
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
RL = 3 Ω
RL = 4 Ω
RL = 8 Ω
VDD = 5.0 V
LINEIN Input
BTL Output
Gain = 6 dB
f − Frequency − Hz
Crosstalk − dB
20 100 1k 10k 20k
−140
−120
−100
−80
−60
−40
−20
0RL = 4 Ω
PO = 1 W
LINEIN Input − BTL Output
Gain = 6 dB
f − Frequency − Hz
Crosstalk − dB
20 100 1k 10k 20k
−140
−120
−100
−80
−60
−40
−20
0RL = 32 Ω
PO = 50 mW
HPIN Input − SE Output
Gain = 0 dB
TPA6013A4
SLOS635 –NOVEMBER 2009
www.ti.com
TOTAL HARMONIC DISTORTION + NOISE (SE) TOTAL HARMONIC DISTORTION + NOISE (SE)
vs vs
OUTPUT POWER OUTPUT VOLTAGE
Figure 10. Figure 11.
TOTAL POWER DISSIPATION (BTL) TOTAL POWER DISSIPATION (SE)
vs vs
TOTAL OUTPUT POWER TOTAL OUTPUT POWER
Figure 12. Figure 13.
CROSSTALK (BTL) CROSSTALK (SE)
vs vs
FREQUENCY FREQUENCY
Figure 14. Figure 15.
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Gain − dB
Input Impedance − Ω
−40 −35 −30 −25 −20 −15 −10 −5 0 5 10 15 20
0
20k
40k
60k
80k
100k
120k Differential
Single−Ended
VDD = 5.0 V
RL = No Load
f − Frequency − Hz
Inter−Channel Crosstalk − dB
20 100 1k 10k 20k
−120
−100
−80
−60
−40
−20
0Line Active
HP Active
VDD = 5.0 V
RL = 4 Ω
VIN = 1 VRMS − BTL Output
Gain = 18 dB
f − Frequency − Hz
PSRR − Power Supply Rejection Ratio − dB
20 100 1k 10k 20k
−80
−60
−40
−20
0Gain = 6 dB
Gain = 18 dB
VDD = 5.0 V
RL = 4 Ω
BTL Output
Supply Ripple = 0.2 Vpp Sine Wave
f − Frequency − Hz
PSRR − Power Supply Rejection Ratio − dB
20 100 1k 10k 20k
−80
−60
−40
−20
0Gain = 0 dB
Gain = 12 dB
VDD = 5.0 V
RL = 32 Ω
SE Output
Supply Ripple = 0.2 Vpp Sine Wave
PO − Total Output Power − W
IDD − Supply Current − A
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
RL = 3 Ω
RL = 4 Ω
RL = 8 Ω
VDD = 5.0 V
LINEIN Input
BTL Output
Gain = 6 dB
PO − Total Output Power − W
IDD − Supply Current − A
0 100m 200m 300m 400m 500m
0
25m
50m
75m
100m
125m
RL = 16 Ω
RL = 32 Ω
VDD = 5.0 V
HPIN Input
SE Output
Gain = 0 dB
TPA6013A4
www.ti.com
SLOS635 –NOVEMBER 2009
INTER-CHANNEL CROSSTALK INPUT IMPEDANCE
vs vs
FREQUENCY GAIN
Figure 16. Figure 17.
POWER SUPPLY REJECTION RATIO (BTL) POWER SUPPLY REJECTION RATIO (SE)
vs vs
FREQUENCY FREQUENCY
Figure 18. Figure 19.
SUPPLY CURRENT (BTL) SUPPLY CURRENT (SE)
vs vs
TOTAL OUTPUT POWER TOTAL OUTPUT POWER
Figure 20. Figure 21.
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APPLICATION INFORMATION
SELECTION OF COMPONENTS
Figure 22 and Figure 23 are schematic diagrams of typical notebook computer application circuits.
A. A 0.1-μF ceramic capacitor should be placed as close as possible to the IC. For filtering lower-frequency noise
signals, a larger electrolytic capacitor of 10 μF or greater should be placed near the audio power amplifier.
Figure 22. Typical TPA6013A4 Application Circuit Using Single-Ended Inputs and Input MUX
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PGND
ROUT-
PVDD
RHPIN
RLINEIN
RIN
VDD
LIN
LLINEIN
LHPIN
PVDD
LOUT-
1ROUT+
SE/BTL
HP/LINE
VOLUME
SEDIFF
SEMAX
AGND
BYPASS
FADE
SHUTDOWN
LOUT+
PGND
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
17
18
19
20
21
22
23
24
CS
NC
VDD
Ci
Ci
CS
Ci
Ci
CS
Power Supply
Left Negative
Differential Input Signal
Power Supply
VDD
100 kΩ
100 kΩ
CC
In From DAC
or
Potentiometer
(DC Voltage)
C(BYP)
System
Control
CC
Right
Speaker
Left
Speaker
Headphones
1 kΩ
1 kΩ
NC
Left Positive Differential
Input Signal
Right Negative
Differential Input Signal
Right Positive
Differential Input Signal
TPA6013A4
www.ti.com
SLOS635 –NOVEMBER 2009
A. A 0.1-μF ceramic capacitor should be placed as close as possible to the IC. For filtering lower-frequency noise
signals, a larger electrolytic capacitor of 10 μF or greater should be placed near the audio power amplifier.
Figure 23. Typical TPA6013A4 Application Circuit Using Differential Inputs
SE/BTL OPERATION
The ability of the TPA6013A4 to easily switch between BTL and SE modes is one of its most important cost
saving features. This feature eliminates the requirement for an additional headphone amplifier in applications
where internal stereo speakers are driven in BTL mode but external headphone or speakers must be
accommodated. Internal to the TPA6013A4, two separate amplifiers drive OUT+ and OUT–. The SE/BTL input
controls the operation of the follower amplifier that drives LOUT– and ROUT–. When SE/BTL is held low, the
amplifier is on and the TPA6013A4 is in the BTL mode. When SE/BTL is held high, the OUT– amplifiers are in a
high output impedance state, which configures the TPA6013A4 as an SE driver from LOUT+ and ROUT+. IDD is
reduced by approximately one-third in SE mode. Control of the SE/BTL input can be from a logic-level CMOS
source or, more typically, from a resistor divider network as shown in Figure 24. The trip level for the SE/BTL
input can be found in the recommended operating conditions table.
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Product Folder Link(s) :TPA6013A4
SE/BTL
ROUT+ 24
R
MUX
RHPIN
RLINEIN5
4
6 RIN
ROUT- 2 1 kΩ
CO
330 µF
100 kΩ
23
100 kΩ
VDD
Input
MUX
Control
22 HP/LINE
_
+_
+
Bypass
_
+
Bypass EN
_
+
Bypass
LOUT+
TPA6013A4
SLOS635 –NOVEMBER 2009
www.ti.com
Figure 24. TPA6013A4 Resistor Divider Network Circuit
Using a 1/8-in. (3,5 mm) stereo headphone jack, the control switch is closed when no plug is inserted. When
closed the 100-kΩ/1-kΩdivider pulls the SE/BTL input low. When a plug is inserted, the 1-kΩresistor is
disconnected and the SE/BTL input is pulled high. When the input goes high, the OUT– amplifier is shut down
causing the speaker to mute (open-circuits the speaker). The OUT+ amplifier then drives through the output
capacitor (Co) into the headphone jack.
HP/LINE OPERATION
The HP/LINE input controls the internal input multiplexer (MUX). Refer to the block diagram in Figure 24. This
allows the device to switch between two separate stereo inputs to the amplifier. For design flexibility, the
HP/LINE control is independent of the output mode, SE or BTL, which is controlled by the aforementioned
SE/BTL pin. To allow the amplifier to switch from the LINE inputs to the HP inputs when the output switches from
BTL mode to SE mode, simply connect the SE/BTL control input to the HP/LINE input.
When this input is logic high, the RHPIN and LHPIN inputs are selected. When this terminal is logic low, the
RLINEIN and LLINEIN inputs are selected. This operation is also detailed in Table 3 and the trip levels for a logic
low (VIL) or logic high (VIH) can be found in the recommended operating conditions table.
SHUTDOWN MODES
The TPA6013A4 employs a shutdown mode of operation designed to reduce supply current (IDD) to the absolute
minimum level during periods of nonuse for battery-power conservation. The SHUTDOWN input terminal should
be held high during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the outputs to
mute and the amplifier to enter a low-current state, IDD = 20 μA. SHUTDOWN should never be left unconnected
because amplifier operation would be unpredictable.
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Table 3. HP/LINE, SE/BTL, and Shutdown Functions
INPUTS (1) AMPLIFIER STATE
HP/LINE SE/BTL SHUTDOWN INPUT OUTPUT
X X Low X Mute
Low Low High Line BTL
Low High High Line SE
High Low High HP BTL
High High High HP SE
(1) Inputs should never be left unconnected.
FADE OPERATION
For design flexibility, a fade mode is provided to slowly ramp up the amplifier gain when coming out of shutdown
mode and conversely ramp the gain down when going into shutdown. This mode provides a smooth transition
between the active and shutdown states and virtually eliminates any pops or clicks on the outputs.
When the FADE input is a logic low, the device is placed into fade-on mode. A logic high on this pin places the
amplifier in the fade-off mode. The voltage trip levels for a logic low (VIL) or logic high (VIH) can be found in the
recommended operating conditions table.
When a logic low is applied to the FADE pin and a logic low is then applied on the SHUTDOWNpin, the channel
gain steps down from gain step to gain step at a rate of two clock cycles per step. With a nominal internal clock
frequency of 58 Hz, this equates to 34 ms (1/24 Hz) per step. The gain steps down until the lowest gain step is
reached. The time it takes to reach this step depends on the gain setting prior to placing the device in shutdown.
For example, if the amplifier is in the highest gain mode of 18 dB, the time it takes to ramp down the channel
gain is 1.05 seconds. This number is calculated by taking the number of steps to reach the lowest gain from the
highest gain, or 31 steps, and multiplying by the time per step, or 34 ms.
After the channel gain is stepped down to the lowest gain, the amplifier begins discharging the bypass capacitor
from the nominal voltage of VDD/2 to ground. This time is dependent on the value of the bypass capacitor. For a
0.47-μF capacitor that is used in the application diagram in Figure 22, the time is approximately 500 ms. This
time scales linearly with the value of bypass capacitor. For example, if a 1-μF capacitor is used for bypass, the
time period to discharge the capacitor to ground is twice that of the 0.47-μF capacitor, or 1 second. Figure 25 is a
waveform captured at the output during the shutdown sequence when the part is in fade-on mode. The gain is
set to the highest level and the output is at VDD when the amplifier is shut down.
When a logic high is placed on the SHUTDOWN pin and the FADE pin is still held low, the device begins the
start-up process. The bypass capacitor will begin charging. Once the bypass voltage reaches the final value of
VDD/2, the gain increases from the lowest gain level to the gain level set by the dc voltage applied to the
VOLUME, SEDIFF, and SEMAX pins.
In the fade-off mode, the amplifier stores the gain value prior to starting the shutdown sequence. The output of
the amplifier immediately drops to VDD/2 and the bypass capacitor begins a smooth discharge to ground. When
shutdown is released, the bypass capacitor charges up to VDD/2 and the channel gain returns immediately to the
value stored in memory. Figure 26 is a waveform captured at the output during the shutdown sequence when the
part is in the fade-off mode. The gain is set to the highest level, and the output is at VDD when the amplifier is
shut down.
The power-up sequence is different from the shutdown sequence and the voltage on the FADEpin does not
change the power-up sequence. Upon a power-up condition, the TPA6013A4 begins in the lowest gain setting
and steps up every 2 clock cycles until the final value is reached as determined by the dc voltage applied to the
VOLUME, SEDIFF, and SEMAX pins.
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ROUT+
Device Shutdown
ROUT+
Device Shutdown
TPA6013A4
SLOS635 –NOVEMBER 2009
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Figure 25. Shutdown Sequence in the Fade-on Figure 26. Shutdown Sequence in the Fade-off
Mode Mode
VOLUME, SEDIFF, AND SEMAX OPERATION
Three pins labeled VOLUME, SEDIFF, and SEMAX control the BTL volume when driving speakers and the SE
volume when driving headphones. All of these pins are controlled with a dc voltage, which should not exceed
VDD.
When driving speakers in BTL mode, the VOLUME pin is the only pin that controls the gain. Table 1 shows the
gain for the BTL mode. The voltages listed in the table are for VDD = 5 V. For a different VDD, the values in the
table scale linearly. If VDD = 4 V, multiply all the voltages in the table by 4 V/5 V, or 0.8.
The TPA6013A4 allows the user to specify a difference between BTL gain and SE gain. This is desirable to avoid
any listening discomfort when plugging in headphones. When switching to SE mode, the SEDIFF and SEMAX
pins control the singe-ended gain proportional to the gain set by the voltage on the VOLUME pin. When SEDIFF
= 0 V, the difference between the BTL gain and the SE gain is 6 dB. Refer to the section labeled bridge-tied load
versus single-ended load for an explanation on why the gain in BTL mode is 2x that of single-ended mode, or
6dB greater. As the voltage on the SEDIFF terminal is increased, the gain in SE mode decreases. The voltage
on the SEDIFF terminal is subtracted from the voltage on the VOLUME terminal and this value is used to
determine the SE gain.
Some audio systems require that the gain be limited in the single-ended mode to a level that is comfortable for
headphone listening. Most volume control devices only have one terminal for setting the gain. For example, if the
speaker gain is 18 dB, the gain in the headphone channel is fixed at 12 dB. This level of gain could cause
discomfort to listeners and the SEMAX pin allows the designer to limit this discomfort when plugging in
headphones. The SEMAX terminal controls the maximum gain for single-ended mode.
The functionality of the SEDIFF and SEMAX pin are combined to set the SE gain. A block diagram of the
combined functionality is shown in Figure 27. The value obtained from the block diagram for SE_VOLUME is a
dc voltage that can be used in conjunction with Table 2 to determine the SE gain. Again, the voltages listed in
the table are for VDD = 5 V. The values must be scaled for other values of VDD.
Table 1 and Table 2 show a range of voltages for each gain step. There is a gap in the voltage between each
gain step. This gap represents the hysteresis about each trip point in the internal comparator. The hysteresis
ensures that the gain control is monotonic and does not oscillate from one gain step to another. If a
potentiometer is used to adjust the voltage on the control terminals, the gain increases as the potentiometer is
turned in one direction and decreases as it is turned back the other direction. The trip point, where the gain
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SEMAX (V)
VOLUME-SEDIFF
SEDIFF (V)
-
+
VOLUME (V) YES
NO
SE_VOLUME (V) = VOLUME (V) - SEDIFF (V)
SE_VOLUME (V) = SEMAX (V)
Is SEMAX>
(VOLUME-SEDIFF)
?
12
13
14
2.702.61 2.73 2.81
BTL Gain-dB
VoltageonVOLUMEPin-V
TPA6013A4
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SLOS635 –NOVEMBER 2009
actually changes, is different depending on whether the voltage is increased or decreased as a result of the
hysteresis about each trip point. The gaps in Table 1 and Table 2 can also be thought of as indeterminate states
where the gain could be in the next higher gain step or the lower gain step depending on the direction the
voltage is changing. If using a DAC to control the volume, set the voltage in the middle of each range to ensure
that the desired gain is achieved.
A pictorial representation of the volume control can be found in Figure 28. The graph focuses on three gain steps
with the trip points defined in Table 1 for BTL gain. The dotted line represents the hysteresis about each gain
step.
Figure 27. Block Diagram of SE Volume Control
Figure 28. DC Volume Control Operation
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Product Folder Link(s) :TPA6013A4
CIN Ri
Rf
Input Signal
ƒ*3 dB +1
2pCRi
fc(highpass) +1
2pRiCi
−3 dB
fc
Ci+1
2pRifc
TPA6013A4
SLOS635 –NOVEMBER 2009
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INPUT RESISTANCE
Each gain setting is achieved by varying the input resistance of the amplifier, which can range from its smallest
value to over six times that value. As a result, if a single capacitor is used in the input high-pass filter, the –3 dB
or cutoff frequency also changes by over six times.
Figure 29. Resistor on Input for Cut-Off Frequency
The input resistance at each gain setting is given in Figure 17.
The –3-dB frequency can be calculated using Equation 1.
(1)
INPUT CAPACITOR, Ci
In the typical application an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, Ciand the input impedance of the amplifier (Ri) form a
high-pass filter with the corner frequency determined in Equation 2.
(2)
The value of Ciis important to consider as it directly affects the bass (low frequency) performance of the circuit.
Consider the example where Riis 70 kΩand the specification calls for a flat-bass response down to 40 Hz.
Equation 2 is reconfigured as Equation 3.
(3)
In this example, Ciis 56.8 nF, so one would likely choose a value in the range of 56 nF to 1 μF. A further
consideration for this capacitor is the leakage path from the input source through the input network (Ci) and the
feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that
reduces useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or
ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor
should face the amplifier input in most applications as the dc level there is held at VDD/2, which is likely higher
than the source dc level. Note that it is important to confirm the capacitor polarity in the application.
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fc(high) +1
2pRLC(C)
−3 dB
fc
TPA6013A4
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SLOS635 –NOVEMBER 2009
POWER SUPPLY DECOUPLING, C(S)
The TPA6013A4 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to
ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents
oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by
using two capacitors of different types that target different types of noise on the power supply leads. For higher
frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic
capacitor, typically 0.1 μF placed as close as possible to the device VDD lead, works best. For filtering
lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 μF or greater placed near the audio
power amplifier is recommended.
MIDRAIL BYPASS CAPACITOR, C(BYP)
The midrail bypass capacitor (C(BYP)) is the most critical capacitor and serves several important functions. During
start-up or recovery from shutdown mode, C(BYP) determines the rate at which the amplifier starts up. The second
function is to reduce noise produced by the power supply caused by coupling into the output drive signal. This
noise is from the midrail generation circuit internal to the amplifier, which appears as degraded PSRR and
THD+N.
Bypass capacitor (C(BYP)) values of 0.47-μF to 1-μF ceramic or tantalum low-ESR capacitors are recommended
for the best THD and noise performance. For the best pop performance, choose a value for C(BYP) that is equal to
or greater than the value chosen for Ci. This ensures that the input capacitors are charged up to the midrail
voltage before C(BYP) is fully charged to the midrail voltage.
OUTPUT COUPLING CAPACITOR, C(C)
In the typical single-supply SE configuration, an output coupling capacitor (C(C)) is required to block the dc bias at
the output of the amplifier, thus preventing dc currents in the load. As with the input coupling capacitor, the
output coupling capacitor and impedance of the load form a high-pass filter governed by Equation 4.
(4)
The main disadvantage, from a performance standpoint, is the load impedances are typically small, which drives
the low-frequency corner higher, degrading the bass response. Large values of C(C) are required to pass low
frequencies into the load. Consider the example where a C(C) of 330 μF is chosen and loads vary from 3Ω,4 Ω,
8Ω, 32Ω, 10 kΩ, and 47 kΩ.Table 4 summarizes the frequency response characteristics of each configuration.
Table 4. Common Load Impedances vs Low Frequency
Output Characteristics in SE Mode
RLC(C) LOWEST FREQUENCY
3Ω330 μF 161 Hz
4Ω330 μF 120 Hz
8Ω330 μF 60 Hz
32 Ω330 µF 15 Hz
10,000 Ω330 μF 0.05 Hz
47,000 Ω330 μF 0.01 Hz
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Power +V(rms)2
RL
V(rms) +VO(PP)
2 2
Ǹ
RL2x VO(PP)
VO(PP)
-VO(PP)
VDD
VDD
TPA6013A4
SLOS635 –NOVEMBER 2009
www.ti.com
As Table 4 indicates, most of the bass response is attenuated into a 4-Ωload, an 8-Ωload is adequate,
headphone response is good, and drive into line level inputs (a home stereo for example) is exceptional.
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout this applications section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this
resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this
resistance, the more the real capacitor behaves like an ideal capacitor.
BRIDGE-TIED LOAD vs SINGLE-ENDED LOAD
Figure 30 shows a Class-AB audio power amplifier (APA) in a BTL configuration. The TPA6013A4 BTL amplifier
consists of two Class-AB amplifiers driving both ends of the load. There are several potential benefits to this
differential drive configuration, but, initially consider power to the load. The differential drive to the speaker
means that as one side is slewing up, the other side is slewing down, and vice versa. This in effect doubles the
voltage swing on the load as compared to a ground referenced load. Plugging 2 × VO(PP) into the power equation,
where voltage is squared, yields 4× the output power from the same supply rail and load impedance (see
Equation 5).
(5)
Figure 30. Bridge-Tied Load Configuration
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f(c) +1
2pRLCC
RL
C(C) VO(PP)
VO(PP)
VDD
-3 dB
fc
TPA6013A4
www.ti.com
SLOS635 –NOVEMBER 2009
In a typical computer sound channel operating at 5 V, bridging raises the power into an 8-Ωspeaker from a
singled-ended (SE, ground reference) limit of 250 mW to 1 W. In sound power that is a 6-dB improvement, which
is loudness that can be heard. In addition to increased power there are frequency response concerns. Consider
the single-supply SE configuration shown in Figure 31. A coupling capacitor is required to block the dc offset
voltage from reaching the load. These capacitors can be quite large (approximately 33μF to 1000μF), so they
tend to be expensive, heavy, occupy valuable PCB area, and have the additional drawback of limiting
low-frequency performance of the system. This frequency limiting effect is due to the high-pass filter network
created with the speaker impedance and the coupling capacitance and is calculated with Equation 6.
(6)
For example, a 68-μF capacitor with an 8-Ωspeaker would attenuate low frequencies below 293 Hz. The BTL
configuration cancels the dc offsets, which eliminates the need for the blocking capacitors. Low-frequency
performance is then limited only by the input network and speaker response. Cost and PCB space are also
minimized by eliminating the bulky coupling capacitor.
Figure 31. Single-Ended Configuration and Frequency Response
Increasing power to the load does carry a penalty of increased internal power dissipation. The increased
dissipation is understandable considering that the BTL configuration produces 4× the output power of the SE
configuration. Internal dissipation versus output power is discussed further in the crest factor and thermal
considerations section.
SINGLE-ENDED OPERATION
In SE mode (see Figure 31), the load is driven from the primary amplifier output for each channel (OUT+).
The amplifier switches single-ended operation when the SE/BTL terminal is held high. This puts the negative
outputs in a high-impedance state, and effectively reduces the amplifier's gain by 6 dB.
BTL AMPLIFIER EFFICIENCY
Class-AB amplifiers are inefficient. The primary cause of these inefficiencies is voltage drop across the output
stage transistors. There are two components of the internal voltage drop. One is the headroom or dc voltage
drop that varies inversely to output power. The second component is due to the sine-wave nature of the output.
The total voltage drop can be calculated by subtracting the RMS value of the output voltage from VDD. The
internal voltage drop multiplied by the RMS value of the supply current (IDDrms) determines the internal power
dissipation of the amplifier.
An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power
supply to the power delivered to the load. To accurately calculate the RMS and average values of power in the
load and in the amplifier, the current and voltage waveform shapes must first be understood (see Figure 32).
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 21
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V(LRMS)
VOIDD
IDD(avg)
Efficiency of a BTL amplifier +PL
PSUP
Where:
PL+VLrms2
RL, andVLRMS +VP
2
Ǹ, therefore, PL+VP2
2RL
and PSUP +VDD IDDavg and IDDavg +1
pŕp
0
VP
RLsin(t) dt +1
p VP
RL[cos(t)]p
0+2VP
pRL
Therefore,
PSUP +2 VDD VP
pRL
Efficiency of a BTL amplifier +
VP2
2 RL
2 VDD VP
pRL
+
pVP
4 VDD
PL = Power delivered to load
PSUP = Power drawn from power supply
VLRMS = RMS voltage on BTL load
RL = Load resistance
VP+2 PLRL
Ǹ
hBTL +p2 PLRL
Ǹ
4 VDD
Where:
Therefore,
VP = Peak voltage on BTL load
IDDavg = Average current drawn from the power supply
VDD = Power supply voltage
ηBTL = Efficiency of a BTL amplifier
TPA6013A4
SLOS635 –NOVEMBER 2009
www.ti.com
Figure 32. Voltage and Current Waveforms for BTL Amplifiers
Although the voltages and currents for SE and BTL are sinusoidal in the load, currents from the supply are very
different between SE and BTL configurations. In an SE application the current waveform is a half-wave rectified
shape, whereas in BTL it is a full-wave rectified waveform. This means RMS conversion factors are different.
Keep in mind that for most of the waveform both the push and pull transistors are not on at the same time, which
supports the fact that each amplifier in the BTL device only draws current from the supply for half the waveform.
The following equations are the basis for calculating amplifier efficiency.
(7)
substituting PLand PSUP into Equation 7,
(8)
Table 5 employs Equation 8 to calculate efficiencies for four different output power levels. Note that the efficiency
of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in
a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full
output power is less than in the half power range. Calculating the efficiency for a specific system is the key to
proper power supply design. For a stereo 1-W audio system with 8-Ωloads and a 5-V supply, the maximum draw
on the power supply is almost 3.25 W.
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PdB +10Log PW
Pref
+10Log 4 W
1 W +6 dB
PW+10PdBń10 Pref
= 250 mW (12-db crest factor)
= 125 mW (15-db crest factor)
= 63 mW (18-db crest factor)
= 500 mW (9-db crest factor)
= 1000 mW (6-db crest factor)
= 2000 mW (3-db crest factor)
TPA6013A4
www.ti.com
SLOS635 –NOVEMBER 2009
Table 5. Efficiency vs Output Power in 5-V, 8-ΩBTL Systems
OUTPUT POWER EFFICIENCY PEAK VOLTAGE INTERNAL DISSIPATION
(W) (%) (V) (W)
0.25 31.4 2.00 0.55
0.50 44.4 2.83 0.62
1.00 62.8 4.00 0.59
1.25 70.2 4.47(1) 0.53
(1) High peak voltages cause the THD to increase.
A final point to remember about Class-AB amplifiers (either SE or BTL) is how to manipulate the terms in the
efficiency equation to utmost advantage when possible. Note that in equation 8, VDD is in the denominator. This
indicates that as VDD goes down, efficiency goes up.
CREST FACTOR AND THERMAL CONSIDERATIONS
Class-AB power amplifiers dissipate a significant amount of heat in the package under normal operating
conditions. A typical music CD requires 12 dB to 15 dB of dynamic range, or headroom above the average power
output, to pass the loudest portions of the signal without distortion. In other words, music typically has a crest
factor between 12 dB and 15 dB. When determining the optimal ambient operating temperature, the internal
dissipated power at the average output power level must be used. From the TPA6013A4 data sheet, one can
see that when the TPA6013A4 is operating from a 5-V supply into a 3-Ωspeaker, that 4-W peaks are available.
Use equation 9 to convert watts to dB.
(9)
Subtracting the headroom restriction to obtain the average listening level without distortion yields:
• 6 dB – 15 dB = –9 dB (15-dB crest factor)
• 6 dB – 12 dB = –6 dB (12-dB crest factor)
• 6 dB – 9 dB = –3 dB (9-dB crest factor)
• 6 dB – 6 dB = 0 dB (6-dB crest factor)
• 6 dB – 3 dB = 3 dB (3-dB crest factor)
To convert dB back into watts use equation 10.
(10)
This is valuable information to consider when attempting to estimate the heat dissipation requirements for the
amplifier system. Comparing the worst case, which is 2 W of continuous power output with a 3-dB crest factor,
against 12-dB and 15-dB applications significantly affects maximum ambient temperature ratings for the system.
Using the power dissipation curves for a 5-V, 3-Ωsystem, the internal dissipation in the TPA6013A4 and
maximum ambient temperatures is shown in Table 6.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s) :TPA6013A4
PD(max) +
2V2
DD
p2RL
ΘJA +1
Derating Factor +1
0.022 +45°CńW
TAMax +TJMax *ΘJA PD
+150 *45(0.6 2)+96°C(15-dB crest factor)
TPA6013A4
SLOS635 –NOVEMBER 2009
www.ti.com
Table 6. TPA6013A4 Power Rating, 5-V, 3-ΩStereo
PEAK OUTPUT POWER POWER DISSIPATION MAXIMUM AMBIENT
AVERAGE OUTPUT POWER
(W) (W/Channel) TEMPERATURE
4 2 W (3 dB) 1.7 –3°C
4 1 W (6 dB) 1.6 6°C
4 500 mW (9 dB) 1.4 24°C
4 250 mW (12 dB) 1.1 51°C
4 125 mW (15 dB) 0.8 78°C
4 63 mW (18 dB) 0.6 96°C
Table 7. TPA6013A4 Power Rating, 5-V, 8-ΩStereo
PEAK OUTPUT POWER POWER DISSIPATION MAXIMUM AMBIENT
AVERAGE OUTPUT POWER
(W) (W/Channel) TEMPERATURE
2.5 1250 mW (3-dB crest factor) 0.55 100°C
2.5 1000 mW (4-dB crest factor) 0.62 94°C
2.5 500 mW (7-dB crest factor) 0.59 97°C
2.5 250 mW (10-dB crest factor) 0.53 102°C
The maximum dissipated power (PD(max)) is reached at a much lower output power level for an 8-Ωload than for
a 3-Ωload. As a result, this simple formula for calculating PD(max) may be used for an 8-Ωapplication.
(11)
However, in the case of a 3-Ωload, the PD(max) occurs at a point well above the normal operating power level.
The amplifier may therefore be operated at a higher ambient temperature than required by the PD(max) formula for
a 3-Ωload.
The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factor
for the PWP package is shown in the dissipation rating table. Use equation 12 to convert this to θJA. .
(12)
To calculate maximum ambient temperatures, first consider that the numbers from the dissipation graphs are per
channel, so the dissipated power needs to be doubled for two channel operation. Given θJA, the maximum
allowable junction temperature, and the total internal dissipation, the maximum ambient temperature can be
calculated using Equation 13. The maximum recommended junction temperature for the TPA6013A4 is 150°C.
The internal dissipation figures are taken from the Power Dissipation vs Output Power graphs.
(13)
NOTE
Internal dissipation of 0.6 W is estimated for a 2-W system with 15-dB crest factor per
channel.
Table 6 and Table 7 show that some applications require no airflow to keep junction temperatures in the
specified range. The TPA6013A4 is designed with thermal protection that turns the device off when the junction
temperature surpasses 150°C to prevent damage to the IC. Table 6 and Table 7 were calculated for maximum
listening volume without distortion. When the output level is reduced the numbers in the table change
significantly. Also, using 8-Ωspeakers increases the thermal performance by increasing amplifier efficiency.
24 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :TPA6013A4
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPA6013A4PWPR HTSSOP PWP 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPA6013A4PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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