We 2 1993 April 1990 Edition 3.0 DATA SHEET MBM27C256A-15/-17/-20/-25 CMOS 256K-BIT UV EPROM CMOS 262,144-BIT UV ERASABLE AND ELECTRICALLY PROGRAMMABLE READ ONLY MEMORY The Fujitsu MBM27C256A is a high speed 262, 144-bits complementary MOS erasable and electrically reprogrammable read only memory (EPROM). It is especially well suited for application where rapid turn-around and/or bit pattern experimentation, and low-power consumption are important. A 28-pin dual-in line package with a transparent lid and 32-pad Leadless Chip Carrier (LCC) are used to package the MBM27C256A. The transparent lid allows the user to expose the device to ultra-violet light in order to erase the memory bit pattern previously programmed. At the completion of erasure, a new pattern can then be written into the memory. The MBM27C256A is fabricated using CMOS double polysilicon gate technology with single transistor stacked gate cells. Itis organized as 32,768 words by 8 bits for use in microprocessor applications. Single +5V operation greatly facilitates its use in systems. CMOS power consumption e Three~state output with OR-tie Standby: 550 wp W max. capability Active: 41 mW/MHz Fast access time: 150 ns max. (MBM27C256A-15) 170 ns max. (MBM27C256A-17) 200 ns max. (MBM27C256A-20) 250 ns max. (MBM27C256A-25) @ TTL compatible inputs/outputs e 32,768 words x 8 bits organization, fully decoded Single location programming e@ Programmable utilizing the quick programming Algorithm @ Single +5V supply, +10% tolerance e@ Standard 28-pin Ceramic Programming Voltage: 12.5V DIP: Suffix: -Z @ No clocks required (fully static @ Standard 32-pad Ceramic operation) LCC: Suffix: -TV ABSOLUTE MAXIMUM RATINGS (see NOTE) co FUJITSU " CERAMIC PACKAGE DIP-28C-C01 CERAMIC PACKAGE LCC-32C-F01 Rating Symbol Value Unit Temperature under Bias Taias -25 to +85 C Storage Temperature Tste -65 to +125 we appa ts/Outputs Voltage with Respect Vin, Vour 0.6 to Veo + 0.3 V Voltage on Ag with Respect to GND Vag -0.6 to +13.5 Vv Vep Voltage with Respect to GND Vep -0.6 to +14 v Supply Voltage with Respect to GND Vee 0.6 to +7 v PIN ASSIGNMENT Vee [1 28 T} Voc Af 2 27 Aw A(]3 26 [7] Ars C4 25 [1] As AsO5 24 TJ A A6 23 [J An A, 7 22 [] OE AC) 8 1D Aw A 9 20 0 GE Aa [] 10 19 [7] O 0,1 18 [] 0; oO, [] 12 171 0; (J 13 16 anes GND[] 14 56 OO Vee Au TotyTuty Tatas) Ay Ay Ay NC oE Aw cE Os 0; +] 4 3 2 1 Tole NOTE: conditions for extended periods may affect device reliability. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded, Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any vohage higher than maximum rated voltages to this high impedance circuit. Copyright 1990 by FUJITSU LIMITEDMBM27C256A-15 MBM27C256A-17 MBM27C256A-20 MBM27C256A-25 Fig. 1 -MBM27C256A BLOCK DIAGRAM Oo; Os OE }_ OUTPUT ENABLE & CHIP ENABLE & BUEEER cE -__ PROGRAM LOGIC Do DATA INPUT BUFFER & : PROGRAMMING e CONTOROL [| : oO; Os Yo COLUMN to * COLUMN : s GATING s . DECODER A, - Ye3 x 12 x 512 9 CELL MATRIX As ROW : Ata * DECODER e Xsi1 Vpp Vec GND CAPACITANCE (tu-25c, = 1mnz) Parameter Symbol Min Typ Max Unit Input Capacitance (Vin = OV) Cw 4 6 pF Output Capacitance (Vour = OV) Court 8 12 pFMBM27C256A-15 MBM27C256A-17 MBM27C256A-20 MBM27C256A-25 FUNCTIONS AND PIN CONNECTIONS Function Address Input Ac Data /O CE OE Vee Vee GND Mode Read Aw Aw Dour Vir Vir +5V +5V GND Output Disable Aus Aw High-Z Viv Vin +5V +5V GND Standby Don't Care Don't Care High-Z Vin Don't Care +5V +5V GND Program Aw Aw Din Vit Vin +6V +12.5V GND Program Verify Aw An Dour Don't Care Vir +6V +12.5V GND Program Inhibit Don't Care Don't Care High-Z Vin Vin +6V +12.5V GND Electronic Signature Ao +12V Code Vir Vir +5V +5V GND RECOMMENDED OPERATING CONDITIONS (Referenced to GND) Parameter Symbol Min Typ Max Unit Vcc Supply Voltage* Vee 45 5.0 5.5 Vv Vee Supply Voltage Vee Vec -0.6 Vee Veo +0.6 V Operating Temperature Ta 0 70 C Note: * Vcc must be applied either before or coincident with Vpe and removed either after or coincident with Vpp. DC CHARACTERISTICS DC CHAR AC TE RISTH unless otherwise noted) Parameter Symbol Min Typ Max Unit Input Load Current (Vin = 5.5V) | 10 pA Output Leakage Current (Vour = 5.5V) Iho | 10 pA Vee Supply Current (Vpp= Vec +0.6V) Ippr 1 100 yA Vee Standby Current (CE = Vin) Isat 1 mA Vee Standby Current (CE = Voc +0.3V, lour = OMA) Isae 1 100 pA Vec Active Current (CE = Vu) lect 2 30 mA Voc Operating Current (f = 4MHz, lour = OMA) lcce 5 30 mA Input High Voltage Vin 2.0 Vec +0.3 V Input Low Voltage Vit 0.1 0.8 Vv Output Low Voltage (lo. = 2.1mA) Vor 0.45 V Output High Voltage (lox = 400A) Von 2.4 V Output High Voltage (lon = 100pA) Von Voc 0.7 VvMBM27C256A-15 MBM27C256A-17 MBM27C256A-20 MBM27C256A-25 Input Pulse Levels: Output Load: Fig. 2 AC TEST CONDITIONS (INCLUDING PROGAMMING) 7 te Input Rise and Fall Times: Timing Measurement Reference Levels: 0.45V to 2.4V <20ns 0.8V and 2.0V for inputs 0.8V and 2.0V for outputs 1 TTL gate and C, = 100pF 4, AC CHARACTERISTICS (Recommended operating conditions unless otherwise noted) MBM27C256A-15 | MBM27C256A-17 | MBM27C256A-20 | MBM27C256A-25 Parameter Symbol Units Min Max Min Max Min Max Min Max Address Access Time"! (CE = OE = Vi) tace 150 170 200 250 ns CE to Output Delay tor 150 170 200 250 ns (OE = Vi) QE to Output Delay toe 60 70 70 100 ns (CE = Vi) Address to Output Hold tou 0 0 0 0 ns Output Enable High to Output Float? tor 0 60 0 60 0 60 0 60 ns Notes: *1 OE may be delayed up to tacctoe after the folling edge of CE without impact on tace. *2 tor is specified from OE or CE, whichever occurs first. Output Floating is defined as the point where data is no longer driven. OPERATION TIMING DIAGRAM Vino ADDRESS ADDRESS VALID 1% a J CE Vin - Vi- J tce Vin -_ OE Vi = \. J hetoe o tor V pt_ tace oH> *HIGH-Z L/)/7> OUTPUT Vo" QS VALID OUTPUT HIGH-ZMBM27C256A-15 MBM27C256A-17 MBM27C256A-20 MBM27C256A-25 PROGRAMMING/ERASING INFORMATION 0 PROGRAMMING Upon delivery from Fujitsu, or after each erasure (see Erasure section), the MBM27C256A has all 262,144 bits in the "1", or high state. "0's" are loaded into the MBM27C256A through the procedure of programming. The MBM27C2S56A is programmed with a fast programming algorithm designed by Fujitsu called quick programming The pro- gramming mode is entered when +12.5V and +6V are applied to Vep and Voc re- spectively, and CE and OE are Vw. A 0.1,.F capacitor between Vpp and GND is needed to prevent excessive voltage tran- sients which could damage the device. The address to be programmed is applied to the proper address pins. The 8 bit data pattern to be written is placed on the re- spective data output pins. The voltage lev- els should be standard TTL levels. When both the address and data are stable, a 1 ms programming pulse is applied to CE ERASURE In order to clear all locations of their pro- grammed contents, it is necessary to ex- pose the MBM27C256A to an ultraviolet light source. A dosage of 15 W-seconds/ cm? is required to completely erase an MBM27C256A. This dosage can be ob- tained by exposure to an ultraviolet lamp (wavelength of 2537 Angstroms (A)) with intensity of 12000uW/cm? for 15 to 21 min- ELECTRONIC SIGNATURE The MBM27C256A has electronic signa- ture mode which is intended for use by pro- gramming equipment for the purpose of automatically matching the device to be programmed with its corresponding pro- and after that one additional pulse which is 3 times as wide as previous pulse is ap- plied to CE to accomplish the program- ming. Procedure of quick programming (Refer to the attached flowchart.) 1) Set the start address (=G) at the ad- dress pins. 2) Set Vcc = 6V, Vee = 12.5V and CE = Vin. 3) Clear the programming pulse counter (Xe-0). 4) Input data to respective pins. 5) Apply ONE Programming pulse (tew = ims Typ.) to CE. 6) Increment the counter (X-X+1). 7) Compare the number (=X) of applied programming pulse with 25 and then verify the programmed data. If pro- grammed data is verified, go to the next step regardless of X value. If X = 25 and programmed data is not verified, the device fails. If X = 25 and programmed utes. The MBM27C256A should be about one inch from the source and all filters should be removed from the UV light source prior to erasure. It is important to note that the MBM27C256A and similar devices, will erase with light sources having wave- lengths shorter than 40004. Although era- sure time will be much longer than with UV gramming algorithm. The electronic signature is activated when +12V is applied to address line Ag (pin 24) of the MBM27C256A. Two identifier bytes are readed out from the outputs by togging data is not verified, go back to the step ). 8) Apply one additional wide programming pulse to CE (3X ms). 9) Compare the address with an end ad- dress (=N). If the programmed address is the end address, proceed to the next step. If not, increment the address (G G+1) and then go to the step 3) for the next address. 10) Set Vcc = Vee = 5V. 11) Verify the all programmed data. If the verification succeeds, the program- ming completes. lf any programmed data is not the same as original data, the device fails. A continuous TTL low level should not ap- ply to CE input pin during the program mode (Vpp = 12.5V, Veg = 6V and OE = Vix) because it is required that one program- ming pulse width does not exceed 78.75 ms at each address. source at 2537A, nevertheless the expo- sure to fluorescent light and sunlight will eventually erase the MBM27C256A, and exposure to them should be prevented to realize maximum system reliability. If used in such an environment, the package win- dows should be covered by an opaque la- bel or substance. address line Ao (pin 10) from Vi, to Vin. The address lines from A; to A13 must be hold at Vi to keep the electronic signature mode. See the table below. Ao oO; Oz O3 O4 Os Os O, Oa Definition Vic 0 0 1 0 0 0 0 0 Manufacture Vin 0 1 0 0 xX 1 1 0 Device Note: Ag= 12V +0.5V A, thru Ag = Ajo thru Ay, = CE = OE = Vy. Aa = Either Vir or Vin. ee aseMBM27C256A-15 MBM27C256A-17 MBM27C256A-20 MBM27C256A-25 PROGRAMMING/ERASING INFORMATION (Continued) PROGRAMMING WAVEFORM oe ee Verify | Additional Program \ T T q tan ee : as sansies See es = Vin - ADDRESS Viv tou toe tor tos ton L i tas ! tos ViwlVou = pata ViWVox __ f= IN STABLE CVALIO ViVou 7 t DATA IN STABLE V Vpp = PP / ee Vi = V Veg?! - ce / Voc tves tow tcen tces tapw toes Dont CareMBM27C256A-15 MBM27C256A-17 MBM27C256A-20 MBM27C256A-25 DC CHARACTERISTICS (Ta = 2545C, Voc"! = 6VL0.25V, Vep? = 12.5V +0.3V) Parameter Symbol Min Typ Max Unit Input Leakage Current (Vin = 6.25V/ 0.45V) ly! 10 BA Vep Supply Current (CE = Vu, OE = Vin) lpee 50 mA Vpp Supply Current (OE = Vi) Ipp3 5 mA Vcc Supply Current lee 30 mA Input Low Level Vit 0.1 0.8 V Input High Level Vin 2.0 Voc +0.3 V Output Low Voltage During Verify (lo. = 2.1mA) Vor 0.45 Vv Output High Voltage During Verify (fo, = 400,A) Vox 2.4 Vv Note: *1 Vcc must be applied either coincidently or before Vpp and removed either coincidently or after Vep. *2 Vep must not be 14 volts or more including overshoot. Permanent device damage may occur if the device is taken out or put into socket remaining Vpp = 12.5 volts. Also, during CE = Vii, OE = Vin, Vep must not be switched from Vcc to Vpr volts or vice versa. AC CHARACTERISTICS (Ta = 2545C, Voc = 6V+0.25V, Vep = 12.5V +0.3V) Parameter Symbol Min Typ Max Unit Address Setup Time tas 2 ps Output Enable Setup Time toes 2 ps Chip Enable Setup Time tees 2 ps Data Setup Time tos 2 ys Vee Setup Time tvps 2 Hs Vee Setup Time tvcs 2 ps Address Hold Time tan 2 ps Data Hoid Time tox 2 ps Chip Enable Hold Time toen 2 ys Output Enable to Output Valid toe 120 ns Output Disable to Output Float Delay tor 105 ns Programming Pulse Width tew 0.95 1 1.05 ms Programming Pulse Number x 1 25 times Additional Programming Pulse Width tapw 2.85 78.75 msMBM27C256A-15 MBM27C256A-17 MBM27C256A-20 MBM27C256A-25 PROGRAMMING/ERASING INFORMATION (Continued) QUICK PROGRAMMING FLOW CHART . Veo =6V40.25V (sar) Vpp = 12.5+0.3V G : Start Address Address = G N : Stop Address { X : Counter Value Veo = 6V Maximum 105ms/Byte Vee = 12.5V Minimum 3.8ms/Byte + Xe-O Apply 1 Prog. Pulse(1ms) See t X<_X+1 SS = ete ee Seca a ne Ota Verify One Byte Apply Additional Programming Pulse (3Xms) Address +1 Address = N? Voc = 5.0V Vpp = 5.0V Verify All Bytes a canegenausnanenaananannnnanenananaanensnanananeante si veeeepesennees , seepaeee ae ee ee eSMBM27C256A-15 MBM27C256A-17 MBM27C256A-20 MBM27C256A-25 PACKAGE DIMENSIONS Standard 28-pin Ceramic DIP (Suffix: -Z) 28-LEAD CERAMIC (CERDIP WITH TRANSPARENT LID) DUAL IN-LINE PACKAGE (CASE No.: DIP-28C-C01) A nn a a a a yee R .025(0.64) +.018 1.64) 5777 Das 14. +0.46 .350(8.89)DIA (14.66 9 18) 600(15.24)TYP 6107015 -.010 +0.38 (15.4970 38) 1 SS eee Lt L +.004 1.450705 (36 3341.27) 010 002 -.015 -0.38 40.10 | f>-100(2.54)Max (0.25 9105) rT .230(5.84)MAX .134+,014 (3.40+0.36) .100+.010 .052+.010 .032(0.81) 0321-018 (2.54+0.25) " (1,32+0.25) TYP Teas 7 300(33.02)REF (0.817530) 01gt-005 . -.003 +0.13 (0.4679 oa) Dimensions in 1988 FUJITSU LIMITED D28007S-3C. inches (millimeters)MBM27C256A-15 MBM27C256A-17 MBM27C256A-20 MBM27C256A-25 PACKAGE DIMENSIONS Standard 32-pad Ceramic LCC (Suffix: -TV) 32-PAD CERAMIC (FRIT SEAL) LEADLESS CHIP CARRIER (CASE No.: LCC-32C-F01) .360(9.14) TYP *PIN NO. 1 / INDEX C.015(0.38) TYP ,, NN om T N ( og .100(2.54) REF QUU;/OUU a {Fo eS i P) Cy oto _ CS *PIN NO. 1 o *- IND .400(10.16) pe--008 | || R.008(0.20/TYP fF 5 a | TP +0. (13.97 548) | [cq (S2PLCS) [ey .050+.006 | 460(11.68) .025+.005 = Cs (1,270.15) TYP (0.64+0.13)TYP} TYP So FE C3 co TB AN f a C.040(1.02)T YP ooog 450-910 (3PLCS) .050+.006 -450 (1.2740.15) 008. ta .045(1.14)TYP tye 045(1.14) TYP (11.43 743) .070(1.78)TYP .300(7.62) .075(1.91)TYP .130(3.30)MAX TYP *Shape of PIN NO.1 INDEX: Subject to change without notice. Dimensions in 1988 FUJITSU LIMITED C32017S-2C inches (millimeters) All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete Information sufficient for construction purposes is not necessarily given. The Information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The Information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. 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