CY2V9950 2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer Features 2.5V or 3.3V operation Split output bank power supplies Output frequency range: 6 MHz to 200 MHz Output-output skew < 150 ps Cycle-cycle jitter < 100 ps Selectable positive or negative edge synchronization Selectable phase-locked loop (PLL) frequency range 8 LVTTL outputs driving 50 terminated lines LVCMOS/LVTTL Over-voltage tolerant reference input 2x, 4x multiply and (1/2)x, (1/4)x divide ratios Spread-Spectrum-compatible Pin-compatible with IDT5V9950 and IDT5T9950 Industrial temperature range: -40C to +85C 32-pin TQFP package The user can program the output banks through 3F[0:1] and 4F[0:1]pins. Any one of the outputs can be connected to feedback input to achieve different reference frequency multiplication and divide ratios and zero input-output delay. The device also features split output bank power supplies which enable the user to run two banks (1Qn and 2Qn) at a power supply level different from that of the other two banks (3Qn and 4Qn). Additionally, the PE pin controls the synchronization of the output signals to either the rising or the falling edge of the reference clock. Pin Configuration Block Diagram PLL 3F1 2Q 1 2F0 2F1 21 20 VDDQ1 1Q0 4Q1 4Q0 VSS 6 7 19 18 1Q1 8 17 VSS /K CY2V9950 sOE# VSS VSS 9 10 11 12 13 14 15 16 3Q 0 3 3Q 1 4Q 0 3 3 TEST 4 5 VDDQ 3 4F1:0 REF PE VDDQ4 2Q1 2Q0 2Q 0 2F1:0 1F0 VDD 1Q 1 1F1 23 22 FB 1F1:0 24 4F0 4F1 1 2 3 VDDQ3 1Q 0 3 VSS 32 31 30 29 28 27 26 25 FB 3F1:0 VDD 3 FS 3 FS VDDQ 1 3Q0 PE 3F0 TEST R EF The CY2V9950 is a low-voltage, low-power, eight-output, 200-MHz clock driver. It features functions necessary to optimize the timing of high performance computer and communication systems. 3Q1 * * * * * * * * * * * * * * Functional Description /M 4Q 1 VDDQ 4 sO E# Cypress Semiconductor Corporation Document #: 38-07436 Rev. *A * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised August 11, 2004 CY2V9950 Pin Definitions Pin 29 13 27 Name REF FB TEST 22 sOE# I/O[1] Type I LVTTL/LVCMOS I LVTTL 3-Level I 2-Level I, PD 4 PE 24, 23, 26, 25, 1, 32, 3, 2 31 19, 20, 15, 16,10,11, 6, 7 21 nF[1:0] VDDQ1[2] 12 VDDQ3[2] 5 VDDQ4[2] 14,30 VDD[2] 8, 9, 17, 18, 28 VSS I, PU I FS nQ[1:0] I O PWR PWR PWR PWR PWR LVTTL 3-Level Description Reference Clock Input. Feedback Input. When MID or HIGH, disables PLL (except for conditions of note 3). REF goes to all outputs. Set LOW for normal operation. Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0 and 2Q1) in a LOW state (for PE = H or M) - 2Q0 and 2Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE# is high, the nF[1:0] pins act as output disable controls for individual banks when nF[1:0] = LL. Set sOE# LOW for normal operation. Selects Positive or Negative Edge Control and High or Low output drive strength. When LOW / HIGH the outputs are synchronized with the negative/positive edge of the reference clock. Please see Table 5. Select frequency of the outputs. Please see Tables 1 and 2. 3-Level LVTTL Selects VCO operating frequency range. Please see Table 4. Four banks of two outputs. Please see Tables 1 and 2 for frequency settings. Power Power supply for Bank 1 and Bank 2 output buffers. Please see Table 6 for supply level constraints Power supply for Bank 3 output buffers. Please see Table 6 for supply level constraints Power supply for Bank 4 output buffers. Please see Table 6 for supply level constraints Power supply for internal circuitry. Please see Table 6 for supply level constraints Ground. Power Power Power Power Device Configuration The outputs of the CY2V9950 can be configured to run at frequencies ranging from 6 to 200 MHz. Banks 3 and 4 output dividers are controlled by 3F[1:0] and 4F[1:0] as indicated in Table 1 and 2 respectively. Table 1. Output Divider Settings - Bank 3 3F[1:0] LL[4] HH Other K - Bank3 Output Divider 2 4 1 Table 2. Output Divider Settings - Bank 4 4F[1:0] LL[4] HH Other M - Bank4 Output Divider 2 Inverted[5] 1 The divider settings, output frequencies, and possible c